Control circuit controlling data input / data output and method

Abstract

To provide a control circuit controlling a data input / a data output, and provide a method.SOLUTION: A control circuit 200 includes a plurality of control elements 224 that has at least one initial control step (m=1) and a final control step (an index m). Each control step includes at least one control element, and the number of control elements of the final control step is larger than that of the initial control step. Each control element receives a first control signal and a second control signal, and controls a current for a data input / a data output in associated with the first control signal and the second control signal. The control circuit starts from the initial control step, and provides the first control signal to each control element in order that it terminates at the final control step. After that, in at least the final control step, the second control signal is provided to the control element in the reverse order, and a current strength of the current for the data input / data output is increased by the provision of the second control signal.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a control circuit and method for controlling data input / data output.

Background Art

[0002] During data input / data output, a signal typically switches (at least) between two states, for example a low voltage (low level potential) and a high voltage (high level potential), for example by a transistor. Such data signals can be provided, for example, at a data input pad / data output pad or a non-contact data input element / data output element.

[0003] FIG. 1A shows two ideal profiles of such data signals.

[0004] The dashed line is a rectangular wave signal 102, which switches between a low voltage (low level potential) and a high voltage (high level potential) without delay, and after this switching, the voltage is kept constant with respect to current intensity variation (low level output current and high level output current). This enables a rapid switching between the two states. After reloading of a network node (line from transmitter to receiver), the current for defining the logic level drops to the current intensity required for maintaining the level (leakage current of transmitter and receiver and / or weak pull-up / pull-down current for defining the receiver input voltage level when the transmitter is in the tri-state mode).

[0005] Sudden current changes preceding voltage potential changes in network nodes (transmitter-to-receiver lines, capacitive network nodes) generate strong (unwanted) electromagnetic emissions (EME), which can then be coupled (galvanically in the power supply sections of the transmitter and receiver, or through electric field coupling via conductive loops on the printed circuit board) to produce noise signals (interference power). Such electromagnetic emissions primarily occur during the transistor switching process and are related to internal connections (process energy), driver strength (i.e., the current strength supplied), switching frequency, and load absorption (capacitive, resistive, inductive).

[0006] The solid line 104 represents the sinusoidal switching course of signal 102 between low and high voltage. A smooth, continuous current intensity course (current difference, rate of change of current per unit time) during voltage level switching reduces electromagnetic emissions because sinusoidal courses do not generate frequency harmonics (only fundamental waves). However, here, the target state (e.g., reaching the maximum or minimum voltage) is only achieved after the switching command, with a time delay. This is also typically undesirable because, generally, it is desirable to provide the shortest possible switching time (to quickly reach the new level state (high data rate / frequency)).

[0007] Figure 1B shows the actual switching current signal 106, which is generated when switching data input / data output from a low voltage level to a high voltage level.

[0008] As can be seen from the comparison between the actual signal 106 in Figure 1B and the ideal signal in Figure 1A, the actual signal 106 exhibits an intermediate state between the two ideal signals, especially during the rise. The rise is not as abrupt as in the case of the square wave signal 102, but not as smooth as in the case of the sinusoidal wave signal 104. Therefore, the actual signal 106 is a compromise between (as low as possible) switching speed and (similarly as low as possible) electromagnetic emissions.

[0009] However, in the latest designs, high switching frequencies with high power consumption are required during data input / output, which can cause electromagnetic emissions to exceed acceptable limits, such as customer-specified limits or legally mandated limits for electromagnetic compatibility (EMC).

[0010] Therefore, there is a need to provide data input / data output with the shortest possible switching time while adhering to electromagnetic emission limits (e.g., EMC limits).

[0011] In various embodiments, the present invention provides a control circuit and method for controlling data input / data output that can minimize electromagnetic emissions caused by the switching process despite short switching times.

[0012] In various embodiments, when switching the data input / output current (also referred to as driver current or drive current) from a minimum to a maximum value, the current change may be smaller than in the prior art near the minimum value (start of level change) or the maximum value (66% of the final level value), and stronger than in the prior art near the intermediate value between the minimum and maximum values ​​(50% of the level change, the steepest current increase for voltage level swapping).

[0013] The control circuit may be configured in various embodiments to achieve a gentle increase in current intensity at the start of the switching process from a low-current data signal to a high-current data signal (when only a small portion of the switching stage is active), a steep, rapid increase in current ("boost") in the middle (when the entire switching stage is active), and a gentle flattening of the current increase near the end (the gradual approximation of the level in the case of a capacitive load causes a decrease in the charging current).

[0014] For this purpose, according to various embodiments, it is possible to utilize the stepwise switching on of control elements that are connected in partially parallel, such as current control elements (e.g., divided transistors, so-called transistor fingers).

[0015] The control elements may be provided in a fir tree-like arrangement, for example, to illustrate concretely, in this arrangement, starting from the tip of the tree (e.g., one or two transistor fingers of the main transistor), a number of parallel-connected control elements (transistor fingers of the main transistor) are partially switched on in sequentially increasing switching steps. This switching behavior, starting from one or two transistor fingers of the main transistor, proceeds with a time delay through parasitic gate resistance and gate capacitance to the next instance (doubling the number of transistor fingers of the main transistor), and further connections of instances up to a depth of four instances (usually further doublings of one instance or more), results in a controlled avalanche-like increase in the switching current.

[0016] During the transition from a partially switched state to a fully switched state, the control element (the transistor finger of the main transistor) is switched on from the opposite side, specifically from the base of the fir tree to the tip of the fir tree.

[0017] This switching on both sides of the main transistor's transistor finger gate results in a more stable and faster switch-on state compared to the switch-on specification from the tip of the fir tree.

[0018] The connection point at the base of the fir tree provides more direct control of the main transistor's transistor finger gate drive (resulting in a smaller gate voltage drop due to the parallel connection of the transistor finger elements).

[0019] Accordingly, a full switching of such a large number of control elements occurs immediately after a partial switching of the control phase, which involves multiple control elements connected in parallel (at the base of the fir tree). This corresponds to a boost mode in which the current intensity increases significantly in a short time. In contrast, partial switching on of fewer control elements at the beginning and end of the switching process can achieve a more gradual increase in current.

[0020] Therefore, capacitive loads can be reloaded to approximate a sinusoidal / cosine function of the switching current, thereby reducing harmonic oscillations that can result in electromagnetic emissions. These electromagnetic emissions can be radiated and / or fed as noise / interference power into control circuits, data input pads / data output pads (e.g., high-speed data interface ports) or similar devices.

[0021] By using a low-emission driver current curve, which is achieved based on the drive control characteristics of the control element, it becomes possible to eliminate or reduce the number of additional circuit elements, such as RC elements, and / or avoid the control element (e.g., a standardized transistor finger element) being subjected to strong electromagnetic emissions. For example, even additional circuits that can be placed on a printed circuit board (PCB) together with the control circuit may have reduced the need to filter and remove the electromagnetic emissions they receive, thereby reducing the component area and, consequently, the chip area and weight.

[0022] Embodiments of the present invention are illustrated and will be described in more detail hereinafter.

Brief Description of the Drawings

[0023] [Figure 1A] It is a diagram showing an ideal case of two types of data signals. [Figure 1B] It is a diagram showing an example of an actual data signal according to the prior art. [Figure 2] It is a schematic diagram of a control circuit according to various embodiments. [Figure 3A] It is a schematic diagram of a control circuit according to various embodiments. [Figure 3B] It is a schematic diagram of a control circuit according to various embodiments. [Figure 4] It is a schematic diagram of a control element assembly according to various embodiments. [Figure 5] It is a schematic diagram of a control circuit according to various embodiments. [Figure 6] It is a diagram showing simulation results regarding currents for data input / data output according to various embodiments in comparison with the prior art. [Figure 7] It is a flowchart of a method for controlling data input / data output according to various embodiments.

[0024] The following detailed description refers to the accompanying drawings, which are part of the detailed description and illustrate specific embodiments in which the present invention can be carried out for illustrative purposes. In this regard, terms indicating direction, such as "up," "down," "front," "back," "forward," and "rear," are used in relation to the orientation of the figures described. Since the components of the embodiments can be positioned in several different orientations, these terms relating to direction are used for illustrative purposes and are not limited thereto. It is obvious that structural or logical modifications can be made using other embodiments without departing from the scope of the present invention. It is obvious that the features of the various exemplary embodiments described herein are combinable with respect to each other unless otherwise noted. Therefore, the following detailed description should not be taken as limiting, and the scope of the present invention is defined by the appended claims.

[0025] Within the scope of this specification, the terms “connected,” “linked,” and “joined” are used to describe direct connection, indirect connection, direct or indirect connection, and direct or indirect joining. In the figures, identical or similar elements are denoted by the same reference numeral, where preferable.

[0026] As described above, the switching of current for data input / output typically generates electromagnetic emissions, particularly during the formation of (sometimes steep) current edges, and sometimes at other points in the current curve.

[0027] In Figure 1B, these points on the current curve are numbered.

[0028] Switching on (labeled reference number 1) can, in some cases, have the strongest effect on emissions. During high-speed switching on, the emission potential can become very high (harmonic oscillations relative to the fundamental frequency). This is because a capacitive load in the data input can behave like a short circuit in the driver transistor (in this case, the switching-on resistance R between the transistor's source and drain during switching on). DSon (This can limit the peak current.)

[0029] The ideal switch-on behavior (in terms of emission) would result in a sinusoidal or cosine wave signal. In this case, the transistor's switch-on resistance changes accordingly from its initial state (reference number 1 in Figure 1B; the desirable optimal course is not realized in Figure 1B, which shows the actual current course according to prior art, and the comparison between Figure 1B and the reference numbers 1-4 used in Figure 1B is only useful for a better understanding and orientation along the current course curve) to a state of low resistance (labeled reference number 2 in Figure 1B). Near the region labeled reference number 2, the rate of change of the current can reach its maximum value (similar to the case of sinusoidal / cosine wave signals).

[0030] The fact that it is labeled reference number 3 suggests that the maximum current may be provided. Furthermore, here, the switch-on resistor R DSon It has been minimized.

[0031] When transitioning from the region labeled with reference number 3 to the region labeled with reference number 4, the rate of current change may be limited by the saturation of the capacitive load.

[0032] The aforementioned form of control circuit ("Fir Tree Concept"), involving stepped partial switching and subsequent full switching of a group of parallel-connected control elements that are switched in stages, was developed with the following in mind: namely, in the phase designated reference number 1, a smooth switching behavior is produced (capacitive short circuit, and therefore the minimum number of transistor fingers of the main transistor is active), and in phase 3, a sufficiently fast and sufficiently strong signal is produced (a boost at the base of the fir tree of the main transistor's transistor fingers), thereby providing, on the one hand, fast switching behavior, and on the other hand, generating a signal that is not sensitive to noise / interference power (and therefore the logic value associated with the current-signal value is stable).

[0033] Therefore, in various embodiments, a high switching frequency with low electromagnetic emissions can be provided by using a special intelligent switch-on sequence of the control elements of the control circuit for data input / data output.

[0034] In other words, neither all control elements are switched simultaneously nor sequentially. Rather, in the first control stage, a small number of control elements (e.g., one control element) are initially switched at least partially transparently to the drive current, and then in the second control stage, a switching sequence is realized in which a larger number of control elements (i.e., more than in the first control stage) (e.g., at least two control elements) are switched simultaneously and partially transparently. In other words, the number of control elements switched simultaneously increases continuously over time, for example, in a cascading or avalanche manner.

[0035] In various embodiments, more than two control steps may be provided, for example, at least three control steps, for example, four or five control steps.

[0036] In the reverse switching sequence, the control element of the control stage may then be switched to further increase its current permeability, for example, to its maximum possible permeability.

[0037] In other words, the resistance of the control elements in the "forward" switching process can be reduced (with an increasing number of control elements at each control stage), while in the reverse "backward" switching process, the resistance (R of the main driver transistor) can be reduced. DSon ) can be further reduced.

[0038] In various embodiments, the provision of a first control signal to a control element in the final control stage in a first direction (forward direction) may trigger the provision of a second control signal to a control element in the final control stage (and possibly other control stages up to the first control stage) in a second direction (backward direction).

[0039] In various embodiments, the control element may be similarly configured as, for example, a transistor finger (e.g., standardized or similar).

[0040] Figures 2, 3A, and 3B show schematic diagrams of the control circuit 200 according to various embodiments, respectively; Figure 4 shows a schematic diagram of a control element assembly 224 that can be part of the control circuit 200 according to various embodiments; and Figure 5 shows a schematic diagram of the control circuit 200 according to various embodiments. Referring to these figures together will facilitate understanding, as these parts are shown in a highly simplified manner for clarity.

[0041] The control circuit 200 may be provided for controlling data input / data output, for example, using data input pads / data output pads, or using non-contact data input elements / data output elements.

[0042] The control circuit 200 may have m control stages, each having at least one initial control stage (m=1) and a final control stage (index m). Typically, more than two control stages may be provided, for example, three, four, or five control stages.

[0043] Each control stage may have at least one control element 224.

[0044] In Figures 2, 3A, and 3B, the control element 224 is shown in a highly simplified form (as a rectangle with two terminals). In the upper right of Figure 3A and the lower left of Figure 3B (where additional reference numbers are provided), an insertion to be understood as a legend symbolically illustrates how the schematics in Figures 2, 3A, and 3B should be understood: each rectangle symbolically represents the gate of a transistor (the transistor finger of the main driver transistor), where the gate has two terminals 224A1 and 224A2. The gate controls the channel connecting the source terminal 224S and the drain terminal 224D. These are symbolically represented in the legend as light gray areas or as lines perpendicular to the gates, and are completely omitted in the "fir tree" representation.

[0045] In Figure 4, one circuit diagram is selected for each individual control element 224. Since the 12 control elements 224 shown in Figure 4 are all formed equally, terminal reference numbers are assigned to multiple individual control elements 224 for clarity.

[0046] In these figures, the control element 224 is indexed (only partially for clarity, for example in Figures 2 and 3A), where these indices represent the control stage m and the ordinal number n within the control stage. Following this scheme, 224_mn is, for example, 224_51 in the case of the first control element of the fifth control stage.

[0047] The number of control elements 224 may increase, for example, with each control stage, or it may remain the same. In some cases, to obtain a specific current progression profile, it may also be possible to decrease the number of control elements 224 n from one control stage to the next. This may be possible as long as it is guaranteed that the number of control elements 224 n(m) in the last (m-th) control stage 224_m is greater than the number of control elements 224_1 n(1) in the first control stage.

[0048] Figure 4 shows three exemplary control element assemblies, which are referred to as the first instance 224_Inst1 (bottom), the second instance 224_Inst2 (center), and the third instance 224_Inst3 (top).

[0049] Instances 224_Inst1 to 224_Inst3 are available as main driver transistors for data input / data output. Accordingly, the control circuit 200 may also be referred to as a data input / data output unit, according to various embodiments that utilize the control element assemblies of instances 224_Inst1 to 224_Inst3.

[0050] The control element assembly of the first instance 224_Inst1 includes one control element 224 in each of the first three control stages and 24 control elements 224 in the fourth and final control stage, thus containing a total of 27 double-finger transistors. This provides a powerful driver with a steep / rapid current rise edge for high data frequencies (i.e., enabling high DC current (approximately 31 mA in this embodiment)).

[0051] The control element assembly of the second instance 224_Inst2 includes one control element 224 in each of the first two control stages, two control elements 224 in the third control stage, and five control elements 224 in the fourth and final control stage, thus including a total of nine double-finger transistors. This provides a moderate-strength driver with a moderate current rise for low data frequencies (i.e., a moderate DC current (approximately 6 mA in this embodiment) is possible).

[0052] The control element assembly of the third instance 224_Inst3 includes one control element 224 in the first control stage, two control elements 224 in the second control stage, five control elements 224 in the third control stage, and ten control elements 224 in the fourth and final control stage, thus containing a total of 18 double-finger transistors. This provides a powerful driver with a moderately steep current rise edge for moderate data frequencies (i.e., enabling high DC current (approximately 17 mA in this embodiment)).

[0053] In Figure 4, the N input section and P input section are shown on the left, forming the tip of the "fir tree," while multiple output sections are shown on the right, with a booster input section below each (these form the base of the "fir tree").

[0054] Each control element 224 may be configured to receive a first control signal and a second control signal, and to control the current for data input / data output flowing between the source 224S and the drain 224D in relation to the first control signal and the second control signal.

[0055] In Figures 3A and 3B, an exemplary transistor of the control element 224 has a first gate terminal 224A1 and a second gate terminal 224A2, respectively. The first gate terminal 224A1 can be located on the first side of the channel that is switched by the gate, and the second gate terminal 224A2 can be located on the second side of the channel, opposite to the first side.

[0056] Here, a first control signal can be provided to the first gate terminal 224A1 of each gate, and a second control signal can be provided to the second gate terminal 224A2 of the same gate.

[0057] The control circuit 200 may be configured to provide a first control signal to each control element (i.e., control element 224_1 first, and control element 224_m last) in a sequence that begins in the first control stage and ends in the last control stage, and then provide a second control signal to the control elements in the reverse sequence, at least in the last control stage (i.e., control element 224_m first in the last control stage, and then, if applicable, control element 224 in the decreasing control stage sequence up to the first control stage).

[0058] This provision may be performed automatically or passively in various embodiments, for example, by capacitive coupling, i.e., the second gate terminal 224A2 of the preceding gate may be electrically connected to the first gate terminal 224A1 of the succeeding gate in order to provide a first control signal. Furthermore, a (stronger) control signal may be directly switched using the signal at the second gate terminal 224A2 of the control element 224_m of the final control stage. This control signal is supplied as a second control signal to this second gate terminal 224A2 of the control element 224_m of the final control stage.

[0059] According to an alternative embodiment, for example, each signal can be supplied to one of the gate outputs of a control unit that supplies a first control signal to a subsequent gate, and vice versa in the case of a second control signal, thereby indirectly or actively switching the control element.

[0060] In further embodiments, the active and passive provision of control signals can be combined, for example, by passively activating a control phase in the forward direction, then actively providing a control signal for switching to the reverse direction, and finally passively activating the control phase in the reverse direction; or by actively activating a control phase in the forward direction, then passively providing a control signal for switching to the reverse direction, and finally actively activating the control phase in the reverse direction.

[0061] The current intensity can be increased by providing a second control signal for data input / output.

[0062] In other words, the control element 224 is not switched completely transparently to the current for data input / output by the first control signal, but only partially transparently, in some cases, especially in relatively higher-order control stages. For example, a portion of the maximum drivable current provided after only the first control signal is provided may be 30% to 80%. Here, the highest percentage may be achievable at the lowest control stage, and the lowest percentage may be achievable at the highest control stage.

[0063] One possible cause is parasitic capacitance that can attenuate the first control signal transmitted from each control element 224 in a control stage to the control element 224 in a subsequent control stage. Therefore, the first control signal may already be too weak, for example, after the first control stage, in order to switch the control element 224 in a subsequent control stage to the state of the minimum achievable resistance.

[0064] For switching the control elements 224 (at least in a first direction in the case of at least one control element 224_1 in the first control stage, and in a backward direction in the case of a control element 224_m in the last control stage - each subsequent control element 224 is switchable by the control element 224 in the preceding control stage), at least one pre-circuit 222 may be provided as part of the control circuit 200. The pre-circuit 222 may have a part A 222A for switching the control elements 224 in the forward direction and a part B 222B for switching the control elements 224 in the backward direction.

[0065] Figure 5 shows the pre-circuit in detail. For each of the three instances shown in Figure 5 (which may be configured as CMOS in various embodiments; namely, a control element assembly 224P based on PMOS transistors and an additional control element assembly 224N based on NMOS transistors, see also Figures 3A and 3B), two pre-circuit portions 222A / B may be provided, namely, a pre-circuit portion 222A / B for the NMOS control element assembly 224N and an additional pre-circuit portion 222A / B for the PMOS control element assembly 224P, and so the pre-circuit 222 may have a total of six (2×3) pre-circuit portions 222A / B shown on the lower side of Figure 5.

[0066] If the number of instances is different, or if they are provided only as PMOS circuits or only as NMOS circuits, the number of pre-circuit sections 222A / B may be changed accordingly.

[0067] The first control signal provided after the final control stage may still be strong enough, despite parasitic capacitance, to be switched, for example using an additional transistor, to supply it to the control element 224_m of the final control stage in order to provide a second control signal.

[0068] During the continuous switching of the control element 224 in the control phase, the second control signal may also be attenuated due to parasitic capacitance. However, in various embodiments, the first and second switching signals may be configured to switch to the minimum achievable resistance state using the combination of the first and second switching signals in the control element 224.

[0069] The first control stage switches a relatively small number of control elements 224_1, and the last control stage switches a relatively large number of control elements 224_m. In the case of "reverse," initially, a large number of control elements are switched to maximum transparency, and only then, if applicable, a small number of control elements are switched by the first control stage. This results in a boost-like, i.e., rapidly and significantly increasing current approximately in the middle of the extrema, along with a slow, uniform increase in the current provided initially and just before reaching the maximum current.

[0070] As further shown in Figure 5, the control circuit 200 may have multiple control element assemblies (instances). These instances may have different characteristics of how the controlled current is driven, for example, with respect to speed and the maximum current obtained, as shown in Figure 4 and concretely illustrated in Figure 6 based on simulation. This can be achieved by the number of control elements 224 being different in comparison between one instance and another in at least one control stage.

[0071] The control circuit 200 may be configured to switch each instance individually. That is, for example, all instances may be switched together in parallel, only one instance of these instances may be switched, or a subset of these instances may be switched.

[0072] For maximum current, i.e., for the fastest switching, all instances can be activated together. In this embodiment, the maximum current can be the sum of the maximum currents of the individual instances 1-3. That is, in the embodiment shown in Figure 4, a maximum current of 31mA + 17mA + 6mA = 54mA can be provided.

[0073] In Figure 6, the aggregated signal, simulated in the embodiment of Figure 4, is shown along with the individual signals. For comparison, the signal from the prior art is also shown in Figure 6, which is slightly shifted horizontally. This time lag occurs for the same switching point (approximately 101.5 ns) in both the control circuit 200 and the prior art control circuit. This is because the interconnection of the double-finger transistors of the three main driver transistors of the data input / data output unit (see Figure 4) causes a time delay (approximately 500 ps in this embodiment) in the control circuit 200. For a better comparison, the prior art signal is again shown at the same footpoint as the aggregated signal in the embodiment described in relation to Figure 4, so that it can be seen that this aggregated signal initially rises more slowly than the prior art signal, but that these two signals reach their maximum values ​​almost simultaneously. This is achieved in various embodiments using a boost, approximately midway between the minimum and maximum currents.

[0074] The comparison in Figure 6 between the conventional current signal curve (dashed line) "adjusted" to t=0, here t=101.5ns, and the total curve for instances 1-3 (solid line) shows that a delay (approximately 300ps in this case) occurs when the switch is turned on. However, this delay is completely recovered by switching on the booster. Furthermore, the maximum current of circuit 200 in various embodiments is approximately 10% lower than that of the conventional technology.

[0075] This initial current adjustment (sine wave rise) during switching eliminates the drawbacks associated with switching delays. The switching time does not increase (ratio of switching time to high / low bit time), resulting in a 500ps delay, which is not critical to the data protocol because it affects the entire duration.

[0076] Furthermore, in various embodiments, for example, in applications where data input / data output is utilized, one or more instances may be switched, while other instances remain unused. This provides great flexibility regarding the generated data signals.

[0077] In various embodiments, the control circuit 200 may be provided with only one control element assembly 224 (or two control element assemblies 224), in which case flexibility is reduced.

[0078] The control of data input / output using the control circuit 200 exemplified in Figure 3A or Figure 3B (i.e., by one control element 224_1 in the first control stage, two control elements 224_2 in the second control stage, four control elements 224_3 in the third control stage, eight control elements 224_4 in the fourth control stage, and sixteen control elements 224_5 in the fifth control stage), which proceeds as described below, can be concretely explained.

[0079] Here, by utilizing the gate, which is part of the transistor forming the control element 224, as an RC element (i.e., gate resistance and gate capacitance in combination with source-drain), it is possible to simulate the slow start for providing current for data input / data output (using one transistor 224_11 in the first control stage) and the subsequent avalanche-like increase in speed (using 16 transistors connected in parallel in the fifth control stage).

[0080] In this case, R DSon(Or its reciprocal) is formed by the number of switched-on transistor fingers per unit of time.

[0081] When the switch is turned on, the "fir tree" is switched on at its narrow termination (i.e., the gate of one transistor in the first control stage), while the wider termination of the "fir tree" (i.e., the 16 transistors in the fifth control stage) can be in a tristate state (e.g., not connected to a potential).

[0082] The gate potential slowly moves through the driver gates of the 32 transistors in five control stages, providing a gate control signal to the gate input of each transistor, thereby partially transparently switching each gate-controlled channel. After this, the gates of the transistors in the fifth control stage are finally switched to the same potential as the gates of the transistors in the first control stage. In detail, this is done by additionally providing a second control signal to the second gate input of each gate.

[0083] In other words, the "fir tree" is additionally switched on from the wide end. This can be done at point 3, which is concretely shown in Figure 1B. Here, this additional switching from the wide end is 1. (Regarding the transistor model used) The process may be delayed by the time constant (delay control). 2. Alternatively, this may be done by an output level-voltage-feedback circuit (which measures the output voltage-saturation point of the load capacitor), in which case the output voltage value is read at 50% to 66%, at which point the second side of the fir tree (the broad base of the fir tree structure of the individual finger transistors of the main transistor) is additionally switched on relative to the tip of the fir tree structure.

[0084] Here, to compensate for the reload delay during switch-on, the partially charged load capacitance is reloaded more quickly. This ensures that the total switching time of the load capacitance is not prolonged, as it is compensated for by such a boost circuit.

[0085] Figure 7 is a flowchart illustrating methods for controlling data input / output according to various embodiments.

[0086] The method may have data input / data output control using a plurality of control stages, each having at least one initial control stage and a final control stage, each having at least one control element, the number of control elements in the final control stage being greater than the number of control elements in the initial control stages, and the method may include providing a first control signal to each control element to provide current for data input / data output in a sequence starting from the initial control stage and ending from the final control stage (710), and then providing a second control signal to at least the control elements in the final control stage in the reverse sequence, where the current intensity of the current provided for data input / data output is increased by the provision of the additional control signal (720).

[0087] The following sections outline some examples of implementations.

[0088] Embodiment 1 provides a control circuit for controlling data input / data output. The control circuit may have a plurality of control stages, each having at least one initial control stage and a final control stage, each having at least one control element, the number of control elements in the final control stage being greater than the number of control elements in the initial control stages, and each control element being configured to receive a first control signal and a second control signal, and to control a current for data input / data output in relation to the first control signal and the second control signal, and the control circuit is configured to provide each control element with a first control signal in the order starting from the initial control stage and ending from the final control stage, and then provide the control element with a second control signal in the reverse order, at least in the final control stage, so that the current intensity of the current for data input / data output increases by the provision of the second control signal.

[0089] Example 2 is the control circuit described in Example 1, wherein each control element has at least one transistor.

[0090] Embodiment 3 is a control circuit according to Embodiment 1 or 2, wherein the first control signal is provided to the first gate terminal of each gate.

[0091] Embodiment 4 is the control circuit described in Embodiment 3, wherein the second control signals are provided to the second gate terminals of the same gate.

[0092] Embodiment 5 is the control circuit described in Embodiment 4, wherein each first gate terminal is located on the first side of the channel that is switched by the gate, and each second gate terminal is located on the second side of the channel, opposite to the first side.

[0093] Example 6 is a control circuit described in any one of Examples 1 to 5, wherein each control element is formed as a CMOS element.

[0094] Example 7 is a control circuit described in any one of Examples 1 to 6, wherein the control circuit is further configured to switch a second control signal using a first control signal in the control element of the final control stage.

[0095] Example 8 is the control circuit described in Example 7, further comprising at least one additional transistor configured to switch a second control signal.

[0096] Example 9 is a control circuit according to any one of Examples 1 to 8, wherein each control element is configured to provide only a portion of the maximum current that can be provided from the control element for data input / data output when only a first control signal is provided.

[0097] Example 10 is the control circuit described in Example 9, with a portion of it being 30% to 80%.

[0098] Example 11 is a control circuit according to Example 9 or 10, wherein a portion thereof is reduced through a sequence of control stages.

[0099] Example 12 is a control circuit according to any one of Examples 1 to 11, wherein each control element is configured to provide the maximum current available from the control element for data input / data output when both a first control signal and a second control signal are provided to the control element.

[0100] Example 13 is a control circuit described in any one of Examples 1 to 12, wherein the control circuit further has an additional plurality of control stages, the additional plurality of control stages are formed similarly to the plurality of control stages, except that the number of control elements in at least one of the plurality of control stages is different from the number of control elements in the corresponding control stages of the additional plurality of control stages, and the additional plurality of control stages are connected in parallel to the plurality of control stages.

[0101] Example 14 is a control circuit according to Example 13, wherein the control circuit further includes a pre-driver circuit configured to switch a plurality of control stages and / or an additional plurality of control stages to a switchable state.

[0102] Example 15 is a control circuit according to any one of Examples 1 to 14, wherein the control circuit further comprises a data input pad / data output pad or a non-contact data input element / data output element to which current is supplied.

[0103] Example 16 is a method for controlling data input / data output using a plurality of control stages, each having at least one first control stage and a last control stage, wherein each control stage has at least one control element, the number of control elements in the last control stage is greater than the number of control elements in the first control stage, and the method comprises providing a first control signal to each control element in the order starting from the first control stage and ending from the last control stage, and thereafter providing a second control signal to at least the control elements in the last control stage in the reverse order, in order to provide current for data input / data output, wherein the current intensity of the current provided for data input / data output is increased by the provision of additional control signals.

[0104] Example 17 is the method described in Example 16, wherein each control element has at least one transistor.

[0105] Example 18 is the method described in Example 16 or 17, wherein a first control signal is provided to the first gate terminal of each gate.

[0106] Example 19 is the method described in Example 18, wherein the second control signals are provided to the second gate terminals of the same gate.

[0107] Example 20 is the method described in Example 19, wherein the first gate terminals are each located on the first side of the channel to be switched by the gates, and the second gate terminals are each located on the second side of the channel, opposite to the first side.

[0108] Example 21 is a method according to any one of Examples 16 to 20, wherein each control element is formed as a CMOS element.

[0109] Example 22 is a method according to any one of Examples 16 to 21, further comprising switching a second control signal using a first control signal provided in the control element of the final control step.

[0110] Example 23 is the method described in Example 22, wherein the control circuit further comprises at least one additional transistor, and the method comprises switching a second control signal by this transistor.

[0111] Example 24 is a method according to any one of Examples 16 to 23, the method further comprising providing only a portion of the maximum current that can be provided from the control element for data input / data output when only a first control signal is provided.

[0112] Example 25 is the method described in Example 24, with a portion of it being 30% to 80%.

[0113] Example 26 is the method described in Example 24 or 25, wherein a portion thereof is reduced through a sequence of control steps.

[0114] Example 27 is a method according to any one of Examples 16 to 26, the method further comprising providing the maximum current that can be supplied from the control element for data input / data output when both a first control signal and a second control signal are supplied to the control element.

[0115] Example 28 is a method according to any one of Examples 16 to 27, wherein the control circuit further has an additional plurality of control stages, the additional plurality of control stages are formed similarly to the plurality of control stages, except that the number of control elements in at least one of the plurality of control stages is different from the number of control elements in the corresponding control stages of the additional plurality of control stages, and the additional plurality of control stages are connected in parallel to the plurality of control stages.

[0116] Example 29 is the method described in Example 28, further comprising switching a plurality of control stages and / or an additional plurality of control stages to a switchable state.

[0117] Other advantageous configurations of the apparatus are evident from the description of the method.

Claims

1. A control circuit for controlling data input / data output, The control circuit - a plurality of control stages, including at least one initial control stage and a final control stage, each of said control stages having at least one control element; the number of control elements in the last control stage is greater than the number of control elements in the first control stage; each of the control elements is configured to receive a first control signal and a second control signal and to control a current for the data input / data output in relation to the first control signal and the second control signal; the control circuit is configured to provide the first control signal to each of the control elements in a sequence starting from the first control phase and ending with the last control phase, and then provide the second control signal to the control elements in the reverse sequence, at least during the last control phase, such that the current intensity of the current for the data input / data output is increased by the provision of the second control signal; Control circuit.

2. Each of the control elements includes at least one transistor. The control circuit of claim 1.

3. the first control signal is provided to a first gate terminal of each gate; The control circuit of claim 1.

4. the second control signals are each provided to a second gate terminal of the same gate; 4. The control circuit of claim 3.

5. the first gate terminals are each disposed on a first side of a channel switched by the gate; the second gate terminals are respectively disposed on second sides of the channels opposite the first sides; 5. The control circuit of claim 4.

6. Each of the control elements is formed as a CMOS device. The control circuit of claim 1.

7. the control circuit is further configured to switch the second control signal using the first control signal of the control element of the last control stage. The control circuit of claim 1.

8. the control circuit further comprises at least one additional transistor configured to switch the second control signal; 8. The control circuit of claim 7.

9. each of the control elements is configured to provide only a portion of the maximum current that can be provided by the control element for the data input / data output when only the first control signal is provided; The control circuit of claim 1.

10. the portion is between 30% and 80%; 10. The control circuit of claim 9.

11. the portion decreases through the sequence of the control steps.

10. The control circuit of claim 9.

12. each of the control elements is configured to provide a maximum current that can be provided by the control element for the data input / data output when both the first control signal and the second control signal are provided to the control element; The control circuit of claim 1.

13. the control circuit further comprises an additional plurality of control stages, the additional plurality of control stages being configured similarly to the first plurality of control stages except that the number of control elements in at least one control stage of the plurality of control stages is different from the number of control elements in a corresponding control stage of the additional plurality of control stages; the additional control stages are connected in parallel to the control stages; The control circuit of claim 1.

14. the control circuit further comprises a pre-driver circuit configured to switch the plurality of control stages and / or the additional plurality of control stages into a switchable state.

14. The control circuit of claim 13.

15. the control circuit further comprises a data input pad / data output pad or a non-contact data input element / data output element to which the current is provided; The control circuit of claim 1.

16. said providing of said first control signal is by capacitive coupling; The control circuit of claim 1.

17. 1. A method for controlling data input / data output using a plurality of control stages, the control stages including at least one initial control stage and a final control stage, comprising: each of said control stages has at least one control element, the number of control elements of said last control stage being greater than the number of control elements of said first control stage; The method comprises: providing a first control signal to each of said control elements in a sequence starting with said first control phase and ending with said last control phase to provide a current for said data input / data output; thereafter, in reverse order, providing a second control signal to at least the control element of the last control stage, the current intensity of the current provided for the data input / data output being increased by the provision of an additional control signal; The method has the following features:

18. Each of the control elements includes at least one transistor.

18. The method of claim 17.

19. providing the first control signal to a first gate terminal of each gate; 18. The method of claim 17.

20. providing said second control signals to second gate terminals of the same gates respectively; 20. The method of claim 19.

21. each of the first gate terminals being disposed on a first side of a channel switched by the gate; each of the second gate terminals being disposed on a second side of the channel opposite the first side; 21. The method of claim 20.

22. forming each of said control elements as a CMOS device; 18. The method of claim 17.

23. The method further comprises switching the second control signal using the first control signal provided in the control element of the last control stage.

18. The method of claim 17.

24. The control circuit further includes at least one additional transistor, and the method includes switching the second control signal with the transistor.

24. The method of claim 23.

25. The method further comprises providing only a portion of a maximum current provideable from the control element for the data input / data output when only the first control signal is provided.

18. The method of claim 17.

26. the portion is between 30% and 80%; 26. The method of claim 25.

27. the portion is reduced through the sequence of the control steps; 26. The method of claim 25.

28. The method further comprises providing a maximum current provideable from the control element for the data input / data output when both the first control signal and the second control signal are provided to the control element.

18. The method of claim 17.

29. the method further comprising an additional plurality of control stages, the additional plurality of control stages being configured similarly to the plurality of control stages except that the number of control elements in at least one control stage of the plurality of control stages is different from the number of control elements in a corresponding control stage of the additional plurality of control stages; the additional control stages are connected in parallel to the control stages; 18. The method of claim 17.

30. the method further comprising switching the plurality of control stages and / or the additional plurality of control stages into a switchable state.

30. The method of claim 29.

31. said providing of said first control signal is by capacitive coupling; 18. The method of claim 17.

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