Voltage fluctuation detection circuit

Abstract

To provide a voltage fluctuation detection circuit capable of detecting voltage fluctuations using a low-voltage semiconductor element.SOLUTION: A voltage fluctuation detection circuit 1 includes a power drop detection circuit 10 that detects a drop in the voltage of a first power supply that outputs a first voltage, and outputs the detected result as a voltage drop detection signal with a second voltage lower than the voltage of the first power supply, an erroneous detection prevention circuit 20 that detects an increase in the voltage of the first power supply and outputs the detected result as a voltage increase detection signal using the second voltage, and a transistor 30 that masks the output of the voltage drop detection signal during a period in which an increase in the voltage of the first power source is detected on the basis of the voltage increase detection signal.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a voltage fluctuation detection circuit.

Background Art

[0002] Conventionally, in the technical field of detecting voltage fluctuations of a power supply mounted on a vehicle, a technique for detecting voltage fluctuations by comparing a power supply voltage with a predetermined reference voltage is known. (For example, refer to Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When attempting to detect power supply voltage fluctuations using the conventional technology as described above, there is a problem that a semiconductor element with high voltage resistance corresponding to the power supply voltage is required.

[0005] The present invention has been made in view of such a situation, and an object thereof is to provide a voltage fluctuation detection circuit capable of using a semiconductor element with low voltage resistance.

Means for Solving the Problems

[0006] A voltage fluctuation detection circuit according to an aspect of the present invention includes a power supply drop detection circuit that detects a decrease in the voltage of a first power supply that outputs a first voltage, and outputs the detected result as a voltage drop detection signal using a second voltage lower than the voltage of the first power supply; a false detection prevention circuit that detects an increase in the voltage of the first power supply, and outputs the detected result as a voltage increase detection signal using the second voltage; and a mask circuit that invalidates the output of the voltage drop detection signal during a period in which an increase in the voltage of the first power supply is detected based on the voltage increase detection signal.

Effects of the Invention

[0007] According to the present invention, a voltage fluctuation detection circuit capable of detecting power supply voltage fluctuations using low-voltage semiconductor elements can be provided. [Brief explanation of the drawing]

[0008] [Figure 1] This figure shows an example of the functional configuration of a voltage fluctuation detection circuit according to the embodiment. [Figure 2] This is a circuit diagram showing an example of the circuit configuration of the power supply drop detection circuit according to the embodiment. [Figure 3] This is a circuit diagram showing an example of the circuit configuration of the false detection prevention circuit according to the embodiment. [Figure 4] This is a timing chart illustrating an example of the operation of the voltage fluctuation detection circuit according to the embodiment. [Figure 5] This is a circuit diagram showing another example of the circuit configuration of the power supply drop detection circuit according to the embodiment. [Figure 6] This is a circuit diagram showing another example of the circuit configuration of the false detection prevention circuit according to the embodiment. [Modes for carrying out the invention]

[0009] [First Embodiment] A voltage fluctuation detection circuit according to an aspect of the present invention will be described in detail below with reference to the accompanying drawings, with reference to preferred embodiments. However, the aspects of the present invention are not limited to these embodiments and include various modifications or improvements. Furthermore, various omissions, substitutions, or modifications of components can be made without departing from the spirit of the present invention.

[0010] [Voltage fluctuation detection circuit] Figure 1 shows an example of the functional configuration of a voltage fluctuation detection circuit according to an embodiment. An example of the functional configuration of the voltage fluctuation detection circuit 1 will be described with reference to this figure.

[0011] The voltage fluctuation detection circuit 1 detects fluctuations in a predetermined power supply voltage. The predetermined power supply voltage is, for example, a voltage that cannot be applied to the gate terminal of a thin-film transistor (low-voltage semiconductor element) with a thin gate insulating film and low gate dielectric breakdown voltage, and requires the use of a thick-film transistor (high-voltage semiconductor element) with a thick gate insulating film and high gate dielectric breakdown voltage for dielectric breakdown protection. Specifically, a lead-acid battery can be used as the detection target of the voltage fluctuation detection circuit 1. Below, an example will be described in which the detection target of the voltage fluctuation detection circuit 1 is a 12V power supply such as a lead-acid battery.

[0012] In the following explanation, the power supply that the voltage fluctuation detection circuit 1 is to be detected by will be referred to as the first power supply, and the voltage output by the first power supply will be referred to as the first voltage or the HV power supply voltage.

[0013] The voltage fluctuation detection circuit 1 includes a power supply drop detection circuit 10, a false detection prevention circuit 20, and a transistor 30 that operates as a mask circuit. The power supply drop detection circuit 10 outputs a voltage drop detection signal DETF. The false detection prevention circuit 20 outputs a voltage rise detection signal DETR.

[0014] The voltage drop detection signal DETF output by the power supply drop detection circuit 10 is input to a control unit (not shown). Although not shown in Figure 1, the voltage rise detection signal DETR may also be connected to a control unit (not shown).

[0015] The power supply drop detection circuit 10 detects a drop in the first voltage. Specifically, the power supply drop detection circuit 10 detects that the amount of drop in the first voltage per unit time (negative slope) is greater than or equal to a predetermined value. The power supply drop detection circuit 10 outputs the detected result as a voltage drop detection signal DETF. The voltage drop detection signal DETF is L (low level) under normal conditions and H (high level) when a voltage drop is detected.

[0016] Here, the second power supply may be generated by, for example, a series regulator or the like that takes the first power supply as an input. Since the voltage drop detection signal DETF is driven by the second power supply, the voltage level of the voltage drop detection signal DETF is lower than the first voltage. In the following description, the voltage level of the voltage drop detection signal DETF may be described as the second voltage or the LV power supply voltage. The voltage level of the second voltage may be, for example, 5V or 3.3V or the like.

[0017] The false detection prevention circuit 20 detects an increase in the power supply voltage. Specifically, the false detection prevention circuit 20 detects that the amount of increase (positive slope) of the power supply voltage per unit time is not less than a predetermined value. The false detection prevention circuit 20 outputs the detected result as a voltage increase detection signal DETR. The voltage increase detection signal DETR is L during normal times and H when a voltage increase is detected. The voltage level of the voltage increase detection signal DETR is lower than the power supply voltage. Note that specifically, the voltage level of the voltage increase detection signal DETR may be the same as the voltage level of the voltage drop detection signal DETF.

[0018] Here, the power supply drop detection circuit 10 may output a false detection signal of a power supply drop at the time of power supply startup, voltage increase, etc. (that is, the voltage drop detection signal DETF instantaneously outputs H). The time of power supply startup is, as an example, the case where the power supply voltage rises from 0V to 12V, and the time of voltage increase is, as an example, the case where the power supply voltage rises from 12V to 24V. When the power supply drop detection circuit 10 outputs a false detection signal at the time of power supply startup, voltage increase, etc., the false detection prevention circuit 20 prevents the false detection signal from being transmitted to the subsequent stage.

[0019] The transistor 30 is an N-channel type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The voltage increase detection signal DETR output by the false detection prevention circuit 20 is connected to the gate terminal of the transistor 30. The voltage drop detection signal DETF output by the power supply drop detection circuit 10 is connected to the drain terminal of the transistor 30. The source terminal of the transistor 30 is connected to the third power supply terminal 103 and grounded.

[0020] In the following description, the gate terminal, source terminal, drain terminal, and bulk terminal (back gate, substrate, or body) of the transistor may be simply referred to as gate, source, drain, and bulk.

[0021] Transistor 30 invalidates (masks) the output of the voltage drop detection signal DETF during the period when it detects the increase in the power supply voltage based on the voltage increase detection signal DETR. Transistor 30 is also described as a mask circuit. Specifically, when the voltage increase detection signal DETR becomes H, the drain-source interval of transistror 30 turns on, and the voltage drop detection signal DETF is fixed to L.

[0022] [Circuit configuration of power supply drop detection circuit] FIG. 2 is a circuit diagram showing an example of the circuit configuration of the power supply drop detection circuit 10 according to the first embodiment. First, an example of the detailed circuit configuration of the power supply drop detection circuit 10 will be described while referring to the figure. The power supply drop detection circuit 10 includes a load 61, a load 62, transistors 63 to 67, a resistor 21, a parasitic diode 22, and an inverter 31.

[0023] The first power supply terminal 101 shown in the figure is an example of a power supply terminal connected to the power supply (first power supply) to be detected by the voltage fluctuation detection circuit 1, and the second power supply terminal 102 is an example of a power supply terminal connected to the logic power supply (second power supply) used for signal processing. The third power supply terminal 103 is, for example, a ground potential or a negative power supply potential. Therefore, the first power supply terminal 101 and the second power supply terminal 102 use the third power supply terminal 103 as a common reference potential.

[0024] Transistor 63 is a P-channel MOSFET for the current mirror. The source and bulk of transistor 63 are connected to the first power supply terminal 101. The gate and drain of transistor 63 are connected to each other. In the following description, the connection point between the gate and drain of transistor 63 may also be referred to as node PG1. Transistor 63 may also be referred to as the first transistor. Transistor 63 is a thin-film transistor (a low-voltage semiconductor device) in which the gate insulating film (gate oxide film) is formed in a thin film form.

[0025] Load 61 is a current source load. Specifically, load 61 is a depletion-type N-channel MOSFET. One end (drain) of load 61 is connected to the gate-drain connection point (node ​​PG1) of transistor 63. The other end (gate, source, and bulk) of transistor 63 is grounded to the third power supply terminal 103. In the following description, load 61 may also be referred to as the first load.

[0026] Transistor 64 is a P-channel MOSFET for current mirroring. The gate of transistor 64 is connected to the connection point (node ​​PG1) of the gate and drain of transistor 63. The source of transistor 64 is connected to the first power supply terminal 101. The drain of transistor 64 is connected to one end of load 62. The bulk of transistor 64 is connected to the gate and drain of transistor 65. In the following description, the connection point between the drain of transistor 64 and load 62 may be referred to as node A. Also, the connection point between the gate and drain of transistor 65 and the bulk of transistor 64 may be referred to as node BG1. Also, in the following description, transistor 64 may be referred to as the second transistor. Note that transistor 64 is a thin-film transistor (a low-voltage semiconductor device).

[0027] Load 62 is a current source load. Specifically, load 62 is a depletion-type N-channel MOSFET. One end (drain) of load 62 is connected to the drain of transistor 64. The other end (gate, source, and bulk) of load 62 is grounded to the third power supply terminal 103. In the following description, load 62 may also be referred to as the second load.

[0028] Furthermore, the resistance value of the load 62 is preferably such that, as a result of voltage division between the voltage of the first power supply terminal 101 and transistor 64, the potential of node A is at or above the H level (i.e., the threshold voltage of inverter 31). The potential of node A is clamped by the clamp circuit described later, so it is sufficient if it is the threshold voltage of inverter 31.

[0029] Transistor 65 is a P-channel MOSFET. The gate and drain of transistor 65 are connected to each other and to the bulk of transistor 64. The source and bulk of transistor 65 are connected to each other and to the gate of transistor 63 and the gate of transistor 64 (node ​​PG1). In the following description, transistor 65 may be referred to as the third transistor. Note that transistor 65 is a thin-film transistor (a low-voltage semiconductor device).

[0030] The resistor 21 and the parasitic diode 22 determine the time constant of the transistor 64. Specifically, the parasitic diode 22 is a parasitic diode formed between the well and bulk of the transistor 64. That is, the time constant of the transistor 64 is determined by the capacitance component of the parasitic diode of the transistor 64 and the resistance value of the resistor 21. The resistor 21 and the parasitic diode 22 are sometimes referred to as the time constant determination circuit.

[0031] It is also possible to replace the parasitic diode 22 with a capacitor, but if a capacitor is used, a thick-film process, which is a high-voltage semiconductor device manufacturing process, must be used. In this embodiment, by using the parasitic diode 22 instead of a capacitor to determine the time constant of the transistor 64, the semiconductor can be manufactured without using a thick-film process.

[0032] Transistors 66 and 67 are N-channel MOSFETs used to clamp the voltage at the connection point (node ​​A) between the drain of transistor 64 and the load 62. The voltage at node A is clamped to the potential between the drains of transistors 66 and 67. Transistors 66 and 67 operate as a clamp circuit that maintains the voltage at node A within a predetermined range from the voltage of the third power supply terminal. In this embodiment, two transistors, transistors 66 and 67, are used, but one or more transistors may be used depending on the clamp voltage. If the number of transistors is n (where n is a natural number of 1 or more), the potential between the drains of the transistors is NchVth, and the potential at the third power supply terminal 103 is VSS, then the clamp voltage is expressed as VSS + n × NchVth. The clamp voltage is determined according to the maximum input voltage of the inverter 31.

[0033] The inverter 31 has an input terminal, an output terminal, and a power terminal. The second power terminal 102 is connected to the power terminal of the inverter 31. The voltage of node A is input to the input terminal of the inverter 31. The output terminal of the inverter 31 outputs a voltage drop detection signal DETF. That is, the power drop detection circuit 10 outputs a signal based on the potential of the connection point (node ​​A) between the drain of transistor 64 and the load 62 as the voltage drop detection signal DETF.

[0034] [Operation of the power supply drop detection circuit] Next, an example of the operation of the power supply drop detection circuit 10 will be described with reference to Figure 2. Under normal conditions, that is, when there is no voltage fluctuation at the first power supply terminal 101, the potential at node A is high. In other words, when the false detection prevention circuit 20 does not detect a drop in voltage at the first power supply terminal 101, the potential at the connection point (node ​​A) between the drain of transistor 64 and the load 62 is high.

[0035] As described above, the potential of node A is clamped by transistors 66 and 67. As a result of the potential of node A being clamped at a predetermined voltage, the inverter 31 will not be damaged even if the input is made of transistors with low voltage resistance and thin gate oxide films. Also, since H is input to the input terminal of inverter 31, inverter 31 outputs L, and the voltage drop detection signal DETF becomes L. In other words, the voltage drop detection signal DETF is L when the false detection prevention circuit 20 does not detect a voltage drop at the first power supply terminal 101.

[0036] When the voltage at the first power supply terminal 101 drops sharply, the bulk potential of transistor 64 falls later than the source potential due to the time constant caused by the capacitance of resistor 21 and parasitic diode 22, because resistor 21 exists between the bulk potential of transistor 64 and the first power supply terminal 101. Therefore, due to the back gate effect, transistor 64 turns off, and the potential at node A changes from H to L. Since L is input to the input terminal of inverter 31, inverter 31 outputs H, and the voltage drop detection signal DETF becomes H.

[0037] In this case, the gate of transistor 63 is protected by self-clamping due to the gate-source voltage of transistor 63 itself. Furthermore, the gate of transistor 64 is protected by clamping due to the gate-source voltage of transistor 65. Transistor 65 acts as a clamping circuit that maintains the gate voltage of transistor 64 within a predetermined range from the first power supply voltage. Therefore, all transistors in the power supply undervoltage detection circuit 10 are protected by voltage withstand protection.

[0038] [Circuit configuration of the false detection prevention circuit] Figure 3 is a circuit diagram showing an example of the circuit configuration of the false detection prevention circuit according to the first embodiment. A detailed example of the circuit configuration of the false detection prevention circuit 20 will be described with reference to this figure. The false detection prevention circuit 20 includes a load 41, a load 42, transistors 43 to 50, a resistor 23, a parasitic diode 24, a capacitor 25, a capacitor 26, and an inverter 32. In the description of the false detection prevention circuit 20, components similar to those in the power supply low detection circuit 10 may be denoted by the same reference numerals, and their description may be omitted.

[0039] Transistor 43 is a P-channel MOSFET for the current mirror. The source and bulk of transistor 43 are connected to the first power supply terminal 101. The gate and drain of transistor 43 are connected to each other. In the following description, the connection point between the gate and drain of transistor 43 may also be referred to as node PG2. Transistor 43 may also be referred to as the fourth transistor. Note that transistor 43 is a thin-film transistor (a low-voltage semiconductor device).

[0040] Load 41 is a current source load. Specifically, load 41 is a depletion-type N-channel MOSFET. One end (drain) of load 41 is connected to the gate-drain connection point (node ​​PG2) of transistor 43. The other end (gate, source, and bulk) of load 41 is grounded to the third power supply terminal 103. In the following description, load 41 may also be referred to as the third load.

[0041] Transistor 44 is a P-channel MOSFET for current mirroring. The gate of transistor 44 is connected to the gate-drain connection point (node ​​PG2) of transistor 43. The source of transistor 44 is connected to the first power supply terminal 101. The drain of transistor 44 is connected to one end of load 42. The bulk of transistor 44 is connected to the gate and drain of transistor 45. In the following description, the connection point between the drain of transistor 44 and load 42 may be referred to as node C. Also, the connection point between the gate-drain connection point of transistor 45 and the bulk of transistor 44 may be referred to as node BG2. Also, in the following description, transistor 44 may be referred to as the fifth transistor. Note that transistor 44 is a thin-film transistor (a low-voltage semiconductor device).

[0042] Load 42 is a current source load. Specifically, load 42 is a depletion-type N-channel MOSFET. One end (drain) of load 42 is connected to the drain of transistor 44. The other end (gate, source, and bulk) of load 42 is grounded to the third power supply terminal 103. In the following description, load 42 may also be referred to as the fourth load.

[0043] Furthermore, it is preferable that the resistance value of load 42 is such that, as a result of voltage division between the voltage at the first power supply terminal 101 and transistor 44, the potential at node C is below the L level (i.e., the threshold voltage of inverter 31). In other words, if the on-resistance of transistor 44 is the same as the on-resistance of transistor 64, the on-resistance of load 42 is smaller than the on-resistance of load 62.

[0044] Transistor 45 is a P-channel MOSFET. The gate and drain of transistor 45 are connected to each other and to the bulk of transistor 44. The source and bulk of transistor 45 are connected to each other and to the gate of transistor 43 and the gate of transistor 44 (node ​​PG2). In the following description, transistor 45 may be referred to as the sixth transistor. Note that transistor 45 is a thin-film transistor (a low-voltage semiconductor device).

[0045] The resistor 23 and the parasitic diode 24 determine the time constant of the transistor 44. Specifically, the parasitic diode 24 is the parasitic diode of transistor 44. That is, the time constant of transistor 44 is determined by the capacitance component of the parasitic diode of transistor 44 and the resistance value of resistor 23. The resistor 23 and the parasitic diode 24 are sometimes referred to as the time constant determination circuit.

[0046] It is also possible to use a capacitor instead of the parasitic diode 24, but if a capacitor is used, a thick-film process must be used. In this embodiment, by using the parasitic diode 24 instead of a capacitor to determine the time constant of the transistor 44, the semiconductor can be manufactured without using a thick-film process.

[0047] Transistors 46 and 47 are N-channel MOSFETs used to clamp the voltage at the connection point (node ​​C) between the drain of transistor 44 and the load 42. The voltage at node C is clamped to the potential between the drains of transistors 46 and 47. Transistors 46 and 47 operate as a clamp circuit to maintain the voltage at node C within a predetermined range from the third power supply voltage. In this embodiment, two transistors, transistors 46 and 47, are used, but one or more transistors may be used depending on the clamp voltage. If the number of transistors is n (where n is a natural number of 1 or more), the potential between the drains and sources of the transistors is NchVth, and the potential at the third power supply terminal 103 is VSS, then the clamp voltage is expressed as VSS + n × NchVth. The clamp voltage is determined according to the maximum input voltage of the capacitor 25.

[0048] Capacitor 25 has one end connected to the connection point (node ​​C) between the drain of transistor 44 and the load 42, and the other end connected to the gate of transistor 50. In the following description, the gate of transistor 50 will also be referred to as node D.

[0049] Transistor 48 is a load transistor that fixes the potential of node D to L under normal conditions. Specifically, transistor 48 is a depletion-type N-channel MOSFET. The drain of transistor 48 is connected to node D. The gate, source, and bulk of transistor 48 are grounded to the third power supply terminal 103. Capacitor 26 is initially connected to node D, and the other end is grounded to the third power terminal 103. Capacitor 25, transistor 48, and capacitor 26 block the DC component at node C and do not transmit it to node D. Capacitor 25, however, transmits the AC component at node C to node D. In other words, capacitor 25, transistor 48, and capacitor 26 operate as a high-pass filter that transmits only the AC component when the potential at node C changes rapidly from L to H.

[0050] Transistor 50 is an N-channel MOSFET. The gate of transistor 50 is connected to capacitor 25. The source and bulk of transistor 50 are grounded to the third power supply terminal 103. The drain of transistor 50 is connected to the source and gate of transistor 49. In the following description, transistor 50 may also be referred to as the seventh transistor. In the following description, the connection point between the drain of transistor 50 and the source and gate of transistor 49 will also be referred to as node E.

[0051] Transistor 49 is a load transistor that fixes the potential of node E to high under normal conditions. Specifically, transistor 49 is a depletion-type N-channel MOSFET. The drain of transistor 49 is connected to the second power supply terminal 102. The gate and source of transistor 49 are connected to node E. The bulk of transistor 49 is grounded to the third power supply terminal 103. In the following description, transistor 49 may also be referred to as the eighth transistor.

[0052] The inverter 32 has an input terminal, an output terminal, and a power terminal. The second power terminal 102 is connected to the power terminal of the inverter 32. The voltage at node E is input to the input terminal of the inverter 32. The output terminal of the inverter 32 outputs a voltage rise detection signal DETR. That is, the false detection prevention circuit 20 outputs a signal based on the potential of the connection point (node ​​E) between the gate and source of transistor 49 and the drain of transistor 50 as the voltage rise detection signal DETR.

[0053] Furthermore, the potential of node E is based on the potential of the connection point (node ​​C) between the drain of transistor 44 and the load 42. In other words, the false detection prevention circuit 20 outputs a signal based on the potential of node C as a voltage rise detection signal DETR.

[0054] [Operation of the false detection prevention circuit] Next, an example of the operation of the false detection prevention circuit 20 will be described with reference to Figure 3.

[0055] Under normal conditions, that is, when there is no voltage fluctuation at the first power supply terminal 101, the potential at node C is low (L). The reason why the potential at node C is low is as described above, by making the resistance of the load 42 smaller than the on-resistance of transistor 44. In other words, when the false detection prevention circuit 20 does not detect a rise in voltage at the first power supply terminal 101, the potential at the connection point (node ​​C) between the drain of transistor 44 and the load 42 is low (L).

[0056] The potential at node C is clamped by transistors 46 and 47. The example shown in the figure illustrates the case with two transistors, but the number of transistors may be n (where n is a natural number greater than or equal to 1). If the potential between the drain and source of the transistors is NchVth and the potential at the third power supply terminal 103 is VSS, then the clamp voltage is expressed as VSS + n × NchVth.

[0057] Under normal conditions, the potential of node D becomes L as a result of being pulled down by transistor 48. Therefore, transistor 50 is turned off, and node E becomes H as a result of being pulled up to the second power supply terminal 102 by transistor 49. Because node E is H, H is input to the input terminal of inverter 32, inverter 32 outputs L, and the voltage rise detection signal DETR becomes L. In other words, the voltage rise detection signal DETR is L when the false detection prevention circuit 20 does not detect a voltage rise at the first power supply terminal 101. Here, since there is a DC blocking capacitance 25 between node C and node D, the potential of node D is not affected by the first power supply terminal 101.

[0058] When the voltage at the first power supply terminal 101 drops sharply, the source potential of transistor 44 drops ahead of the bulk voltage due to the time constant caused by the capacitance of resistor 23 and parasitic diode 24, because resistor 23 exists between the bulk voltage and the first power supply terminal 101. Therefore, due to the back gate effect, transistor 44 turns off, and the potential at node C remains L. Because the potential at node C remains L, the potential at node D also remains L. Therefore, transistor 50 remains off, and node E remains H as a result of being pulled up to the second power supply terminal 102 by transistor 49. Because node E remains H, H is input to the input terminal of inverter 32, inverter 32 outputs L, and the voltage rise detection signal DETR remains L.

[0059] When the voltage at the first power supply terminal 101 rises sharply, the source potential of transistor 44 rises ahead of the bulk voltage due to the time constant caused by the capacitance of resistor 23 and parasitic diode 24, because resistor 23 exists between the bulk voltage and the first power supply terminal 101. Therefore, due to the back gate effect, transistor 44 turns on, and the potential of node C changes from L to H. Because the potential of node C has risen sharply to H, capacitance 25 transmits a signal that has changed from L to H as an AC component, and the potential of node D also changes from L to H. Therefore, H is input to the gate of transistor 50, causing it to turn on, and node E is pulled down to the third power supply terminal 103 by transistor 50, resulting in a change from H to L. It is preferable that the resistance value of transistor 49 be larger than the on-resistance of transistor 50 so that node E becomes L when transistor 50 turns on. Because node E has changed from H to L, L is input to the input terminal of inverter 32, inverter 32 outputs H, and the voltage rise detection signal DETR outputs H.

[0060] In this case, the gate of transistor 43 is protected by self-clamping. Furthermore, the gate of transistor 44 is protected by clamping with transistor 45. Transistor 45 acts as a clamping circuit that maintains the gate voltage of transistor 44 within a predetermined range from the first power supply voltage. Additionally, the gates of capacitor 25 and transistor 50 are protected by clamping with transistors 46 and 47. Therefore, all transistors in the false detection prevention circuit 20 are protected by voltage withstand protection.

[0061] Returning to Figure 1, even if the voltage drop detection signal DETF incorrectly outputs H when the voltage at the first power supply terminal 101 rises sharply, the false detection prevention circuit 20 outputs H as the voltage rise detection signal DETR, causing the gate of transistor 30 to become H and turn on transistor 30. As a result, the voltage drop detection signal DETF is pulled down to the third power supply terminal 103 and fixed to L. Therefore, with the voltage fluctuation detection circuit 1, even if the voltage drop detection signal DETF incorrectly outputs H when the voltage at the first power supply terminal 101 rises sharply, false detection will not occur.

[0062] [Operation timing] Figure 4 is a timing chart illustrating an example of the operation of the voltage fluctuation detection circuit 1 according to the first embodiment. Referring to this figure, the changes in the potential of each node when the voltage of the first power supply terminal 101 rises and falls will be explained. Figure 4(A) shows the changes in the potential of each node in the power supply drop detection circuit 10, Figure 4(B) shows the changes in the potential of each node in the false detection prevention circuit 20, and Figure 4(C) shows the changes in the potential of the voltage drop detection signal DETF and the voltage rise detection signal DETR. Each figure shows the change in voltage over time, with the vertical axis representing voltage and the horizontal axis representing time. The horizontal axis time [time] is common to Figures 4(A), 4(B), and 4(C). In Figures 4(A) and 4(B), the voltage [V] on the vertical axis represents the voltage as an analog value. In Figure 4(C), the voltage [Vlogic] on the vertical axis represents the voltage as a digital value (H or L).

[0063] First, let's explain the operation when the voltage at the first power supply terminal 101 rises. Before time t1, the voltage at the first power supply terminal 101 is 0. From time t1 to time t2, the voltage at the first power supply terminal 101 rises from 0 to the first HV power supply voltage level VDDH.

[0064] Referring to Figure 4(A), the changes in the potential of each node in the power supply drop detection circuit 10 will be explained. The figure shows the potential of node A, the potential of the second power supply terminal 102, the potential of node PG1, the potential of node BG1, and the potential of the first power supply terminal 101. When the potential of the first power supply terminal 101 rises at time t1, the potentials of the second power supply terminal 102, node PG1, and node BG1 also rise. As a result of the rise in potential, the potential of the first power supply terminal 101 is fixed at the first HV power supply voltage level VDDH, the potential of the second power supply terminal 102 is fixed at the LV power supply voltage level VREG, and the potential of node PG1 is fixed at potential VPG1H. The potential of node BG1 is fixed at a potential that is smaller than the first HV power supply voltage level VDDH, which is the potential of the first power supply terminal 101, by the source-bulk voltage VSB of transistor 64.

[0065] Here, because the bulk of transistor 64 has a resistor 21 and a parasitic diode 22, the bulk of transistor 64 falls later than the source, and transistor 64 turns off. The period during which transistor 64 is off is based on the time constant determined by the resistor 21 and the parasitic diode 22. Because transistor 64 is off, the potential of node A is pulled down by the load 62 and becomes L. Because node A is L, L is input to inverter 31, and inverter 31 outputs H. Therefore, as shown in Figure 4(C), the voltage drop detection signal DETF becomes H.

[0066] After a predetermined time has elapsed, the bulk potential of transistor 64 rises, and when transistor 64 turns on, the potential of node A becomes the voltage divided by transistor 64 and load 62 again, and the potential of node A becomes H. Because node A becomes H, H is input to inverter 31, and inverter 31 outputs L. Therefore, as shown in Figure 4(C), the voltage drop detection signal DETF becomes L.

[0067] Referring to Figure 4(B), the changes in the potential of each node in the false detection prevention circuit 20 will be explained. The figure shows the potential of node C, node D, node E, the potential of the second power supply terminal 102, the potential of node PG2, the potential of node BG2, and the potential of the first power supply terminal 101. When the potential of the first power supply terminal 101 rises at time t1, the potentials of the second power supply terminal 102, node PG2, and node BG2 also rise. As a result of the rise in potential, the potential of the first power supply terminal 101 is fixed at the first HV power supply voltage level VDDH, the potential of the second power supply terminal 102 is fixed at the LV power supply voltage level VREG, and the potential of node PG2 is fixed at potential VPG2H. The potential of node BG2 is fixed at a potential that is smaller than the first HV power supply voltage level VDDH, which is the potential of the first power supply terminal 101, by the source-bulk voltage VSB of transistor 44.

[0068] Here, during the period from time t1 to time t2, the potential of node C rises. Since node C is clamped by transistors 46 and 47, it is fixed at the clamp voltage VCLAMP. As node C changes sharply, capacitor 26 is charged. As a result of the charge in capacitor 26, the potential of node D rises along with the rise in the potential of node C until the potential of node C reaches the clamp voltage VCLAMP. When the change in node C stops, the charge stored in capacitor 26 is discharged to the third power supply terminal 103 via transistor 48.

[0069] During the period from time t1 to time t2, the potential of node E rises once, but as charge is accumulated in capacitor 26, the potential of node D rises to the operating voltage of transistor 50, causing transistor 50 to turn on, and the potential of node E becomes L. When the potential of node E becomes L, L is input to inverter 32, and inverter 32 outputs H. That is, as shown in Figure 4(C), as the potential of the first power supply terminal 101 rises sharply, the voltage rise detection signal DETR becomes H.

[0070] Returning to Figure 4(B), the potential of node C is fixed at the clamp voltage VCLAMP, so the charge stored in capacitor 26 is discharged to the third power supply terminal 103 via transistor 48, and the potential of node D gradually decreases. The time constant for the discharge of node D is determined by the resistance components of capacitor 26 and transistor 48. When the potential of node D decreases and falls below the operating voltage of transistor 50, transistor 50 turns off, node E is pulled up to the second power supply terminal 102 by transistor 49, and the potential of node E becomes H. When the potential of node E becomes H, H is input to inverter 32, and inverter 32 outputs L. That is, as shown in Figure 4(C), after the potential of the first power supply terminal 101 rises sharply, the voltage rise detection signal DETR becomes L after a predetermined time has elapsed. This predetermined time, which is the pulse width of the voltage rise detection signal DETR, is determined by the time constant for the discharge of node D.

[0071] Next, the operation when the voltage of the first power supply terminal 101 drops will be described. Between time t3 and time t4, the voltage of the first power supply terminal 101 drops from the first HV power supply voltage level VDDH to the second HV power supply voltage level VDDL.

[0072] Referring to Figure 4(A), the changes in the potential of each node in the power supply drop detection circuit 10 will be explained. When the potential of the first power supply terminal 101 decreases at time t3, the potentials of node PG1 and node BG1 also decrease. As a result of the decrease in potential, the potential of the first power supply terminal 101 and node BG1 are fixed at the second HV power supply voltage level VDDL. The potential of node PG1 is fixed at a potential VPG1L which is less than the second HV power supply voltage level VDDL, which is the potential of the first power supply terminal 101, by the source-gate voltage VSG of transistor 64.

[0073] Here, because the bulk of transistor 64 has a resistor 21 and a parasitic diode 22, the bulk of transistor 64 falls later than the source, and transistor 64 turns off. The period during which transistor 64 is off is based on the time constant determined by the resistor 21 and the parasitic diode 22. Because transistor 64 is off, the potential of node A is pulled down by the load 62 and becomes L. Because node A is L, L is input to inverter 31, and inverter 31 outputs H. Therefore, as shown in Figure 4(C), the voltage drop detection signal DETF becomes H.

[0074] After a predetermined time has elapsed, the bulk potential of transistor 64 rises, and when transistor 64 turns on, the potential of node A becomes the voltage divided by transistor 64 and load 62 again, and the potential of node A becomes H. Because node A becomes H, H is input to inverter 31, and inverter 31 outputs L. Therefore, as shown in Figure 4(C), the voltage drop detection signal DETF becomes L.

[0075] Referring to Figure 4(B), the changes in the potential of each node in the false detection prevention circuit 20 will be explained. When the potential of the first power supply terminal 101 decreases at time t3, the potentials of node PG2 and node BG2 also decrease. As a result of the decrease in potential, the potential of the first power supply terminal 101 and node BG2 are fixed at the second HV power supply voltage level VDDL. The potential of node PG2 is fixed at a potential VPG2L which is less than the second HV power supply voltage level VDDL, which is the potential of the first power supply terminal 101, by the source-gate voltage VSG of transistor 44.

[0076] When the voltage at the first power supply terminal 101 drops, the transistor 44 turns off due to the resistor 23 and the parasitic diode 24, but since the potential at node C is already at the L level, the potential at node C does not change. In other words, when the voltage at the first power supply terminal 101 drops, the voltage rise detection signal DETR does not change and remains L.

[0077] [Summary of the First Embodiment] According to the embodiment described above, the voltage fluctuation detection circuit 1 includes a power supply drop detection circuit 10 to detect a drop in the voltage at the first power supply terminal 101, and outputs the detected result as a voltage drop detection signal DETF at a voltage lower than the voltage at the first power supply terminal 101. It also includes a false detection prevention circuit 20 to detect an increase in the voltage at the first power supply terminal 101, and outputs the detected result as a voltage increase detection signal DETR at a voltage lower than the voltage at the first power supply terminal 101. The transistor 30 disables the output of the voltage drop detection signal DETF during the period when an increase in the voltage at the first power supply terminal 101 is detected based on the voltage increase detection signal DETR. Therefore, according to this embodiment, even if the power supply drop detection circuit 10 mistakenly outputs the voltage drop detection signal DETF, such as when the power supply is started up, the false detection prevention circuit 20 can suppress the false detection.

[0078] In conventional methods, detecting battery voltage fluctuations required the use of devices such as thick-film transistors (high-voltage semiconductor devices) with high gate breakdown voltage. However, using thick-film transistors necessitated the use of manufacturing processes for thick films, resulting in higher costs compared to thin-film transistors. Furthermore, using thick-film transistors made it more difficult to obtain the desired electrical characteristics compared to thin-film transistors (low-voltage semiconductor devices).

[0079] According to the first embodiment described above, the power supply drop detection circuit 10 is configured with the circuit shown in Figure 2, and transistors 63, 64, and 65 are all thin-film transistors (low-voltage semiconductor elements). In other words, the power supply drop detection circuit 10 detects voltage fluctuations in the 12V system without using thick-film transistors (high-voltage semiconductor elements). Therefore, according to this embodiment, since a thick-film process is not used, it can be manufactured at a low cost. Furthermore, according to this embodiment, since a thick-film process is not used, the range of processes that can be used to manufacture the power supply drop detection circuit 10 is broadened, and the degree of freedom in process selection can be increased.

[0080] Furthermore, according to the first embodiment described above, the false detection prevention circuit 20 uses the capacitance component of a parasitic diode to determine the time constant of the transistor 64. Therefore, according to this embodiment, since high-voltage capacitance is not used, the power supply drop detection circuit 10 can be manufactured without using a thick-film process. Thus, cost reduction and freedom of process selection can be increased.

[0081] Furthermore, according to the first embodiment described above, the false detection prevention circuit 20 is configured with the circuit shown in Figure 3, and transistors 43, 44, and 45 are all thin-film transistors (low-voltage semiconductor elements). In other words, the false detection prevention circuit 20 detects voltage fluctuations in the 12V system without using thick-film transistors (high-voltage semiconductor elements). Therefore, according to this embodiment, since a thick-film process is not used, it can be manufactured at a low cost. In addition, according to this embodiment, since a thick-film process is not used, the range of processes that can be used to manufacture the false detection prevention circuit 20 is broadened, and the degree of freedom in process selection can be increased.

[0082] Furthermore, according to the first embodiment described above, the false detection prevention circuit 20 is configured with the circuit shown in Figure 3. That is, the false detection prevention circuit 20 includes a capacitor 25 to block the DC component, extracts only the signal component when the potential of the first power supply terminal 101 rises, and determines the period for turning on the transistor 50 using the transistor 48 and the capacitor 26. Therefore, the false detection prevention circuit 20 can output a pulse for a predetermined period when the potential of the first power supply terminal 101 rises, and even if the power supply drop detection circuit 10 falsely detects that the potential of the first power supply terminal 101 has risen, the output can be disabled. In addition, since none of the capacitor elements and transistors in the false detection prevention circuit 20 use a thick-film process, the range of processes that can be used to manufacture the false detection prevention circuit 20 is broadened, and the degree of freedom in process selection is increased.

[0083] Furthermore, according to the first embodiment described above, the resistance value is set such that the voltage obtained by dividing the voltage at the first power terminal 101 by the transistor 64 and the load 62 is higher than the voltage obtained by dividing the voltage at the first power terminal 101 by the transistor 44 and the load 42. Therefore, when the power supply drop detection circuit 10 does not detect a drop in the voltage at the first power terminal 101, the potential at node A is high and the potential at node C is low. Thus, according to this embodiment, it is possible to detect abrupt changes in the voltage at the first power terminal 101.

[0084] [Second Embodiment] [Circuit configuration of the power supply drop detection circuit] Figure 5 is a circuit diagram showing an example of the circuit configuration of the power supply drop detection circuit 10a according to the second embodiment. A detailed example of the circuit configuration of the power supply drop detection circuit 10a will be described with reference to Figure 5. The power supply drop detection circuit 10a includes a load 81, a load 82, a transistor 68, a resistor 71, a resistor 72, a capacitor 73, and a capacitor 74.

[0085] The first power terminal 101 shown in Figure 5 is an example of a power terminal connected to the power supply (first power supply) that is the target of detection by the voltage fluctuation detection circuit 1, and the second power terminal 102 is an example of a power terminal connected to the logic power supply (second power supply) used for signal processing. The third power terminal 103 is, for example, the ground potential or the negative power supply potential. Therefore, the first power terminal 101 and the second power terminal 102 use the third power terminal 103 as a common reference potential.

[0086] The connection of the power supply drop detection circuit 10a will now be described. The first terminal of resistor 71 is connected to the first power supply terminal 101. The second terminal of resistor 71 is connected to the first terminal of resistor 72 and the first terminal of capacitor 73 via node F. The second terminal of capacitor 73 is connected to the load 81, the first terminal of capacitor 74, and the gate terminal of transistor 68 via node G. The source terminal of transistor 68 is connected to the second power supply terminal 102. The drain terminal of transistor 68 is connected to the load 82. Transistor 68 is an enhancement-type P-channel MOS transistor that outputs a voltage drop detection signal DETF from its drain terminal. The second terminal of resistor 72 and the second terminal of capacitor 74 are connected to the third power supply terminal 103.

[0087] Loads 81 and 82 are current source loads. Loads 81 and 82 have depletion-type N-channel MOS transistors. The depletion-type N-channel MOS transistor of load 81 has its drain terminal connected to the second power supply terminal 102, its gate and source terminals connected to node G, and its bulk connected to the third power supply terminal 103. Load 81 operates to charge capacitance 74 and hold node G at H. The depletion-type N-channel MOS transistor of load 82 has its drain terminal connected to the drain terminal of transistor 68, and its gate, source, and bulk terminals connected to the third power supply terminal 103. Load 82 operates to hold the drain terminal of transistor 68 at L.

[0088] The operation of the power supply drop detection circuit 10a will now be explained. Resistors 71 and 72 divide and step down the first power supply voltage at the first power supply terminal 101. Capacitors 73 and 74 operate as DC blocking capacitances.

[0089] Here, the voltage at the first power supply terminal 101 is 28V at its maximum, the voltage at the second power supply terminal 102 is 3.6V, each transistor is a thin-film transistor (low-voltage semiconductor element) with a thin gate film thickness, and the dielectric breakdown voltage of the gate terminal of each transistor is 3.6V. If the voltage division ratio of resistors 71 and 72 is 9:1, then a maximum voltage of 2.8V is applied to the gate terminal of each transistor. Node G is DC-disconnected from node F by capacitor 73. Node G is held high by load 81. Since high is input to the gate terminal of transistor 68, it outputs a low voltage detection signal DETF from its drain terminal.

[0090] Assume the voltage at the first power supply terminal 101 drops sharply. A sharp voltage fluctuation signal is transmitted from node F, which divides the voltage at the first power supply terminal 101 using resistors 71 and 72, to node G via capacitor 73, causing node G to change from H to L. Transistor 68 turns on, and the drain terminal of transistor 68 outputs a voltage drop detection signal DETF of H. The voltage at node G, which has changed to L, changes back to H as the load 81 charges capacitor 74. When node G becomes H, transistor 68 turns off again, and the drain terminal of transistor 68 outputs a voltage drop detection signal DETF of L.

[0091] [Circuit configuration of the false detection prevention circuit] Figure 6 is a circuit diagram showing an example of the circuit configuration of the false detection prevention circuit 20a according to the second embodiment. A detailed example of the circuit configuration of the false detection prevention circuit 20a will be described with reference to Figure 6. The false detection prevention circuit 20a includes a load 83, a load 84, a transistor 69, an inverter 33, a resistor 75, a resistor 76, a capacitor 77, and a capacitor 78.

[0092] The first power terminal 101 shown in Figure 6 is an example of a power terminal connected to the power supply (first power supply) that is the target of detection by the voltage fluctuation detection circuit 1, and the second power terminal 102 is an example of a power terminal connected to the logic power supply (second power supply) used for signal processing. The third power terminal 103 is, for example, the ground potential or the negative power supply potential. Therefore, the first power terminal 101 and the second power terminal 102 use the third power terminal 103 as a common reference potential.

[0093] The connection of the false detection prevention circuit 20a will now be described. The first terminal of resistor 75 is connected to the first power supply terminal 101. The second terminal of resistor 75 is connected to the first terminal of resistor 76 and the first terminal of capacitor 77 via node J. The second terminal of capacitor 77 is connected to the load 83, the first terminal of capacitor 78, and the gate terminal of transistor 69 via node K. The drain terminal of transistor 69 is connected to the load 84 and the input terminal of inverter 33 via node M. The source terminal and bulk of transistor 69 are connected to the third power supply terminal 103. Transistor 69 is an enhancement-type N-channel MOS transistor that outputs a voltage rise detection signal DETR from its drain terminal via node M and inverter 33. The second terminal of resistor 76 and the second terminal of capacitor 78 are connected to the third power supply terminal 103. The power supply terminal of inverter 33 is connected to the second power supply terminal 102. Inverter 33 outputs a voltage rise detection signal DETR from its output terminal.

[0094] Loads 83 and 84 are current source loads. Loads 83 and 84 have depletion-type N-channel MOS transistors. The depletion-type N-channel MOS transistor of load 83 has its drain terminal connected to node K, and its gate terminal, source terminal and bulk are connected to the third power supply terminal 103. Load 83 operates by discharging a charge of capacitance 78 and holding node K at L. The depletion-type N-channel MOS transistor of load 84 has its drain terminal connected to the second power supply terminal, its gate terminal and source terminal are connected to node M, and its bulk is connected to the third power supply terminal 103. Load 84 operates by holding node M at H.

[0095] The operation of the false detection prevention circuit 20a will now be explained. Resistors 75 and 76 divide and step down the first power supply voltage at the first power supply terminal 101. Capacitors 77 and 78 operate as DC blocking capacitances.

[0096] Here, the voltage at the first power supply terminal 101 is 28V at its maximum, the voltage at the second power supply terminal 102 is 3.6V, each transistor is a thin-film transistor (low-voltage semiconductor element) with a thin gate film thickness, and the dielectric breakdown voltage of the gate terminal of each transistor is 3.6V. If the voltage division ratio of resistors 75 and 76 is 9:1, then a maximum voltage of 2.8V is applied to the gate terminal of each transistor. Node K is DC-disconnected from node J by capacitor 77. In the steady state, node J is held at L by load 83. Since L is input to the gate terminal of transistor 69, the drain terminal is held at H. The inverter 33 connected from the drain terminal via node M outputs a voltage rise detection signal DETR from its output terminal.

[0097] Assume the voltage at the first power supply terminal 101 rises sharply to 28V (maximum operating voltage). A sharp voltage fluctuation signal is transmitted from node K, which divides the voltage at the first power supply terminal 101 using resistors 75 and 76, to node K via capacitor 77, causing node K to change from L to H. Transistor 69 turns on, and node M changes from H to L. Inverter 33 outputs a voltage rise detection signal DETR of H. The voltage at node K, which has changed to H, changes back to L as the load 83 discharges capacitor 78. When node K becomes L, transistor 69 turns off again, and node M changes from L to H. Inverter 33 outputs a voltage rise detection signal DETR of L.

[0098] According to the second embodiment described above, the power supply drop detection circuit 10a is configured with the circuit shown in Figure 5, and the transistors constituting load 81, load 82, and transistor 68 are all thin-film transistors (low-voltage semiconductor elements). In other words, the power supply drop detection circuit 10a detects voltage fluctuations in the 12V system without using thick-film transistors (high-voltage semiconductor elements). Therefore, according to this embodiment, since a thick-film process is not used, it can be manufactured at a low cost. Furthermore, according to this embodiment, since a thick-film process is not used, the range of processes that can be used to manufacture the power supply drop detection circuit 10a is broadened, and the degree of freedom in process selection can be increased.

[0099] Furthermore, according to the second embodiment described above, the false detection prevention circuit 20a is configured with the circuit shown in Figure 6, and the transistors constituting load 83, load 84, and transistor 69 are all thin-film transistors (low-voltage semiconductor elements). In other words, the false detection prevention circuit 20a detects voltage fluctuations in the 12V system without using thick-film transistors (high-voltage semiconductor elements). Therefore, according to this embodiment, since a thick-film process is not used, it can be manufactured at a low cost. In addition, according to this embodiment, since a thick-film process is not used, the range of processes that can be used to manufacture the false detection prevention circuit 20a is broadened, and the degree of freedom in process selection can be increased.

[0100] Although embodiments for carrying out the present invention have been described above using examples, the present invention is not limited in any way to these embodiments, and various modifications and substitutions can be made without departing from the spirit of the present invention. [Explanation of Symbols]

[0101] 1…Voltage fluctuation detection circuit 10, 10A... Power supply low detection circuit 20, 20a... False detection prevention circuit 30… Transistors DETF…Drop-of-Fault Detector Signal DETR… Voltage rise detection signal 101...First power terminal (first power voltage, HV power voltage) 102...Second power terminal (second power voltage, LV power voltage) 103...Third power terminal (Third power voltage, VSS) 41, 42, 61, 62, 81, 82, 83, 84… Load 43, 44, 45, 46, 47, 48, 49, 50, 63, 64, 65, 66, 67, 68, 69… Transistors 21, 23, 71, 72, 75, 76… Resistor 22, 24... Parasitic diodes 31, 32, 33… Inverter 25, 26, 73, 74, 77, 78…capacity A, C, D, E, F, G, J, K, M, PG1, PG2, BG1, BG2...Node

Claims

1. A power supply voltage drop detection circuit that detects a voltage drop in a first power supply that outputs a first voltage, and outputs the detected result as a voltage drop detection signal by a second voltage of a second power supply that is lower than the voltage of the first power supply; An error detection prevention circuit that detects an increase in the voltage of the first power supply, and outputs the detected result as a voltage increase detection signal by the second voltage; A mask circuit that invalidates the output of the voltage drop detection signal during a period in which an increase in the voltage of the first power supply is detected based on the voltage increase detection signal; A voltage fluctuation detection circuit comprising the same.

2. The voltage fluctuation detection circuit according to claim 1, wherein the mask circuit includes a first transistor having a gate connected to the error detection prevention circuit, a drain connected to the power supply voltage drop detection circuit, and a source connected to a third power supply.

3. The power supply voltage drop detection circuit includes: A second transistor having a source and a back gate connected to the first power supply, and a gate and a drain connected to each other; A third transistor having a gate connected to a connection point between the gate and the drain of the second transistor, a source connected to the first power supply, a drain connected to an input terminal of an inverter and a first clamp circuit, and a back gate connected to a second clamp circuit and the first power supply via a first resistor; The voltage fluctuation detection circuit according to claim 1, further comprising the inverter driven by the second power supply and outputting the voltage drop detection signal.

4. The second clamp circuit clamps the back gate voltage of the third transistor so that it does not deviate from the voltage of the first power supply by a predetermined voltage or more. The first clamp circuit clamps the input voltage of the inverter so that it does not deviate from the voltage of the third power supply by a predetermined voltage or more. The voltage fluctuation detection circuit according to claim 3.

5. The error detection prevention circuit includes: A fourth transistor having a source and a back gate connected to the first power supply, and a gate and a drain connected to each other; A fifth transistor having a gate connected to a connection point between the gate and the drain of the fourth transistor, a source connected to the first power supply, a drain connected to the gate of a fifth transistor via a first capacitor, and a back gate connected to a third clamp circuit and the first power supply via a second resistor. The third clamping circuit includes a sixth transistor in which a gate and a drain are connected to each other, a source and a bulk are connected to each other, and a connection point of the source and the bulk is connected to the gate of the fourth transistor and the gate of the fifth transistor. The voltage fluctuation detection circuit according to claim 1.

6. The third clamping circuit clamps such that a back gate voltage of the fifth transistor does not deviate from the voltage of the first power supply by a predetermined voltage or more. The voltage fluctuation detection circuit according to claim 5.

7. The power supply drop detection circuit includes a third resistor having a first terminal connected to the first power supply, a second terminal connected to the first terminal of the fourth resistor and the first terminal of the third capacitor; the fourth resistor having a second terminal connected to the third power supply; the third capacitor having a second terminal connected to the gate of the seventh transistor; and the seventh transistor having a source terminal connected to the second power supply and outputting the voltage drop detection signal from a drain terminal. The voltage fluctuation detection circuit according to claim 1.

8. The false detection prevention circuit includes a fifth resistor having a first terminal connected to the first power supply, a second terminal connected to the first terminal of the sixth resistor and the first terminal of the fifth capacitor; the sixth resistor having a second terminal connected to the third power supply; the fifth capacitor having a second terminal connected to the gate of the eighth transistor; and the eighth transistor having a drain terminal connected to an input terminal of an inverter and a source terminal connected to the third power supply. The voltage fluctuation detection circuit according to claim 1.

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