Semiconductor device, method for manufacturing semiconductor device, apparatus, substrate, and method for manufacturing substrate

Abstract

To improve the protection characteristics of a protection circuit, while preventing an increase in the chip area.SOLUTION: A semiconductor device comprises: a semiconductor layer that has a first surface and a second surface, and is provided with a semiconductor element and a protection circuit between the first surface and the second surface; and wiring layers that are arranged on the first surface, and are electrically connected with the protection circuit. The semiconductor device includes a first heat dissipation layer that is arranged between the semiconductor layer and the wiring layer in most proximity to the semiconductor layer, and is not electrically connected with the protection circuit. In plan view of the first surface, the first heat dissipation layer is arranged at a position overlapping at least part of the protection circuit.SELECTED DRAWING: Figure 10

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, a method for manufacturing a semiconductor device, an apparatus, a substrate, and a method for manufacturing a substrate. [Background technology]

[0002] In the field of semiconductors such as memories and image sensors, semiconductor devices equipped with protection circuits are known. Patent Document 1 proposes a device configuration that reduces contact resistance by increasing the ground area between the protection circuit and the contact layer. Such a device configuration is expected to improve heat dissipation and the protection characteristics of the protection circuit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2010-165737 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, the photoelectric conversion device described in Patent Document 1 has a problem in that the chip area increases with an increase in the contact area between the protection circuit and the contact layer.

[0005] The present invention has been made in consideration of the above problems, and has an object to provide a semiconductor device including a protection circuit with improved protection characteristics while suppressing an increase in chip area. [Means for solving the problem]

[0006] According to one disclosure of the present specification, there is provided a semiconductor device comprising: a semiconductor layer having a first surface and a second surface, with a semiconductor element and a protection circuit provided between the first surface and the second surface; and a wiring layer arranged on the first surface side and electrically connected to the protection circuit, wherein the semiconductor device further comprises a first heat dissipation layer arranged between the wiring layer closest to the semiconductor layer and the semiconductor layer and not electrically connected to the protection circuit, and wherein, in a planar view of the first surface side, the first heat dissipation layer is arranged in a position overlapping at least a portion of the protection circuit. Effect of the Invention

[0007] According to the present invention, in a semiconductor device including a protection circuit, it is possible to provide a protection circuit with improved protection characteristics while suppressing an increase in chip area. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view illustrating a semiconductor device; [Diagram 2] A block diagram illustrating a protection circuit in a semiconductor device. [Diagram 3] A block diagram illustrating a protection circuit in a semiconductor device. [Figure 4] A circuit diagram illustrating a protection circuit in a semiconductor device. [Diagram 5] A circuit diagram illustrating a protection circuit in a semiconductor device. [Figure 6] A circuit diagram illustrating a protection circuit in a semiconductor device. [Figure 7] 1 is a cross-sectional view illustrating a semiconductor device; [Figure 8] FIG. 1 is a plan view illustrating a semiconductor device; [Figure 9] 1 is a cross-sectional view illustrating a semiconductor device; [Figure 10] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to a first embodiment. [Figure 11] FIG. 1 is a plan view illustrating a semiconductor device according to a first embodiment; [Figure 12] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to a first embodiment. [Figure 13]FIG. 1 is a plan view illustrating a semiconductor device according to a first embodiment; [Figure 14] FIG. 1 is a plan view illustrating a semiconductor device according to a first embodiment; [Figure 15] FIG. 1 is a plan view illustrating a semiconductor device according to a first embodiment; [Figure 16] FIG. 1 is a plan view illustrating a semiconductor device according to a first embodiment; [Figure 17] FIG. 1 is a plan view illustrating a semiconductor device according to a first embodiment; [Figure 18] FIG. 1 is a plan view illustrating a semiconductor device according to a first embodiment; [Figure 19] FIG. 1 is a plan view illustrating a semiconductor device according to a first embodiment; [Figure 20] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to a first embodiment. [Figure 21] FIG. 11 is a cross-sectional view illustrating a semiconductor device according to a second embodiment. [Figure 22] FIG. 11 is a cross-sectional view illustrating a semiconductor device according to a second embodiment. [Diagram 23] FIG. 11 is a cross-sectional view illustrating a semiconductor device according to a third embodiment. [Figure 24] FIG. 11 is a plan view illustrating a semiconductor device according to a third embodiment. [Diagram 25] FIG. 11 is a plan view illustrating a semiconductor device according to a third embodiment. [Figure 26] FIG. 11 is a cross-sectional view illustrating a semiconductor device according to a third embodiment. [Figure 27] FIG. 13 is a cross-sectional view illustrating a semiconductor device according to a fourth embodiment. [Figure 28] FIG. 13 is a cross-sectional view illustrating a semiconductor device according to a fourth embodiment. [Figure 29] FIG. 13 is a cross-sectional view illustrating a semiconductor device according to a fifth embodiment. [Diagram 30] 3D diagram illustrating a heat dissipation layer according to the fifth embodiment [Diagram 31] FIG. 13 is a schematic diagram illustrating a device according to a sixth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Each embodiment will be described below with reference to the drawings. Note that the following embodiments do not limit the invention according to the claims. Although a plurality of features are described in the embodiments, not all of these features are necessarily essential to the invention, and the plurality of features may be combined in any manner. Furthermore, in the attached drawings, the same or similar configurations are given the same reference numbers, and duplicated descriptions are omitted. Furthermore, in each embodiment described below, a CMOS sensor will be mainly described as an example of a photoelectric conversion device. However, each embodiment is not limited to a CMOS sensor, and can be applied to other examples of photoelectric conversion devices. For example, there are CCDs, imaging devices, distance measuring devices (devices for distance measurement using focus detection or TOF (Time Of Flight)), photometric devices (devices for measuring the amount of incident light, etc.), etc.

[0010] In this specification, terms indicating specific directions or positions (for example, "upper", "lower", "right", "left" and other terms including these terms) are used as necessary. The use of these terms is for the purpose of facilitating understanding of the embodiments with reference to the drawings, and the technical scope of the present invention is not limited by the meaning of these terms.

[0011] In the following description, the substrate will be described as including not only the semiconductor layer, but also an insulating film and a wiring layer provided on the semiconductor layer.

[0012] In this specification, the phrase "electrically connecting component A and component B" does not necessarily mean that component A and component B are directly connected to each other. For example, even if another component C is connected between component A and component B, it is sufficient that they are electrically connected to each other.

[0013] In this specification, the term "plane" refers to a surface in a direction parallel to the main surface of a semiconductor substrate. The main surface of a semiconductor substrate may be a light incident surface of a semiconductor substrate including a photoelectric conversion unit, a surface on which a plurality of ADCs are repeatedly arranged, or a bonding surface between substrates in a stacked photoelectric conversion device. In addition, the term "planar view" refers to a view from a direction perpendicular to the main surface of the semiconductor substrate. In addition, the term "cross section" refers to a surface in a direction perpendicular to the light incident surface of the semiconductor layer. In addition, the term "cross section" refers to a view from a direction parallel to the main surface of the semiconductor substrate.

[0014] Metallic members such as wiring and pads described in this specification may be composed of a single metal element or may be a mixture (alloy). For example, wiring described as copper wiring may be composed of a single copper element or may be composed mainly of copper and further contain other components. Also, for example, a pad connected to an external terminal may be composed of a single aluminum element or may be composed mainly of aluminum and further contain other components. The copper wiring and aluminum pads shown here are examples and can be changed to various metals. Also, the wiring and pads shown here are examples of metallic members used in semiconductor devices and can be applied to other metallic members.

[0015] A configuration common to each embodiment of the semiconductor device according to the present invention will be described with reference to FIGS. 1 to 9. FIG.

[0016] 1 is an example of a plan view of a semiconductor device 111. The semiconductor device 111 has a first pad 100, a first protection circuit 101, and a semiconductor element .

[0017] The first pad 100 may be a pad for outputting a signal generated within the semiconductor device 111 to the outside, or may be a pad for inputting a voltage or the like supplied from the outside to drive the circuitry of the semiconductor device 111.

[0018] A plurality of first pads 100 and first protection circuits 101 are disposed in the semiconductor device 111, but they do not need to have the same configuration, and they do not need to be electrically connected to each other. In addition, in Fig. 1, the first protection circuits are disposed between the first pads 100 in order to increase the area of ​​the semiconductor element 102, but they may be disposed between the first pads 100 and the semiconductor element 102.

[0019] Here, the first pad 100 includes, for example, a second pad 100A and a third pad 100B, which will be described later. Also, the first protection circuit 101 includes, for example, a second protection circuit 101A and a third protection circuit 101B, which will be described later.

[0020] 2 is an example of a block diagram showing a second protection circuit 101A in the semiconductor device 111. The semiconductor device 111 according to the first embodiment has a second pad 100A, a second protection circuit 101A, a semiconductor element 102, a first reference potential line 103A, and a second reference potential line 103B.

[0021] The second protection circuit 101A is electrically connected to the second pad 100A, the semiconductor element 102, the first reference potential line 103A, and the second reference potential line 103B. The second protection circuit 101A is a circuit for protecting the semiconductor element 102 from external noise such as static electricity and surge voltage input from the second pad 100A. Each protection circuit is configured, for example, by a diode, a Gate Grounded MOS (hereinafter abbreviated as GGMOS), an RC Trigger MOS (hereinafter abbreviated as power clamp MOS transistor), or a combination of these elements. In this specification, a configuration using a diode will be described as an example, but this is merely an example and is not limited to this configuration.

[0022] The first reference potential line 103A and the second reference potential line 103B are wirings to which a reference potential is applied, such as a power supply wiring or a ground wiring. In this specification, the first reference potential line 103A will be described as a power supply wiring (VDD) and the second reference potential line 103B as a ground wiring (GND: ground potential).

[0023] The semiconductor element 102 is, for example, an internal circuit provided within the semiconductor device 111, and may include a driver circuit for amplifying an external signal.

[0024] FIG. 3 is an example of a block diagram showing the third protection circuit 101B in the semiconductor device 111. The third protection circuit 101B is electrically connected to the first reference potential line 103A and the second reference potential line 103B, respectively. The third protection circuit 101B does not affect the operation of the semiconductor device 111 during normal operation. On the other hand, when external noise is input from the second pad 100A that applies a voltage to the first reference potential line 103A, the third protection circuit 101B becomes a path for discharging the external noise to the second reference potential line 103B, and can protect the semiconductor element 102. Also, when external noise is input from the second pad 100A and transmitted to the first reference potential line 103A via the second protection circuit 101A, the third protection circuit 101B becomes a path for discharging the external noise to the second reference potential line 103B, and can protect the semiconductor element 102. Although the semiconductor element 102 is not explicitly shown in FIG. 3, it may be arranged so as to be electrically connected to the first reference potential line 103A, or it may be arranged so as to be electrically connected to the second reference potential line 103B.

[0025] 4 is an example of a circuit diagram of the second protection circuit 101A. When a power supply voltage is applied to the first reference potential line 103A, no current flows through the first diode 104 and the second diode 105, except for leakage current. On the other hand, when an excessively positive voltage is applied to the second pad 100A due to electrostatic discharge, a current flows through the first diode 104 to the first reference potential line 103A. When an excessively negative voltage is applied to the second pad 100A, a current flows through the second diode 105 to the second reference potential line 103B. This operation makes it possible to suppress the destruction of the semiconductor element 102 due to electrostatic discharge.

[0026] FIG. 5 is a diagram showing an example of the circuit diagram of the second protection circuit 101A different from that of FIG. 4. The difference from FIG. 4 is that an N-type GGMOS 106 is arranged instead of the second diode 105. The GGMOS 106 has the same structure as a normal MOS transistor, but has a structure in which the gate and source are shorted and connected to GND. In addition, the drain is connected to the second pad 100A, the first diode 104, and the semiconductor element 102. When a voltage is applied to the drain of the GGMOS 106, no current flows until a specific voltage is exceeded, and when the specific voltage is exceeded, a current flows (snapback operation).

[0027] In Fig. 4, when a negative voltage is applied to the second pad 100A during normal operation of the semiconductor device 111, a current flows to GND via the second diode 105, which may cause an increase in current consumption or a malfunction. In the second protection circuit 101A of Fig. 5, even when a negative voltage is applied to the second pad 100A during normal operation, no current flows through the GGMOS, and the influence on the normal operation of the semiconductor device 111 can be suppressed compared to the second protection circuit 101A of Fig. 4. Here, in Fig. 5, the first diode 104 may be replaced with a GGMOS. In addition to the circuit elements shown in Fig. 5, for example, circuit elements such as resistors and capacitors may be provided.

[0028] FIG. 6 is an example of a circuit diagram of the third protection circuit 101B. The third protection circuit 101B includes a power clamp MOS transistor. The power clamp MOS transistor includes a series circuit (RC series circuit) of a resistive element 108 and a capacitive element 109 provided between the first reference potential line 103A and the second reference potential line 103B, and a CMOS inverter 110 having an input terminal connected to a connection point between the resistive element and the capacitive element. The output terminal of the CMOS inverter 110 is connected to the gate electrode of the MOS transistor 107. In FIG. 5, the CMOS inverter 110 is illustrated as a single stage, but may be connected in multiple stages. Also, an N-type MOS transistor is illustrated as the MOS transistor 107, but a P-type MOS transistor may be connected.

[0029] The operation of the power clamp MOS transistor will be described below. When an excessively large positive voltage is applied to the first reference potential line 103A due to electrostatic discharge, the potential of the inverter input terminal becomes lower than the potential of the first reference potential line 103A within the time period of the time constant R×C of the RC series circuit. As a result, the potential of the output terminal of the inverter 110 becomes the Hight level, and the MOS transistor 107 is turned on. On the other hand, during normal operation, the input terminal of the CMOS inverter becomes the Hight level, the output terminal becomes the Low level, and the MOS transistor 107 is turned off. In this way, the power clamp MOS transistor does not affect the normal operation of the semiconductor device 111, and the MOS transistor 107 turns on only during electrostatic discharge to release the charge.

[0030] Fig. 7 is an example of a cross-sectional view of a semiconductor device 111 taken along dashed line A-A' shown in Fig. 1. The semiconductor device 111 has a first pad 100, a first wiring layer 113, a second wiring layer 114, a contact layer 118, a first via layer 119, and a semiconductor member 112.

[0031] The semiconductor member 112 has a semiconductor layer 201. The semiconductor layer 201 has a first surface 202 and a second surface 203, and has a first protective circuit 101, a semiconductor element 102, and an element isolation region 120 between the first surface 202 and the second surface 203. Here, the first protective circuit 101 includes at least a part of the element isolation region 120. Note that the semiconductor member 112 is generally made of silicon, but may be a semiconductor member made of a compound including a plurality of elements.

[0032] A contact layer 118, a first wiring layer 113, a first via layer 119, and a second wiring layer 114 are provided on the first surface 202 in that order, going away from the first surface 202. The contact layer 118 electrically connects the first protection circuit 101 and the first wiring layer 113, and the first via layer 119 electrically connects the first wiring layer 113 and the second wiring layer 114.

[0033] The first pad 100 mainly contains a metal such as aluminum, and the first wiring layer 113 and the second wiring layer 114 mainly contain a metal such as copper or cobalt.

[0034] 7, only the second wiring layer is shown, and the first pad 100 is open on the second wiring layer 114, but this is not limited to the configuration. The semiconductor device 111 may include wiring layers other than those shown in Fig. 7, but among the multiple wiring layers, the first wiring layer 113 is closest to the semiconductor layer 201. In Fig. 7, the first pad 100 is provided on the first surface 202 side, but it may be provided on the second surface 203 side.

[0035] Fig. 8 is an example of a plan view of the periphery of the first protection circuit 101 in Fig. 7. In Fig. 8, the upper layers above the first wiring layer 113 shown in Fig. 7 are omitted. The first protection circuit 101 has an N-type activation region 116, a P-type activation region 117, and an element isolation region 120. Note that Fig. 8 merely illustrates a general N-type diode, and does not limit the configuration of the protection circuit.

[0036] FIG. 9 is an example of a cross-sectional view of the first protection circuit 101 and its periphery taken along the dashed line BB' in FIG. 8. FIG. 9 shows an example in which an N-type structure is used as the semiconductor member 112, and the first protection circuit 101 has a P-type well region 115. The P-type well region 115 is formed on the N-type structure, and an N-type activation region 116 and a P-type activation region 117 are formed therein. The first protection circuit 101 is electrically connected to the first wiring layer 113 by a contact layer 118. Furthermore, the N-type activation region 116 and the P-type activation region 117 are each isolated by an element isolation region 120. The element isolation region 120 is formed of, for example, STI or LOCOS. A diode is formed between the P-type well region 115 and the N-type activation region 116 formed on the P-type well region 115, and the potential of the P-type well region 115 is applied by the P-type activation region 117.

[0037] In the example shown in FIG. 7, when an overcurrent flows through the first protection circuit 101 due to electrostatic discharge or the like, heat generation and heat accumulation due to the overcurrent in the first protection circuit 101 are conducted in the direction of the element isolation region 120, the direction of the first surface 202, and the direction of the second surface 203. However, if this heat conduction is insufficient, the current conductivity of the first protection circuit 101 decreases with an increase in temperature, and the first protection circuit 101 may not be able to fully exert its protection function. In addition, if excessive heat conduction occurs in the direction of the first surface 202, the wiring layer, via, or contact layer may melt, leading to a malfunction of the semiconductor device 111. In the above example, heat conduction in the direction of the second surface 203 via the element isolation region 120 can be expected. However, if heat conduction in the direction of the second surface 203 via the element isolation region 120 does not occur sufficiently due to the element isolation region 120 being provided on the first surface 202 side, the protection function of the first protection circuit 101 may also be reduced.

[0038] First Embodiment The structure of a semiconductor device 111 according to a first embodiment of the present invention will be described with reference to FIGS.

[0039] Fig. 10 is an example of a cross-sectional view of the semiconductor device 111 according to the first embodiment taken along dashed line A-A' in Fig. 1. This embodiment differs from the example shown in Fig. 7 in that a first heat dissipation layer 121 is provided between the first wiring layer 113 and the semiconductor layer 201. In addition, the first heat dissipation layer 121 is provided at a position overlapping at least a portion of the first protection circuit 101 in a plan view of the first surface 202 side.

[0040] The first heat dissipation layer 121 is not electrically connected to the first protection circuit 101. In this embodiment, the first heat dissipation layer 121 is described as being in an electrically floating state, but it may be fixed to a potential such as VDD or GND as long as it is not a discharge path of the first protection circuit. In order to fix the potential to a potential such as VDD or GND, the first heat dissipation layer 121 may be electrically connected to a pad that is not electrically connected to the first protection circuit 101.

[0041] The first heat dissipation layer 121 includes a conductive material, for example, at least one of a simple metal such as tungsten, copper, aluminum, titanium, cobalt, or nickel, or an alloy containing these metals. The metal element mainly contained in the first heat dissipation layer 121 may be the same as or different from the metal element mainly contained in the first wiring layer 113 and the second wiring layer 114.

[0042] Fig. 11 is an example of a plan view of the periphery of first protection circuit 101 in Fig. 10. In Fig. 11, the upper layers above first wiring layer 113 are omitted. In Fig. 11, first heat dissipation layer 121 is provided so as to cover the entire first protection circuit 101 except for the region of contact layer 118. That is, in a plan view of the first surface 202 side, contact layer 118 is provided inside the region surrounded by first heat dissipation layer 121.

[0043] Fig. 12 is an example of a cross-sectional view of the periphery of the first protection circuit 101 taken along dashed line BB' in Fig. 11. According to the first embodiment, when an overcurrent flows through the first protection circuit 101 due to, for example, electrostatic discharge, the first heat dissipation layer 121 dissipates heat generated or accumulated due to the overcurrent in the direction of the first surface 202, thereby suppressing a temperature rise in the first protection circuit 101. This increases the current conductivity of the first protection circuit 101, thereby improving the protection characteristics.

[0044] Furthermore, in the case where excessive heat conduction occurs in the direction of the first wiring layer 113, the first heat dissipation layer 121 is provided between the first protection circuit 101 and the first wiring layer 113 to promote heat dissipation and suppress heat conduction to the first wiring layer 113 and the wiring layers provided thereon. Even if the first heat dissipation layer 121 melts, the effect on the circuit operation can be reduced compared to the case where the first wiring layer 113 melts. Therefore, a highly reliable first protection circuit 101 can be realized in which the wiring layers, vias, and contact layers are less likely to melt than the first protection circuit 101 of the example shown in FIG. 7.

[0045] As described above, in the semiconductor device 111 of this embodiment, the area of ​​the first protection circuit 101 does not increase compared to the area of ​​the first protection circuit 101 in the example shown in FIG. 7, so that it is expected that the protection characteristics can be improved while suppressing an increase in chip area.

[0046] In addition, in the semiconductor device 111 of this embodiment, since the current conductivity of the first protection circuit 101 is increased, the first protection circuit 101 is smaller than the example shown in FIG. 7, and therefore it is possible to achieve characteristics equivalent to those of the first protection circuit 101 in the example shown in FIG. 7.

[0047] 13, 14, and 15 show examples different from the plan view of the periphery of the first protection circuit 101 shown in Fig. 11. Compared to Fig. 11, Figs. 13, 14, and 15 provide an improved degree of freedom in the layout of the contact layer 118, and can increase the space margin between the contact layer 118 and the first heat dissipation layer 121. This reduces the possibility that the contact layer 118 and the first heat dissipation layer 121 will come into contact with each other due to manufacturing variations, and can suppress the risk of malfunction of the semiconductor device 111.

[0048] As shown in Figs. 11, 13, 14, and 15, various layouts of the first heat dissipation layer 121 are possible. In plan view on the first surface 202 side, the first heat dissipation layer 121 may be provided between the contact layers 118. In plan view on the first surface 202 side, the contact layers 118 may be provided between the first heat dissipation layers 121. In plan view on the first surface 202 side, the first heat dissipation layer 121 may be provided at a position overlapping at least a part of the well region 115. In plan view on the first surface 202 side, the first heat dissipation layer 121 may be provided at a position overlapping at least a part of the N-type activation region 116 and the P-type activation region 117. Furthermore, in plan view on the first surface 202 side, first heat dissipation layer 121 may be provided at a position overlapping at least a portion of well region 115 and at least a portion of N-type activation region 116 and P-type activation region 117. Furthermore, first heat dissipation layer 121 may be provided at a position overlapping an end of well region 115 in plan view on the first surface 202 side.

[0049] As an example of the improvement in the degree of freedom of layout, the effect of FIG. 15 will be described below with reference to FIGS. 16 to 20. In this description, a configuration including up to the third wiring layer 123 will be described, but the present invention is not limited to this. Here, the second via layer 122 electrically connects the second wiring layer 114 and the third wiring layer 123. Note that FIGS. 16 to 19 show plan views of the layout shown in FIG. 15 for each layer. Also, the first heat dissipation layer 121 is omitted from FIGS. 16 to 18.

[0050] 16 is a plan view of the periphery of the first protection circuit 101 in the layout shown in FIG. 15, with the upper layers above the second wiring layer 114 omitted, and shows the first protection circuit 101, the first wiring layer 113, and the first via layer 119.

[0051] Figure 17 is a plan view of the area around the first protection circuit 101 in the layout shown in Figure 15, with the layers above the third wiring layer 123 omitted, and shows the first protection circuit 101, the first wiring layer 113, the second wiring layer 114, and the second via layer 122.

[0052] FIG. 18 is a plan view of the area around the first protection circuit 101 in the layout shown in FIG. 15, with the layers above the third wiring layer 123 omitted, and shows the first protection circuit 101, the first wiring layer 113, the second wiring layer 114, and the third wiring layer 123.

[0053] FIG. 19 is a plan view in which the first pad 100, the semiconductor element 102, and the first heat dissipation layer 121 are added to FIG.

[0054] 19, the first pad 100 is connected to the first protection circuit 101 via the third wiring layer 123. The first protection circuit 101 is connected to the semiconductor element 102 via the second wiring layer 114. Thus, the first pad 100 is connected to the semiconductor element 102 via the first protection circuit 101. Note that in FIG. 19, the positional relationship between the first pad 100, the first protection circuit 101, and the semiconductor element 102 is depicted according to the arrangement in FIG. 1, but the first protection circuit 101 may be disposed between the facing first pad 100 and the semiconductor element 102.

[0055] Here, when considering the wiring path from the first pad 100 to the semiconductor element 102, a resistance difference occurs in the wiring path according to the difference in the wiring path length. In particular, around the corners of the first protection circuit 101, there are the shortest wiring path and the longest wiring path, and the difference in the wiring path length occurs significantly. Therefore, when an overcurrent flows from the first pad 100 to the semiconductor element 102 through the first protection circuit 101 during electrostatic discharge, there is a risk of a bias in the current density due to the resistance difference in this wiring path. As a result, there is a risk of defects such as melting due to heat generation of the wiring layer, via, and contact layer around the corners of the first protection circuit 101. In response to this, as shown in FIG. 19, the first heat dissipation layer 121 is arranged so as to overlap at least the periphery of the corners of the first protection circuit 101 in a plan view on the first surface 202 side, so that the first protection circuit 101 with improved protection characteristics can be provided while suppressing an increase in chip area. Furthermore, since the first heat dissipation layer 121 is disposed so as to cover the periphery of the corners of the first protection circuit 101, the first protection circuit 101 can be laid out with a high degree of freedom without being restricted by the arrangement of the first heat dissipation layer 121.

[0056] It should be noted that the layouts in FIGS. 16, 17, 18, and 19 are merely examples and are not limited to these.

[0057] FIG. 20 is an example of a cross-sectional view of the periphery of first protection circuit 101 taken along dashed line BB' shown in FIG.

[0058] Second Embodiment 21 and 22, the structure of a semiconductor device 111 according to a second embodiment of the present invention will be described, focusing on the differences from the first embodiment. The same components as those in the first embodiment are denoted by the same reference numerals, and the description of these components may be omitted or simplified.

[0059] 21 is an example of a cross-sectional view of the semiconductor device 111 according to the second embodiment taken along dashed line A-A' in FIG. 21 differs from the first embodiment in that the semiconductor element 102 includes a photoelectric conversion unit 125 and a peripheral circuit 124 for processing a signal detected by the photoelectric conversion unit 125. The photoelectric conversion unit 125 has, for example, a light-shielding film 132 for blocking light. Here, the light-shielding film 132 is disposed at a position overlapping at least a portion of the photoelectric conversion unit 125 in a plan view on the first surface 202 side.

[0060] According to the second embodiment, by forming the light shielding film 132 and the first heat dissipation layer 121 in parallel processes, it is not necessary to develop a new process, and it is possible to reduce development costs and manufacturing costs. The process of forming the light shielding film 132 and the process of forming the first heat dissipation layer 121 do not necessarily need to be performed at the same time, and it is sufficient that each process overlaps partially. In the semiconductor device 111 shown in FIG. 21, light may be incident on the photoelectric conversion unit 125 from the first surface 202, or light may be incident on the photoelectric conversion unit 125 from the second surface 203. In addition, the semiconductor device 111 shown in FIG. 21 has a single-layer structure.

[0061] FIG. 22 shows a laminated structure of the structure of FIG. 21, which is a single layer structure. FIG. 22 shows a structure in which a circuit board 126 including a peripheral circuit 124 is laminated on a semiconductor layer 201. The semiconductor member 112 is electrically connected to the circuit board 126 via a joint 127. The semiconductor member 112 has at least a photoelectric conversion unit 125 and a first protective circuit 101, and the circuit board 126 has at least a peripheral circuit 124. In FIG. 22, the semiconductor member 112 has a first pad 100, and the circuit board 126 has a fourth pad 128, and the first pad 100 and the first protective circuit 101 are connected. Here, the fourth pad 128 may be connected to the first protective circuit 101 via the joint 127. The circuit board 126 may also have a wiring layer and a fourth protective circuit 129, and may have a heat dissipation layer between the wiring layer closest to the semiconductor layer included in the circuit board 126 and the semiconductor layer, although this is omitted in the figure. When a heat dissipation layer is provided, the heat dissipation layer is disposed at a position overlapping at least a portion of the fourth protection circuit 129 in plan view on the first surface 202 side.

[0062] Third embodiment 23 to 26, the structure of a semiconductor device 111 according to a third embodiment of the present invention will be described, focusing on the differences from the first and second embodiments. The same components as those in the first and second embodiments are denoted by the same reference numerals, and the description of these components may be omitted or simplified.

[0063] 23 is a cross-sectional view of the semiconductor device 111 according to the third embodiment taken along the dashed line A-A' in FIG. 1. The third embodiment is different from the first and second embodiments in the structure of the heat dissipation layer. In the third embodiment, a second heat dissipation layer 130 is disposed between the first surface 202 and the second surface 203 so as to contact the element isolation region 120. Here, the first protection circuit 101 is provided at a first depth from the first surface 202, and the second heat dissipation layer 130 is also provided at a first depth from the first surface 202.

[0064] The second heat dissipation layer 130 includes a conductive material, such as at least one of a simple metal such as tungsten, copper, aluminum, titanium, cobalt, or nickel, an alloy mainly containing these metals, and a compound of metal and polysilicon. The metal element mainly contained in the second heat dissipation layer 130 may be the same as or different from the metal element mainly contained in the first wiring layer 113 and the second wiring layer 114.

[0065] 24 is an example of a plan view of the periphery of the first protection circuit 101 in FIG. 23. In FIG. 24, the upper layers above the first wiring layer 113 are omitted. In FIG. 24, the second heat dissipation layer 130 is arranged so as to surround the outer periphery of the contact layer 118. That is, in a plan view of the first surface 202 side, the contact layer 118 is arranged inside the region surrounded by the second heat dissipation layer 130. The second heat dissipation layer 130 may be arranged inside the first protection circuit 101 or outside the first protection circuit 101.

[0066] FIG. 25 shows an example different from the plan view of the periphery of the first protection circuit 101 shown in FIG. 25 differs from FIG. 24 in that the second heat dissipation layer 130 is provided in the shape of multiple cylinders. In FIG. 25, it is possible to increase the surface area of ​​the second heat dissipation layer 130 compared to FIG. 24, and further improvement in heat dissipation can be expected. Note that the cylindrical shapes in FIG. 25 are merely examples and are not limited thereto.

[0067] 26 is an example of a cross-sectional view of the periphery of the first protection circuit 101 taken along the dashed line BB' shown in FIG. 24. According to the third embodiment, when an overcurrent flows through the first protection circuit 101 due to electrostatic discharge or the like, heat generation and heat accumulation caused by the overcurrent can be dissipated in the direction of the second surface 203 via the second heat dissipation layer 130, thereby suppressing a temperature rise in the first protection circuit 101. This can increase the current conductivity of the first protection circuit 101 and improve the protection characteristics. Note that by forming the second heat dissipation layer 130 deeper in the depth direction of the semiconductor layer 201, the surface area of ​​the second heat dissipation layer 130 can be increased, and the heat dissipation properties can be further improved.

[0068] As described above, in the semiconductor device 111 of this embodiment, the area of ​​the first protection circuit 101 is less likely to increase compared to the area of ​​the first protection circuit 101 in the example shown in FIG. 7, so that it is expected that the protection characteristics can be improved while suppressing an increase in chip area.

[0069] In addition, in the semiconductor device 111 of this embodiment, since the current conductivity of the first protection circuit 101 is increased, the first protection circuit 101 is smaller than the example shown in FIG. 7, and therefore it is possible to achieve characteristics equivalent to those of the first protection circuit 101 in the example shown in FIG. 7.

[0070] Fourth embodiment 27 to 28, the structure of a semiconductor device 111 according to a fourth embodiment of the present invention will be described, focusing on the differences from the first to third embodiments. The same components as those in the first to third embodiments are denoted by the same reference numerals, and the description of these components may be omitted or simplified.

[0071] Fig. 27 is a cross-sectional view of the semiconductor device 111 according to the fourth embodiment taken along dashed line A-A' in Fig. 1. The photoelectric conversion unit 125 has an isolation unit 131 for reducing noise, for example. Here, the isolation unit 131 is provided at a first depth in the semiconductor layer 201.

[0072] According to the fourth embodiment, the separation section 131 and the second heat dissipation layer 130 are formed in parallel processes, so that development of a new process is not necessary, and development costs and manufacturing costs can be reduced. The process of forming the separation section 131 and the process of forming the second heat dissipation layer 130 do not necessarily need to be performed at the same time, and each process may be partially overlapped. In the semiconductor device 111 shown in FIG. 27, light may be incident on the photoelectric conversion section 125 from the first surface 202, or light may be incident on the photoelectric conversion section 125 from the second surface 203. The semiconductor device 111 shown in FIG. 27 has a single-layer structure.

[0073] FIG. 28 shows a laminated structure of the structure of FIG. 27, which is a single layer structure. FIG. 28 shows a structure in which a circuit board 126 including a peripheral circuit 124 is laminated on a semiconductor layer 201. The semiconductor member 112 is electrically connected to the circuit board 126 via a joint 127. The semiconductor member 112 has at least a photoelectric conversion unit 125 and a first protective circuit 101, and the circuit board 126 has at least a peripheral circuit 124. In FIG. 28, the semiconductor member 112 has a first pad 100, the circuit board 126 has a fourth pad 128, and the first pad 100 and the first protective circuit 101 are connected. Here, the fourth pad 128 may be connected to the first protective circuit 101 via the joint 127. The circuit board 126 may also have a fourth protective circuit 129, and although not shown in the figure, the circuit board 126 may have a heat dissipation layer so as to be in contact with the element isolation region. When a heat dissipation layer is provided, the heat dissipation layer is disposed at the same depth as the fourth protection circuit 129 .

[0074] Fifth embodiment 29 to 30, the structure of a semiconductor device 111 according to a fifth embodiment of the present invention will be described, focusing on the differences from the first to fourth embodiments. The same components as those in the first to fourth embodiments are denoted by the same reference numerals, and the description of these components may be omitted or simplified.

[0075] Fig. 29 is a cross-sectional view of the semiconductor device 111 according to the fifth embodiment taken along the dashed line A-A' shown in Fig. 1. The fifth embodiment has a structure that combines Fig. 10 of the first embodiment and Fig. 23 of the third embodiment. That is, the fifth embodiment has a first heat dissipation layer 121 disposed between the semiconductor layer 201 and the first wiring layer 113, and a second heat dissipation layer 130 disposed between the first surface 202 and the second surface 203. The first heat dissipation layer 121 and the second heat dissipation layer 130 may or may not be electrically connected to each other.

[0076] Fig. 30 shows an example of a three-dimensional structure in the case where the first heat dissipation layer 121 and the second heat dissipation layer 130 are electrically connected in Fig. 29. By combining the first and third embodiments to form a comb-shaped fin shape or a pin-holder shape, like a so-called heat sink structure, the surface area of ​​the heat dissipation layer can be increased and heat dissipation can be further improved.

[0077] According to the fifth embodiment, it is possible to improve the protection characteristics of the first protection circuit 101 compared to the first and third embodiments. Alternatively, it is possible to achieve characteristics equivalent to those of the first protection circuit 101 of the first and third embodiments using a first protection circuit 101 that is smaller in size compared to the first and third embodiments.

[0078] Although not shown in the drawings, similarly to the second and fourth embodiments, the semiconductor element 102 may include a photoelectric conversion unit 125 and a peripheral circuit 124 for processing a signal detected by the photoelectric conversion unit 125. In addition, in the semiconductor device 111 shown in FIG. 29, light may be incident on the photoelectric conversion unit 125 from the first surface 202, or light may be incident on the photoelectric conversion unit 125 from the second surface 203. In addition, although the semiconductor device 111 shown in FIG. 29 has a single-layer structure, it may have a structure in which a circuit board including the peripheral circuit 124 is laminated on the semiconductor layer 201.

[0079] Sixth embodiment The sixth embodiment is applicable to any of the first to fifth embodiments. FIG. 31(a) is a schematic diagram for explaining an apparatus 9191 including the semiconductor device 111 of this embodiment. The apparatus 9191 including the semiconductor device 111 will be explained in detail. The semiconductor device 111 can include a package 920 that houses the semiconductor device 910 in addition to a semiconductor device 910 having a semiconductor layer 201. The package 920 can include a base to which the semiconductor device 910 is fixed, and a lid such as glass that faces the semiconductor device 910. The package 920 can further include a bonding member such as a bonding wire or a bump that connects a terminal provided on the base and a terminal provided on the semiconductor device 910.

[0080] The device 9191 can include at least one of an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 corresponds to the semiconductor device 111. The optical device 940 is, for example, a lens, a shutter, or a mirror. The control device 950 controls the semiconductor device 111. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0081] The processing device 960 processes a signal output from the semiconductor device 111. The processing device 960 is a semiconductor device such as a CPU or ASIC for configuring an AFE (analog front end) or a DFE (digital front end). The display device 970 is an EL display device or a liquid crystal display device that displays information (images) obtained by the semiconductor device 111. The storage device 980 is a magnetic device or a semiconductor device that stores information (images) obtained by the semiconductor device 111. The storage device 980 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0082] The mechanical device 990 has a moving part or a propulsion part such as a motor or an engine. In the device 9191, the signal output from the semiconductor device 111 is displayed on the display device 970, or transmitted to the outside by a communication device (not shown) included in the device 9191. For this purpose, the device 9191 preferably further includes a storage device 980 and a processing device 960 in addition to the memory circuit and arithmetic circuit included in the semiconductor device 111. The mechanical device 990 may be controlled based on the signal output from the semiconductor device 111.

[0083] The device 9191 is also suitable for electronic devices such as information terminals (e.g., smartphones and wearable devices) with a photographing function and cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). The mechanical device 990 in the camera can drive components of the optical device 940 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in the camera can move the semiconductor device 111 for vibration isolation operation.

[0084] The device 9191 may be transportation equipment such as a vehicle, a ship, or an aircraft. The mechanical device 990 in the transportation equipment may be used as a moving device. The device 9191 as a transportation equipment is suitable for transporting the semiconductor device 111 or for assisting and / or automating driving (piloting) by using a photographing function. The processing device 960 for assisting and / or automating driving (piloting) can perform processing for operating the mechanical device 990 as a moving device based on information obtained by the semiconductor device 111. Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analytical device such as an electron microscope, an office machine such as a copier, or an industrial device such as a robot.

[0085] According to the above-described embodiment, it is possible to obtain good pixel characteristics. Therefore, the value of the semiconductor device can be increased. In this case, increasing the value corresponds to at least one of adding functions, improving performance, improving characteristics, improving reliability, improving manufacturing yield, reducing environmental load, reducing costs, reducing size, and reducing weight.

[0086] Therefore, if the semiconductor device 111 according to this embodiment is used in the equipment 9191, the value of the equipment can be improved. For example, by mounting the semiconductor device 111 on a transport equipment, excellent performance can be obtained when photographing the outside of the transport equipment or measuring the external environment. Therefore, in manufacturing and selling the transport equipment, it is advantageous to decide to mount the semiconductor device according to this embodiment on the transport equipment in order to improve the performance of the transport equipment itself. In particular, the semiconductor device 111 is suitable for transport equipment that performs driving assistance and / or automatic driving of the transport equipment using information obtained by the semiconductor device.

[0087] The photoelectric conversion system and the moving object of this embodiment will be described with reference to FIGS.

[0088] FIG. 31(a) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 8 has a photoelectric conversion device 80. The photoelectric conversion device 80 is a photoelectric conversion device (imaging device) described in any of the above embodiments. The photoelectric conversion system 8 has an image processing unit 801 that performs image processing on a plurality of image data acquired by the photoelectric conversion device 80, and a parallax acquisition unit 802 that calculates parallax (phase difference of parallax images) from the plurality of image data acquired by the photoelectric conversion system 8. The photoelectric conversion system 8 also has a distance acquisition unit 803 that calculates a distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax acquisition unit 802 and the distance acquisition unit 803 are examples of distance information acquisition means that acquire distance information to the object. That is, the distance information is information related to the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 804 may determine the possibility of collision using any of these distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination of these.

[0089] The photoelectric conversion system 8 is connected to a vehicle information acquisition device 810, and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 8 is also connected to a control ECU 820, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the judgment result of the collision judgment unit 804. The photoelectric conversion system 8 is also connected to an alarm device 830 that issues an alarm to the driver based on the judgment result of the collision judgment unit 804. For example, when the judgment result of the collision judgment unit 804 indicates that there is a high possibility of a collision, the control ECU 820 performs vehicle control to avoid a collision and reduce damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 830 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., and vibrating the seat belt or steering wheel.

[0090] In this embodiment, the surroundings of the vehicle, for example the front or rear, are imaged by the photoelectric conversion system 8. Fig. 31(c) shows the photoelectric conversion system when imaging the area in front of the vehicle (imaging range 850). The vehicle information acquisition device 810 sends an instruction to the photoelectric conversion system 8 or the photoelectric conversion device 80. With this configuration, the accuracy of distance measurement can be further improved.

[0091] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, control of automatic driving to prevent deviation from lanes, etc. Furthermore, the photoelectric conversion system is not limited to vehicles such as the vehicle itself, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the present invention can be applied not only to moving bodies, but also to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0092] The above-described embodiments can be modified as appropriate without departing from the technical concept. The disclosure of this specification includes not only what is described in this specification, but also all matters that can be understood from this specification and the drawings attached hereto. The disclosure of this specification also includes the complement of the concepts described in this specification. In other words, if this specification contains a statement that "A is greater than B," for example, this specification can be said to disclose that "A is not greater than B" even if the statement that "A is not greater than B" is omitted. This is because when it is stated that "A is greater than B," it is assumed that the case in which "A is not greater than B" is taken into consideration.

[0093] The disclosure of this embodiment includes the following configurations and methods.

[0094] (Configuration 1) A semiconductor device comprising: a semiconductor layer having a first surface and a second surface, with a semiconductor element and a protection circuit provided between the first surface and the second surface; and a wiring layer arranged on the first surface side and electrically connected to the protection circuit, wherein the semiconductor device further comprises a first heat dissipation layer arranged between the wiring layer closest to the semiconductor layer and the semiconductor layer and not electrically connected to the protection circuit, and wherein, in a planar view of the first surface side, the first heat dissipation layer is arranged in a position overlapping at least a portion of the protection circuit.

[0095] (Configuration 2) The semiconductor device described in Configuration 1, characterized in that, in a planar view of the first surface side, a contact layer electrically connecting the protection circuit and the wiring layer is arranged inside the area surrounded by the first heat dissipation layer.

[0096] (Structure 3) A semiconductor device according to structure 1 or 2, characterized in that, in a planar view of the first surface side, a plurality of contact layers are arranged to electrically connect the protection circuit and the wiring layer, and the first heat dissipation layer is arranged between the plurality of contact layers.

[0097] (Structure 4) A semiconductor device according to any one of structures 1 to 3, characterized in that, in a planar view of the first surface side, a contact layer electrically connecting the protection circuit and the wiring layer is arranged between multiple of the first heat dissipation layers.

[0098] (Structure 5) The semiconductor device according to any one of structures 1 to 4, wherein the first heat dissipation layer is arranged in a position overlapping at least a portion of a well region included in the protection circuit when viewed in a plan view from the first surface side.

[0099] (Configuration 6) The semiconductor switching device according to any one of configurations 1 to 5, wherein the first heat dissipation layer is arranged at a position overlapping at least a portion of an active region included in the protection circuit when viewed in a plan view from the first surface side.

[0100] (Structure 7) The semiconductor device according to any one of structures 1 to 6, wherein the first heat dissipation layer contains at least one of a metal element selected from the group consisting of tungsten, copper, aluminum, titanium, cobalt, and nickel, and an alloy containing the metal.

[0101] (Configuration 8) The semiconductor device according to any one of configurations 1 to 7, wherein the wiring layer and the first heat dissipation layer contain metals and have different main elements.

[0102] (Structure 9) A semiconductor device described in any one of structures 1 to 8, characterized in that an element isolation region and a second heat dissipation layer containing a metal are arranged between the first surface and the second surface, the protection circuit includes the element isolation region, the second heat dissipation layer is in contact with the element isolation region, the protection circuit is arranged at a first depth from the first surface, and the second heat dissipation layer is arranged at the first depth from the first surface.

[0103] (Structure 10) The semiconductor device according to Structure 9, wherein the second heat dissipation layer contains at least one of a metal such as tungsten, copper, aluminum, titanium, cobalt, or nickel, an alloy containing such a metal, or a compound of metal and polysilicon.

[0104] (Configuration 11) The semiconductor device according to any one of configurations 1 to 10, wherein the semiconductor element includes a peripheral circuit that processes a signal detected by the photoelectric conversion portion.

[0105] (Configuration 12) The semiconductor device according to any one of configurations 1 to 11, wherein the semiconductor element includes a photoelectric conversion portion.

[0106] (Configuration 13) The semiconductor device according to configuration 12, wherein light is incident on the photoelectric conversion portion from the second surface.

[0107] (Configuration 14) The semiconductor device according to configuration 13, further comprising a circuit board including a peripheral circuit for processing a signal detected by the photoelectric conversion portion, the circuit board being laminated on the semiconductor layer.

[0108] (Configuration 15) The semiconductor device according to any one of configurations 1 to 14, wherein the first heat dissipation layer is electrically connected to a pad that is not electrically connected to the protection circuit.

[0109] (Structure 16) A semiconductor device comprising a semiconductor layer having a first surface and a second surface, in which a semiconductor element, a protection circuit, and an element isolation region are provided between the first surface and the second surface, wherein the protection circuit includes the element isolation region and is arranged between the first surface and the second surface so as to be in contact with the element isolation region, and further comprising a second heat dissipation layer containing a metal, wherein the protection circuit is arranged at a first depth from the first surface, and the second heat dissipation layer is arranged at the first depth from the first surface.

[0110] (Configuration 17) An apparatus including a semiconductor device according to any one of configurations 1 to 16, further including at least one of an optical device corresponding to the semiconductor device, a control device controlling the semiconductor device, a processing device processing a signal output from the semiconductor device, a display device displaying information obtained by the semiconductor device, a memory device storing information obtained by the semiconductor device, and a mechanical device operating based on information obtained by the semiconductor device.

[0111] (Structure 18) A substrate comprising: a semiconductor layer having a first surface and a second surface, with a semiconductor element and a protection circuit provided between the first surface and the second surface; and a wiring layer arranged on the first surface side and electrically connected to the protection circuit, wherein the substrate further comprises a first heat dissipation layer arranged between the wiring layer closest to the semiconductor layer and the semiconductor layer and not electrically connected to the protection circuit, wherein, in a planar view of the first surface side, the first heat dissipation layer is arranged in a position overlapping at least a portion of the protection circuit.

[0112] (Method 1) A method for manufacturing a semiconductor device including a semiconductor layer having a first surface and a second surface, with a photoelectric conversion section and a protection circuit provided between the first surface and the second surface, a light-shielding film arranged on the first surface side, and a wiring layer arranged on the first surface side and electrically connected to the protection circuit, characterized in that the following steps are carried out in parallel: forming the light-shielding film between the wiring layer closest to the semiconductor layer and the semiconductor layer, at a position overlapping with at least a portion of the photoelectric conversion section in a planar view on the first surface side; and forming a first heat dissipation layer not electrically connected to the protection circuit, between the wiring layer closest to the semiconductor layer and the semiconductor layer, at a position overlapping with at least a portion of the protection circuit in a planar view on the first surface side.

[0113] (Method 2) A method for manufacturing a substrate including a semiconductor layer having a first surface and a second surface, with a photoelectric conversion section and a protection circuit provided between the first surface and the second surface, a light-shielding film arranged on the first surface side, and a wiring layer arranged on the first surface side and electrically connected to the protection circuit, characterized in that the following steps are carried out in parallel: forming the light-shielding film between the wiring layer closest to the semiconductor layer and the semiconductor layer, at a position overlapping with at least a portion of the photoelectric conversion section in a planar view on the first surface side; and forming a first heat dissipation layer not electrically connected to the protection circuit, between the wiring layer closest to the semiconductor layer and the semiconductor layer, at a position overlapping with at least a portion of the protection circuit in a planar view on the first surface side. [Explanation of symbols]

[0114] 201 Semiconductor layer 202 Page 1 203 2nd page 102 Semiconductor elements 101 1st protection circuit 111 Semiconductor device 113 1st wiring layer 121 1st heat dissipation layer

Claims

1. A semiconductor device comprising a semiconductor layer having a first surface and a second surface, with a semiconductor element and a protection circuit provided between the first surface and the second surface, a wiring layer disposed on the first surface side and electrically connected to the protection circuit, or a plurality of wiring layers disposed on the first surface side and electrically connected to the protection circuit, and comprising: a first heat dissipation layer disposed between the wiring layer and the semiconductor layer or between the wiring layer closest to the semiconductor layer among the plurality of wiring layers and the semiconductor layer, and not electrically connected to the protection circuit, wherein in a plan view from the first surface side, the first heat dissipation layer is disposed at a position overlapping at least a part of the protection circuit. A semiconductor device characterized by the above.

2. The semiconductor device according to claim 1, wherein in a plan view from the first surface side, a contact layer electrically connecting the protection circuit and the wiring layer is disposed inside a region surrounded by the first heat dissipation layer.

3. The semiconductor device according to claim 1, wherein in a plan view from the first surface side, a plurality of contact layers electrically connecting the protection circuit and the wiring layer are disposed, and the first heat dissipation layer is disposed between the plurality of contact layers.

4. The semiconductor device according to claim 1, wherein in a plan view from the first surface side, a contact layer electrically connecting the protection circuit and the wiring layer is disposed between a plurality of the first heat dissipation layers.

5. The semiconductor device according to claim 1, wherein in a plan view from the first surface side, the first heat dissipation layer is disposed at a position overlapping at least a part of a well region included in the protection circuit.

6. The semiconductor device according to claim 1, wherein in a plan view from the first surface side, the first heat dissipation layer is disposed at a position overlapping at least a part of an activation region included in the protection circuit.

7. The semiconductor device according to claim 1, wherein the first heat dissipation layer includes at least one of a single metal of tungsten, copper, aluminum, titanium, cobalt, nickel, and an alloy containing the metal.

8. The semiconductor device according to claim 1, wherein the wiring layer and the first heat dissipation layer contain a metal, and their main elements are different from each other.

9. An element isolation region and a second heat dissipation layer containing a metal are disposed between the first surface and the second surface. The protection circuit includes the element isolation region. The second heat dissipation layer is in contact with the element isolation region. The protection circuit is disposed at a first depth from the first surface, and the second heat dissipation layer is disposed at the first depth from the first surface. The semiconductor device according to claim 1, characterized in that.

10. The semiconductor device according to claim 9, wherein the second heat dissipation layer includes at least one of a single metal of tungsten, copper, aluminum, titanium, cobalt, nickel, an alloy containing the metal, and a compound of a metal and polysilicon.

11. The semiconductor device according to claim 1, characterized in that the semiconductor element includes a peripheral circuit that processes a signal detected by the photoelectric conversion unit.

12. The semiconductor device according to claim 1, characterized in that the semiconductor element includes a photoelectric conversion unit.

13. The semiconductor device according to claim 12, characterized in that light is incident on the photoelectric conversion unit from the second surface.

14. The semiconductor device according to claim 13, characterized in that a circuit board including a peripheral circuit that processes a signal detected by the photoelectric conversion unit is laminated on the semiconductor layer.

15. The semiconductor device according to claim 1, characterized in that the first heat dissipation layer is electrically connected to a pad that is not electrically connected to the protection circuit.

16. A semiconductor device including a semiconductor layer having a first surface and a second surface, with a semiconductor element, a protection circuit, and an element isolation region provided between the first surface and the second surface, wherein the protection circuit includes the element isolation region, and a second heat dissipation layer including a metal is provided between the first surface and the second surface so as to be in contact with the element isolation region, wherein the protection circuit is disposed at a first depth from the first surface, and the second heat dissipation layer is disposed at the first depth from the first surface. A semiconductor device characterized by the above.

17. A semiconductor layer having a first surface and a second surface, with a photoelectric conversion section and a protection circuit provided between the first surface and the second surface, a light-shielding film disposed on the first surface side, a wiring layer disposed on the first surface side and electrically connected to the protection circuit, or a plurality of wiring layers disposed on the first surface side and electrically connected to the protection circuit, A method for manufacturing a semiconductor device including: forming the light-shielding film at a position overlapping at least a part of the photoelectric conversion section in a plan view from the first surface side between the wiring layer and the semiconductor layer or between the wiring layer closest to the semiconductor layer among the plurality of wiring layers and the semiconductor layer; forming a first heat dissipation layer not electrically connected to the protection circuit at a position overlapping at least a part of the protection circuit in a plan view from the first surface side between the wiring layer and the semiconductor layer, in parallel. A method for manufacturing a semiconductor device characterized by the above.

18. An apparatus including the semiconductor device according to any one of Claims 1 to 16, an optical device corresponding to the semiconductor device, a control device for controlling the semiconductor device, a processing device for processing a signal output from the semiconductor device, a display device for displaying information obtained by the semiconductor device. A storage device that stores information obtained by the semiconductor device, and, A device characterized by further comprising at least one of a mechanical device that operates based on information obtained by the semiconductor device.

19. A semiconductor layer having a first surface and a second surface, with a semiconductor element and a protection circuit provided between the first surface and the second surface, A wiring layer disposed on the first surface side and electrically connected to the protection circuit, or a plurality of wiring layers disposed on the first surface side and electrically connected to the protection circuit, A substrate comprising: A first heat dissipation layer disposed between the wiring layer and the semiconductor layer or between the wiring layer closest to the semiconductor layer among the plurality of wiring layers and the semiconductor layer, and not electrically connected to the protection circuit, In a plan view of the first surface side, the first heat dissipation layer is disposed at a position overlapping at least a part of the protection circuit A substrate characterized by this.

20. A semiconductor layer having a first surface and a second surface, with a photoelectric conversion unit and a protection circuit provided between the first surface and the second surface, A light-shielding film disposed on the first surface side, A wiring layer disposed on the first surface side and electrically connected to the protection circuit, or a plurality of wiring layers disposed on the first surface side and electrically connected to the protection circuit, A method for manufacturing a substrate comprising: A step of forming the light-shielding film at a position overlapping at least a part of the photoelectric conversion unit in a plan view of the first surface side between the wiring layer and the semiconductor layer or between the wiring layer closest to the semiconductor layer among the plurality of wiring layers and the semiconductor layer, A step of forming a first heat dissipation layer that is not electrically connected to the protection circuit at a position overlapping at least a part of the protection circuit in a plan view of the first surface side between the wiring layer and the semiconductor layer is carried out in parallel A method for manufacturing a substrate characterized by this.

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