Semiconductor device

Abstract

To provide a semiconductor device including a hydrogen trap region which prevents hydrogen from entering a channel region.SOLUTION: A semiconductor device includes: an oxide insulation layer; an oxide semiconductor layer on the oxide insulation layer; a gate insulation layer which covers the oxide semiconductor layer and is on the oxide insulation layer and the oxide semiconductor layer; a gate electrode on the gate insulation layer; and a protective insulation layer which covers the gate electrode and is on the gate insulation layer and the gate electrode. The gate insulation layer includes a first region overlapping the gate electrode and a second region which does not overlap the gate electrode and is in contact with the protective insulation layer. The oxide insulation layer includes a third region overlapping the gate electrode and a fourth region which does not overlap the gate electrode and the oxide semiconductor layer and is in contact with the gate insulation layer. An impurity is contained in a source region and a drain region of the oxide semiconductor layer and the second region, and a hydrogen concentration in the second region is higher than a hydrogen concentration in the first region.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] An embodiment of the present invention relates to a semiconductor device that uses an oxide semiconductor as a channel. [Background technology]

[0002] In recent years, semiconductor devices using oxide semiconductors as channels instead of silicon semiconductors such as amorphous silicon, low-temperature polysilicon, and single crystal silicon have been developed (see, for example, Patent Documents 1 to 6). Semiconductor devices including such oxide semiconductors can be formed with a simple structure and a low-temperature process, similar to semiconductor devices including amorphous silicon. In addition, semiconductor devices including oxide semiconductors are known to have higher field-effect mobility than semiconductor devices including amorphous silicon. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2021-141338 A [Patent Document 2] JP 2014-099601 A [Patent Document 3] Patent Publication No. 2021-153196 [Patent Document 4] JP 2018-006730 A [Patent Document 5] JP 2016-184771 A [Patent Document 6] Patent Publication No. 2021-108405 Summary of the Invention [Problem to be solved by the invention]

[0004] In an oxide semiconductor, carriers are generated when hydrogen is trapped in oxygen defects. By utilizing this mechanism, in a semiconductor device, oxygen defects are formed in an oxide semiconductor layer, and hydrogen is supplied to the formed oxygen defects, thereby forming a source region and a drain region in the oxide semiconductor layer having a higher carrier concentration than a channel region electrically connected to a source electrode and a drain electrode. On the other hand, when hydrogen diffuses into the channel region of the oxide semiconductor layer, the channel region does not function as a channel. That is, the diffusion of hydrogen into the channel region changes the threshold voltage in the electrical characteristics of the semiconductor device, and the variation in the threshold voltage increases, resulting in a decrease in the manufacturing yield of the semiconductor device. Therefore, an oxide containing excess oxygen capable of trapping hydrogen is used as an insulating layer in contact with the oxide semiconductor layer to prevent hydrogen from entering the channel region.

[0005] However, since an oxide containing excess oxygen functions as an electron trap, a semiconductor device containing such an oxide has a significantly reduced reliability. Therefore, a semiconductor device capable of supplying hydrogen to a source region and a drain region of an oxide semiconductor layer and preventing hydrogen from entering a channel region of the oxide semiconductor layer without reducing reliability is desired.

[0006] In view of the above problems, an object of one embodiment of the present invention is to provide a semiconductor device including a hydrogen trapping region that prevents hydrogen from entering a channel region. [Means for solving the problem]

[0007] A semiconductor device according to one embodiment of the present invention includes an oxide insulating layer, an oxide semiconductor layer on the oxide insulating layer, a gate insulating layer on the oxide semiconductor layer and on the oxide insulating layer, a gate electrode on the gate insulating layer, and a protective insulating layer on the gate electrode and covering the gate electrode, wherein the gate insulating layer includes a first region overlapping with the gate electrode and a second region not overlapping with the gate electrode and in contact with the protective insulating layer, the oxide insulating layer includes a third region overlapping with the gate electrode and a fourth region not overlapping with the gate electrode and the oxide semiconductor layer and in contact with the gate insulating layer, the oxide semiconductor layer includes a channel region, and a source region and a drain region having a carrier concentration higher than that of the channel region, the source region, the drain region, and the second region contain impurities, and the hydrogen concentration of the second region is higher than the hydrogen concentration of the first region. [Brief description of the drawings]

[0008] [Figure 1] 1 is a schematic cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention; [Diagram 2] 1 is a schematic plan view showing a configuration of a semiconductor device according to an embodiment of the present invention; [Diagram 3] 1 is a schematic enlarged partial cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention; [Figure 4] 5 is a graph showing a profile of the concentration of an impurity ion-implanted into a second region and a fourth region in a semiconductor device according to an embodiment of the present invention. [Diagram 5] 1 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 6] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 8] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 9]1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 10] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 12] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 13] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 14] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 15] 5A to 5C are schematic cross-sectional views illustrating the hydrogen trapping function of the second region and the fourth region in the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 16] 5A to 5C are schematic cross-sectional views illustrating the hydrogen trapping function of the second region and the fourth region in the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 17] 5A to 5C are schematic cross-sectional views illustrating the hydrogen trapping function of a protective insulating layer in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 18] 1 is a schematic plan view showing a configuration of a semiconductor device according to an embodiment of the present invention; [Figure 19] 4 is a graph showing electrical characteristics of the semiconductor devices of Example 1 and Example 2. [Figure 20] 13 is a graph showing the concentration profiles of boron in ion implantation carried out in the manufacture of semiconductor devices according to Examples 3 to 8. [Figure 21] 13 is a graph showing the concentration profiles of boron in ion implantation carried out in the manufacture of semiconductor devices according to Examples 9 to 14. [Figure 22] 13 is a graph showing electrical characteristics of the semiconductor devices of Examples 3 to 14. [Figure 23]1 is a graph showing electrical characteristics of the semiconductor devices of Comparative Example 1 and Comparative Example 2. [Figure 24] 13 is a graph showing a concentration profile of boron in ion implantation carried out in the manufacture of semiconductor devices according to Comparative Examples 3 to 5. [Diagram 25] 13 is a graph showing the concentration profiles of boron in ion implantation carried out in the manufacture of semiconductor devices according to Comparative Examples 6 to 8. [Figure 26] 13 is a graph showing electrical characteristics of the semiconductor devices of Comparative Examples 3 to 8. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Each embodiment of the present invention will be described below with reference to the drawings. The following disclosure is merely an example. A configuration that a person skilled in the art can easily come up with by appropriately modifying the configuration of the embodiment while maintaining the gist of the invention is naturally included in the scope of the present invention. In order to make the explanation clearer, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. In this specification and each figure, elements similar to those described above with respect to the previous figures may be given the same reference numerals, and detailed explanations may be omitted as appropriate.

[0010] In this specification, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "upper". Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "down". Thus, for convenience of explanation, the terms "up" or "down" are used in the explanation, but for example, the substrate and the oxide semiconductor layer may be arranged so that their vertical relationship is reversed from that shown in the figure. In the following explanation, for example, the expression "oxide semiconductor layer on a substrate" merely describes the vertical relationship between the substrate and the oxide semiconductor layer as described above, and other members may be arranged between the substrate and the oxide semiconductor layer. "Up" or "down" means the order of stacking in a structure in which multiple layers are stacked, and when a pixel electrode is expressed as being above a semiconductor device, the semiconductor device and the pixel electrode may not overlap in a planar view. On the other hand, when a pixel electrode is expressed as being vertically above a semiconductor device, the semiconductor device and the pixel electrode may overlap in a planar view.

[0011] In this specification, the terms "film" and "layer" may be used interchangeably in some cases.

[0012] The term "display device" refers to a structure that displays an image using an electro-optical layer. For example, the term display device may refer to a display panel including an electro-optical layer, or may refer to a structure in which other optical members (e.g., a polarizing member, a backlight, a touch panel, etc.) are attached to a display cell. The "electro-optical layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer, unless technically inconsistent. Therefore, the embodiments described below will be described by taking a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer as examples of display devices, but the structure in this embodiment can be applied to display devices including other electro-optical layers as described above.

[0013] In this specification, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude cases where α includes other elements.

[0014] The following embodiments can be combined with each other as long as no technical contradiction occurs.

[0015] First Embodiment A semiconductor device 10 according to one embodiment of the present invention will be described with reference to Figures 1 to 15. The semiconductor device 10 can be used, for example, in a display device, an integrated circuit (IC) such as a microprocessor (Micro-Processing Unit: MPU), or a memory circuit.

[0016] [1. Configuration of Semiconductor Device 10] The configuration of a semiconductor device 10 according to one embodiment of the present invention will be described with reference to Fig. 1 and Fig. 2. Fig. 1 is a schematic cross-sectional view showing the configuration of the semiconductor device 10 according to one embodiment of the present invention. Fig. 2 is a schematic plan view showing the configuration of the semiconductor device 10 according to one embodiment of the present invention. Specifically, Fig. 1 is a cross-sectional view taken along line A-A' in Fig. 2.

[0017] As shown in FIG. 1, the semiconductor device 10 includes a substrate 100, a light-shielding layer 105, a nitride insulating layer 110, an oxide insulating layer 120, an oxide semiconductor layer 140, a gate insulating layer 150, a gate electrode 160, a protective insulating layer 170, a source electrode 201, and a drain electrode 203. The light-shielding layer 105 is provided on the substrate 100. The nitride insulating layer 110 covers the upper surface and end surfaces of the light-shielding layer 105 and is provided on the substrate 100. The oxide insulating layer 120 is provided on the nitride insulating layer 110. The oxide semiconductor layer 140 is provided on the oxide insulating layer 120. The gate insulating layer 150 covers the upper surface and end surfaces of the oxide semiconductor layer 140 and is provided on the oxide insulating layer 120. The gate electrode 160 overlaps the oxide semiconductor layer 140 and is provided on the gate insulating layer 150. The protective insulating layer 170 covers the upper surface and end surfaces of the gate electrode 160 and is provided on the gate insulating layer 150. The gate insulating layer 150 and the protective insulating layer 170 are provided with openings 171 and 173 through which a part of the upper surface of the oxide semiconductor layer 140 is exposed. The source electrode 201 is provided on the protective insulating layer 170 and inside the opening 171, and is in contact with the oxide semiconductor layer 140. Similarly, the drain electrode 203 is provided on the protective insulating layer 170 and inside the opening 173, and is in contact with the oxide semiconductor layer 140. In the following description, when the source electrode 201 and the drain electrode 203 are not particularly distinguished from each other, they may be collectively referred to as the source-drain electrode 200.

[0018] The oxide semiconductor layer 140 is divided into a source region S, a drain region D, and a channel region CH with respect to the gate electrode 160. That is, the oxide semiconductor layer 140 includes the channel region CH overlapping with the gate electrode 160, and the source region S and the drain region D not overlapping with the gate electrode 160. In the film thickness direction of the oxide semiconductor layer 140, the end of the channel region CH coincides with the end of the gate electrode 160. The channel region CH has a semiconductor property. Each of the source region S and the drain region D has a conductor property. Therefore, the carrier concentration of the source region S and the drain region D is higher than the carrier concentration of the channel region CH. The source electrode 201 and the drain electrode 203 are in contact with the source region S and the drain region D, respectively, and are electrically connected to the oxide semiconductor layer 140. In addition, the oxide semiconductor layer 140 may have a single-layer structure or a multilayer structure.

[0019] 2, each of the light-shielding layer 105 and the gate electrode 160 has a certain width in the D1 direction and extends in the D2 direction perpendicular to the D1 direction. In the D1 direction, the width of the light-shielding layer 105 is larger than the width of the gate electrode 160. The channel region CH completely overlaps with the light-shielding layer 105. In the semiconductor device 10, the D1 direction corresponds to the direction in which a current flows from the source electrode 201 to the drain electrode 203 through the oxide semiconductor layer 140. Therefore, the length of the channel region CH in the D1 direction is the channel length L, and the width of the channel region CH in the D2 direction is the channel width W.

[0020] The substrate 100 can support each layer constituting the semiconductor device 10. For example, a rigid substrate having light-transmitting properties, such as a glass substrate, a quartz substrate, or a sapphire substrate, can be used as the substrate 100. A rigid substrate having no light-transmitting properties, such as a silicon substrate, can also be used as the substrate. A flexible substrate having light-transmitting properties, such as a polyimide resin substrate, an acrylic resin substrate, a siloxane resin substrate, or a fluororesin substrate, can also be used as the substrate. In order to improve the heat resistance of the substrate 100, impurities may be introduced into the above-mentioned resin substrate. Note that a substrate in which a silicon oxide film or a silicon nitride film is formed on the above-mentioned rigid substrate or flexible substrate can also be used as the substrate 100.

[0021] The light-shielding layer 105 can reflect or absorb external light. As described above, the light-shielding layer 105 is provided to have an area larger than the channel region CH of the oxide semiconductor layer 140, and therefore can block external light incident on the channel region CH. For example, aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), tungsten (W), or an alloy or compound thereof can be used as the light-shielding layer 105. Furthermore, when electrical conductivity is not required, the light-shielding layer 105 does not necessarily need to contain a metal. For example, a black matrix made of a black resin can be used as the light-shielding layer 105. Furthermore, the light-shielding layer 105 may have a single-layer structure or a laminated structure. For example, the light-shielding layer 105 may have a laminated structure of a red color filter, a green color filter, and a blue color filter.

[0022] The nitride insulating layer 110 can prevent impurities (e.g., sodium, etc.) contained in the substrate 100 or impurities (e.g., water, etc.) entering from the outside from diffusing into the oxide semiconductor layer 140. For example, a nitride containing silicon or aluminum can be used as the nitride insulating layer 110. Specifically, silicon nitride (SiN x ), silicon oxynitride (SiN x O y), Aluminum Nitride (AlN x ), or aluminum oxide nitride (AlN x O y ) or the like can be used. The nitride insulating layer 110 may have a single layer structure or a stacked layer structure.

[0023] Each of the oxide insulating layer 120 and the gate insulating layer 150 includes a hydrogen trapping region, and can suppress the intrusion of hydrogen into the channel region CH. The hydrogen trapping region will be described in detail later. Each of the oxide insulating layer 120 and the gate insulating layer 150 can be made of, for example, an oxide containing silicon or aluminum. Specifically, the oxide insulating layer 120 can be made of silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ), or aluminum oxide nitride (AlO x N y Each of the oxide insulating layer 120 and the gate insulating layer 150 may have a single layer structure or a stacked layer structure.

[0024] The protective insulating layer 170 can prevent impurities (such as water) entering from the outside from diffusing into the oxide semiconductor layer 140. The protective insulating layer 170 can also function as a hydrogen supply source for the source region S and the drain region D. For example, an oxide or nitride containing silicon or aluminum can be used as the protective insulating layer 170. Specifically, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ), or aluminum oxide nitride (AlO x N y ), or silicon nitride (SiN x ), silicon oxynitride (SiN x O y ), Aluminum Nitride (AlN x), or aluminum oxide nitride (AlN x O y ) can be used. The protective insulating layer 170 may have a single-layer structure or a stacked-layer structure. When the protective insulating layer 170 has a stacked-layer structure, the protective insulating layer 170 preferably has a stacked-layer structure (nitride / oxide) in which a nitride is stacked on an oxide.

[0025] Here, silicon oxynitride (SiO x N y ) and aluminum oxide nitride (AlO x N y ) are oxides that contain a smaller ratio (x>y) of nitrogen (N) than oxygen (O). Silicon oxynitride (SiN x O y ) and aluminum oxide nitride (AlN x O y ) are nitrides that contain a smaller proportion of oxygen than nitrogen (x>y).

[0026] The gate electrode 160, the source electrode 201, and the drain electrode 203 are conductive. For example, copper (Cu), aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), or bismuth (Bi), or an alloy or compound thereof, can be used for each of the gate electrode 160, the source electrode 201, and the drain electrode 203. Each of the gate electrode 160, the source electrode 201, and the drain electrode 203 may have a single-layer structure or a laminated structure.

[0027] acid The nitride semiconductor layer 140 may have an amorphous structure or a polycrystalline structure.

[0028] A detailed method for manufacturing the oxide semiconductor layer 140 will be described later in the manufacturing method of the semiconductor device 10, but the oxide semiconductor layer 140 can be formed by sputtering. The composition of the oxide semiconductor layer 140 formed by sputtering depends on the composition of the sputtering target. .child In this case, the composition of the metal elements in the oxide semiconductor layer 140 can be specified based on the composition of the metal elements in the sputtering target. In addition, when the oxide semiconductor layer 140 has a polycrystalline structure, the composition of the oxide semiconductor film may be specified by using an X-ray diffraction (XRD) method. Specifically, the composition of the metal elements in the oxide semiconductor film can be specified based on the crystal structure and lattice constant of the oxide semiconductor film obtained by the XRD method. Furthermore, the composition of the metal elements in the oxide semiconductor layer 140 can also be specified by using an X-ray fluorescence analysis or an Electron Probe Micro Analyzer (EPMA) analysis. Note that the oxygen element contained in the oxide semiconductor layer 140 is not limited to this because it changes depending on the process conditions of the sputtering.

[0029] [2. Hydrogen trapping area configuration] The hydrogen trapping region is formed in the oxide insulating layer 120 and the gate insulating layer 150. The configurations of the oxide insulating layer 120 and the gate insulating layer 150 will be further described with reference to Figs. 3 and 4. Fig. 3 is a schematic partially enlarged cross-sectional view showing the configuration of a semiconductor device 10 according to one embodiment of the present invention. Specifically, Fig. 3 is an enlarged cross-sectional view of a region P in Fig. 1. Note that the region P shown in Fig. 3 is a region in the vicinity of the drain region D, but the vicinity of the source region S also has a similar configuration to the region P.

[0030] The gate insulating layer 150 includes a first region 150-1 and a second region 150-2. The first region 150-1 is a region that overlaps with the gate electrode 160 in the thickness direction of the gate insulating layer 150 (or in the plan view of the semiconductor device 10). In other words, the first region 150-1 is a region that contacts with the channel region CH of the oxide semiconductor layer 140 and the gate electrode 160. The second region 150-2 is a region that does not overlap with the gate electrode 160 and the oxide semiconductor layer 140 in the thickness direction of the gate insulating layer 150 (or in the plan view of the semiconductor device 10). In other words, the second region 150-2 is a region that is located outside the drain region D of the oxide semiconductor layer 140 and contacts with the protective insulating layer 170 and the oxide insulating layer 120.

[0031] The oxide insulating layer 120 includes a third region 120-1 and a fourth region 120-2. The third region 120-1 is a region that overlaps with the gate electrode 160 in the thickness direction of the oxide insulating layer 120 (or in the planar view of the semiconductor device 10). In other words, the third region 120-1 is a region that contacts with the channel region CH of the oxide semiconductor layer 140. The fourth region 120-2 is a region that does not overlap with the gate electrode 160 and the oxide semiconductor layer 140 in the thickness direction of the oxide insulating layer 120 (or in the planar view of the semiconductor device 10). In other words, the fourth region 120-2 is a region that is located outside the drain region D of the oxide semiconductor layer 140 and contacts with the gate insulating layer 150.

[0032] The first region 150-1 and the third region 120-1 face each other via the channel region CH of the oxide semiconductor layer 140. The second region 150-2 and the fourth region 120-2 are in contact with each other outside the drain region D of the oxide semiconductor layer 140.

[0033] Although details will be described later, the source region S and the drain region D of the oxide semiconductor layer 140 are formed by ion implantation of an impurity using the gate electrode 160 as a mask. As the impurity, for example, boron (B), phosphorus (P), argon (Ar), or nitrogen (N) is used. By the ion implantation, oxygen defects are generated in the source region S and the drain region D of the oxide semiconductor layer 140. Hydrogen is trapped in the generated oxygen defects, thereby lowering the resistance of the source region S and the drain region D.

[0034] Since the ion implantation is performed through the gate insulating layer 150, dangling bond defects DB are generated in the gate insulating layer 150 by the ion implantation. Furthermore, dangling bond defects DB are also generated in the oxide insulating layer 120 by the ion implantation. As described above, since the ion implantation of impurities is performed using the gate electrode 160 as a mask, the impurities are not implanted in the region overlapping with the gate electrode 160, and dangling bond defects DB are not generated. That is, as shown in FIG. 3, the first region 150-1 and the third region 120-1 overlapping with the gate electrode 160 do not include dangling bond defects DB. On the other hand, the second region 150-2 and the fourth region 120-2 not overlapping with the gate electrode 160 include dangling bond defects DB. For example, when silicon oxide is used as the gate insulating layer 150 and the oxide insulating layer 120, silicon dangling bond defects DB are formed in the second region 150-2 and the fourth region 120-2.

[0035] The dangling bond defects DB in the second region 150-2 and the fourth region 120-2 can trap hydrogen. That is, in the semiconductor device 10, the second region 150-2 and the fourth region 120-2 can function as hydrogen trapping regions. Therefore, the hydrogen concentration in the second region 150-2 is higher than the hydrogen concentration in the first region 150-1. Similarly, the hydrogen concentration in the fourth region 120-2 is higher than the hydrogen concentration in the third region 120-1.

[0036] The second region 150-2 and the fourth region 120-2 contain ion-implanted impurities. The ion implantation is performed based on a concentration profile of the impurities, and the concentration distribution of the impurities contained in the second region 150-2 and the fourth region 120-2 corresponds to the concentration profile. Therefore, the defect amount of the dangling bond defects in the second region 150-2 and the fourth region 120-2 can be controlled based on the concentration profile.

[0037] 4 is a graph showing the concentration profile of the impurity ion-implanted into the second region 150-2 and the fourth region 120-2 in the semiconductor device 10 according to one embodiment of the present invention. The horizontal axis of FIG. 4 indicates the depth of the fourth region 120-2 in the positive direction and the depth of the second region 150-2 in the negative direction, with the interface between the second region 150-2 and the fourth region 120-2 (or the interface between the gate insulating layer 150 and the oxide insulating layer 120) being 0 nm. In other words, the positive direction indicates the position from the interface in the fourth region 120-2, and the negative direction indicates the position from the interface in the second region 150-2. Four different concentration profiles (a) to (d) are shown in FIG. 4.

[0038] In order for the hydrogen trapping region to function to suppress the intrusion of hydrogen into the channel region CH of the oxide semiconductor layer 140, it is necessary to form dangling bond defects DB having a predetermined defect amount. In addition, it is preferable that impurities are ion-implanted not only into the gate insulating layer 150 located above the oxide semiconductor layer 140 but also into the oxide insulating layer 120 located below the oxide semiconductor layer 140 to form dangling bond defects DB. That is, by forming a hydrogen trapping region including dangling bond defects DB having a predetermined defect amount in the gate insulating layer 150 and the oxide insulating layer 120, the electrical characteristics of the semiconductor device 10 can be improved.

[0039] The peak of the impurity concentration profile may be in the second region 150-2 or in the fourth region 120-2. In Fig. 4, the concentration profile (a) has a peak in the second region 150-2, and the concentration profiles (b) to (d) have peaks in the fourth region 120-2.

[0040] In the fourth region 120-2, the impurity concentration at the position of +16 nm (i.e., the position 16 nm away from the interface in the film thickness direction of the oxide insulating layer 120) is 1×10 18 / cm 3 or more (see concentration profiles (a) to (d)), and preferably 5×10 18 / cm 3 (See concentration profiles (a) to (c)).

[0041] In the fourth region 120-2, the impurity concentration at a position of +40 nm (i.e., a position 40 nm away from the interface in the film thickness direction of the oxide insulating layer 120) is 1×10 16 / cm 3 More preferably, 1×10 17 / cm 3 More preferably, it is 1×10 18 / cm 3 That is all. All of the concentration profiles (a) to (d) shown in Fig. 4 satisfy the above range.

[0042] In the fourth region 120-2, the impurity concentration in the region from 0 nm to +40 nm (i.e., the region from the interface to a position 40 nm away in the film thickness direction of the oxide insulating layer 120) is 1×10 16 / cm 3 Preferably, in the fourth region, the impurity concentration in the region from 0 nm to +100 nm (i.e., the region from the interface to a position 100 nm away in the film thickness direction of the oxide insulating layer 120) is 1×10 16 / cm 3More preferably, in the fourth region, the impurity concentration in the region from 0 nm to +150 nm (i.e., the region from the interface to a position 150 nm away in the film thickness direction of the oxide insulating layer 120) is 1×10 16 / cm 3 That is all. All of the concentration profiles (a) to (d) shown in FIG. 4 satisfy the above range. When the thickness of the oxide insulating layer 120 is less than 100 nm, the thickness of the oxide insulating layer 120 may exceed the above range. In that case, it is sufficient that the total thickness of the oxide insulating layer 120 and the nitride insulating layer 110 is within the above range. That is, impurities may be implanted into the nitride insulating layer 110. However, the maximum impurity concentration in the nitride insulating layer 110 is not more than 1×10 19 / cm 3 It is preferable to adjust the doping conditions as follows:

[0043] When the impurity concentration in the fourth region 120-2 is within the above range, dangling bond defects DB having a sufficient amount of defects are formed in the gate insulating layer 150 and the oxide insulating layer 120. That is, the gate insulating layer 150 and the oxide insulating layer 120 include a hydrogen trapping region, and the electrical characteristics of the semiconductor device 10 can be improved.

[0044] The configuration of the semiconductor device 10 has been described above, but the semiconductor device 10 described above is a so-called top-gate type transistor. The semiconductor device 10 can be modified in various ways. For example, when the light-shielding layer 105 is conductive, the semiconductor device 10 may be configured such that the light-shielding layer 105 functions as a gate electrode, and the nitride insulating layer 110 and the oxide insulating layer 120 function as gate insulating layers. In this case, the semiconductor device 10 is a so-called dual-gate type transistor. When the light-shielding layer 105 is conductive, the light-shielding layer 105 may be a floating electrode or may be connected to the source electrode 201. Furthermore, the semiconductor device 10 may be a so-called bottom-gate type transistor in which the light-shielding layer 105 functions as a main gate electrode.

[0045] [3. Method for Manufacturing Semiconductor Device 10] A method for manufacturing the semiconductor device 10 according to one embodiment of the present invention will be described with reference to Fig. 5 to Fig. 13. Fig. 5 is a flowchart showing a method for manufacturing the semiconductor device 10 according to one embodiment of the present invention. Figs. 6 to 13 are schematic cross-sectional views showing a method for manufacturing the semiconductor device 10 according to one embodiment of the present invention.

[0046] 5, the method for manufacturing the semiconductor device 10 includes steps S1010 to S1120. Steps S1010 to S1120 will be described in order below, but the order of the steps may be reversed in the method for manufacturing the semiconductor device 10. Furthermore, the method for manufacturing the semiconductor device 10 may include additional steps.

[0047] In step S1010, a light-shielding layer 105 having a predetermined pattern is formed on the substrate 100 (see FIG. 6). The light-shielding layer 105 is patterned by using a photolithography method.

[0048] In step S1020, the nitride insulating layer 110 and the oxide insulating layer 120 are formed in this order on the light-shielding layer 105 (see FIG. 7). The nitride insulating layer 110 and the oxide insulating layer 120 are formed by using a CVD method. For example, a silicon nitride film and a silicon oxide film are formed as the nitride insulating layer 110 and the oxide insulating layer 120, respectively. The silicon nitride film and the silicon oxide film can also be formed successively in the same chamber by changing the reactive gas.

[0049] In a step described later, dangling bond defects having a hydrogen trapping function are formed in a predetermined region of the oxide insulating layer 120. Therefore, the oxide insulating layer 120 does not need to be a film containing excess oxygen that serves as a hydrogen trap, and is preferably a dense film with few defects that is formed at 350° C. or higher. When the oxide insulating layer 120 is a film containing excess oxygen, the reliability of the semiconductor device 10 is reduced. However, when the oxide insulating layer 120 is a dense film, the reliability of the semiconductor device 10 can be improved.

[0050] The thickness of the nitride insulating layer 110 is, for example, 50 nm to 500 nm, preferably 150 nm to 300 nm, and the thickness of the oxide insulating layer 120 is, for example, 50 nm to 500 nm, preferably 150 nm to 300 nm.

[0051] In step S1030, the oxide semiconductor film 145 is formed on the oxide insulating layer 120 (see FIG. 8). The oxide semiconductor film 145 is formed by a sputtering method. The thickness of the oxide semiconductor film 145 is, for example, 10 nm to 100 nm, preferably 15 nm to 70 nm, and more preferably 15 nm to 40 nm.

[0052] The oxide semiconductor film 145 in step S1030 is amorphous. .vinegar When the oxide semiconductor film 145 is formed by a sputtering method, the oxide semiconductor film 145 is formed while controlling the temperature of the object to be formed (the substrate 100 and the layer formed on the substrate 100) to 100° C. or less, preferably 80° C. or less, and more preferably 50° C. or less. The oxide semiconductor film 145 is formed under a condition of a low oxygen partial pressure. The oxygen partial pressure is 2% or more and 20% or less, preferably 3% or more and 15% or less, and more preferably 3% or more and 10% or less.

[0053] In step S1040, the oxide semiconductor film 145 is patterned (see FIG. 9). The oxide semiconductor film 145 is patterned by photolithography. The oxide semiconductor film 145 may be etched by wet etching or dry etching. In the wet etching, an acidic etchant may be used. For example, oxalic acid, PAN, sulfuric acid, hydrogen peroxide solution, or hydrofluoric acid may be used as the etchant. 。

[0054] In step S1050, a heat treatment is performed on the oxide semiconductor film 145. Hereinafter, the heat treatment performed in step S1050 is referred to as "OS annealing". In the OS annealing, the oxide semiconductor film 145 is held at a predetermined target temperature for a predetermined time. The predetermined target temperature is 300° C. or more and 500° C. or less, and preferably 350° C. or more and 450° C. or less. The holding time at the target temperature is 15 minutes or more and 120 minutes or less, and preferably 30 minutes or more and 60 minutes or less. The OS annealing crystallizes the oxide semiconductor film 145, and the oxide semiconductor layer 145 having a polycrystalline structure is formed. 0 is is formed.

[0055] In step S1060, the gate insulating layer 150 is formed on the oxide semiconductor layer 140 (see FIG. 10). The gate insulating layer 150 is formed by using a CVD method. For example, silicon oxide is formed as the gate insulating layer 150. In order to reduce defects in the gate insulating layer 150, the gate insulating layer 150 may be formed at a film formation temperature of 350° C. or higher. The thickness of the gate insulating layer 150 is 50 nm to 300 nm, preferably 60 nm to 200 nm, and more preferably 70 nm to 150 nm.

[0056] In step S1070, a heat treatment is performed on the oxide semiconductor layer 140. Hereinafter, the heat treatment performed in step S1070 is referred to as "oxidation annealing." When the gate insulating layer 150 is formed on the oxide semiconductor layer 140, many oxygen defects are generated on the upper surface and side surfaces of the oxide semiconductor layer 140. When oxidation annealing is performed in a state in which the oxide semiconductor layer 140 is surrounded by the oxide insulating layer 120 and the gate insulating layer 150, oxygen is supplied to the oxide semiconductor layer 140 through the oxide insulating layer 120 and the gate insulating layer 150, and the oxygen defects in the oxide semiconductor layer 140 are repaired.

[0057] In step S1080, a gate electrode 160 having a predetermined pattern is formed on the gate insulating layer 150 (see FIG. 11). The gate electrode 160 is formed by sputtering or atomic layer deposition, and the gate electrode 160 is patterned by photolithography.

[0058] In step S1090, a source region S and a drain region D are formed in the oxide semiconductor layer 140 (see FIG. 12). The source region S and the drain region D are formed by ion implantation. The ion implantation can be performed using an ion doping device or an ion implantation device. Specifically, impurities are implanted into the oxide semiconductor layer 140 through the gate insulating layer 150 using the gate electrode 160 as a mask. For example, boron (B), phosphorus (P), argon (Ar), nitrogen (N), or the like is used as the implanted impurity. In the source region S and the drain region D that do not overlap with the gate electrode 160, oxygen defects are generated by the ion implantation, and hydrogen is trapped in the generated oxygen defects. This reduces the resistance of the source region S and the drain region D. On the other hand, in the channel region that overlaps with the gate electrode 160, impurities are not implanted, so that oxygen defects are not generated and the resistance of the channel region CH does not decrease.

[0059] In step S1090, impurities are also implanted into the oxide insulating layer 120 through the gate insulating layer 150. Dangling bond defects DB are generated by ion implantation in the gate insulating layer 150 and the oxide insulating layer 120. The gate insulating layer 150 and the oxide insulating layer 120 also contain impurities such as boron (B), phosphorus (P), argon (Ar), or nitrogen (N).

[0060] In step S1100, a protective insulating layer 170 is formed on the gate insulating layer 150 and the gate electrode 160 (see FIG. 13). The protective insulating layer 170 is formed by using a CVD method. For example, a silicon oxide film and a silicon nitride film are formed as the protective insulating layer 170. The thickness of the protective insulating layer 170 is 50 nm or more and 500 nm or less.

[0061] Steps S1090 and S1100 will now be described in more detail with reference to Figures 15 and 16. Figures 15 and 16 are schematic cross-sectional views illustrating the hydrogen trapping function of second region 150-2 and fourth region 120-2 in a manufacturing method for semiconductor device 10 according to an embodiment of the present invention.

[0062] 15, when step S1090 is performed, a second region 150-2 and a fourth region 120-2 having dangling bond defects DB are formed in the gate insulating layer 150 and the oxide insulating layer 120, respectively. The positions and defect amounts of the dangling bond defects DB can be controlled by adjusting the process parameters of the ion implantation (e.g., dose amount, acceleration voltage, plasma power, etc.). The dose amount is 1×10 14 / cm 2 or more, preferably 5×10 14 / cm 2 More preferably, it is 1×10 15 / cm 2 However, the acceleration voltage is not limited thereto. The acceleration voltage is more than 10 keV, preferably 15 keV or more, and more preferably 20 keV or more. In the second region 150-2 and the fourth region 120-2, the dangling bond defects DB can trap hydrogen. That is, the second region 150-2 and the fourth region 120-2 can function as hydrogen trapping regions.

[0063] In order for the protective insulating layer 170 to have a function of preventing the diffusion of impurities from the outside, the protective insulating layer 170 is preferably a dense film with few defects formed at 350° C. or higher. The protective insulating layer 170 formed under the above-mentioned conditions usually contains a large amount of hydrogen. In addition, because the film formation temperature is high, hydrogen diffuses into the gate insulating layer 150 during the formation of the protective insulating layer 170. Therefore, if at least the gate insulating layer 150 does not have a hydrogen trapping region, hydrogen diffuses through the gate insulating layer 150 to the source region S and drain region D of the oxide semiconductor layer 140 as well as the channel region CH.

[0064] 16, in step S1100, when the second region 150-2 and the fourth region 120-2 are formed in the gate insulating layer 150 and the oxide insulating layer 120, respectively, dangling bond defects DB in the second region 150-2 and the fourth region 120-2 trap hydrogen diffused from the protective insulating layer 170 during the formation of the protective insulating layer 170. Therefore, in step S1100, it is possible to suppress the intrusion of hydrogen into the channel region CH of the oxide semiconductor layer 140. In addition, since a dense film containing hydrogen can be used as the protective insulating layer 170, a sufficient amount of hydrogen can be supplied to the source region S and the drain region D containing oxygen defects.

[0065] As described above, by forming hydrogen trapping regions in the gate insulating layer 150 and the oxide insulating layer 120 in step S1090, it is possible to suppress the intrusion of hydrogen into the channel region CH in steps S1100 and after. On the other hand, it is possible to supply a sufficient amount of hydrogen to oxygen defects in the source region S and the drain region D. Therefore, Since the variation due to the process is reduced, it is possible to suppress the variation in the electrical characteristics of the semiconductor device 10. In other words, the manufacturing yield of the semiconductor device is improved.

[0066] Returning to FIG. 5 again, step S1110 and subsequent steps will be described.

[0067] In step S1110, openings 171 and 173 are formed in the gate insulating layer 150 and the protective insulating layer 170 (see FIG. 14). By forming the openings 171 and 173, the source region S and the drain region D of the oxide semiconductor layer 140 are exposed.

[0068] In step S1120, the source electrode 201 is formed on the protective insulating layer 170 and inside the opening 171, and the drain electrode 203 is formed on the protective insulating layer 170 and inside the opening 173. The source electrode 201 and the drain electrode 203 are formed as the same layer. Specifically, the source electrode 201 and the drain electrode 203 are formed by patterning one conductive film that has been deposited. Through the above steps, the semiconductor device 10 shown in FIG. 1 is manufactured.

[0069] Although the manufacturing method of the semiconductor device 10 has been described above, the manufacturing method of the semiconductor device 10 is not limited to this. For example, a step of injecting impurities into the protective insulating layer 170 may be included. Here, the step of injecting impurities into the protective insulating layer 170 will be described with reference to Fig. 17. Fig. 17 is a schematic cross-sectional view illustrating the hydrogen trapping function of the protective insulating layer 170 in the manufacturing method of the semiconductor device 10 according to one embodiment of the present invention.

[0070] As shown in FIG. 17, when impurities are implanted into the protective insulating layer 170, dangling bond defects DB are formed in the protective insulating layer 170. In this case, hydrogen is trapped not only in the dangling bond defects DB in the second region 150-2 and the fourth region 120-2 but also in the dangling bond defects DB in the protective insulating layer 170. That is, the protective insulating layer 170 has a hydrogen trapping function. Therefore, the dangling bond defects DB in the protective insulating layer 170 trap the hydrogen contained in the protective insulating layer 170, and it is possible to prevent the hydrogen from diffusing into the gate insulating layer 150. In addition, the protective insulating layer 170 can also trap hydrogen that has entered the protective insulating layer 170 from the outside. Since the diffusion of hydrogen to the channel region CH is prevented, the reliability of the semiconductor device 10 is further improved.

[0071] In the semiconductor device 10 according to this embodiment, hydrogen trapping regions are formed in the gate insulating layer 150 above the oxide semiconductor layer 140 and in the oxide insulating layer 120 below the oxide semiconductor layer 140. Therefore, in the semiconductor device 10, it is possible to suppress the intrusion of hydrogen into the channel region CH of the oxide semiconductor layer 140. Therefore, it is possible to sufficiently reduce the carrier concentration in the channel region CH, and thus it is possible to suppress the variation in threshold voltage in the electrical characteristics of the semiconductor device 10.

[0072] <Second embodiment> A semiconductor device 10A according to one embodiment of the present invention will be described with reference to Fig. 18. Fig. 18 is a schematic plan view showing the configuration of the semiconductor device 10A according to one embodiment of the present invention. Note that when the configuration of the semiconductor device 10A is similar to that of the semiconductor device 10, the description of the configuration of the semiconductor device 10A may be omitted.

[0073] As shown in FIG. 18, the semiconductor device 10A includes a light-shielding layer 105A, an oxide semiconductor layer 140A, a gate electrode 160A, a source electrode 201A, and a drain electrode 203A. A nitride insulating layer and an oxide insulating layer are formed between the light-shielding layer 105A and the oxide semiconductor layer 140A. A gate insulating layer is formed between the oxide semiconductor layer 140A and the gate electrode 160A. A protective insulating layer is formed between the gate electrode 160A and the source electrode 201A and between the gate electrode 160A and the drain electrode 203A. The nitride insulating layer, the oxide insulating layer, the gate insulating layer, and the protective insulating layer are similar to the nitride insulating layer 110, the oxide insulating layer 120, the gate insulating layer 150, and the protective insulating layer 170 described in the first embodiment, respectively, and therefore their description will be omitted.

[0074] The gate insulating layer and the protective insulating layer are provided with openings 171A and 173A. The source electrode 201A is electrically connected to the source region S of the oxide semiconductor layer 140A through the opening 171A. Similarly, the drain electrode 203A is electrically connected to the drain region D of the oxide semiconductor layer 140A through the opening 173A. The planar shape of the gate electrode 160A on the oxide semiconductor layer 140A is U-shaped. In the planar view, the source electrode 201A is disposed inside the U-shape, and the drain electrode 203A is disposed outside the U-shape. In the channel region CH, the width of the gate electrode 160A is the channel length L, and the length of the gate electrode 160A along the U-shape is the channel width W. As shown in FIG. 18, in the semiconductor device 10A, the channel width W can be made larger than the channel length L, so that the current can be increased.

[0075] In the semiconductor device 10A, impurity ions are implanted through the gate insulating layer using the gate electrode 160A as a mask, and hydrogen trapping regions are formed in the gate insulating layer and the oxide insulating layer. Therefore, hydrogen that penetrates into the oxide semiconductor layer 140A can be suppressed, and the semiconductor device 10A has small variations in electrical characteristics. In particular, variations in threshold voltage in the electrical characteristics can be suppressed. EXAMPLES

[0076] The semiconductor device 10 will be described in further detail based on a fabricated sample.

[0077] [1. Differences with and without ion implantation] [1-1. Preparation of Example Samples] As samples of Example 1 and Example 2, semiconductor devices were fabricated using the manufacturing method described in the first embodiment. That is, in Example 1 and Example 2, boron ion implantation was performed through the gate insulating layer 150 in the manufacture of the semiconductor device. Example 1 Acid The oxide semiconductor layer had an amorphous structure before the OS annealing, but was crystallized after the OS annealing to have a polycrystalline structure. .fruitThe oxide semiconductor layer of Example 2 has an amorphous structure even after OS annealing. Construction include.

[0078] [1-2. Preparation of Comparative Example Samples] As samples of Comparative Example 1 and Comparative Example 2, semiconductor devices were fabricated using the manufacturing method described in the first embodiment without ion implantation. . ratio The oxide semiconductor layer of Comparative Example 2 has an amorphous structure. Construction include.

[0079] [1-3. Electrical characteristics] FIG. 19 is a graph showing the electrical characteristics of the semiconductor devices of Example 1 and Example 2. FIG. 23 is a graph showing the electrical characteristics of the semiconductor devices of Comparative Example 1 and Comparative Example 2. Each of the graphs shown in FIG. 19 and FIG. 23 shows the electrical characteristics of 26 samples having a channel width W / channel length L=4.5 μm / 3.0 μm. The vertical axis of the graph showing the electrical characteristics shows the drain current Id, and the horizontal axis shows the gate voltage Vg. The measurement conditions for the electrical characteristics of each sample are as shown in Table 1.

[0080] [Table 1]

[0081] As shown in Fig. 19, electrical characteristics with small variations in threshold voltage were obtained in the samples of Example 1 and Example 2. On the other hand, as shown in Fig. 23, in the sample of Comparative Example 1, the threshold voltage was shifted to the negative side, and electrical characteristics with large variations were obtained. Also, in the sample of Comparative Example 2, the threshold voltage could not be confirmed in the gate voltage range of -15V to +15V.

[0082] From the results of FIG. 19 and FIG. 23, regardless of whether the oxide semiconductor layer has a polycrystalline structure or an amorphous structure, when ion implantation is performed through the gate insulating layer, electrical characteristics are obtained that show switching performance in which the current increases sharply when the gate voltage is near 0V. On the other hand, when ion implantation is not performed through the gate insulating layer, electrical characteristics that show switching performance are not obtained. This is presumably because the insulating properties of the channel region are reduced due to an increase in the carrier concentration in the channel region of the oxide semiconductor layer. Unlike the samples of Example 1 and Example 2, in the samples of Comparative Example 1 and Comparative Example 2, no hydrogen trapping region is formed in the gate insulating layer and the oxide semiconductor layer by ion implantation. Therefore, it is considered that hydrogen easily penetrates into the channel region of the oxide semiconductor layer through the gate insulating layer and the oxide insulating layer. The penetrated hydrogen is trapped by oxygen defects in the channel region to generate carriers, and the carrier concentration in the channel region increases.

[0083] [2. Differences due to ion implantation conditions] [2-1. Preparation of Example Samples] As samples of Examples 3 to 14, semiconductor devices were fabricated using the manufacturing method described in the first embodiment. .fruit The samples of Examples 3 to 8 have Structure A. The samples of Examples 9 to 14 have Structure B. The conditions of Structure A and Structure B are as shown in Table 2.

[0084] [Table 2]

[0085] The conditions for the boron ion implantation through the gate insulating layer are as shown in Table 3. The boron concentration profile in each sample is shown in Fig. 20 and Fig. 21. Fig. 20 is a graph showing the boron concentration profile of the ion implantation performed in the fabrication of the semiconductor devices of Examples 3 to 8. Fig. 21 is a graph showing the boron concentration profile of the ion implantation performed in the fabrication of the semiconductor devices of Examples 9 to 14. In Figs. 20 and 21, the horizontal axis of the graph represents the distance from the interface between the gate insulating layer and the oxide insulating layer when the interface is set to 0 nm (the oxide insulating layer side is the positive direction and the gate insulating layer side is the negative direction), and the vertical axis of the graph represents the boron concentration.

[0086] [Table 3]

[0087] The concentration profiles of the samples of Examples 3 to 5 have a peak in the gate insulating layer. The concentration profiles of the samples of Examples 6 to 14 have a peak in the oxide insulating layer. In the samples of Examples 3 to 14, the boron concentration in the oxide insulating layer at a position 16 nm away from the interface between the gate insulating layer and the oxide insulating layer in the film thickness direction of the oxide insulating layer is 1×10 18 / cm 3 In the samples of Examples 3 to 14, the concentration of boron in the oxide insulating layer at a position 40 nm away from the interface between the gate insulating layer and the oxide insulating layer in the film thickness direction of the oxide insulating layer was 1×10 17 / cm 3 Thus, in the samples of Examples 3 to 14, the boron concentration in the region from the interface between the gate insulating layer and the oxide insulating layer to a position 40 nm away in the film thickness direction of the oxide insulating layer is 1×10 16 / cm 3 That's all.

[0088] The concentration of boron in the oxide insulating layer will be described in more detail. In the samples of Examples 3 to 14, the concentration of boron in the oxide insulating layer at a position 16 nm away from the interface between the gate insulating layer and the oxide insulating layer in the film thickness direction of the oxide insulating layer was 5×10 18 / cm 3 In particular, in the samples of Example 4, Example 5, Example 7, Example 8, Example 10, Example 11, Example 13, and Example 14, the concentration of boron in the oxide insulating layer at a position 16 nm away from the interface between the gate insulating layer and the oxide insulating layer in the film thickness direction of the oxide insulating layer is 2×10 19 / cm 3 In the samples of Examples 3 to 14, the concentration of boron in the oxide insulating layer at a position 40 nm away from the interface between the gate insulating layer and the oxide insulating layer in the film thickness direction of the oxide insulating layer was 1×10 18 / cm 3 In particular, in the samples of Example 4, Example 5, Example 7, Example 8, Example 13, and Example 14, the concentration of boron in the oxide insulating layer at a position 40 nm away from the interface between the gate insulating layer and the oxide insulating layer in the film thickness direction of the oxide insulating layer is 2×10 19 / cm 3 In the samples of Examples 3 to 8 and Examples 12 to 14, the boron concentration in the region from the interface between the gate insulating layer and the oxide insulating layer to a position 100 nm away in the film thickness direction of the oxide insulating layer is 1×10 16 / cm 3 In particular, in Examples 6 to 8, the boron concentration in the region from the interface between the gate insulating layer and the oxide insulating layer to a position 150 nm away in the film thickness direction of the oxide insulating layer is 1×10 16 / cm 3 That's all.

[0089] [2-2. Preparation of Comparative Example Samples] As samples of Comparative Example 3 to Comparative Example 8, semiconductor devices were fabricated under ion implantation conditions different from those of Example 3 to Example 14. The structures and ion implantation conditions of the samples of Comparative Example 3 to Comparative Example 8 are as shown in Table 4. The boron concentration profile of each sample is shown in Figs. 24 and 25. Fig. 24 is a graph showing the boron concentration profile of the ion implantation performed in the fabrication of the semiconductor devices of Comparative Examples 3 to 5. Fig. 25 is a graph showing the boron concentration profile of the ion implantation performed in the fabrication of the semiconductor devices of Comparative Examples 6 to 8. In Figs. 24 and 25, the horizontal axis of the graphs represents the distance from the interface between the gate insulating layer and the oxide insulating layer when the interface is set to 0 nm (the oxide insulating layer side is the positive direction and the gate insulating layer side is the negative direction), and the vertical axis of the graphs represents the boron concentration.

[0090] [Table 4]

[0091] The concentration profiles of the samples of Comparative Example 3 to Comparative Example 8 have a peak in the gate insulating layer. In the samples of Comparative Example 3 to Comparative Example 5, the boron concentration in the oxide insulating layer at a position 16 nm away from the interface between the gate insulating layer and the oxide insulating layer in the film thickness direction of the oxide insulating layer is 1×10 17 / cm 3 5×10 or more 18 / cm 3 In the samples of Comparative Example 6 to Comparative Example 8, the boron concentration in the oxide insulating layer at a position 16 nm away from the interface between the gate insulating layer and the oxide insulating layer in the film thickness direction of the oxide insulating layer is less than 1×10 16 / cm 3 In the samples of Comparative Example 3 to Comparative Example 8, the boron concentration in the oxide insulating layer at a position 40 nm away from the interface between the gate insulating layer and the oxide insulating layer in the film thickness direction of the oxide insulating layer is less than 1×10 16 / cm 3Therefore, in the samples of Comparative Example 3 to Comparative Example 8, the boron concentration in the region from the interface between the gate insulating layer and the oxide insulating layer to a position 40 nm away in the film thickness direction of the oxide insulating layer is less than 1×10 16 / cm 3 That's not all.

[0092] [2-3. Electrical characteristics] Fig. 22 is a graph showing the electrical characteristics of the semiconductor devices of Examples 3 to 14. Fig. 26 is a graph showing the electrical characteristics of the semiconductor devices of Comparative Examples 3 to 8. Each of the graphs shown in Fig. 22 and Fig. 26 shows the electrical characteristics of 26 samples having a channel width W / channel length L = 4.5 μm / 3.0 μm. The measurement conditions for the electrical characteristics of each sample are the same as those shown in Table 1.

[0093] As shown in Fig. 22, transistor characteristics with small variations in threshold voltage were obtained in the samples of Examples 3 to 14. On the other hand, as shown in Fig. 26, in the samples of Comparative Examples 3 to 8, the threshold voltage was shifted to the negative side, and electrical characteristics with large variations were obtained.

[0094] 22 and 26, it can be seen that when ion implantation is performed through the gate insulating layer, by implanting boron not only into the gate insulating layer but also to a certain depth into the oxide insulating layer, the variation in threshold voltage of the semiconductor device can be suppressed. In the samples of Examples 3 to 14, the hydrogen trapping region is formed deeper into the oxide insulating layer than in the samples of Comparative Examples 3 to 8. This is thought to have suppressed hydrogen from penetrating into the channel region of the oxide semiconductor layer through the oxide insulating layer.

[0095] The above-described embodiments of the present invention may be combined as appropriate as long as they are not mutually inconsistent. Furthermore, those in which a person skilled in the art appropriately adds or removes components or modifies designs, or adds or omits steps or modifies conditions based on the embodiments, are also included in the scope of the present invention as long as they include the gist of the present invention.

[0096] Even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, those which are clear from the description in this specification or which can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0097] 10, 10A: semiconductor device, 100: substrate, 105, 105A: light shielding layer, 110: nitride insulating layer, 120: oxide insulating layer, 120-1: third region, 120-2: fourth region, 140, 140A: oxide semiconductor layer, 145: oxide semiconductor film, 150: gate insulating layer, 150-1: first region, 150-2: second region, 160, 160A: gate electrode, 170: protective insulating layer, 171, 171A: opening, 173, 173A: opening, 200: source / drain electrode, 201, 201A: source electrode, 203, 203A: drain electrode

Claims

1. an oxide insulating layer; an oxide semiconductor layer on the oxide insulating layer; a gate insulating layer covering the oxide semiconductor layer and on the oxide insulating layer and the oxide semiconductor layer; a gate electrode on the gate insulating layer; a protective insulating layer over the gate insulating layer and the gate electrode, covering the gate electrode; The gate insulating layer is a first region overlapping the gate electrode; a second region that does not overlap the gate electrode and is in contact with the protective insulating layer; The oxide insulating layer is a third region overlapping the gate electrode; a fourth region that does not overlap with the gate electrode or the oxide semiconductor layer and is in contact with the gate insulating layer, The oxide semiconductor layer is A channel region; a source region and a drain region having a carrier concentration greater than that of the channel region; each of the source region, the drain region, and the second region includes an impurity; A semiconductor device, wherein the hydrogen concentration in the second region is greater than the hydrogen concentration in the first region.

2. the fourth region includes the impurity, 2. The semiconductor device according to claim 1, wherein the hydrogen concentration in said fourth region is greater than the hydrogen concentration in said third region.

3. In the fourth region, the concentration of the impurity at a position 16 nm away from the interface with the gate insulating layer in the film thickness direction of the oxide insulating layer is 1×10 １８ / cm ３ The semiconductor device according to claim 2 .

4. In the fourth region, the concentration of the impurity at a position 16 nm away from the interface with the gate insulating layer in the film thickness direction of the oxide insulating layer is 5×10 １８ / cm ３ The semiconductor device according to claim 2 .

5. In the fourth region, the concentration of the impurity at a position 40 nm away from the interface with the gate insulating layer in the film thickness direction of the oxide insulating layer is 1×10 １６ / cm ３ The semiconductor device according to claim 2 .

6. In the fourth region, the concentration of the impurity at a position 40 nm away from the interface with the gate insulating layer in the film thickness direction of the oxide insulating layer is 1×10 １７ / cm ３ The semiconductor device according to claim 2 .

7. In the fourth region, the concentration of the impurity at a position 40 nm away from the interface with the gate insulating layer in the film thickness direction of the oxide insulating layer is 1×10 １８ / cm ３ The semiconductor device according to claim 2 .

8. In the fourth region, the concentration of the impurity in a region from the interface with the gate insulating layer to a position 40 nm away in a film thickness direction of the oxide insulating layer is 1×10 １６ / cm ３ The semiconductor device according to claim 2 .

9. In the fourth region, the concentration of the impurity in a region from the interface with the gate insulating layer to a position 100 nm away in a film thickness direction of the oxide insulating layer is 1×10 １６ / cm ３ The semiconductor device according to claim 2 .

10. In the fourth region, the concentration of the impurity in a region from the interface with the gate insulating layer to a position 150 nm away in a film thickness direction of the oxide insulating layer is 1×10 １６ / cm ３ The semiconductor device according to claim 2 .

11. 11. The semiconductor device according to claim 1, wherein the impurity is one selected from the group consisting of boron, phosphorus, argon, and nitrogen.

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