Semiconductor device

Abstract

To provide a semiconductor device including a hydrogen trap region that prevents hydrogen from entering a channel region.SOLUTION: A semiconductor device includes an oxide insulating layer, an oxide semiconductor layer, a gate insulating layer, a gate electrode, and a protection insulating layer. The semiconductor device is sectioned into a first region overlapping with the gate electrode, a second region not overlapping with the gate electrode and overlapping with the oxide semiconductor layer, and a third region overlapping with neither the gate electrode nor the oxide semiconductor layer. In the first region, the gate insulating layer has a thickness of 200 nm or more. In the second region and the third region, the gate insulating layer has a thickness of 150 nm or less. The amount of impurities in the oxide semiconductor layer in the second region is greater than the amount of impurities in the oxide semiconductor layer in the first region. The amount of impurities in the oxide insulating layer in the third region is greater than the amount of impurities in the oxide insulating layer in the first region.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device using an oxide semiconductor as a channel.

Background Art

[0002] In recent years, development of semiconductor devices using an oxide semiconductor as a channel has been underway in place of silicon semiconductors such as amorphous silicon, low-temperature polysilicon, and single-crystalline silicon (see, for example, Patent Documents 1 to 6). Such a semiconductor device including an oxide semiconductor can be formed with a simple structure and a low-temperature process, similar to a thin-film transistor including amorphous silicon. Further, a semiconductor device including an oxide semiconductor is known to have a higher field-effect mobility than a semiconductor device including amorphous silicon.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Summary of the Invention

Problems to be Solved by the Invention

[0004] In an oxide semiconductor, carriers are generated when hydrogen binds to oxygen vacancies. By utilizing this mechanism, in a semiconductor device, oxygen vacancies are formed in an oxide semiconductor layer, and hydrogen is supplied to the formed oxygen vacancies, thereby forming source regions and drain regions that are low-resistance regions. On the other hand, when hydrogen diffuses into the channel region of the oxide semiconductor layer, the function as a channel of the semiconductor device deteriorates. Specifically, when hydrogen diffuses into the channel region, the threshold voltage in the electrical characteristics of the semiconductor device changes, so the variation in the threshold voltage increases and the manufacturing yield of the semiconductor device decreases. Therefore, by using an oxide layer containing excess oxygen that can trap hydrogen as an insulating layer in contact with the oxide semiconductor layer, the intrusion of hydrogen into the channel region is suppressed.

[0005] However, since the oxide layer containing excess oxygen functions as an electron trap, the reliability of a semiconductor device including such an oxide layer is significantly reduced. Therefore, there is a need for a semiconductor device that can suppress a decrease in reliability, supply hydrogen to the source region and drain region of the oxide semiconductor layer, and suppress the intrusion of hydrogen into the channel region of the oxide semiconductor layer.

[0006] One object of an embodiment of the present invention is to provide a semiconductor device including a hydrogen trap region that prevents the intrusion of hydrogen into a channel region in view of the above problems.

Means for Solving the Problems

[0007] A semiconductor device according to an embodiment of the present invention includes an oxide insulating layer, an oxide semiconductor layer on the oxide insulating layer, a gate insulating layer on the oxide semiconductor layer covering the oxide insulating layer and the oxide semiconductor layer, a gate electrode on the gate insulating layer, and a protective insulating layer on the gate insulating layer covering the gate insulating layer and the gate electrode. The semiconductor device is divided into a first region overlapping the gate electrode, a second region not overlapping the gate electrode and overlapping the oxide semiconductor layer, and a third region not overlapping the gate electrode and the oxide semiconductor layer. The thickness of the gate insulating layer in the first region is 200 nm or more. The thickness of the gate insulating layer in the second region and the third region is 150 nm or less. The amount of impurities contained in the oxide semiconductor layer in the second region is larger than the amount of impurities contained in the oxide semiconductor layer in the first region. The amount of impurities contained in the oxide insulating layer in the third region is larger than the amount of impurities contained in the oxide insulating layer in the first region.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Embodiments for Carrying Out the Invention

[0009] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The following disclosure is merely an example. Configurations that can be easily conceived by those skilled in the art by appropriately changing the configuration of the embodiment while maintaining the gist of the invention are naturally included in the scope of the present invention. The drawings are schematically represented in terms of the width, thickness, shape, etc. of each part compared to the actual aspect in order to make the explanation clearer. However, the illustrated shape is merely an example and does not limit the interpretation of the present invention. In this specification and each drawing, elements that are the same as those described above with respect to the previously shown drawings may be given the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0010] In each embodiment of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as up or upward. Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as down or downward. Thus, for the sake of convenience of explanation, the terms upward or downward are used for explanation. However, for example, the substrate and the oxide semiconductor layer may be arranged such that their vertical relationship is reversed from that shown in the drawings. In the following description, for example, the expression an oxide semiconductor layer on a substrate merely explains the vertical relationship between the substrate and the oxide semiconductor layer as described above, and other members may be disposed between the substrate and the oxide semiconductor layer. Upward or downward means the stacking order in a structure in which a plurality of layers are stacked. When referring to a pixel electrode above a transistor, in a plan view, the transistor and the pixel electrode may have a positional relationship in which they do not overlap. On the other hand, when referring to a pixel electrode directly above a transistor in a plan view, it means a positional relationship in which the transistor and the pixel electrode overlap.

[0011] In this specification, the term "film" and the term "layer" may be interchanged with each other in some cases.

[0012] The "display device" refers to a structure that displays an image using an electro-optical layer. For example, the term "display device" may refer to a display panel including an electro-optical layer, or may refer to a structure in which other optical members (for example, a polarizing member, a backlight, a touch panel, etc.) are attached to a display cell. The "electro-optical layer" may include a liquid crystal layer, an electroluminescence (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer as long as no technical contradiction occurs. Therefore, in the embodiments described below, a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer will be exemplified and described as display devices. However, the structure in the present embodiment can be applied to a display device including other electro-optical layers described above.

[0013] In this specification, expressions such as "α includes A, B, or C", "α includes any one of A, B, and C", "α includes one selected from the group consisting of A, B, and C", etc., do not exclude the case where α includes a plurality of combinations of A to C unless otherwise specified. Furthermore, these expressions do not exclude the case where α includes other elements.

[0014] Note that the following embodiments can be combined with each other as long as no technical contradiction occurs.

[0015] With reference to FIGS. 1 to 16, a semiconductor device according to an embodiment of the present invention will be described. The semiconductor device of the embodiment shown below may be used in an integrated circuit (IC) such as a micro - processing unit (MPU) or a memory circuit in addition to the transistor used in the display device.

[0016] [1. Configuration of Semiconductor Device 10] With reference to FIGS. 1 and 2, the configuration of a semiconductor device 10 according to an embodiment of the present invention will be described. FIG. 1 is a cross - sectional view showing an overview of the semiconductor device according to an embodiment of the present invention. FIG. 2 is a plan view showing an overview of the semiconductor device according to an embodiment of the present invention.

[0017] As shown in FIG. 1, the semiconductor device 10 is provided above the substrate 100. The semiconductor device 10 includes a light - shielding layer 105, a nitride insulating layer 110, an oxide insulating layer 120, an oxide semiconductor layer 140, a gate insulating layer 150, a gate electrode 160, insulating layers 170, 180, a source electrode 201, and a drain electrode 203. When the source electrode 201 and the drain electrode 203 are not particularly distinguished, they may be collectively referred to as the source - drain electrode 200.

[0018] The light-shielding layer 105 is provided on the substrate 100. The nitride insulating layer 110 and the oxide insulating layer 120 are provided on the substrate 100 and the light-shielding layer 105. The nitride insulating layer 110 covers the upper surface and the ends of the light-shielding layer 105. The oxide semiconductor layer 140 is provided on the oxide insulating layer 120. The oxide semiconductor layer 140 is patterned. A part of the oxide insulating layer 120 extends outside the pattern of the oxide semiconductor layer 140 beyond the ends of the oxide semiconductor layer 140.

[0019] In this embodiment, a configuration in which the oxide insulating layer 120 and the oxide semiconductor layer 140 are in contact is illustrated, but the configuration is not limited thereto. For example, a metal oxide layer may be provided between the oxide insulating layer 120 and the oxide semiconductor layer 140, and the gate insulating layer 150 may not be in contact with the oxide insulating layer 120. For example, as the metal oxide layer, a metal oxide mainly composed of aluminum may be used. Specifically, aluminum oxide may be used as the metal oxide layer.

[0020] The gate electrode 160 faces the oxide semiconductor layer 140 above the oxide semiconductor layer 140. The gate insulating layer 150 is provided between the oxide semiconductor layer 140 and the gate electrode 160. The gate insulating layer 150 is in contact with the oxide semiconductor layer 140. Among the main surfaces of the oxide semiconductor layer 140, the surface in contact with the gate insulating layer 150 is referred to as the upper surface 141. Among the main surfaces of the oxide semiconductor layer 140, the surface in contact with the oxide insulating layer 120 is referred to as the lower surface 142. The surface between the upper surface 141 and the lower surface 142 is referred to as the side surface 143. The gate insulating layer 150 covers the upper surface 141 and the side surface 143 of the oxide semiconductor layer 140 and is in contact with the oxide insulating layer 120 in a region outside the pattern of the oxide semiconductor layer 140 (a third region A3 described later). In other words, the gate insulating layer 150 covers the oxide semiconductor layer 140 and is provided on the oxide insulating layer 120 and the oxide semiconductor layer 140.

[0021] The insulating layer 170 is provided over the gate insulating layer 150 and the gate electrode 160. The insulating layer 170 covers the gate electrode 160. The insulating layer 180 is provided over the insulating layer 170. The insulating layers 170 and 180 are provided with openings 171 and 173 reaching the oxide semiconductor layer 140. The source electrode 201 is provided inside the opening 171. The source electrode 201 is in contact with the oxide semiconductor layer 140 at the bottom of the opening 171. The drain electrode 203 is provided inside the opening 173. The drain electrode 203 is in contact with the oxide semiconductor layer 140 at the bottom of the opening 173.

[0022] The light-shielding layer 105 functions as a light-shielding film for the oxide semiconductor layer 140. The nitride insulating layer 110 functions as a barrier film that shields impurities diffusing from the substrate 100 toward the oxide semiconductor layer 140. The light-shielding layer 105 may function as a bottom gate of the semiconductor device 10. In this case, the nitride insulating layer 110 and the oxide insulating layer 120 function as a gate insulating layer for the bottom gate.

[0023] The operation of the semiconductor device 10 is mainly controlled by the voltage supplied to the gate electrode 160. When the light-shielding layer 105 functions as a bottom gate, an auxiliary voltage is supplied to the light-shielding layer 105. However, the same voltage as that of the gate electrode 160 may be supplied to the light-shielding layer 105. On the other hand, when the light-shielding layer 105 is simply used as a light-shielding film, no specific voltage is supplied to the light-shielding layer 105, and the potential of the light-shielding layer 105 may be floating. Or, the light-shielding layer 105 may be an insulator.

[0024] The semiconductor device 10 is divided into a first region A1, a second region A2, and a third region A3 with reference to the patterns of the gate electrode 160 and the oxide semiconductor layer 140, respectively. The first region A1 is a region that overlaps the gate electrode 160 in plan view. The second region A2 is a region that does not overlap the gate electrode 160 in plan view and overlaps the oxide semiconductor layer 140. The third region A3 is a region that does not overlap both the gate electrode 160 and the oxide semiconductor layer 140 in plan view.

[0025] The thickness of the gate insulating layer 150 in the second region A2 and the third region A3 is smaller than the thickness of the gate insulating layer 150 in the first region A1. In other words, the thickness of the gate insulating layer 150 in the region that does not overlap with the gate electrode 160 in plan view is smaller than the thickness of the gate insulating layer 150 in the region that overlaps with the gate electrode 160. Although details will be described later, the thickness of the gate insulating layer 150 in the first region A1 is 200 nm or more. The thickness of the gate insulating layer 150 in the first region A1 may be 250 nm or more, or 300 nm or more. The thickness of the gate insulating layer 150 in the second region A2 and the third region A3 is 150 nm or less. The thickness of the gate insulating layer 150 in the second region A2 and the third region A3 may be 100 nm or less, 50 nm or less, or 30 nm or less. For example, by setting the thickness of the gate insulating layer 150 in the second region A2 and the third region A3 to be 50 nm or more and 100 nm or less, it is possible to ensure the hydrogen blocking function diffused from the insulating layer 170 while introducing sufficient impurities into the oxide insulating layer 120 by ion implantation.

[0026] The oxide semiconductor layer 140 is divided into a source region S, a drain region D, and a channel region CH with reference to the pattern of the gate electrode 160. The source region S and the drain region D are regions corresponding to the second region A2. The channel region CH is a region corresponding to the first region A1. In plan view, the end portions in the channel region CH coincide with the end portions of the gate electrode 160. The oxide semiconductor layer 140 in the channel region CH has semiconductor properties. Each oxide semiconductor layer 140 in the source region S and the drain region D has conductor properties. That is, the carrier concentration of the oxide semiconductor layer 140 in the source region S and the drain region D is higher than the carrier concentration of the oxide semiconductor layer 140 in the channel region CH. The source electrode 201 and the drain electrode 203 are in contact with the oxide semiconductor layer 140 in the source region S and the drain region D, respectively, and are electrically connected to the oxide semiconductor layer 140. The oxide semiconductor layer 140 may have a single-layer structure or a stacked structure.

[0027] In this embodiment, as the semiconductor device 10, a configuration in which a top-gate transistor having a gate electrode 160 provided above an oxide semiconductor layer 140 is used is exemplified, but the present invention is not limited to this configuration. For example, as described above, the semiconductor device 10 may be a dual-gate transistor in which a light-shielding layer 105 functions as a gate in addition to the gate electrode 160. Alternatively, the semiconductor device 10 may be a bottom-gate transistor in which the light-shielding layer 105 mainly functions as a gate. The above configuration is merely one embodiment, and the present invention is not limited to the above configuration.

[0028] In the D1 direction shown in FIG. 2, the width of the light-shielding layer 105 is larger than the width of the gate electrode 160. The D1 direction is the direction connecting the source electrode 201 and the drain electrode 203, and is the direction indicating the channel length L of the semiconductor device 10. Specifically, the length in the D1 direction in the region (channel region CH) where the oxide semiconductor layer 140 and the gate electrode 160 overlap is the channel length L, and the width in the D2 direction in the channel region CH is the channel width W. The light-shielding layer 105 and the gate electrode 160 extend in the D2 direction.

[0029] In FIG. 2, a configuration in which the source / drain electrodes 200 do not overlap the light-shielding layer 105 and the gate electrode 160 in a plan view is exemplified, but the present invention is not limited to this configuration. For example, in a plan view, the source / drain electrodes 200 may overlap at least one of the light-shielding layer 105 and the gate electrode 160. The above configuration is merely one embodiment, and the present invention is not limited to the above configuration.

[0030] [2. Materials of Each Member of Semiconductor Device 10] As the substrate 100, a rigid substrate having translucency, such as a glass substrate, a quartz substrate, and a sapphire substrate, is used. When the substrate 100 needs to have flexibility, as the substrate 100, a substrate containing a resin, such as a polyimide substrate, an acrylic substrate, a siloxane substrate, and a fluororesin substrate, is used. When a substrate containing a resin is used as the substrate 100, impurities may be introduced into the above resin in order to improve the heat resistance of the substrate 100. In particular, when the semiconductor device 10 is a top emission type display, since the substrate 100 does not need to be transparent, impurities that deteriorate the transparency of the substrate 100 may be used. When the semiconductor device 10 is used in an integrated circuit that is not a display device, as the substrate 100, a substrate that does not have translucency, such as a semiconductor substrate such as a silicon substrate, a silicon carbide substrate, and a compound semiconductor substrate, or a conductive substrate such as a stainless steel substrate, is used.

[0031] As the light-shielding layer 105, the gate electrode 160, and the source / drain electrodes 200, a general metal material is used. For example, as these members, for example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof are used. As the light-shielding layer 105, the gate electrode 160, and the source / drain electrodes 200, the above materials may be used in a single layer or in a stacked layer. When conductivity is not required for the light-shielding layer 105, materials other than the above metal materials may be used. For example, as the light-shielding layer 105, a black matrix such as a black resin may be used. The light-shielding layer 105 may have a single-layer structure or a stacked structure. For example, the light-shielding layer 105 may have a stacked structure of a red color filter, a green color filter, and a blue color filter.

[0032] As the nitride insulating layer 110, the oxide insulating layer 120, and the insulating layers 170 and 180, general insulating materials are used. For example, as the oxide insulating layer 120 and the insulating layer 180, silicon oxide (SiO x) Silicon oxynitride (SiO x N y ) Aluminum oxide (AlO x ) Aluminum oxynitride (AlO x N y ) and other inorganic insulating layers are used. As the nitride insulating layer 110 and the insulating layer 170, silicon nitride (SiN x ) Silicon oxynitride (SiN x O y ) Aluminum nitride (AlN x ) Aluminum oxynitride (AlN x O y ) and other inorganic insulating layers are used. However, as the insulating layer 170, silicon oxide (SiO x ) Silicon oxynitride (SiO x N y ) Aluminum oxide (AlO x ) Aluminum oxynitride (AlO x N y ) and other inorganic insulating layers may be used. As the insulating layer 180, silicon nitride (SiN x ) Silicon oxynitride (SiN x O y ) Aluminum nitride (AlN x ) Aluminum oxynitride (AlN x O y ) and other inorganic insulating layers may be used.

[0033] As the gate insulating layer 150, an insulating layer containing oxygen among the above insulating layers is used. For example, as the gate insulating layer 150, silicon oxide (SiO x ) Silicon oxynitride (SiO x N y ) Aluminum oxide (AlO x ) Aluminum oxynitride (AlO x N y ) and other inorganic insulating layers are used.

[0034] As the oxide insulating layer 120, an insulating layer having a function of releasing oxygen by heat treatment is used. That is, as the oxide insulating layer 120, an oxide insulating layer containing excess oxygen is used. The temperature of the heat treatment in which the oxide insulating layer 120 releases oxygen is, for example, 600 °C or lower, 500 °C or lower, 450 °C or lower, or 400 °C or lower. That is, the oxide insulating layer 120 releases oxygen at the heat treatment temperature performed in the manufacturing process of the semiconductor device 10 when a glass substrate is used as the substrate 100, for example. An insulating layer having a function of releasing oxygen by heat treatment may be used for at least one of the insulating layers 170 and 180, similarly to the oxide insulating layer 120.

[0035] As the gate insulating layer 150, an insulating layer with few defects is used. For example, when comparing the oxygen composition ratio in the gate insulating layer 150 with the oxygen composition ratio in an insulating layer having the same composition as the gate insulating layer 150 (hereinafter referred to as "other insulating layer"), the oxygen composition ratio in the gate insulating layer 150 is closer to the stoichiometric ratio for the insulating layer than the oxygen composition ratio in the other insulating layer. Specifically, when silicon oxide (SiO x ) is used for each of the gate insulating layer 150 and the insulating layer 180, the oxygen composition ratio in the silicon oxide used as the gate insulating layer 150 is closer to the stoichiometric ratio of silicon oxide than the oxygen composition ratio in the silicon oxide used as the insulating layer 180. For example, as the gate insulating layer 150, a layer in which no defects are observed when evaluated by the electron spin resonance method (ESR) may be used.

[0036] The above SiO x N y and AlO x N y are silicon compounds and aluminum compounds containing nitrogen (N) in a ratio less than that of oxygen (O) (x > y). SiN x O y and AlN x O y are silicon compounds and aluminum compounds containing oxygen in a ratio less than that of nitrogen (x > y).

[0037] As the oxide semiconductor layer 140, a metal oxide having semiconductor characteristics can be used. 。

[0038] Although a detailed manufacturing method of the oxide semiconductor layer 140 will be described later, the oxide semiconductor layer 140 can be formed by a sputtering method. The composition of the oxide semiconductor layer 140 formed by the sputtering method depends on the composition of the sputtering target. 。This In this case, the composition of the metal elements of the oxide semiconductor layer 140 can be specified based on the composition of the metal elements of the sputtering target.

[0039] When the oxide semiconductor layer 140 has a polycrystalline structure, the composition of the oxide semiconductor layer may be specified using an X-ray Diffraction (XRD) method. Specifically, based on the crystal structure and lattice constant of the oxide semiconductor layer obtained by the XRD method, the composition of the metal elements of the oxide semiconductor layer can be specified. Furthermore, the composition of the metal elements of the oxide semiconductor layer 140 can also be specified using fluorescent X-ray analysis or Electron Probe Micro Analyzer (EPMA) analysis, etc. However, since the oxygen element contained in the oxide semiconductor layer 140 varies depending on the process conditions of sputtering and the like, this is not always the case.

[0040] As described above, the oxide semiconductor layer 140 may have an amorphous structure or a polycrystalline structure. 。

[0041] As described above, when a metal oxide layer is provided between the oxide insulating layer 120 and the oxide semiconductor layer 140, a metal oxide mainly composed of aluminum is used as the metal oxide layer. For example, as the metal oxide layer, aluminum oxide (AlO x ), aluminum oxynitride (AlO x N y ), aluminum nitride oxide (AlN x O y ), aluminum nitride (AlN xAn inorganic insulating layer such as... is used. The "metal oxide layer mainly composed of aluminum" means that the ratio of aluminum contained in the metal oxide layer is 1% or more of the entire metal oxide layer. The ratio of aluminum contained in the metal oxide layer may be 5% or more and 70% or less, 10% or more and 60% or less, or 30% or more and 50% or less of the entire metal oxide layer. The above ratio may be a mass ratio or a weight ratio.

[0042] [3. Configuration of Hydrogen Trap Region] The hydrogen trap region is formed in the oxide insulating layer 120 and the gate insulating layer 150. Therefore, with reference to FIGS. 3 and 4, the configuration of the hydrogen trap region formed in the oxide insulating layer 120 and the gate insulating layer 150 will be described. FIG. 3 is a schematic partial enlarged cross-sectional view showing the configuration of a semiconductor device according to an embodiment of the present invention. Specifically, FIG. 3 is an enlarged cross-sectional view of region P in FIG. 1. The region P shown in FIG. 3 is a region near the drain region D, but the region near the source region S also has the same configuration as region P.

[0043] The oxide insulating layer 120 and the gate insulating layer 150 are divided into a first region A1, a second region A2, and a third region A3. The oxide insulating layer 120 in each region is denoted as oxide insulating layer 120-1, 120-2, 120-3, respectively. Similarly, the gate insulating layer 150 in each region is denoted as gate insulating layer 150-1, 150-2, 150-3, respectively. As described above, the thicknesses of the gate insulating layers 150-2 and 150-3 are smaller than the thickness of the gate insulating layer 150-1. The oxide insulating layers 120-1 and 120-2 are in contact with the oxide semiconductor layer 140. The oxide insulating layer 120-3 is in contact with the gate insulating layer 150-3. The gate insulating layer 150-1 is in contact with the oxide semiconductor layer 140 and the gate electrode 160 in the channel region CH. The gate insulating layer 150-2 is in contact with the oxide semiconductor layer 140 and the insulating layer 170 in the drain region D. The gate insulating layer 150-3 is located outside the drain region D and is in contact with the oxide insulating layer 120 and the insulating layer 170.

[0044] As will be described later, the oxide semiconductor layers 140 in the source region S and the drain region D are formed by ion implantation of impurities using the gate electrode 160 as a mask. As the impurities, for example, boron (B), phosphorus (P), argon (Ar), or nitrogen (N) is used. By ion implantation, oxygen defects are generated in the oxide semiconductor layers 140 in the source region S and the drain region D. When hydrogen is trapped in the generated oxygen defects, the oxide semiconductor layers 140 in the source region S and the drain region D are made to have a lower resistance. Since the silicon nitride layer contains more hydrogen than the silicon oxide layer, for example, when silicon nitride is used as the insulating layer 170, the oxide semiconductor layers 140 in the source region S and the drain region D can be made to have a lower resistance.

[0045] Since the ion implantation is performed through the gate insulating layer 150, dangling bond defects DB are generated in the gate insulating layer 150 by the ion implantation. In the second region A2, the ion-implanted impurities reach the oxide insulating layer 120 beyond the gate insulating layer 150 and the oxide semiconductor layer 140. Similarly, in the third region A3, the ion-implanted impurities reach the oxide insulating layer 120 beyond the gate insulating layer 150. Therefore, dangling bond defects DB are also generated in the oxide insulating layer 120 in the second region A2 and the third region A3.

[0046] Since the ion implantation of impurities is performed using the gate electrode 160 as a mask, in the first region A1, the impurities are not implanted into the oxide insulating layer 120-1 and the gate insulating layer 150-1, and dangling bond defects DB are not generated in these insulating layers. On the other hand, as described above, dangling bond defects DB are generated in the oxide insulating layers 120-2, 120-3 and the gate insulating layers 150-2, 150-3. For example, when silicon oxide is used as the gate insulating layer 150 and the oxide insulating layer 120, silicon dangling bond defects DB are formed in the oxide insulating layers 120-2, 120-3 and the gate insulating layers 150-2, 150-3.

[0047] The dangling bond defects DB formed in the oxide insulating layer 120 and the gate insulating layer 150 trap hydrogen. That is, in the semiconductor device 10, the oxide insulating layers 120-2, 120-3 and the gate insulating layers 150-2, 150-3 function as hydrogen trap regions. Therefore, for example, since hydrogen diffused from the insulating layer 170 during the film formation of the insulating layer 170 is trapped by the dangling bond defects DB in these insulating layers, it is possible to suppress hydrogen from entering the oxide semiconductor layer 140 in the channel region CH. Therefore, in the state after the insulating layer 170 is formed, the hydrogen concentration in the oxide insulating layers 120-2, 120-3 is higher than the hydrogen concentration in the oxide insulating layer 120-1. Similarly, the hydrogen concentration in the gate insulating layers 150-2, 150-3 is higher than the hydrogen concentration in the gate insulating layer 150-1.

[0048] Since the above-mentioned dangling bond defects DB are formed by ion implantation, the oxide insulating layers 120-2, 120-3 and the gate insulating layers 150-2, 150-3 contain impurities introduced by ion implantation. The distribution of the amount of the dangling bond defects DB formed in the oxide insulating layers 120-2, 120-3 and the gate insulating layers 150-2, 150-3 corresponds to the concentration profiles of the impurities contained therein. That is, by adjusting the profile of the impurities obtained by ion implantation, the position and amount of the dangling bond defects DB can be adjusted.

[0049] Although details will be described later, in order to suppress the occurrence of abnormalities in the electrical characteristics of the semiconductor device 10 due to hydrogen entering the oxide semiconductor layer 140 in the channel region CH, it is effective to form the dangling bond defects DB in the oxide insulating layer 120. Therefore, it is necessary to implant impurities so as to reach the oxide insulating layer 120 through the gate insulating layer 150.

[0050] For example, in the case of a semiconductor device that requires high-voltage resistance for the gate insulating layer, the thickness of the gate insulating layer 150 is required to be 200 nm or more. On the other hand, when impurities are made to reach the oxide insulating layer 120 by ion implantation, since there is a limit due to the acceleration voltage of the ion implantation apparatus, the thickness of the gate insulating layer 150 is required to be 150 nm or less. In order to satisfy these requirements, a configuration in which the thicknesses of the gate insulating layers 150-2 and 150-3 are smaller than the thickness of the gate insulating layer 150-1 is adopted.

[0051] FIG. 4 is a graph showing impurity concentration profiles in the first region A1 to the third region A3 in a semiconductor device according to an embodiment of the present invention. The vertical axis of each of the three concentration profiles shown in FIG. 4 indicates the concentration of impurities per unit volume (Concentration [ / cm3]), and the horizontal axis indicates the name of the layer in the depth direction. "UC" on the horizontal axis corresponds to the oxide insulating layer 120 and the nitride insulating layer 110. "OS" corresponds to the oxide semiconductor layer 140. "GI" corresponds to the gate insulating layer 150. "GL" corresponds to the gate electrode 160. "PAS" corresponds to the insulating layer 170.

[0052] As shown in FIG. 4, in the first region A1, the impurity concentration profile has a peak in the gate electrode 160 (GL). Therefore, in the depth direction in the first region A1, the amount of impurities contained in a predetermined position of the gate electrode 160 is more than each of the amount of impurities contained in a predetermined position of the gate insulating layer 150, the amount of impurities contained in a predetermined position of the oxide semiconductor layer 140, and the amount of impurities contained in a predetermined position of the oxide insulating layer 120. The above-mentioned "depth direction" means the thickness direction of each layer. The metal material has a high stopping power for impurities introduced by ion implantation. When a metal material is used as the gate electrode 160, the impurities are blocked by the gate electrode 160 and do not reach the gate insulating layer 150 (GI). Therefore, no dangling bond defect DB due to the introduction of impurities is formed in the gate insulating layer 150 and the oxide insulating layer 120 in the first region A1. However, as long as it does not affect the electrical characteristics of the semiconductor device 10, the impurities may reach the gate insulating layer 150.

[0053] In the second region A2, the impurity concentration profile has a peak in the oxide semiconductor layer 140 (OS). Therefore, in the depth direction in the second region A2, the amount of impurities contained in a predetermined position of the oxide semiconductor layer 140 is more than the amount of impurities contained in a predetermined position of the gate insulating layer 150 and more than each of the amount of impurities contained in a predetermined position of the oxide insulating layer 120. The purpose of introducing the impurities is to reduce the resistance of the oxide semiconductor layer 140 in the source region S and the drain region D, so the ion implantation conditions are set so as to obtain the above-mentioned concentration profile. The amount of impurities contained in the oxide semiconductor layer 140 in the second region A2 is more than the amount of impurities contained in the oxide semiconductor layer 140 in the first region A1. Similarly, the amount of impurities contained in the oxide insulating layer 120 (UC) in the second region A2 is more than the amount of impurities contained in the oxide insulating layer 120 in the first region A1. Similarly, the amount of impurities contained in the gate insulating layer 150 (GI) in the second region A2 is more than the amount of impurities contained in the gate insulating layer 150 in the first region A1.

[0054] Due to the impurity concentration profile as described above, impurities are also introduced into the gate insulating layer 150 and the oxide insulating layer 120 in the second region A2. Therefore, dangling bond defects DB associated with the introduction of impurities are formed in the gate insulating layer 150 and the oxide insulating layer 120. However, in the second region A2, the concentration of impurities present in the gate insulating layer 150 and the oxide insulating layer 120 is lower than the concentration of impurities present in the oxide semiconductor layer 140.

[0055] In the third region A3, the impurity concentration profile has a peak in the oxide insulating layer 120 (UC). Therefore, in the depth direction in the third region A3, the amount of impurities contained in a predetermined position of the oxide insulating layer 120 is larger than the amount of impurities contained in a predetermined position of the gate insulating layer 150. The oxide semiconductor layer 140 is not provided on the oxide insulating layer 120 in the third region A3. Further, in the second region A2 and the third region A3, the thickness of the gate insulating layer 150 is the same. As a result, instead of a peak in the concentration profile existing in the oxide semiconductor layer 140 in the second region A2, a peak in the concentration profile exists in the oxide insulating layer 120 in the third region A3. That is, the amount of impurities contained in the oxide insulating layer 120 in the third region A3 is larger than the amount of impurities contained in the oxide insulating layer 120 in the first region A1, and is larger than the amount of impurities contained in the oxide insulating layer 120 in the second region A2. Similarly, the amount of impurities contained in the gate insulating layer 150 in the third region A3 is larger than the amount of impurities contained in the gate insulating layer 150 in the first region A1, and is equivalent to the amount of impurities contained in a predetermined position of the gate insulating layer 150 in the depth direction in the second region A2.

[0056] Due to the impurity concentration profile as described above, dangling bond defects DB associated with the introduction of impurities are formed in the oxide insulating layer 120. As described above, since there is a peak in the concentration profile in the oxide insulating layer 120 in the third region A3, the amount of dangling bond defects DB present in the oxide insulating layer 120 in the third region A3 is greater than the amount of dangling bond defects DB present in the oxide insulating layer 120 in the second region A2. Therefore, the oxide insulating layer 120 in the third region A3 can trap more hydrogen than the gate insulating layer 150 in the third region A3 and can trap more hydrogen than the oxide insulating layer 120 in the second region A2.

[0057] In this embodiment, in the depth direction in the third region A3, the amount of impurities contained at a predetermined position in the oxide insulating layer 120 is 1×10 16 / cm 3 or more, 1×10 17 / cm 3 or more, or 1×10 18 / cm 3 or more. The predetermined position may be the position of the peak of the concentration profile or may be the position corresponding to the interface between the oxide insulating layer 120 and the gate insulating layer 150. Alternatively, the predetermined position may be a position that has moved a predetermined depth in the direction of the oxide insulating layer 120 from the position corresponding to the interface.

[0058] In this embodiment, a configuration is exemplified in which the amount of impurities contained in the oxide insulating layer 120 in the third region A3 is larger than the amount of impurities contained in the oxide insulating layer 120 in the second region A2, but the configuration is not limited thereto. Similarly, in this embodiment, a configuration is exemplified in which the peak of the impurity concentration profile in the third region A3 exists in the oxide insulating layer 120, but the configuration is not limited thereto. The peak may exist in the gate insulating layer 150. That is, in the third region A3, the amount of impurities contained in the oxide insulating layer 120 may be less than the amount of impurities contained in the gate insulating layer 150. In this case, the peak of the impurity concentration profile in the second region A2 also exists in the gate insulating layer 150. That is, in the second region A2, the amount of impurities contained in the oxide semiconductor layer 140 may be less than the amount of impurities contained in the gate insulating layer 150.

[0059] Referring to FIG. 2, the channel region CH corresponds to the first region A1, the source region S and the drain region D correspond to the second region A2, and the region other than the channel region CH, the source region S, and the drain region D corresponds to the third region A3. That is, the channel region CH is sandwiched by the second regions A2 and surrounded by the third region A3. Therefore, for example, hydrogen diffused from the insulating layer 170 during the film formation of the insulating layer 170 is trapped by the dangling bond defects DB formed in the gate insulating layer 150 and the oxide insulating layer 120 provided in the second region A2 and the third region A3 located around the channel region CH. As a result, it is possible to suppress the hydrogen from entering the oxide semiconductor layer 140 in the channel region CH.

[0060] [4. Manufacturing Method of Semiconductor Device 10] With reference to FIGS. 5 to 13, a manufacturing method of a semiconductor device 10 according to an embodiment of the present invention will be described. FIG. 5 is a sequence diagram showing a manufacturing method of a semiconductor device according to an embodiment of the present invention. FIGS. 6 to 13 are cross-sectional views showing a manufacturing method of a semiconductor device according to an embodiment of the present invention.

[0061] As shown in FIGS. 5 and 6, a light-shielding layer 105 is formed on a substrate 100, and a nitride insulating layer 110 and an oxide insulating layer 120 are formed on the light-shielding layer 105 (``insulating layer / light-shielding layer formation'' in step S1001 of FIG. 5). As the nitride insulating layer 110, for example, silicon nitride is formed. As the oxide insulating layer 120, for example, silicon oxide is formed. The nitride insulating layer 110 and the oxide insulating layer 120 are formed by a CVD (Chemical Vapor Deposition) method. For example, the thickness of the nitride insulating layer 110 is 50 nm or more and 500 nm or less, or 150 nm or more and 300 nm or less. The thickness of the oxide insulating layer 120 is 50 nm or more and 500 nm or less, or 150 nm or more and 300 nm or less.

[0062] By using silicon nitride as the nitride insulating layer 110, the nitride insulating layer 110 can block impurities that diffuse from the substrate 100 side toward the oxide semiconductor layer 140, for example. For example, the silicon oxide used as the oxide insulating layer 120 is silicon oxide having a physical property of releasing oxygen by heat treatment.

[0063] As shown in FIGS. 5 and 7, an oxide semiconductor layer 140 is formed on the oxide insulating layer 120 (``OS film formation'' in step S1002 of FIG. 5). The oxide semiconductor layer 140 is formed by a sputtering method or an atomic layer deposition method (ALD: Atomic Layer Deposition).

[0064] When a metal oxide layer mainly composed of aluminum is provided between the oxide insulating layer 120 and the oxide semiconductor layer 140, the metal oxide layer is also formed by the sputtering method or the atomic layer deposition method as described above.

[0065] The thickness of the oxide semiconductor layer 140 is, for example, 10 nm or more and 100 nm or less, 15 nm or more and 70 nm or less, or 20 nm or more and 40 nm or less. In the present embodiment, the thickness of the oxide semiconductor layer 140 is 30 nm. The oxide semiconductor layer 140 before heat treatment (OS annealing) described later is amorphous.

[0066] example For example, when the oxide semiconductor layer 140 is formed by a sputtering method, the oxide semiconductor layer 140 is formed while controlling the temperature of the object to be film-formed (the substrate 100 and the structure formed thereon).

[0067] When film formation is performed on the object to be film-formed by a sputtering method, ions generated in the plasma and atoms rebounded by the sputtering target collide with the object to be film-formed. Therefore, the temperature of the object to be film-formed rises with the film formation process. 。Above In order to control the temperature of the object to be film-formed as described above, for example, film formation can be performed while cooling the object to be film-formed. For example, the object to be film-formed can be cooled from the surface opposite to the film-formed surface so that the temperature of the film-formed surface of the object to be film-formed (hereinafter referred to as "film formation temperature") becomes 100°C or lower, 70°C or lower, 50°C or lower, or 30°C or lower. 。Acid The oxygen partial pressure in the film formation conditions of the oxide semiconductor layer 140 is 2% or more and 20% or less, 3% or more and 15% or less, or 3% or more and 10% or less.

[0068] As shown in FIGS. 5 and 8, a pattern of the oxide semiconductor layer 140 is formed (the "OS pattern formation" in step S1003 of FIG. 5). Although not shown, a resist mask is formed on the oxide semiconductor layer 140, and the oxide semiconductor layer 140 is etched using the resist mask. As the etching of the oxide semiconductor layer 140, wet etching may be used, or dry etching may be used. As the wet etching, etching can be performed using an acidic etchant. As the etchant, for example, oxalic acid, PAN, sulfuric acid, hydrogen peroxide water, or hydrofluoric acid can be used. 。

[0069] After the patterning of the oxide semiconductor layer 140, a heat treatment (OS annealing) is performed on the oxide semiconductor layer 140 (the "OS annealing" in step S1004 of FIG. 5). In the OS annealing, the oxide semiconductor layer 140 is held at a predetermined reaching temperature for a predetermined time. The predetermined reaching temperature is 300°C or higher and 500°C or lower, or 350°C or higher and 450°C or lower. The holding time at the reaching temperature is 15 minutes or longer and 120 minutes or shorter, or 30 minutes or longer and 60 minutes or shorter. In this embodiment, the oxide semiconductor layer 140 is crystallized by this OS annealing. However, the oxide semiconductor layer 140 does not necessarily have to be crystallized by the OS annealing.

[0070] As shown in FIGS. 5 and 9, a gate insulating layer 150 is formed (the "GI formation" in step S1005 of FIG. 5). As the gate insulating layer 150, for example, silicon oxide is formed. The gate insulating layer 150 is formed by a CVD method. For example, in order to form an insulating layer with few defects as described above as the gate insulating layer 150, the gate insulating layer 150 may be formed at a film formation temperature of 350°C or higher. The thickness of the gate insulating layer 150 is, for example, 200 nm or more and 500 nm or less, 200 nm or more and 400 nm or less, or 250 nm or more and 350 nm or less. After forming the gate insulating layer 150, a process of implanting oxygen into the upper part of the gate insulating layer 150 may be performed. As the process of implanting oxygen, a configuration in which a metal oxide layer is formed on the gate insulating layer 150 by a sputtering method may be performed.

[0071] While the gate insulating layer 150 is formed on the oxide semiconductor layer 140, a heat treatment (oxidation annealing) is performed to supply oxygen to the oxide semiconductor layer 140 (the "oxidation annealing" in step S1006 of FIG. 5). In the process from when the oxide semiconductor layer 140 is formed until the gate insulating layer 150 is formed on the oxide semiconductor layer 140, many oxygen deficiencies occur on the upper surface 141 and the side surface 143 of the oxide semiconductor layer 140. By the above oxidation annealing, the oxygen released from the oxide insulating layer 120 and the gate insulating layer 150 is supplied to the oxide semiconductor layer 140, and the oxygen deficiencies are repaired. When the process of implanting oxygen into the gate insulating layer 150 is not performed, the oxidation annealing may be performed in a state where an insulating layer that releases oxygen by heat treatment is formed on the gate insulating layer 150.

[0072] In order to increase the amount of oxygen supplied from the gate insulating layer 150 to the oxide semiconductor layer 140, a metal oxide layer mainly composed of aluminum may be formed on the gate insulating layer 150 by a sputtering method, and the oxidation annealing may be performed in that state. As this metal oxide layer, aluminum oxide with high barrier properties against gas is used, so that the oxygen implanted into the gate insulating layer 150 during the oxidation annealing can be suppressed from diffusing outward. By the formation of the above metal oxide layer and the oxidation annealing, the oxygen implanted into the gate insulating layer 150 is efficiently supplied to the oxide semiconductor layer 140.

[0073] As shown in FIGS. 5 and 10, a gate electrode 160 is formed and a gate insulating layer 150 is half-etched ("GE formation + GI half-etching" in step S1007 of FIG. 5). The gate electrode 160 is formed by a sputtering method or an atomic layer deposition method and is patterned through a photolithography process. The gate electrode 160 and the gate insulating layer 150 may be etched in the same process (same conditions), or each may be etched in different processes (different conditions). That is, the half-etching of the gate insulating layer 150 may be performed by over-etching in the etching process for the gate electrode 160, or after the etching of the gate electrode 160, it may be performed by an etching different from the etching for the gate electrode 160 using the gate electrode 160 as a mask.

[0074] By the half-etching of the gate insulating layer 150, the thickness of the gate insulating layer 150 in the second region A2 and the third region A3 is thinned to 150 nm or less. The thickness of the gate insulating layer 150 after half-etching may be 100 nm or less, 50 nm or less, or 30 nm or less. In other words, the amount of half-etching of the gate insulating layer 150 is more than at least 50 nm. The amount of the half-etching may be more than 100 nm, more than 150 nm, or more than 170 nm. The thickness of the gate insulating layer 150 after half-etching is determined so that impurities reach the oxide insulating layer 120 by ion implantation described later.

[0075] As shown in FIG. 11, the gate electrode 160 is patterned, and impurity ions are implanted into the oxide semiconductor layer 140 in a state where the thickness of the gate insulating layer 150 in the second region A2 and the third region A3 is thinned to 150 nm or less by half etching ("impurity ion implantation" in step S1008 of FIG. 5). Specifically, using the gate electrode 160 as a mask, impurities are implanted into the oxide insulating layer 120, the oxide semiconductor layer 140, and the gate insulating layer 150 through the half-etched gate insulating layer 150. By ion implantation, elements such as boron (B), phosphorus (P), argon (Ar), or nitrogen (N) are implanted into the oxide insulating layer 120, the oxide semiconductor layer 140, and the gate insulating layer 150.

[0076] In the oxide semiconductor layer 140 in the second region A2 that does not overlap with the gate electrode 160, oxygen defects are generated by ion implantation. When hydrogen is trapped in the generated oxygen defects, the resistance of the oxide semiconductor layer 140 in the second region A2 decreases. On the other hand, in the oxide semiconductor layer 140 in the first region A1 that overlaps with the gate electrode 160, since no impurities are implanted, no oxygen defects are generated, and the resistance in the first region A1 does not decrease. Through the above process, a channel region CH is formed in the oxide semiconductor layer 140 in the first region A1, and a source region S and a drain region D are formed in the oxide semiconductor layer 140 in the second region A2.

[0077] By the above ion implantation, dangling bond defects DB are generated in the oxide insulating layer 120 and the gate insulating layer 150 in the second region A2 and the third region A3. The position and amount of the dangling bond defects DB can be controlled by adjusting the process parameters of ion implantation (for example, dose amount, acceleration voltage, plasma power, etc.). For example, the dose amount is 1×10 14 / cm 2 or more, 5×10 14 / cm 2 or more, or 1×10 15 / cm 2 or more. For example, the acceleration voltage is more than 10 keV, 15 keV or more, or 20 keV or more.

[0078] As shown in FIGS. 5 and 12, insulating layers 170 and 180 are formed as interlayer films on the gate insulating layer 150 and the gate electrode 160 (the "interlayer film formation" in step S1009 of FIG. 5). The insulating layers 170 and 180 are formed by CVD method. For example, a silicon nitride layer is formed as the insulating layer 170, and a silicon oxide layer is formed as the insulating layer 180. The materials used as the insulating layers 170 and 180 are not limited to the above. The thickness of the insulating layer 170 is 50 nm or more and 500 nm or less. The thickness of the insulating layer 180 is 50 nm or more and 500 nm or less.

[0079] As shown in FIGS. 5 and 13, openings 171 and 173 are formed in the gate insulating layer 150 and the insulating layers 170 and 180 (the "contact opening" in step S1010 of FIG. 5). The oxide semiconductor layer 140 in the source region S is exposed by the opening 171. The oxide semiconductor layer 140 in the drain region D is exposed by the opening 173. By forming the source / drain electrode 200 on the oxide semiconductor layer 140 exposed by the openings 171 and 173 and on the insulating layer 180 (the "SD formation" in step S1011 of FIG. 5), the semiconductor device 10 shown in FIG. 1 is completed.

[0080] [5. Hydrogen Traps in Dangling Bond Defects DB] Referring to FIGS. 4, 5, and 14, due to the ion implantation in step S1008, impurities are also implanted into the gate insulating layer 150 (GI) and the oxide insulating layer 120 (UC) in the second region A2 and the third region A3. By this ion implantation of impurities, dangling bond defects DB are generated in the gate insulating layer 150 and the oxide insulating layer 120 in the second region A2 and the third region A3. That is, the gate insulating layer 150 and the oxide insulating layer 120 contain impurities such as boron (B), phosphorus (P), argon (Ar), or nitrogen (N). In the case of this embodiment, among the gate insulating layer 150 and the oxide insulating layer 120 in the second region A2 and the third region A3, the amount of impurities contained in the oxide insulating layer 120 in the third region A3 is the largest. The amounts of impurities contained in the gate insulating layer 150 in the second region A2 and the third region A3 are the same. The dangling bond defects DB formed in the gate insulating layer 150 and the oxide insulating layer 120 when impurities are introduced as described above are schematically shown in FIG. 14.

[0081] In order for the insulating layer 170 to have the function of blocking the impurities diffused from above, the insulating layer 170 is preferably a dense film with few defects. In order to obtain such an insulating layer 170, it is necessary to form the insulating layer 170 at a high temperature. For example, when a silicon nitride layer is formed as the insulating layer 170 at a high temperature, the insulating layer 170 contains a large amount of hydrogen, and a large amount of hydrogen diffuses from the insulating layer 170 to the gate insulating layer 150 due to the film formation temperature. Therefore, if hydrogen trap regions are not formed in the gate insulating layer 150 and the oxide insulating layer 120, hydrogen diffuses not only to the oxide semiconductor layer 140 in the source region S and the drain region D but also to the oxide semiconductor layer 140 in the channel region CH through the gate insulating layer 150 and the oxide insulating layer 120.

[0082] In step S1008, when the dangling bond defect DB shown in FIG. 14 is formed in the gate insulating layer 150 and the oxide insulating layer 120, as shown in FIG. 15, hydrogen H diffused from the insulating layer 170 during the film formation of the insulating layer 170 is trapped by the dangling bond defect DB (a "circle" is superimposed on a "cross"). Therefore, in step S1009, it is possible to suppress hydrogen H diffused from the insulating layer 170 during or after the film formation from entering the oxide semiconductor layer 140 in the channel region CH. Therefore, since a film containing a large amount of hydrogen can be used as the insulating layer 170, an insulating layer 170 with a high impurity blocking function can be realized. Furthermore, the oxide semiconductor layers 140 in the source region S and the drain region D can be sufficiently reduced in resistance.

[0083] In the case of this embodiment, among the gate insulating layer 150 and the oxide insulating layer 120 in the second region A2 and the third region A3, the amount of hydrogen H trapped in the oxide insulating layer 120 in the third region A3 is the largest. The amounts of hydrogen H trapped in the gate insulating layers 150 in the second region A2 and the third region A3 are the same.

[0084] FIG. 16 is a schematic cross-sectional view for explaining the effect of hydrogen trapping and a diagram showing the electrical characteristics of a semiconductor device according to an embodiment of the present invention. The electrical characteristics shown in FIG. 16 show the results of investigating the influence of the location (layer) where hydrogen trapping is formed on the electrical characteristics. The electrical characteristics shown in FIG. 16(A) are the electrical characteristics when no (relatively few) hydrogen traps are formed in both the oxide insulating layer 120 and the gate insulating layer 150. The electrical characteristics shown in FIG. 16(B) are the electrical characteristics when hydrogen traps are formed only in the gate insulating layer 150. The electrical characteristics shown in FIG. 16(C) are the electrical characteristics when hydrogen traps are formed only in the oxide insulating layer 120.

[0085] The above hydrogen traps are not formed by ion implantation of impurities as in this embodiment, but are formed by pseudo-adjusting the film formation conditions of each insulating layer. In the configuration of FIG. 16, a silicon oxide layer is used as the oxide insulating layer 120 and the gate insulating layer 150. When a silicon oxide layer is formed under conditions containing an excessive amount of oxygen, it has been found that the silicon oxide layer contains many hydrogen traps. That is, under the conditions shown in FIG. 16(B), a silicon oxide layer containing an excessive amount of oxygen is used as the gate insulating layer 150. Under the conditions shown in FIG. 16(C), a silicon oxide layer containing an excessive amount of oxygen is used as the oxide insulating layer 120. In FIG. 16, it is the same as the configuration of FIG. 1 except that the gate insulating layer 150 in the region not overlapping with the gate electrode 160 is removed.

[0086] As shown in FIG. 16(A), when hydrogen traps are not formed in both the oxide insulating layer 120 and the gate insulating layer 150, a hump in the electrical characteristics is confirmed. It has been found that the hump in the electrical characteristics is generated when hydrogen during the formation of the insulating layer 170 penetrates into the oxide semiconductor layer 140 in the channel region CH. As shown in FIG. 16(B), when hydrogen traps are formed only in the gate insulating layer 150, the hump in the electrical characteristics is not improved. On the other hand, as shown in FIG. 16(C), when hydrogen traps are formed only in the oxide insulating layer 120, the hump in the electrical characteristics is reduced. From these results, it can be seen that it is important to form hydrogen traps in the oxide insulating layer 120 in order to suppress the penetration of hydrogen into the oxide semiconductor layer 140 in the channel region CH.

[0087] In this embodiment, as shown in FIGS. 2, 4, and 14, in the third region A3 surrounding the channel region CH, many dangling bond defects DB are formed in the oxide insulating layer 120, so that hydrogen can be prevented from penetrating into the oxide semiconductor layer 140 in the channel region CH. As a result, a semiconductor device 10 having electrical characteristics with suppressed humps can be obtained.

[0088] As long as the embodiments described above as embodiments of the present invention do not contradict each other, they can be implemented in appropriate combinations. Also, based on each embodiment, those in which a person skilled in the art has appropriately added, deleted, or changed the design of components, or added, omitted, or changed the conditions of the process, as long as they have the gist of the present invention, they are included in the scope of the present invention.

[0089] Even for other operational effects different from the operational effects brought about by the aspects of each of the above-described embodiments, those that are obvious from the description of this specification or can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention.

Description of Reference Numerals

[0090] 10: Semiconductor device, 100: Substrate, 105: Light-shielding layer, 110: Nitride insulating layer, 120: Oxide insulating layer, 140: Oxide semiconductor layer, 141: Upper surface, 142: Lower surface, 143: Side surface, 150: Gate insulating layer, 160: Gate electrode, 170: Insulating layer, 171: Opening, 173: Opening, 180: Insulating layer, 200: Source / drain electrode, 201: Source electrode, 203: Drain electrode, A1: First region, A2: Second region, A3: Third region, CH: Channel region, D: Drain region, DB: Dangling bond defect, S: Source region

Claims

1. an oxide insulating layer; an oxide semiconductor layer on the oxide insulating layer; a gate insulating layer covering the oxide semiconductor layer and on the oxide insulating layer and the oxide semiconductor layer; a gate electrode on the gate insulating layer; a protective insulating layer over the gate insulating layer and the gate electrode, covering the gate electrode; a first region overlapping the gate electrode; a second region that does not overlap the gate electrode and overlaps the oxide semiconductor layer; a third region that does not overlap the gate electrode and the oxide semiconductor layer; the thickness of the gate insulating layer in the first region is 200 nm or more; the thickness of the gate insulating layer in the second region and the third region is 150 nm or less; an amount of impurities contained in the oxide semiconductor layer in the second region is greater than an amount of the impurities contained in the oxide semiconductor layer in the first region; a quantity of the impurity contained in the oxide insulating layer in the third region is greater than a quantity of the impurity contained in the oxide insulating layer in the first region.

2. 2 . The semiconductor device according to claim 1 , wherein an amount of the impurity contained in the oxide insulating layer in the third region is greater than an amount of the impurity contained in the oxide insulating layer in the second region.

3. 3 . The semiconductor device according to claim 2 , wherein an amount of the impurity contained in the oxide insulating layer in the second region is greater than an amount of the impurity contained in the oxide insulating layer in the first region.

4. 4. The semiconductor device according to claim 3, wherein an amount of the impurity contained in the gate insulating layer in the second region and the third region is greater than an amount of the impurity contained in the gate insulating layer in the first region.

5. 2 . The semiconductor device according to claim 1 , wherein in the third region, a peak of a profile of the impurity in a thickness direction of the oxide insulating layer and the gate insulating layer is present in the oxide insulating layer.

6. 6. The semiconductor device according to claim 5, wherein in the second region, a peak of a profile of the impurity in a thickness direction of the oxide insulating layer, the oxide semiconductor layer, and the gate insulating layer is present in the oxide semiconductor layer.

7. 7. The semiconductor device according to claim 6, wherein in the first region, a peak of a profile of the impurity in a film thickness direction of the oxide insulating layer, the oxide semiconductor layer, the gate insulating layer, and the gate electrode is present in the gate electrode.

8. 2 . The semiconductor device according to claim 1 , wherein an amount of the impurity contained at a predetermined position in the third region in a depth direction is greater than an amount of the impurity contained at a predetermined position in the gate insulating layer.

9. 9. The semiconductor device according to claim 8, wherein, in a depth direction in the second region, an amount of the impurity contained at a predetermined position in the oxide semiconductor layer is greater than an amount of the impurity contained at a predetermined position in the gate insulating layer and is greater than an amount of the impurity contained at a predetermined position in the oxide insulating layer.

10. 10. The semiconductor device according to claim 9, wherein an amount of said impurity contained in said gate electrode at a predetermined position in a depth direction in said first region is greater than an amount of said impurity contained in said gate insulating layer at a predetermined position.

11. The semiconductor device according to claim 1 , wherein in the third region, the oxide insulating layer is in contact with the gate insulating layer, and the gate insulating layer is in contact with the protective insulating layer.

12. 12. The semiconductor device according to claim 1, wherein the thickness of said gate insulating layer in said second region and said third region is not less than 50 nm and not more than 100 nm.

Images