Trench gate type semiconductor device and manufacturing method for the same

Abstract

To provide a technique of reducing both the channel resistance and the contact resistance.SOLUTION: A trench gate type semiconductor device includes a semiconductor substrate, a first trench, a second trench, a gate insulating film, a gate electrode, and an upper electrode. The semiconductor substrate includes an n-type first semiconductor region in contact with the upper electrode, a p-type body region disposed below the first semiconductor region and extending from a position in contact with the gate insulating film in the first trench to a position in contact with the gate insulating film in the second trench, and an n-type second semiconductor region disposed below the body region and extending from the gate insulating film in the first trench to the position in contact with the gate insulating film in the second trench. A maximum value of the distance between the first trench and the second trench in a depth range where the body region is disposed is less than 200 nm. The distance between the first trench and the second trench on an upper surface of the semiconductor substrate is larger than the maximum value.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The technology disclosed in this specification relates to a trench gate type semiconductor device and a manufacturing method thereof. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device with a trench gate. This semiconductor device has a semiconductor substrate having a plurality of trenches spaced apart on its upper surface, a gate insulating film and a gate electrode disposed in the trenches, and an upper electrode covering the upper surface of the semiconductor substrate. The semiconductor substrate also has an n-type source region, a p-type body region, and an n-type drift region. The source region is disposed between the two trenches and contacts the upper electrode. The body region is disposed between the two trenches and extends from a position in contact with the gate insulating film in one trench to a position in contact with the gate insulating film in the other trench. The drift region is disposed between the two trenches, disposed below the body region, and separated from the source region by the body region.

[0003] In this semiconductor device, the distance between two adjacent trenches is relatively small, and when the semiconductor device is turned on, the substantially entire body region located between the trenches is inverted to form a channel. In this specification, the phenomenon in which the substantially entire body region functions as a channel when the semiconductor device is turned on is referred to as the FinFET effect. When the FinFET effect occurs, electrons flow even at positions away from the gate insulating film. Therefore, the electrons are less susceptible to scattering caused by the interface between the gate insulating film and the body region. Therefore, the mobility of electrons can be improved, and the channel resistance is reduced. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] British Patent No. 2572442 Summary of the Invention [Problem to be solved by the invention]

[0005] As described above, in the semiconductor device of Patent Document 1, the channel resistance can be reduced by narrowing the distance between two adjacent trenches. However, in the semiconductor device of Patent Document 1, since the distance between two adjacent trenches is small, it is difficult to ensure the contact area between the source region and the upper electrode. This causes a problem of high contact resistance. This specification provides a technology for reducing both the channel resistance and the contact resistance. [Means for solving the problem]

[0006] A trench-gate semiconductor device (10) disclosed in this specification comprises a semiconductor substrate (12), a first trench (22a) provided in an upper surface (12a) of the semiconductor substrate, a second trench (22b) provided in the upper surface of the semiconductor substrate at a distance from the first trench, a gate insulating film (24) covering the inner surfaces of the first trench and the second trench, gate electrodes (26) disposed in the first trench and the second trench and insulated from the semiconductor substrate by the gate insulating film, and an upper electrode (70) covering the upper surface of the semiconductor substrate. The semiconductor substrate has an n-type first semiconductor region (30) disposed between the first trench and the second trench and in contact with the upper electrode, a p-type body region (32) disposed between the first trench and the second trench, disposed below the first semiconductor region, and extending from a position in contact with the gate insulating film in the first trench to a position in contact with the gate insulating film in the second trench, and an n-type second semiconductor region (34) disposed between the first trench and the second trench, disposed below the body region, extending from the gate insulating film in the first trench to a position in contact with the gate insulating film in the second trench, and separated from the first semiconductor region by the body region. The maximum value of the interval between the first trench and the second trench in the depth range in which the body region is disposed is less than 200 nm. The interval between the first trench and the second trench at the upper surface of the semiconductor substrate is greater than the maximum value.

[0007] In the trench-gate semiconductor device, the body region extends from a position in contact with the gate insulating film in the first trench to a position in contact with the gate insulating film in the second trench. Also, the maximum value of the distance between the first trench and the second trench in the depth range in which the body region is located is less than 200 nm, which is sufficiently small to generate the FinFET effect. Therefore, when the semiconductor device is turned on, a channel is formed in almost the entire body region.

[0008] In addition, in the above trench gate type semiconductor device, the distance between the first trench and the second trench on the upper surface of the semiconductor substrate is greater than the maximum value. Therefore, the contact area between the first semiconductor region and the upper electrode is relatively large. Therefore, the contact resistance between the first semiconductor region and the upper electrode is small. As described above, this trench gate type semiconductor device can achieve low channel resistance and low contact resistance.

[0009] A method for manufacturing a trench-gate type semiconductor device (10) disclosed in the present specification includes the steps of: preparing a first substrate (60) having an n-type first semiconductor region (30) provided on an upper surface of an n-type substrate (50), a p-type body region (32) provided on the upper surface of the first semiconductor region, and an n-type second semiconductor region (34) provided on the upper surface of the body region; forming an amorphous layer (40) near an upper surface of the second semiconductor region; and forming a first trench (22a) and a second trench (22b), each of which reaches the first semiconductor region from the upper surface of the second semiconductor region, such that a maximum value of a distance between the first trench and the second trench in a depth range in which the body region is located is less than 200 nm, and a distance between the first trench and the second trench at the bottom of the first trench and the second trench is greater than the maximum value. the step of forming the first trench and the second trench; the step of forming a first insulating film (42, 44) covering an inner surface of the first trench and an inner surface of the second trench, a gate electrode (26) disposed in the first trench and the second trench, and a second insulating film (46) covering an upper surface of the gate electrode; the step of planarizing the upper surface of the second semiconductor region and the upper surface of the second insulating film so that the amorphous layer remains; the step of preparing an n-type second substrate (62) having an amorphous layer (48) formed near the upper surface; the step of bonding the first substrate and the second substrate so that the amorphous layer of the first substrate and the amorphous layer of the second substrate face each other; the step of grinding the first substrate from the n-type substrate side to expose the first semiconductor region and the first insulating film; and the step of forming an electrode (70) in contact with the exposed first semiconductor region.

[0010] Generally, it is relatively easy to form a trench whose width is narrower at the bottom than at the top, while it is difficult to form a trench whose width is wider at the bottom than at the top. In the above manufacturing method, each trench is formed in the first substrate so that the interval between the first trench and the second trench at the bottom of the first trench and the second trench is larger than the maximum interval between the first trench and the second trench in the depth range in which the body region is disposed. Then, the upper surface of the second substrate (the surface on which the amorphous layer is formed) is bonded to the trench formation surface of the first substrate (i.e., the surface on the second semiconductor region side). That is, the first substrate on which the trench is formed is bonded to the second substrate by turning it upside down. Thereafter, the surface opposite to the trench formation surface (i.e., the surface on the first substrate side of the bonded substrate) is ground to expose the first semiconductor region and the first insulating film in the trench. Then, an electrode is formed in contact with the exposed first semiconductor region. This makes it possible to obtain trenches in which the distance between the first trench and the second trench at the position where the electrode is contacted (the portion that was the bottom of the first trench and the second trench) is greater than the maximum value. This makes it possible to ensure the contact area between the first semiconductor region and the electrode. Furthermore, the first trench and the second trench are formed so that the maximum value is less than 200 nm. As a result, a semiconductor device having low channel resistance due to the FinFET effect and low contact resistance can be manufactured. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a cross-sectional view of a trench gate type semiconductor device according to an embodiment. [Diagram 2] 1A to 1C are diagrams for explaining a manufacturing process of a trench gate type semiconductor device. [Diagram 3] 1A to 1C are diagrams for explaining a manufacturing process of a trench gate type semiconductor device. [Figure 4] 1A to 1C are diagrams for explaining a manufacturing process of a trench gate type semiconductor device. [Diagram 5] 1A to 1C are diagrams for explaining a manufacturing process of a trench gate type semiconductor device. [Figure 6] 1A to 1C are diagrams for explaining a manufacturing process of a trench gate type semiconductor device. [Figure 7] 1A to 1C are diagrams for explaining a manufacturing process of a trench gate type semiconductor device. [Figure 8] 1A to 1C are diagrams for explaining a manufacturing process of a trench gate type semiconductor device. [Figure 9] 1A to 1C are diagrams for explaining a manufacturing process of a trench gate type semiconductor device. [Figure 10] 1A to 1C are diagrams for explaining a manufacturing process of a trench gate type semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] In the trench-gate semiconductor device disclosed in this specification as an example, a distance between the first trench and the second trench may decrease from the upper surface of the semiconductor substrate toward a lower side.

[0013] (Example) The trench-gate type semiconductor device 10 (hereinafter simply referred to as the semiconductor device 10) of the embodiment shown in FIG. 1 is a metal-oxide-semiconductor field effect transistor (MOSFET). The semiconductor device 10 has a semiconductor substrate 12. The semiconductor substrate 12 is made of silicon carbide (SiC). However, the material of the semiconductor substrate 12 is not particularly limited, and may be, for example, silicon (Si), gallium nitride (GaN), diamond, or the like. Hereinafter, one direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as the x-direction, a direction parallel to the upper surface 12a and perpendicular to the x-direction is referred to as the y-direction, and a thickness direction of the semiconductor substrate 12 is referred to as the z-direction.

[0014] A plurality of trenches 22 are provided on the upper surface 12a of the semiconductor substrate 12. Each trench 22 extends long in the y direction. Each trench 22 extends parallel to each other at intervals in the x direction. The inner surface of each trench 22 is covered with a gate insulating film 24. A gate electrode 26 made of, for example, polysilicon is disposed inside each trench 22. The gate insulating film 24 also covers the upper surface of the gate electrode 26. That is, the gate electrode 26 is surrounded by the gate insulating film 24. The gate electrode 26 is insulated from the semiconductor substrate 12 by the gate insulating film 24. A part of the gate insulating film 24 is exposed on the upper surface 12a of the semiconductor substrate 12. The width (i.e., the length in the x direction) of each trench 22 becomes wider from the upper surface 12a of the semiconductor substrate 12 downward. Both side surfaces of each trench 22 are inclined so as to move away from the center of the trench 22 toward the bottom surface side. More specifically, both side surfaces of each trench 22 are composed of a first side surface 23a connected to the upper surface 12a of the semiconductor substrate 12 and a second side surface 23b connected to the lower end of the first side surface 23a. The first side surface 23a extends while slightly curving so as to be convex upward. The second side surface 23b extends in a substantially planar shape. The angle between the second side surface 23b and the upper surface 12a is larger than the angle between the first side surface 23a and the upper surface 12a (i.e., the second side surface 23b has a gentler inclination than the first side surface 23a). Most of the side surfaces of the trench 22 are composed of the second side surface 23b. Hereinafter, for convenience of explanation, the trench 22 on the left side in FIG. 1 may be referred to as the first trench 22a, and the trench 22 on the right side in FIG. 1 may be referred to as the second trench 22b. Although not shown, in FIG. 1, a plurality of trenches similar to trench 22 are formed on the left side of first trench 22a and on the right side of second trench 22b.

[0015] An upper electrode 70 is disposed on the upper surface 12a of the semiconductor substrate 12. The upper electrode 70 has a source contact electrode 70a and a source electrode 70b. The source contact electrode 70a is made of, for example, nickel silicide (NiSi), titanium silicide (TiSi), or the like. The source contact electrode 70a is provided in an area where the gate insulating film 24 is not exposed. The source electrode 70b is made of, for example, aluminum silicon (AlSi). The source electrode 70b covers the source contact electrode 70a and the upper surface of the gate insulating film 24. The upper electrode 70 is insulated from the gate electrode 26 by the gate insulating film 24. A lower electrode 72 is disposed on the lower surface 12b of the semiconductor substrate 12. The lower electrode 72 is in contact with substantially the entire lower surface 12b of the semiconductor substrate 12.

[0016] Within the semiconductor substrate 12, a source region 30, a body region 32, a drift region 34, and a drain region 36 are provided.

[0017] The source region 30 is an n-type region. The source region 30 is disposed at a position exposed on the upper surface 12a of the semiconductor substrate 12, and is in ohmic contact with the upper electrode 70 (source contact electrode 70a). The source region 30 extends from the gate insulating film 24 in the first trench 22a to a position where it contacts the gate insulating film 24 in the second trench 22b. The source region 30 contacts each of the gate insulating films 24 at the upper end of the first trench 22a and the upper end of the second trench 22b.

[0018] The body region 32 is a p-type region. The body region 32 is in contact with the source region 30. The body region 32 extends below the source region 30 from the gate insulating film 24 in the first trench 22a to a position where the body region 32 is in contact with the gate insulating film 24 in the second trench 22b. The body region 32 is in contact with the gate insulating films in the trenches 22a and 22b below the source region 30. Although not shown, the body region 32 is in ohmic contact with the source contact electrode 70a in a cross section different from that in FIG. 1.

[0019] The drift region 34 is an n-type region. The drift region 34 is disposed below the body region 32. The drift region 34 extends from the gate insulating film 24 in the first trench 22a to a position where it contacts the gate insulating film 24 in the second trench 22b. The drift region 34 is separated from the source region 30 by the body region 32. The drift region 34 is distributed to a depth range below the lower end of each trench 22. The drift region 34 covers the bottom of the first trench 22a and also covers the bottom of the second trench 22b.

[0020] The drain region 36 is an n-type region. The drain region 36 has a higher n-type impurity concentration than the drift region 34. The drain region 36 is disposed below the drift region 34. The drain region 36 is exposed at the lower surface 12b of the semiconductor substrate 12. The drain region 36 is in ohmic contact with the lower electrode 72.

[0021] As shown in FIG. 1, the body region 32 is disposed in a depth range D b Now, what is the maximum value W of the distance W between the first trench 22a and the second trench 22b (the distance between the opposing side surfaces of two adjacent trenches 22)? F In this embodiment, the width of each trench 22 increases toward the bottom, so that the depth range D b The maximum value W F is the upper end of the body region 32. In addition, since the width of each trench 22 increases toward the lower side, the interval W between the first trench 22a and the second trench 22b on the upper surface 12a of the semiconductor substrate 12 is T is the maximum value W F Greater than.

[0022] Next, the operation of the semiconductor device 10 will be described. When the semiconductor device 10 is used, the semiconductor device 10, a load (e.g., a motor), and a power source are connected in series. A power supply voltage is applied to the series circuit of the semiconductor device 10 and the load. The power supply voltage is applied in a direction such that the drain side (lower electrode 72) of the semiconductor device 10 has a higher potential than the source side (upper electrode 70). When the semiconductor device 10 is turned on, the potential of the gate electrode 26 is increased to a potential higher than the gate threshold. In the process of increasing the potential of the gate electrode 26, first, the body region 32 in the range where the gate insulating film 24 in the first trench 22a and the gate insulating film 24 in the second trench 22b contact each other is inverted to n-type. In this embodiment, the depth range D in which the body region 32 is arranged is inverted to n-type. b The maximum value W of the distance W between the first trench 22a and the second trench 22b in F (i.e., the maximum width of the body region 32) is less than 200 nm. Since the width of the body region 32 is sufficiently narrow, when the potential of the gate electrode 26 is further increased, the FinFET effect occurs, causing an inversion layer to expand, and the substantially entire region of the body region 32 is inverted to n-type. As a result, a channel is formed in the substantially entire region of the body region 32 between the first trench 22a and the second trench 22b. When the source region 30 and the drift region 34 are connected by the channel, electrons flow from the source region 30 to the drift region 34 through the channel. This turns on the semiconductor device 10. When the semiconductor device 10 is turned off, the potential of the gate electrode 26 is made lower than the gate threshold. Then, the channel formed in the body region 32 disappears, and the semiconductor device 10 turns off.

[0023] As described above, in the semiconductor device 10 of this embodiment, the body region 32 is disposed in the depth range D b The maximum value W of the distance W between the first trench 22a and the second trench 22b in F is less than 200 nm, which is sufficiently small to enable the FinFET effect to occur. Therefore, a channel can be formed in almost the entire area of ​​the body region 32. Therefore, the semiconductor device 10 has a low channel resistance.

[0024] In addition, the distance W between the first trench 22a and the second trench 22b on the upper surface 12a of the semiconductor substrate 12 is T However, the above maximum value W F That is, source region 30 is exposed over a wide area of ​​upper surface 12a of semiconductor substrate 12. This makes it possible to ensure a sufficient contact area between source region 30 and upper electrode 70 (source contact electrode 70a). Therefore, semiconductor device 10 has a low contact resistance.

[0025] As described above, according to the semiconductor device 10 of this embodiment, a low channel resistance and a low contact resistance can be achieved.

[0026] Next, a method for manufacturing the semiconductor device 10 will be described with reference to Fig. 2 to Fig. 10. First, as shown in Fig. 2, a first substrate 60 is prepared, which has an n-type substrate 50, an n-type source region 30 provided on the n-type substrate 50, a p-type body region 32 provided on the source region 30, and an n-type drift region 34 provided on the body region 32. The first substrate 60 can be manufactured, for example, by forming the source region 30, the body region 32, and the drift region 34 on the n-type substrate 50 by appropriately combining known techniques such as epitaxial growth and ion implantation.

[0027] 3, an amorphous layer 40 is formed near the upper surface of the drift region 34. Here, for example, argon atoms are irradiated onto the upper surface of the drift region 34. This disrupts the atomic arrangement near the upper surface of the drift region 34, and the amorphous layer 40 is formed.

[0028] Next, as shown in FIG. 4, a plurality of trenches 22 are selectively formed in the upper surface of the drift region 34 by etching. Here, the trenches 22 are formed so as to extend from the upper surface of the drift region 34 through the body region 32 to the vicinity of the bottom surface of the source region 30. The side surfaces of the trenches 22 formed by etching the first substrate 60 are inclined in a direction such that the width of the upper end of the trench 22 is wider than the width of the bottom of the trench 22. In other words, the trenches 22 are formed so that the width gradually narrows toward the lower side. Also, the trenches 22 are formed so that their bottom surfaces have a curved shape. Note that in this process, the depth range D in which the body region 32 is disposed is inclined. b Each trench 22 is formed so that the maximum value of the interval W between two adjacent trenches 22 (the first trench 22a and the second trench 22b) is less than 200 nm. B Each trench 22 is formed so that the width W is greater than the maximum width W.

[0029] 5, an insulating film 42 is formed so as to cover the bottom surface of each trench 22. The insulating film 42 is formed so that its upper end is located lower than the upper end of the source region 30. Next, an insulating film 44 is formed on the side surface of each trench 22, and then polysilicon is deposited inside each trench 22 to form a gate electrode 26. The gate electrode 26 is formed so that its upper end is located higher than the upper end of the body region 32. Next, an insulating film 46 is formed so as to cover the upper surface of the gate electrode 26.

[0030] 6, the upper surface of the drift region 34 and the upper surface of the insulating film 46 are planarized by, for example, CMP (Chemical Mechanical Polishing) technology so as to leave the amorphous layer 40. The remaining insulating films 42, 44, and 46 become the gate insulating film 24.

[0031] Next, a second substrate 62 shown in FIG. 7 is prepared. The second substrate 62 has an n-type drain region 36 and an n-type drift region 34 provided on the drain region 36. The second substrate 62 can be manufactured, for example, by forming the drift region 34 by epitaxial growth on an n-type substrate that will become the drain region 36. Then, an amorphous layer 48 is formed near the upper surface of the drift region 34. The amorphous layer 48 can be formed by the same process as the amorphous layer 40 in FIG. 3.

[0032] Next, as shown in FIG. 8, the first substrate 60 and the second substrate 62 are bonded. Here, in a vacuum environment, the first substrate 60 and the second substrate 62 are in contact with each other so that the amorphous layer 40 of the first substrate 60 and the amorphous layer 48 of the second substrate 62 face each other, and heat treatment is performed at about 1000° C. As a result, the disordered atoms of the amorphous layers 40 and 48 flow in an aligned direction, and the amorphous layers 40 and 48 return to a crystalline state. In this process, the first substrate 60 and the second substrate 62 are bonded. Note that in FIG. 8 and subsequent figures, the first substrate 60 in FIG. 2 to FIG. 7 is depicted upside down.

[0033] 9, the n-type substrate 50 is removed. Specifically, the first substrate 60 is ground from the n-type substrate 50 side by using, for example, a CMP technique to expose the source region 30 and the gate insulating film 24 (insulating film 42). The first substrate 60 and the second substrate 62 after grinding become the semiconductor substrate 12.

[0034] 10 , an upper electrode 70 in contact with the source region 30 is formed on the upper surface 12a of the semiconductor substrate 12. Specifically, a source contact electrode 70a is formed to cover the exposed area of ​​the source region 30, and then a source electrode 70b is formed to cover the source contact electrode 70a and the gate insulating film 24.

[0035] Thereafter, a lower electrode 72 is formed on the lower surface 12b of the semiconductor substrate 12, thereby completing the semiconductor device 10 shown in FIG.

[0036] In the above-described manufacturing method, the distance W between the first trench 22a and the second trench 22b at the bottom of the first trench 22a and the second trench 22b is B However, the depth range D in which the body region 32 is arranged b Each trench 22 is formed in the first substrate 60 so that the distance W between the first trench 22a and the second trench 22b in the first substrate 60 is larger than the maximum distance W between the first trench 22a and the second trench 22b in the first substrate 60. Then, the upper surface of the second substrate 62 (the surface on which the amorphous layer 48 is formed) is bonded to the trench formation surface of the first substrate 60 (i.e., the surface on the drift region 34 side). That is, the first substrate 60 on which the trench 22 is formed is bonded to the second substrate 62 by turning it upside down. Thereafter, the surface on the opposite side to the trench formation surface (i.e., the surface on the first substrate side of the bonded substrate) is ground to expose the source region 30 and the gate insulating film 24 (insulating film 42) in the trench 22. Then, the upper electrode 70 is formed in contact with the exposed source region 30. As a result, the trench 22 can be obtained such that the distance between the first trench 22a and the second trench 22b at the position in contact with the upper electrode 70 (the portion that was the bottom of the first trench 22a and the second trench 22b) is larger than the maximum distance. In this manner, in the above-described manufacturing method, by preparing two substrates 60, 62, it is possible to obtain a trench 22 whose lower part is wider than its upper part, which was difficult to achieve in the past. This makes it possible to ensure the contact area between the source region 30 and the upper electrode 70. In addition, the first trench 22a and the second trench 22b are formed so that the above-mentioned maximum value is less than 200 nm. As a result, it is possible to manufacture a semiconductor device 10 having a low channel resistance due to the FinFET effect and a low contact resistance.

[0037] The source region 30 is an example of a “first semiconductor region,” and the drift region 34 is an example of a “second semiconductor region.” The insulating films 42 and 44 are an example of a “first insulating film,” and the insulating film 46 is an example of a “second insulating film.”

[0038] In the above-described embodiment, the side of the trench 22 is composed of the first side 23a and the second side 23b. However, the side of the trench 22 may be composed of, for example, only the second side 23b. Also, in the above-described embodiment, the side of the trench 22 becomes smaller from the upper surface 12a of the semiconductor substrate 12 toward the lower side, but this is not limited to such a configuration. In the technology disclosed in this specification, the distance between the first trench 22a and the second trench 22b on the upper surface 12a of the semiconductor substrate 12 (in other words, the width of the source region 30 exposed between the two trenches 22) is a maximum value W F The shape of the side surface of trench 22 is not particularly limited as long as it is larger than the above.

[0039] In the above-described embodiment, the source region 30 is in contact with the gate insulating film 24. However, the source region 30 does not have to be in contact with the gate insulating film 24. In the technology disclosed in this specification, a channel is formed in almost the entire body region 32, so that electrons flow even in positions in the body region 32 that are distant from the gate insulating film 24. Therefore, even if the source region 30 is not in contact with the gate insulating film 24, electrons can flow from the upper electrode 70 to the lower electrode 72 via the source region 30, the channel, the drift region 34, and the drain region 36.

[0040] In the above-described embodiment, the semiconductor device 10 is a MOSFET. However, the semiconductor device 10 may be an IGBT (Insulated Gate Bipolar Transistor). By changing the drain region 36 to a p-type region, an IGBT structure can be obtained.

[0041] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes to the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or drawings achieves multiple objectives simultaneously, and achieving one of the objectives itself has technical utility. [Explanation of symbols]

[0042] 10: trench gate type semiconductor device, 12: semiconductor substrate, 22a: first trench, 22b: second trench, 24: gate insulating film, 26: gate electrode, 30: source region, 32: body region, 34: drift region, 36: drain region, 70: upper electrode, 72: lower electrode

Claims

1. A trench gate type semiconductor device (10), A semiconductor substrate (12); A first trench (22a) provided in an upper surface (12a) of the semiconductor substrate; a second trench (22b) disposed in the top surface of the semiconductor substrate and spaced apart from the first trench; a gate insulating film (24) covering the inner surface of the first trench and the inner surface of the second trench; a gate electrode (26) disposed in the first trench and the second trench and insulated from the semiconductor substrate by the gate insulating film; an upper electrode (70) covering the upper surface of the semiconductor substrate; Equipped with The semiconductor substrate is a first n-type semiconductor region (30) disposed between the first trench and the second trench and in contact with the upper electrode; a p-type body region (32) disposed between the first trench and the second trench, disposed below the first semiconductor region, and extending from a position in contact with the gate insulating film in the first trench to a position in contact with the gate insulating film in the second trench; a second semiconductor region (34) of n-type, disposed between the first trench and the second trench, disposed below the body region, extending from the gate insulating film in the first trench to a position contacting the gate insulating film in the second trench, and separated from the first semiconductor region by the body region; It has a maximum value of a distance between the first trench and the second trench in a depth range in which the body region is disposed is less than 200 nm; a distance between the first trench and the second trench at the top surface of the semiconductor substrate is greater than the maximum value; A trench gate semiconductor device.

2. 2. The trench gate type semiconductor device according to claim 1, wherein a distance between said first trench and said second trench decreases from said upper surface of said semiconductor substrate toward a lower side.

3. A method for manufacturing a trench gate semiconductor device (10), comprising the steps of: The method includes the steps of: preparing a first substrate (60) having an n-type first semiconductor region (30) provided on an upper surface of an n-type substrate (50), a p-type body region (32) provided on an upper surface of the first semiconductor region, and an n-type second semiconductor region (34) provided on an upper surface of the body region; forming an amorphous layer (40) adjacent an upper surface of the second semiconductor region; forming a first trench (22a) and a second trench (22b), each of which reaches the first semiconductor region from the upper surface of the second semiconductor region, such that a maximum value of a distance between the first trench and the second trench in a depth range in which the body region is disposed is less than 200 nm, and a distance between the first trench and the second trench at a bottom of the first trench and the second trench is greater than the maximum value; forming a first insulating film (42, 44) covering the inner surface of the first trench and the inner surface of the second trench, a gate electrode (26) disposed in the first trench and the second trench, and a second insulating film (46) covering an upper surface of the gate electrode; planarizing the upper surface of the second semiconductor region and an upper surface of the second insulating film so that the amorphous layer remains; Providing an n-type second substrate (62) having an amorphous layer (48) formed near an upper surface thereof; bonding the first substrate and the second substrate such that the amorphous layer of the first substrate faces the amorphous layer of the second substrate; grinding the first substrate from the n-type substrate side to expose the first semiconductor region and the first insulating film; forming an electrode (70) in contact with the exposed first semiconductor region; A manufacturing method comprising:

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