Trench contact structures for next-generation integrated circuit structure fabrication

Abstract

To provide 10-nanometer node and smaller integrated circuit structure fabrication and the resulting structures.SOLUTION: An integrated circuit structure 3900 includes an N-type semiconductor device and a P-type semiconductor device. A semiconductor source or a drain region 3958 is adjacent to a gate electrode 3952, and a semiconductor source or a drain region 3910 is adjacent to a gate electrode 3902. A trench contact structure 3970 is over the semiconductor source or a drain region 3958, and a trench contact structure 3930 is over the semiconductor source or a drain region 3910. The trench contact structure 3970 and the trench contact structure 3930 both comprise a U-shaped metal layer 3916 and a T-shaped metal layer 3918 on and over the entirety of the U-shaped metal layer 3916.SELECTED DRAWING: Figure 39H

Description

[Technical Field]

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] This application claims the benefit of U.S. Provisional Application No. 62 / 593,149, filed November 30, 2017, entitled "Next Generation Integrated Circuit Structure Manufacturing," the entire contents of which are incorporated herein by reference.

[0002] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate to the field of next generation integrated circuit structure fabrication, and in particular to the fabrication of integrated circuit structures at the 10 nanometer node and smaller, and the resulting structures. [Background technology]

[0003] Over the past few decades, the scaling of features in integrated circuits has been the driving force behind the ever-growing semiconductor industry. Scaling to smaller and smaller features allows for an increased density of functional units on the limited real estate of a semiconductor chip. For example, reducing the size of transistors allows for a greater number of memory or logic devices to be integrated onto a chip, resulting in the production of products with increased capacity. However, the move toward ever greater capacity is not without challenges. The need to optimize the performance of each device is becoming increasingly evident.

[0004] Variabilities in traditional and currently known manufacturing processes may limit the ability to advance further into the 10 nanometer node or sub-10 nanometer node range. Consequently, the fabrication of functional components required for future technology nodes may require the introduction of new methods or the integration of new technologies into or replacement of current manufacturing processes. [Brief explanation of the drawings]

[0005] [Figure 1A] 1 illustrates a cross-sectional view of an initial structure of a hard mask material layer formed on an interlevel dielectric (ILD) layer after deposition and before patterning.

[0006] [Figure 1B] 1B shows a cross-sectional view of the structure of FIG. 1A after patterning of the hard mask layer by pitch 2 division.

[0007] [Figure 2A] FIG. 1 is a schematic diagram of a pitch-four approach used in fabricating semiconductor fins according to an embodiment of the present disclosure.

[0008] [Figure 2B] FIG. 1 illustrates a cross-sectional view of a semiconductor fin fabricated using a pitch-by-four approach, according to one embodiment of the present disclosure.

[0009] [Figure 3A] FIG. 1 is a schematic diagram of an integrated fin pitch quartering approach used to fabricate semiconductor fins, according to one embodiment of the present disclosure.

[0010] [Figure 3B] FIG. 1 illustrates a cross-sectional view of a semiconductor fin fabricated using an integrated fin pitch quartering approach in accordance with an embodiment of the present disclosure.

[0011] [Figure 4A] 1A-1D are cross-sectional views illustrating various steps in a method for fabricating multiple semiconductor fins, according to one embodiment of the present disclosure. [Figure 4B] 1A-1D are cross-sectional views illustrating various steps in a method for fabricating multiple semiconductor fins, according to one embodiment of the present disclosure. [Figure 4C] 1A-1D are cross-sectional views illustrating various steps in a method for fabricating multiple semiconductor fins, according to one embodiment of the present disclosure.

[0012] [Figure 5A] FIG. 1 illustrates a cross-sectional view of a pair of semiconductor fins separated by a triple-layer trench isolation structure according to an embodiment of the present disclosure.

[0013] [Figure 5B] FIG. 10 illustrates a cross-sectional view of another pair of semiconductor fins separated by another three-layer trench isolation structure in accordance with another embodiment of the present disclosure.

[0014] [Figure 6A] 1A-1D illustrate cross-sectional views of various steps in the fabrication of a triple-layer trench isolation structure according to one embodiment of the present disclosure. [Figure 6B] 1A-1D illustrate cross-sectional views of various steps in the fabrication of a triple-layer trench isolation structure according to one embodiment of the present disclosure. [Figure 6C] 1A-1D illustrate cross-sectional views of various steps in the fabrication of a triple-layer trench isolation structure according to one embodiment of the present disclosure. [Figure 6D] 1A-1D illustrate cross-sectional views of various steps in the fabrication of a triple-layer trench isolation structure according to one embodiment of the present disclosure.

[0015] [Figure 7A] 1A-1D illustrate perspective three-dimensional cross-sectional views of various steps in a method for fabricating an integrated circuit structure, according to one embodiment of the present disclosure. [Figure 7B] 1A-1D illustrate perspective three-dimensional cross-sectional views of various steps in a method for fabricating an integrated circuit structure, according to one embodiment of the present disclosure. [Figure 7C] 1A-1D illustrate perspective three-dimensional cross-sectional views of various steps in a method for fabricating an integrated circuit structure, according to one embodiment of the present disclosure. [Figure 7D] 1A-1D illustrate perspective three-dimensional cross-sectional views of various steps in a method for fabricating an integrated circuit structure, according to one embodiment of the present disclosure. [Figure 7E] 1A-1D illustrate perspective three-dimensional cross-sectional views of various steps in a method for fabricating an integrated circuit structure, according to one embodiment of the present disclosure.

[0016] [Figure 8A] 7A-7D show slightly projected cross-sectional views taken along axis a-a' of FIG. 7E for various steps in a method of fabricating an integrated circuit structure according to one embodiment of the present disclosure. [Figure 8B]7A-7D show slightly projected cross-sectional views taken along axis a-a' of FIG. 7E for various steps in a method of fabricating an integrated circuit structure according to one embodiment of the present disclosure. [Figure 8C] 7A-7D show slightly projected cross-sectional views taken along axis a-a' of FIG. 7E for various steps in a method of fabricating an integrated circuit structure according to one embodiment of the present disclosure. [Figure 8D] 7A-7D show slightly projected cross-sectional views taken along axis a-a' of FIG. 7E for various steps in a method of fabricating an integrated circuit structure according to one embodiment of the present disclosure. [Figure 8E] 7A-7D show slightly projected cross-sectional views taken along axis a-a' of FIG. 7E for various steps in a method of fabricating an integrated circuit structure according to one embodiment of the present disclosure. [Figure 8F] 7A-7D show slightly projected cross-sectional views taken along axis a-a' of FIG. 7E for various steps in a method of fabricating an integrated circuit structure according to one embodiment of the present disclosure.

[0017] [Figure 9A] 7B shows a slightly projected cross-sectional view of an integrated circuit structure including a permanent gate stack and epitaxial source or drain regions according to one embodiment of the present disclosure, taken along axis a-a' of FIG. 7E.

[0018] [Figure 9B] 7B illustrates a cross-sectional view of an integrated circuit structure including epitaxial source or drain regions and a multi-layer trench isolation structure taken along axis bb' of FIG. 7E according to one embodiment of the present disclosure.

[0019] [Figure 10] 1 illustrates a cross-sectional view of an integrated circuit structure cut at a source or drain location according to one embodiment of the present disclosure.

[0020] [Figure 11]1 illustrates a cross-sectional view of another integrated circuit structure cut at a source or drain location in accordance with an embodiment of the present disclosure.

[0021] [Figure 12A] 1A-1C illustrate cross-sectional views taken at a source or drain location, illustrating various steps in the fabrication of an integrated circuit structure, according to one embodiment of the present disclosure. [Figure 12B] 1A-1C illustrate cross-sectional views taken at a source or drain location, illustrating various steps in the fabrication of an integrated circuit structure, according to one embodiment of the present disclosure. [Figure 12C] 1A-1C illustrate cross-sectional views taken at a source or drain location, illustrating various steps in the fabrication of an integrated circuit structure, according to one embodiment of the present disclosure. [Figure 12D] 1A-1C illustrate cross-sectional views taken at a source or drain location, illustrating various steps in the fabrication of an integrated circuit structure, according to one embodiment of the present disclosure.

[0022] [Figure 13A] 1A-1C show plan views illustrating various steps in a method for patterning a fin with multiple gate spacings to form a localized isolation structure according to an embodiment of the present disclosure. [Figure 13B] 1A-1C show plan views illustrating various steps in a method for patterning a fin with multiple gate spacings to form a localized isolation structure according to an embodiment of the present disclosure.

[0023] [Figure 14A] 10A-10C show plan views illustrating various steps in a method for patterning a fin with a single gate spacing to form a local isolation structure according to another embodiment of the present disclosure. [Figure 14B] 10A-10C show plan views illustrating various steps in a method for patterning a fin with a single gate spacing to form a local isolation structure according to another embodiment of the present disclosure. [Figure 14C] 10A-10C show plan views illustrating various steps in a method for patterning a fin with a single gate spacing to form a local isolation structure according to another embodiment of the present disclosure. [Figure 14D] 10A-10C show plan views illustrating various steps in a method for patterning a fin with a single gate spacing to form a local isolation structure according to another embodiment of the present disclosure.

[0024] [Figure 15] 1 illustrates a cross-sectional view of an integrated circuit structure with a fin having multiple gate spacing for localized isolation according to one embodiment of the present disclosure.

[0025] [Figure 16A] 1 illustrates a cross-sectional view of an integrated circuit structure with a fin having a single gate spacing for localized isolation according to another embodiment of the present disclosure.

[0026] [Figure 16B] 1A-1C illustrate cross-sectional views showing locations where fin isolation structures may be formed in place of gate electrodes according to an embodiment of the present disclosure.

[0027] [Figure 17A] 10 illustrates various possible depths for fin cuts manufactured using a fin trim isolation approach, according to one embodiment of the present disclosure. [Figure 17B] 10 illustrates various possible depths for fin cuts manufactured using a fin trim isolation approach, according to one embodiment of the present disclosure. [Figure 17C] 10 illustrates various possible depths for fin cuts manufactured using a fin trim isolation approach, according to one embodiment of the present disclosure.

[0028] [Figure 18] 1A-1C show plan views and corresponding cross-sectional views taken along axis a-a' illustrating possible options for the depth of local and global locations of fin cuts within a fin according to one embodiment of the present disclosure.

[0029] [Figure 19A]1A-1D illustrate cross-sectional views of various steps in a method for selecting a fin end stressor location at the end of a fin having a wide cut, according to one embodiment of the present disclosure. [Figure 19B] 1A-1D illustrate cross-sectional views of various steps in a method for selecting a fin end stressor location at the end of a fin having a wide cut, according to one embodiment of the present disclosure.

[0030] [Figure 20A] 1A-1D illustrate cross-sectional views of various steps in a method for selecting a fin end stressor location at the end of a fin having a localized cut, according to one embodiment of the present disclosure. [Figure 20B] 1A-1D illustrate cross-sectional views of various steps in a method for selecting a fin end stressor location at the end of a fin having a localized cut, according to one embodiment of the present disclosure.

[0031] [Figure 21A] 1A-1D illustrate cross-sectional views of various steps in a method of fabricating an integrated circuit structure with differentiated fin end dielectric plugs according to an embodiment of the present disclosure. [Figure 21B] 1A-1D illustrate cross-sectional views of various steps in a method of fabricating an integrated circuit structure with differentiated fin end dielectric plugs according to an embodiment of the present disclosure. [Figure 21C] 1A-1D illustrate cross-sectional views of various steps in a method of fabricating an integrated circuit structure with differentiated fin end dielectric plugs according to an embodiment of the present disclosure. [Figure 21D] 1A-1D illustrate cross-sectional views of various steps in a method of fabricating an integrated circuit structure with differentiated fin end dielectric plugs according to an embodiment of the present disclosure. [Figure 21E] 1A-1D illustrate cross-sectional views of various steps in a method of fabricating an integrated circuit structure with differentiated fin end dielectric plugs according to an embodiment of the present disclosure. [Figure 21F] 1A-1D illustrate cross-sectional views of various steps in a method of fabricating an integrated circuit structure with differentiated fin end dielectric plugs according to an embodiment of the present disclosure. [Figure 21G]1A-1D illustrate cross-sectional views of various steps in a method of fabricating an integrated circuit structure with differentiated fin end dielectric plugs according to an embodiment of the present disclosure. [Figure 21H] 1A-1D illustrate cross-sectional views of various steps in a method of fabricating an integrated circuit structure with differentiated fin end dielectric plugs according to an embodiment of the present disclosure. [Figure 21I] 1A-1D illustrate cross-sectional views of various steps in a method of fabricating an integrated circuit structure with differentiated fin end dielectric plugs according to an embodiment of the present disclosure. [Figure 21J] 1A-1D illustrate cross-sectional views of various steps in a method of fabricating an integrated circuit structure with differentiated fin end dielectric plugs according to an embodiment of the present disclosure. [Figure 21K] 1A-1D illustrate cross-sectional views of various steps in a method of fabricating an integrated circuit structure with differentiated fin end dielectric plugs according to an embodiment of the present disclosure. [Figure 21L] 1A-1D illustrate cross-sectional views of various steps in a method of fabricating an integrated circuit structure with differentiated fin end dielectric plugs according to an embodiment of the present disclosure. [Figure 21M] 1A-1D illustrate cross-sectional views of various steps in a method of fabricating an integrated circuit structure with differentiated fin end dielectric plugs according to an embodiment of the present disclosure.

[0032] [Figure 22A] 1 illustrates a cross-sectional view of an exemplary structure of a PMOS fin edge stressor dielectric plug in accordance with an embodiment of the present disclosure. [Figure 22B] 1 illustrates a cross-sectional view of an exemplary structure of a PMOS fin edge stressor dielectric plug in accordance with an embodiment of the present disclosure. [Figure 22C] 1 illustrates a cross-sectional view of an exemplary structure of a PMOS fin edge stressor dielectric plug in accordance with an embodiment of the present disclosure. [Figure 22D] 1 illustrates a cross-sectional view of an exemplary structure of a PMOS fin edge stressor dielectric plug in accordance with an embodiment of the present disclosure.

[0033] [Figure 23A]1 illustrates a cross-sectional view of another semiconductor structure having fin edge stress-inducing features in accordance with another embodiment of the present disclosure.

[0034] [Figure 23B] 1 shows a cross-sectional view of another semiconductor structure having fin-edge stress-inducing features in accordance with another embodiment of the present disclosure.

[0035] [Figure 24A] FIG. 1 illustrates a perspective view of a fin having uniaxial tensile stress according to an embodiment of the present disclosure.

[0036] [Figure 24B] FIG. 1 illustrates a perspective view of a fin having compressive uniaxial stress according to an embodiment of the present disclosure.

[0037] [Figure 25A] 1A-1C illustrate plan views illustrating various steps in a method for patterning fins at a single gate spacing to form local isolation structures at select gate line cut locations according to an embodiment of the present disclosure. [Figure 25B] 1A-1C illustrate plan views illustrating various steps in a method for patterning fins at a single gate spacing to form local isolation structures at select gate line cut locations according to an embodiment of the present disclosure.

[0038] [Figure 26A] 25C show cross-sectional views of various possibilities for the location of poly cuts and fin trim isolation (FTI) local fin cuts, as well as dielectric plugs for the location of poly cuts only, for various regions of the structure of FIG. 25B in accordance with one embodiment of the present disclosure. [Figure 26B] 25B show cross-sectional views of various possibilities for the locations of poly cuts and fin trim isolation (FTI) local fin cuts, as well as dielectric plugs for locations of poly cuts only, for various regions of the structure of FIG. 25B in accordance with one embodiment of the present disclosure. [Figure 26C]25B show cross-sectional views of various possibilities for the locations of poly cuts and fin trim isolation (FTI) local fin cuts, as well as dielectric plugs for locations of poly cuts only, for various regions of the structure of FIG. 25B in accordance with one embodiment of the present disclosure.

[0039] [Figure 27A] 1A-1C illustrate a plan view and corresponding cross-sectional view of an integrated circuit structure including a gate line cut with a dielectric plug extending into a dielectric spacer of the gate line according to one embodiment of the present disclosure.

[0040] [Figure 27B] 10A-10C show plan views and corresponding cross-sectional views of an integrated circuit structure including a gate line cut with a dielectric plug extending beyond the dielectric spacer of the gate line according to another embodiment of the present disclosure.

[0041] [Figure 28A] 1A-1C illustrate cross-sectional views of various steps in a method for manufacturing an integrated circuit structure including a gate line cut having a dielectric plug with an upper portion extending beyond the dielectric spacer of the gate line and a lower portion extending into the dielectric spacer of the gate line, according to another embodiment of the present disclosure. [Figure 28B] 1A-1C illustrate cross-sectional views of various steps in a method for manufacturing an integrated circuit structure including a gate line cut having a dielectric plug with an upper portion extending beyond the dielectric spacer of the gate line and a lower portion extending into the dielectric spacer of the gate line, according to another embodiment of the present disclosure. [Figure 28C] 1A-1C illustrate cross-sectional views of various steps in a method for manufacturing an integrated circuit structure including a gate line cut having a dielectric plug with an upper portion extending beyond the dielectric spacer of the gate line and a lower portion extending into the dielectric spacer of the gate line, according to another embodiment of the present disclosure. [Figure 28D] 1A-1C illustrate cross-sectional views of various steps in a method for manufacturing an integrated circuit structure including a gate line cut having a dielectric plug with an upper portion extending beyond the dielectric spacer of the gate line and a lower portion extending into the dielectric spacer of the gate line, according to another embodiment of the present disclosure. [Figure 28E] 1A-1C illustrate cross-sectional views of various steps in a method for manufacturing an integrated circuit structure including a gate line cut having a dielectric plug with an upper portion extending beyond the dielectric spacer of the gate line and a lower portion extending into the dielectric spacer of the gate line, according to another embodiment of the present disclosure. [Figure 28F] 1A-1C illustrate cross-sectional views of various steps in a method for manufacturing an integrated circuit structure including a gate line cut having a dielectric plug with an upper portion extending beyond the dielectric spacer of the gate line and a lower portion extending into the dielectric spacer of the gate line, according to another embodiment of the present disclosure.

[0042] [Figure 29A] 1A-1C illustrate a plan view and corresponding cross-sectional view of an integrated circuit structure with residual dummy gate material at the bottom portion of a permanent gate stack according to one embodiment of the present disclosure. [Figure 29B] 1A-1C illustrate a plan view and corresponding cross-sectional view of an integrated circuit structure with residual dummy gate material at the bottom portion of a permanent gate stack according to one embodiment of the present disclosure. [Figure 29C] 1A-1C illustrate a plan view and corresponding cross-sectional view of an integrated circuit structure with residual dummy gate material at the bottom portion of a permanent gate stack according to one embodiment of the present disclosure.

[0043] [Figure 30A] 5A-5C illustrate cross-sectional views of various steps in a method of fabricating an integrated circuit structure with residual dummy gate material in a bottom portion of a permanent gate stack according to another embodiment of the present disclosure. [Figure 30B] 5A-5C illustrate cross-sectional views of various steps in a method of fabricating an integrated circuit structure with residual dummy gate material in a bottom portion of a permanent gate stack according to another embodiment of the present disclosure. [Figure 30C] 5A-5C illustrate cross-sectional views of various steps in a method of fabricating an integrated circuit structure with residual dummy gate material in a bottom portion of a permanent gate stack according to another embodiment of the present disclosure. [Figure 30D]5A-5C illustrate cross-sectional views of various steps in a method of fabricating an integrated circuit structure with residual dummy gate material in a bottom portion of a permanent gate stack according to another embodiment of the present disclosure.

[0044] [Figure 31A] 1 illustrates a cross-sectional view of a semiconductor device having a ferroelectric or antiferroelectric gate dielectric structure according to an embodiment of the present disclosure.

[0045] [Figure 31B] 3 illustrates a cross-sectional view of another semiconductor device having a ferroelectric or antiferroelectric gate dielectric structure according to another embodiment of the present disclosure.

[0046] [Figure 32A] FIG. 1 illustrates a plan view of multiple gate lines above a pair of semiconductor fins according to an embodiment of the present disclosure.

[0047] [Figure 32B] FIG. 32B shows a cross-sectional view taken along axis aa' of FIG. 32A according to one embodiment of the present disclosure.

[0048] [Figure 33A] FIG. 1 illustrates a cross-sectional view of a pair of NMOS devices with differentiated voltage thresholds based on tailored doping and a pair of PMOS devices with differentiated voltage thresholds based on tailored doping, according to one embodiment of the present disclosure.

[0049] [Figure 33B] FIG. 10 illustrates a cross-sectional view of a pair of NMOS devices having differentiated voltage thresholds based on differentiated gate electrode structures and a pair of PMOS devices having differentiated voltage thresholds based on differentiated gate electrode structures according to another embodiment of the present disclosure.

[0050] [Figure 34A]1 illustrates a cross-sectional view of a triplet of NMOS devices with differentiated voltage thresholds based on differentiated gate electrode structures and tailored doping, and a triplet of PMOS devices with differentiated voltage thresholds based on differentiated gate electrode structures and tailored doping, in accordance with one embodiment of the present disclosure.

[0051] [Figure 34B] 1 illustrates a cross-sectional view of a triplet of NMOS devices with differentiated voltage thresholds based on differentiated gate electrode structures and tailored doping, and a triplet of PMOS devices with differentiated voltage thresholds based on differentiated gate electrode structures and tailored doping, according to another embodiment of the present disclosure.

[0052] [Figure 35A] 5A-5C illustrate cross-sectional views of various steps in a method for fabricating NMOS devices with differentiated voltage thresholds based on differentiated gate electrode structures according to another embodiment of the present disclosure. [Figure 35B] 5A-5C illustrate cross-sectional views of various steps in a method for fabricating NMOS devices with differentiated voltage thresholds based on differentiated gate electrode structures according to another embodiment of the present disclosure. [Figure 35C] 5A-5C illustrate cross-sectional views of various steps in a method for fabricating NMOS devices with differentiated voltage thresholds based on differentiated gate electrode structures according to another embodiment of the present disclosure. [Figure 35D] 5A-5C illustrate cross-sectional views of various steps in a method for fabricating NMOS devices with differentiated voltage thresholds based on differentiated gate electrode structures according to another embodiment of the present disclosure.

[0053] [Figure 36A] 5A-5C illustrate cross-sectional views of various steps in a method for fabricating PMOS devices with differentiated voltage thresholds based on differentiated gate electrode structures according to another embodiment of the present disclosure. [Figure 36B]5A-5C illustrate cross-sectional views of various steps in a method for fabricating PMOS devices with differentiated voltage thresholds based on differentiated gate electrode structures according to another embodiment of the present disclosure. [Figure 36C] 5A-5C illustrate cross-sectional views of various steps in a method for fabricating PMOS devices with differentiated voltage thresholds based on differentiated gate electrode structures according to another embodiment of the present disclosure. [Figure 36D] 5A-5C illustrate cross-sectional views of various steps in a method for fabricating PMOS devices with differentiated voltage thresholds based on differentiated gate electrode structures according to another embodiment of the present disclosure.

[0054] [Figure 37] 1 illustrates a cross-sectional view of an integrated circuit structure with a P / N junction according to one embodiment of the present disclosure.

[0055] [Figure 38A] 1A-1D illustrate cross-sectional views of various steps in a method of manufacturing an integrated circuit structure using a dual metal gate replacement gate process flow according to an embodiment of the present disclosure. [Figure 38B] 1A-1D illustrate cross-sectional views of various steps in a method of manufacturing an integrated circuit structure using a dual metal gate replacement gate process flow according to an embodiment of the present disclosure. [Figure 38C] 1A-1D illustrate cross-sectional views of various steps in a method of manufacturing an integrated circuit structure using a dual metal gate replacement gate process flow according to an embodiment of the present disclosure. [Figure 38D] 1A-1D illustrate cross-sectional views of various steps in a method of manufacturing an integrated circuit structure using a dual metal gate replacement gate process flow according to an embodiment of the present disclosure. [Figure 38E] 1A-1D illustrate cross-sectional views of various steps in a method of manufacturing an integrated circuit structure using a dual metal gate replacement gate process flow according to an embodiment of the present disclosure. [Figure 38F]1A-1D illustrate cross-sectional views of various steps in a method of manufacturing an integrated circuit structure using a dual metal gate replacement gate process flow according to an embodiment of the present disclosure. [Figure 38G] 1A-1D illustrate cross-sectional views of various steps in a method of manufacturing an integrated circuit structure using a dual metal gate replacement gate process flow according to an embodiment of the present disclosure. [Figure 38H] 1A-1D illustrate cross-sectional views of various steps in a method of manufacturing an integrated circuit structure using a dual metal gate replacement gate process flow according to an embodiment of the present disclosure.

[0056] [Figure 39A] 1A-1D illustrate cross-sectional views illustrating various steps in a method for fabricating a dual silicide-based integrated circuit according to one embodiment of the present disclosure. [Figure 39B] 1A-1D illustrate cross-sectional views illustrating various steps in a method for fabricating a dual silicide-based integrated circuit according to one embodiment of the present disclosure. [Figure 39C] 1A-1D illustrate cross-sectional views illustrating various steps in a method for fabricating a dual silicide-based integrated circuit according to one embodiment of the present disclosure. [Figure 39D] 1A-1D illustrate cross-sectional views illustrating various steps in a method for fabricating a dual silicide-based integrated circuit according to one embodiment of the present disclosure. [Figure 39E] 1A-1D illustrate cross-sectional views illustrating various steps in a method for fabricating a dual silicide-based integrated circuit according to one embodiment of the present disclosure. [Figure 39F] 1A-1D illustrate cross-sectional views illustrating various steps in a method for fabricating a dual silicide-based integrated circuit according to one embodiment of the present disclosure. [Figure 39G] 1A-1D illustrate cross-sectional views illustrating various steps in a method for fabricating a dual silicide-based integrated circuit according to one embodiment of the present disclosure. [Figure 39H] 1A-1D illustrate cross-sectional views illustrating various steps in a method for fabricating a dual silicide-based integrated circuit according to one embodiment of the present disclosure.

[0057] [Figure 40A] 1 illustrates a cross-sectional view of an integrated circuit structure with trench contacts for NMOS devices according to one embodiment of the present disclosure.

[0058] [Figure 40B] 1 illustrates a cross-sectional view of an integrated circuit structure with trench contacts for PMOS devices according to another embodiment of the present disclosure.

[0059] [Figure 41A] 1 illustrates a cross-sectional view of a semiconductor device having conductive contacts on source or drain regions according to an embodiment of the present disclosure.

[0060] [Figure 41B] FIG. 2 illustrates a cross-sectional view of another semiconductor device having conductive contacts on raised source or drain regions in accordance with an embodiment of the present disclosure.

[0061] [Figure 42] FIG. 1 illustrates a plan view of multiple gate lines above a pair of semiconductor fins, according to an embodiment of the present disclosure.

[0062] [Figure 43A] 42A-42D show cross-sectional views taken along axis a-a' of FIG. 42 for various steps in a method of fabricating an integrated circuit structure according to one embodiment of the present disclosure. [Figure 43B] 42A-42D show cross-sectional views taken along axis a-a' of FIG. 42 for various steps in a method of fabricating an integrated circuit structure according to one embodiment of the present disclosure. [Figure 43C] 42A-42D show cross-sectional views taken along axis a-a' of FIG. 42 for various steps in a method of fabricating an integrated circuit structure according to one embodiment of the present disclosure.

[0063] [Figure 44] 43 illustrates a cross-sectional view of an integrated circuit structure taken along axis bb' of FIG. 42, according to one embodiment of the present disclosure.

[0064] [Figure 45A] FIG. 1 illustrates a plan view of an integrated circuit structure including trench contact plugs having a hard mask material thereon, according to one embodiment of the present disclosure. [Figure 45B] 1A-1C illustrate cross-sectional views corresponding to plan views of an integrated circuit structure including trench contact plugs having hard mask material thereon in accordance with one embodiment of the present disclosure.

[0065] [Figure 46A] 1A-1C illustrate cross-sectional views illustrating various steps in a method of fabricating an integrated circuit structure including trench contact plugs having a hard mask material thereon, in accordance with an embodiment of the present disclosure. [Figure 46B] 1A-1C illustrate cross-sectional views illustrating various steps in a method of fabricating an integrated circuit structure including trench contact plugs having a hard mask material thereon, in accordance with an embodiment of the present disclosure. [Figure 46C] 1A-1C illustrate cross-sectional views illustrating various steps in a method of fabricating an integrated circuit structure including trench contact plugs having a hard mask material thereon, in accordance with an embodiment of the present disclosure. [Figure 46D] 1A-1C illustrate cross-sectional views illustrating various steps in a method of fabricating an integrated circuit structure including trench contact plugs having a hard mask material thereon, in accordance with an embodiment of the present disclosure.

[0066] [Figure 47A] 1 illustrates a plan view of a semiconductor device having a gate contact disposed over an inactive portion of a gate electrode. [Figure 47B] 1 illustrates a cross-sectional view of a non-planar semiconductor device having a gate contact disposed over an inactive portion of a gate electrode.

[0067] [Figure 48A] 1 illustrates a plan view of a semiconductor device having a gate contact via disposed above an active portion of a gate electrode according to an embodiment of the present disclosure. [Figure 48B] FIG. 2 illustrates a cross-sectional view of a non-planar semiconductor device having a gate contact via located above an active portion of a gate electrode according to an embodiment of the present disclosure.

[0068] [Figure 49A] 1A-1C illustrate cross-sectional views illustrating various steps in a method of manufacturing a semiconductor structure having a gate contact structure disposed above an active portion of the gate, according to one embodiment of the present disclosure. [Figure 49B] 1A-1C illustrate cross-sectional views illustrating various steps in a method of manufacturing a semiconductor structure having a gate contact structure disposed above an active portion of the gate, according to one embodiment of the present disclosure. [Figure 49C] 1A-1C illustrate cross-sectional views illustrating various steps in a method of manufacturing a semiconductor structure having a gate contact structure disposed above an active portion of the gate, according to one embodiment of the present disclosure. [Figure 49D] 1A-1C illustrate cross-sectional views illustrating various steps in a method of manufacturing a semiconductor structure having a gate contact structure disposed above an active portion of the gate, according to one embodiment of the present disclosure.

[0069] [Figure 50] 1A-1C illustrate a plan view and corresponding cross-sectional views of an integrated circuit structure with a trench contact including an overlying insulating cap layer according to one embodiment of the present disclosure.

[0070] [Figure 51A] 1A-1C illustrate cross-sectional views of various integrated circuit structures, each having a trench contact including an overlying insulating cap layer and a gate stack including an overlying insulating cap layer, according to an embodiment of the present disclosure. [Figure 51B] 1A-1C illustrate cross-sectional views of various integrated circuit structures, each having a trench contact including an overlying insulating cap layer and a gate stack including an overlying insulating cap layer, according to an embodiment of the present disclosure. [Figure 51C]1A-1C illustrate cross-sectional views of various integrated circuit structures, each having a trench contact including an overlying insulating cap layer and a gate stack including an overlying insulating cap layer, according to an embodiment of the present disclosure. [Figure 51D] 1A-1C illustrate cross-sectional views of various integrated circuit structures, each having a trench contact including an overlying insulating cap layer and a gate stack including an overlying insulating cap layer, according to an embodiment of the present disclosure. [Figure 51E] 1A-1C illustrate cross-sectional views of various integrated circuit structures, each having a trench contact including an overlying insulating cap layer and a gate stack including an overlying insulating cap layer, according to an embodiment of the present disclosure. [Figure 51F] 1A-1C illustrate cross-sectional views of various integrated circuit structures, each having a trench contact including an overlying insulating cap layer and a gate stack including an overlying insulating cap layer, according to an embodiment of the present disclosure.

[0071] [Figure 52A] 10 illustrates a plan view of another semiconductor device having a gate contact via located above an active portion of the gate according to another embodiment of the present disclosure.

[0072] [Figure 52B] 1 illustrates a plan view of another semiconductor device having a trench contact via coupling a pair of trench contacts according to another embodiment of the present disclosure.

[0073] [Figure 53A] 1A-1C illustrate cross-sectional views illustrating various steps in a method of manufacturing an integrated circuit structure comprising a gate stack with an overlying insulating cap layer according to an embodiment of the present disclosure. [Figure 53B] 1A-1C illustrate cross-sectional views illustrating various steps in a method of manufacturing an integrated circuit structure comprising a gate stack with an overlying insulating cap layer according to an embodiment of the present disclosure. [Figure 53C] 1A-1C illustrate cross-sectional views illustrating various steps in a method of manufacturing an integrated circuit structure comprising a gate stack with an overlying insulating cap layer according to an embodiment of the present disclosure. [Figure 53D] 1A-1C illustrate cross-sectional views illustrating various steps in a method of manufacturing an integrated circuit structure comprising a gate stack with an overlying insulating cap layer according to an embodiment of the present disclosure. [Figure 53E] 1A-1C illustrate cross-sectional views illustrating various steps in a method of manufacturing an integrated circuit structure comprising a gate stack with an overlying insulating cap layer according to an embodiment of the present disclosure.

[0074] [Figure 54] FIG. 1 is a schematic diagram of a pitch-four approach used to fabricate trenches for interconnect structures, according to one embodiment of the present disclosure.

[0075] [Figure 55A] 1 illustrates a cross-sectional view of a metallization layer fabricated using a pitch-by-four scheme according to one embodiment of the present disclosure.

[0076] [Figure 55B] 1 illustrates a cross-sectional view of a metallization layer fabricated using a two-pitch division scheme above a metallization layer fabricated using a four-pitch division scheme, according to one embodiment of the present disclosure.

[0077] [Figure 56A] 1 illustrates a cross-sectional view of an integrated circuit structure with a metallization layer having a different metal line composition above a metallization layer having a metal line composition according to one embodiment of the present disclosure.

[0078] [Figure 56B] 1 illustrates a cross-sectional view of an integrated circuit structure comprising a metallization layer having a metal line composition bonded to a metallization layer having a different metal line composition in accordance with one embodiment of the present disclosure.

[0079] [Figure 57A] 1A-1C illustrate cross-sectional views of individual interconnect lines having various liner and conductive capping structure arrangements according to an embodiment of the present disclosure. [Figure 57B] 1A-1C illustrate cross-sectional views of individual interconnect lines having various liner and conductive capping structure arrangements according to an embodiment of the present disclosure. [Figure 57C] 1A-1C illustrate cross-sectional views of individual interconnect lines having various liner and conductive capping structure arrangements according to an embodiment of the present disclosure.

[0080] [Figure 58] 1 illustrates a cross-sectional view of an integrated circuit structure with four metallization layers having different metal line compositions and pitches above two metallization layers having different metal line compositions and smaller pitches in accordance with one embodiment of the present disclosure.

[0081] [Figure 59A] 1A-1C illustrate cross-sectional views of various interconnect lines as via configurations with a bottom conductive layer according to an embodiment of the present disclosure. [Figure 59B] 1A-1C illustrate cross-sectional views of various interconnect lines as via configurations with a bottom conductive layer according to an embodiment of the present disclosure. [Figure 59C] 1A-1C illustrate cross-sectional views of various interconnect lines as via configurations with a bottom conductive layer according to an embodiment of the present disclosure. [Figure 59D] 1A-1C illustrate cross-sectional views of various interconnect lines as via configurations with a bottom conductive layer according to an embodiment of the present disclosure.

[0082] [Figure 60A] 1 illustrates a cross-sectional view of a structural layout of recessed line topography in a BEOL metallization layer according to one embodiment of the present disclosure. [Figure 60B] 1 illustrates a cross-sectional view of a structural layout of recessed line topography in a BEOL metallization layer according to one embodiment of the present disclosure. [Figure 60C] 1 illustrates a cross-sectional view of a structural layout of recessed line topography in a BEOL metallization layer according to one embodiment of the present disclosure. [Figure 60D] 1 illustrates a cross-sectional view of a structural layout of recessed line topography in a BEOL metallization layer according to one embodiment of the present disclosure.

[0083] [Figure 61A] 1 illustrates a cross-sectional view of a structural layout of a stepped polygonal topography of a BEOL metallization layer according to one embodiment of the present disclosure. [Figure 61B] 1 illustrates a cross-sectional view of a structural layout of a stepped polygonal topography of a BEOL metallization layer according to one embodiment of the present disclosure. [Figure 61C] 1 illustrates a cross-sectional view of a structural layout of a stepped polygonal topography of a BEOL metallization layer according to one embodiment of the present disclosure. [Figure 61D] 1 illustrates a cross-sectional view of a structural layout of a stepped polygonal topography of a BEOL metallization layer according to one embodiment of the present disclosure.

[0084] [Figure 62A] 1A-1C illustrate a plan view and corresponding cross-sectional view of a metallization layer taken along plan view axis a-a' according to one embodiment of the present disclosure.

[0085] [Figure 62B] 1 illustrates a cross-sectional view of a line end or plug according to one embodiment of the present disclosure.

[0086] [Figure 62C] 1 illustrates another cross-sectional view of a line end or plug according to an embodiment of the present disclosure.

[0087] [Figure 63A] 1A-1D show plan views and corresponding cross-sectional views illustrating various steps in a plug end processing scheme according to one embodiment of the present disclosure. [Figure 63B] 1A-1D show plan views and corresponding cross-sectional views illustrating various steps in a plug end processing scheme according to one embodiment of the present disclosure. [Figure 63C] 1A-1D show plan views and corresponding cross-sectional views illustrating various steps in a plug end processing scheme according to one embodiment of the present disclosure. [Figure 63D]1A-1D show plan views and corresponding cross-sectional views illustrating various steps in a plug end processing scheme according to one embodiment of the present disclosure. [Figure 63E] 1A-1D show plan views and corresponding cross-sectional views illustrating various steps in a plug end processing scheme according to one embodiment of the present disclosure. [Figure 63F] 1A-1D show plan views and corresponding cross-sectional views illustrating various steps in a plug end processing scheme according to one embodiment of the present disclosure.

[0088] [Figure 64A] 1 illustrates a cross-sectional view of a conductive wire plug having a seam therein according to one embodiment of the present disclosure.

[0089] [Figure 64B] 1 illustrates a cross-sectional view of a stack of metallization layers including a conductive line plug at a lower metal line level according to an embodiment of the present disclosure.

[0090] [Figure 65] 1 shows a first view of a cell layout for a memory cell.

[0091] [Figure 66] 1 illustrates a first view of a cell layout for a memory cell with internal node jumpers according to one embodiment of the present disclosure.

[0092] [Figure 67] 1 shows a second view of the cell layout for the memory cells.

[0093] [Figure 68] 10 illustrates a second view of a cell layout for a memory cell with internal node jumpers according to one embodiment of the present disclosure.

[0094] [Figure 69] 10 shows a third view of a cell layout for a memory cell.

[0095] [Figure 70] 10 illustrates a third view of a cell layout for a memory cell with internal node jumpers according to one embodiment of the present disclosure.

[0096] [Figure 71A] 1 illustrates a bit cell layout and schematic diagram of a six-transistor (6T) static random access memory SRAM according to one embodiment of the present disclosure. [Figure 71B] 1 illustrates a bit cell layout and schematic diagram of a six-transistor (6T) static random access memory SRAM according to one embodiment of the present disclosure.

[0097] [Figure 72] 1A-1C illustrate cross-sectional views of two different layouts for the same standard cell according to one embodiment of the present disclosure.

[0098] [Figure 73] 1A-1C illustrate plan views of four different cell configurations, showing even (E) or odd (O) designations, according to one embodiment of the present disclosure.

[0099] [Figure 74] 1 illustrates a plan view of a block-level polygrid according to one embodiment of the present disclosure.

[0100] [Figure 75] 1 illustrates an exemplary acceptable (passing) layout based on standard cells with different versions, according to one embodiment of the present disclosure.

[0101] [Figure 76] 1 illustrates an exemplary unacceptable (failed) layout based on standard cells with different versions, according to one embodiment of the present disclosure.

[0102] [Figure 77]10 illustrates another exemplary acceptable (passing) layout based on standard cells with different versions, according to an embodiment of the present disclosure.

[0103] [Figure 78] 1 illustrates a partially cut-away plan view and corresponding cross-sectional view of a fin-based thin film resistor structure, the cross-sectional view being taken along axis a-a' of the partially cut-away plan view, according to one embodiment of the present disclosure.

[0104] [Figure 79] 1A-1D show plan views and corresponding cross-sectional views illustrating various steps in a method for fabricating a fin-based thin film resistor structure according to one embodiment of the present disclosure. [Figure 80] 1A-1D show plan views and corresponding cross-sectional views illustrating various steps in a method for fabricating a fin-based thin film resistor structure according to one embodiment of the present disclosure. [Figure 81] 1A-1D show plan views and corresponding cross-sectional views illustrating various steps in a method for fabricating a fin-based thin film resistor structure according to one embodiment of the present disclosure. [Figure 82] 1A-1D show plan views and corresponding cross-sectional views illustrating various steps in a method for fabricating a fin-based thin film resistor structure according to one embodiment of the present disclosure. [Figure 83] 1A-1D show plan views and corresponding cross-sectional views illustrating various steps in a method for fabricating a fin-based thin film resistor structure according to one embodiment of the present disclosure.

[0105] [Figure 84] 1A-1C illustrate plan views of a fin-based thin film resistor structure with various exemplary locations for anode or cathode electrode contacts according to an embodiment of the present disclosure.

[0106] [Figure 85A] 1A-1D show plan views of various fin shapes for fabricating a fin-based precision resistor according to an embodiment of the present disclosure. [Figure 85B]1A-1D show plan views of various fin shapes for fabricating a fin-based precision resistor according to an embodiment of the present disclosure. [Figure 85C] 1A-1D show plan views of various fin shapes for fabricating a fin-based precision resistor according to an embodiment of the present disclosure. [Figure 85D] 1A-1D show plan views of various fin shapes for fabricating a fin-based precision resistor according to an embodiment of the present disclosure.

[0107] [Figure 86] 1 illustrates a cross-sectional view of a lithographic mask structure according to an embodiment of the present disclosure.

[0108] [Figure 87] 1 illustrates a computing device according to one embodiment of the present disclosure.

[0109] [Figure 88] 1 illustrates an interposer including one or more embodiments of the present disclosure.

[0110] [Figure 89] FIG. 1 is an isometric view of a mobile computing platform utilizing an IC manufactured according to one or more processes described herein or including one or more features described herein, in accordance with one embodiment of the present disclosure.

[0111] [Figure 90] FIG. 1 illustrates a cross-sectional view of a flip-chip mounted die according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0112] Next-generation integrated circuit structure fabrication is described. In the following description, numerous specific details are set forth, such as specific integration and material regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to those skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, have not been described in detail in order to avoid unnecessarily obscuring embodiments of the present disclosure. Furthermore, it should be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

[0113] The following Detailed Description is merely exemplary in nature and is not intended to limit the embodiments of the subject matter or the application and uses of such embodiments. As used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding Technical Field, Background, or Summary or the Detailed Description below.

[0114] This specification includes references to "one embodiment" or "an embodiment." The appearances of the phrases "in one embodiment" or "in an embodiment" do not necessarily refer to the same embodiment. The particular features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure.

[0115] [term] The following paragraphs provide definitions or context for terms found in this disclosure (including the appended claims).

[0116] "Comprising" - This term is open-ended. When this term is used in the following claims, it does not exclude additional structures or steps.

[0117] "Configured to" - Various units or components may be described or claimed as "configured to" perform one or more tasks. In such contexts, "configured to" is used to connote structure by indicating that the unit or component includes structure that performs one or more tasks during operation. Thus, a unit or component may be said to be configured to perform a task even when the specified unit or component is not currently operating (e.g., not powered on or active). Describing a unit or circuit or component as "configured to" perform one or more tasks expressly does not intend to invoke 35 U.S.C. 112, paragraph 6, with respect to that unit or component.

[0118] "first," "second," etc. As used herein, these terms are used as designators for the nouns that follow them and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.).

[0119] "Coupled" - The following statement refers to elements or nodes or features that are "coupled" together. As used herein, unless expressly stated otherwise, "coupled" means that one element or node or feature is directly or indirectly connected to (or in direct or indirect communication with) another element or node or feature, not necessarily by a mechanical coupling.

[0120] Additionally, certain terminology may also be used in the following description for reference purposes only and is therefore not intended to be limiting. For example, terms such as "top," "bottom," "upper," and "lower" refer to directions within the referenced drawings. Terms such as "front," "back," "rear," "side," "outward," and "inward" describe the orientation and / or location of parts of a component in a consistent, but arbitrary, coordinate system that becomes apparent by reference to the text and associated drawings that describe the described component. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

[0121] "Suppress" - As used herein, suppression is used to describe a reduced or minimized effect. When a component or feature is described as suppressing an action, operation, or condition, it may completely prevent that result or outcome, or future state. Additionally, "suppression" can also refer to a decrease or reduction in an outcome, performance, or effect that would otherwise occur. Thus, when a component, element, or feature is said to suppress a result or condition, it is not necessary to completely prevent or eliminate the result or condition.

[0122] Embodiments described herein may relate to semiconductor processing and construction at the substrate front-end (FEOL). FEOL is the first part of integrated circuit (IC) manufacturing, where individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned into a semiconductor substrate or layer. FEOL generally encompasses everything up to but not including the deposition of metal interconnect layers. After the last FEOL step, the result typically is a wafer with isolated (e.g., free of any wires) transistors.

[0123] Embodiments described herein may relate to semiconductor processing and structures at the back-end of the wiring (BEOL). BEOL is the second portion of IC manufacturing where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer, e.g., one or more metallization layers. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In the BEOL portion of the manufacturing process, contacts (pads), interconnect wires, vias, and dielectric structures are formed. In modern IC processes, more than 10 metal layers can be added at the back-end of the wiring.

[0124] The embodiments described below may be applied to FEOL processes and structures, BEOL processes and structures, or both FEOL and BEOL processes and structures. In particular, while example processing schemes may be presented using the context of FEOL processing, such approaches may also be applied to BEOL processing. Similarly, while example processing schemes may be presented using the context of BEOL processing, such approaches may also be applied to FEOL processing.

[0125] Pitch division processes and patterning schemes may be implemented to enable or may be included as part of the embodiments described herein. Pitch division patterning typically refers to pitch division by 2, pitch division by 4, etc. Pitch division schemes may be applied to FEOL processing, BEOL processing, or both FEOL (device) and BEOL (metallization) processing. According to one or more embodiments described herein, optical lithography is first implemented to print unidirectional (e.g., either strictly unidirectional or primarily unidirectional) lines at a predefined pitch. Pitch division processes are then implemented as a technique to increase line density.

[0126] In one embodiment, the term "grating structure" for a fin, gate line, metal line, ILD line, or hardmask line is used herein to refer to a dense pitch grating structure. In such an embodiment, the dense pitch is not directly achievable through selective lithography. For example, a pattern based on selective lithography may be initially formed, but the pitch may be divided by two by using spacer mask patterning, as known in the art. Furthermore, the original pitch may be divided by four by a second spacer mask patterning. Thus, the grid-like patterns described herein may have metal lines, ILD lines, or hardmask lines with substantially consistent widths spaced at a substantially consistent pitch. For example, in some embodiments, the pitch may vary by less than 10 percent and the width may vary by less than 10 percent, and in some embodiments, the pitch may vary by less than 5 percent and the width may vary by less than 5 percent. The grid may be fabricated by patterning, pitch-dividing, pitch-dividing, or pitch-dividing, or other pitch-dividing approaches. In one embodiment, the grating is not necessarily a single pitch.

[0127] In a first example, a pitch divide-by-two can be implemented to double the line density of the fabricated grating structure. Figure 1A shows a cross-sectional view of an initial structure after deposition but before patterning of a hard mask material layer formed on an interlevel dielectric (ILD) layer. Figure 1B shows a cross-sectional view of the structure of Figure 1A after patterning of the hard mask layer using a pitch divide-by-two.

[0128] 1A, an initial structure 100 has a hard mask material layer 104 formed on an interlevel dielectric (ILD) layer 102. A patterned mask 106 is disposed above the hard mask material layer 104. The patterned mask 106 has spacers 108 formed on the hard mask material layer 104 and along the sidewalls of its features (lines).

[0129] Referring to FIG. 1B , the hard mask material layer 104 is patterned using a pitch-by-two approach. Specifically, the patterned mask 106 is first removed. The resulting spacer 108 pattern doubles the density or halves the pitch or features of the mask 106. The spacer 108 pattern is transferred to the hard mask material layer 104, for example, by an etching process, to form the patterned hard mask 110, as illustrated in FIG. 1B . In one such embodiment, the patterned hard mask 110 is formed to have a grid pattern with unidirectional lines. The grid pattern of the patterned hard mask 110 can be a dense-pitched grid structure. For example, the dense pitch may not be directly achievable through the selected lithography technique. Furthermore, although not shown, the original pitch can be divided by four by a second spacer mask patterning. 1B may have hard mask lines with a constant width relative to each other, spaced apart at a constant pitch, and the dimensions achieved may be much smaller than the critical dimensions of the lithographic techniques employed.

[0130] Thus, for either the substrate process (FEOL) or the interconnect process (BEOL), or both, of the integration scheme, the blanket film can be patterned using lithography and etch processes, which may involve, for example, spacer-based double patterning (SBDP) or pitch division by 2, or spacer-based quadruple patterning (SBQP) or pitch division by 4. It should be understood that other pitch division approaches can also be implemented. In any case, in one embodiment, a grid layout can be fabricated by a selected lithography approach, such as 193 nm immersion lithography (193i). The pitch division can be implemented to increase the linear density of the grid layout by a factor of n. A grid layout formed using 193i lithography and an n-fold pitch division can be expressed as a 193i+P / n pitch division. In such an embodiment, 193 nm immersion scaling can be extended to many generations with cost-effective pitch division.

[0131] In the fabrication of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, have become more widely used as device dimensions continue to shrink. Tri-gate transistors are generally fabricated on either bulk silicon substrates or silicon-on-insulator substrates. In some cases, bulk silicon substrates are preferred due to their lower cost and compatibility with existing high-yield bulk silicon substrate infrastructure.

[0132] However, multi-gate transistors cannot be scaled without impact. As the dimensions of these building blocks of microelectronic circuits decrease, and as the number of building blocks that can be fabricated in a given area increases, the constraints on the semiconductor processes used to fabricate these building blocks become greater.

[0133] According to one or more embodiments of the present disclosure, a quarter pitch approach is implemented for patterning the semiconductor layer to form the semiconductor fins. In one or more embodiments, an integrated fin quarter pitch approach is implemented.

[0134] 2A is a schematic diagram of a quarter pitch approach 200 used to fabricate a semiconductor fin according to one embodiment of the present disclosure, and FIG. 2B shows a cross-sectional view of a semiconductor fin fabricated using the quarter pitch approach according to one embodiment of the present disclosure.

[0135] Referring to FIG. 2A , in step (a), a photoresist layer (PR) is patterned to form photoresist features 202. The photoresist features 202 can be patterned using standard lithography processing techniques, such as immersion lithography. In step (b), the photoresist features 202 are used to pattern a material layer, such as an insulator or dielectric hard mask layer, to form first backbone (BB1) features 204. First spacer (SP1) features 206 are then formed adjacent to the sidewalls of the first backbone feature 204. In step (c), the first backbone feature 204 is removed, leaving only the first spacer feature 206. Before or during the removal of the first backbone feature 204, the first spacer feature 206 can be thinned to form a thinned first spacer feature 206′ as illustrated in FIG. 2A . This thinning can be performed before (as shown) or after the removal of BB1 (feature 204), depending on the required spacing and size needed for the BB2 feature (208, described below). In step (d), the first spacer feature 206 or the thinned first spacer feature 206' is used to pattern a material layer, such as an insulator or dielectric hard mask layer, to form a second backbone (BB2) feature 208. Second spacer (SP2) features 210 are then formed adjacent the sidewalls of the second backbone feature 208. In step (e), the second backbone feature 208 is removed, leaving only the second spacer feature 210. The remaining second spacer feature 210 can then be used to pattern a semiconductor layer to provide a plurality of semiconductor fins having a pitch that is a quarter dimension relative to the initial patterned photoresist feature 202. 2B, a plurality of semiconductor fins 250, such as silicon fins formed from a bulk silicon layer, are formed using the second spacer features 210 as a mask for patterning, such as dry or plasma etch patterning. In the example of FIG. 2B, the plurality of semiconductor fins 250 have essentially the same pitch and spacing throughout.

[0136] It should be appreciated that modifying the spacing between the initially patterned photoresist features can alter the structural outcome of the pitch quartering process. In one example, Figure 3A is a schematic diagram of an integrated fin pitch quartering approach 300 used to fabricate a semiconductor fin in accordance with an embodiment of the present disclosure. Figure 3B shows a cross-sectional view of a semiconductor fin fabricated using the integrated fin pitch quartering approach in accordance with an embodiment of the present disclosure.

[0137] Referring to FIG. 3A , in step (a), a photoresist layer (PR) is patterned to form photoresist features 302. The photoresist features 302 can be patterned using standard lithography processing techniques, such as immersion lithography, but their spacing (e.g., spacing referred to as sub-design rule spacing) can ultimately interfere with the design rules required to generate a uniform pitch-multiplied pattern. In step (b), the photoresist features 302 are used to pattern a material layer, such as an insulator or dielectric hard mask layer, to form a first backbone (BB1) feature 304. Next, a first spacer (SP1) feature 306 is formed adjacent to the sidewall of the first backbone feature 304. However, in contrast to the scheme shown in FIG. 2A , some of the adjacent first spacer features 306 are integral spacer features as a result of the photoresist features 302 being denser. In step (c), the first backbone feature 304 is removed, leaving only the first spacer feature 306. Before or after removing the first backbone feature 304, a portion of the first spacer feature 306 may be thinned to form a thinned first spacer feature 306', as shown in FIG. 3A . In step (d), the first spacer feature 306 and the thinned first spacer feature 306' are used to pattern a material layer, such as an insulator or dielectric hard mask layer, to form a second backbone (BB2) feature 308. Second spacer (SP2) features 310 are then formed adjacent the sidewalls of the second backbone feature 308. However, in locations where the BB2 feature 308 is an integral feature, such as the central BB2 feature 308 in FIG. 3A , no second spacers are formed. In step (e), the second backbone feature 308 is removed, leaving only the second spacer feature 310. The remaining second spacer feature 310 may then be used to pattern a semiconductor layer to provide a plurality of semiconductor fins having a quarter pitch dimension compared to the initial patterned photoresist feature 302.

[0138] By way of example, referring to FIG. 3B , multiple semiconductor fins 350, such as silicon fins formed from a bulk silicon layer, are formed using the second spacer features 310 as a mask for patterning, e.g., dry or plasma etch patterning. However, in the example of FIG. 3B , the multiple semiconductor fins 350 have various pitches and spacings. Such an integrated fin spacer patterning approach can be implemented to essentially eliminate the presence of fins at specific locations in a multiple fin pattern. Thus, integrating the first spacer features 306 at specific locations allows for the fabrication of six or four fins based on two first backbone features 304 that typically produce eight fins as described in connection with FIGS. 2A and 2B . As an example, fins within a board can have a tighter pitch than would normally be possible by creating fins at a uniform pitch and then cutting away the unnecessary fins. However, the latter approach can still be implemented in accordance with embodiments described herein.

[0139] In an exemplary embodiment, referring to FIG. 3B of an integrated circuit structure, a first plurality of semiconductor fins 352 have a longest dimension along a first direction (y, into the page). Adjacent individual semiconductor fins 353 of the first plurality of semiconductor fins 352 are spaced apart from one another by a first amount (S1) in a second direction (x), orthogonal to the first direction y. A second plurality of semiconductor fins 354 have a longest dimension along the first direction y. Adjacent individual semiconductor fins 355 of the second plurality of semiconductor fins 354 are spaced apart from one another by the first amount (S1) in the second direction. Proximate semiconductor fins 356 of the first plurality of semiconductor fins 352 and semiconductor fins 357 of the second plurality of semiconductor fins 354 are spaced apart from one another by a second amount (S2) in the second direction x. In one embodiment, the second amount S2 is greater than the first amount S1 but less than twice the first amount S1. In another embodiment, the second amount S2 is greater than twice the first amount S1.

[0140] In one embodiment, the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354 comprise silicon. In one embodiment, the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354 are contiguous with an underlying monocrystalline silicon substrate. In one embodiment, each of the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354 has sidewalls that taper outwardly along the second direction x from the top to the bottom of each of the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354. In one embodiment, the first plurality of semiconductor fins 352 includes exactly five semiconductor fins, and the second plurality of semiconductor fins 354 includes exactly five semiconductor fins.

[0141] 3A and 3B, in another exemplary embodiment, a method for fabricating an integrated circuit structure includes forming a first primary backbone structure 304 (left BBl) and a second primary backbone structure 304 (right BBl). Primary spacer structures 306 are formed adjacent to sidewalls of the first primary backbone structure 304 (left BBl) and the second primary backbone structure 304 (right BBl). The primary spacer structures 306 between the first primary backbone structure 304 (left BBl) and the second primary backbone structure 304 (right BBl) are integrated. The first primary backbone structure (left BBl) and the second primary backbone structure (right BBl) are removed to provide first, second, third, and fourth secondary backbone structures 308. The second and third secondary backbone structures (e.g., the middle pair of secondary backbone structures 308) are integrated. Secondary spacer structures 310 are formed adjacent to sidewalls of the first, second, third, and fourth secondary backbone structures 308. The first, second, third, and fourth secondary backbone structures 308 are then removed. The semiconductor material is then patterned with the secondary spacer structures 310 to form semiconductor fins 350 in the semiconductor material.

[0142] In one embodiment, the first primary backbone structure 304 (left BB1) and the second primary backbone structure 304 (right BB1) are patterned with a sub-design rule spacing between the first and second primary backbone structures. In one embodiment, the semiconductor material includes silicon. In one embodiment, each of the semiconductor fins 350 has sidewalls that taper outwardly along a second direction x from the top to the bottom of each of the semiconductor fins 350. In one embodiment, the semiconductor fins 350 are continuous with the underlying single crystal silicon substrate. In one embodiment, patterning the semiconductor material with the secondary spacer structures 310 includes forming a first plurality of semiconductor fins 352 having a longest dimension along a first direction y, wherein adjacent individual semiconductor fins of the first plurality of semiconductor fins 352 are spaced apart from each other by a first amount S1 in a second direction x that is orthogonal to the first direction y. A second plurality of semiconductor fins 354 are formed having a longest dimension along a first direction y, and adjacent individual semiconductor fins of the second plurality of semiconductor fins 354 are spaced apart from one another in the second direction x by a first amount S1. Proximate semiconductor fins 356 of the first plurality of semiconductor fins 352 and semiconductor fins 357 of the second plurality of semiconductor fins 354 are spaced apart from one another in the second direction x by a second amount S2. In one embodiment, the second amount S2 is greater than the first amount S1. In one such embodiment, the second amount S2 is less than twice the first amount S1. In another such embodiment, the second amount S2 is greater than twice but less than three times the first amount S1. In one embodiment, as illustrated in FIG. 3B , the first plurality of semiconductor fins 352 has exactly five semiconductor fins, and the second plurality of semiconductor fins 254 has exactly five semiconductor fins.

[0143] In another aspect, in a fin trimming process where fin removal is performed instead of an integrated fin approach, it should be understood that the fins may be trimmed (removed) by physically removing the fins during hard mask patterning. As an example of the latter approach, Figures 4A-4C show cross-sectional views illustrating various steps in a method for fabricating multiple semiconductor fins, according to one embodiment of the present disclosure.

[0144] Referring to FIG. 4A , a patterned hard mask layer 402 is formed over a semiconductor layer 404, such as a bulk monocrystalline silicon layer. Referring to FIG. 4B , fins 406 are then formed in the semiconductor layer 404, for example, by a dry or plasma etching process. Referring to FIG. 4C , selected fins 406 are removed, for example, by using a masking and etching process. In the example shown, one of the fins 406 may be removed, leaving a remnant fin stub 408, as illustrated in FIG. 4C . In such a “trim fin last” approach, the hard mask 402 is patterned as a whole to provide a lattice structure without removing or altering individual features. The number of fins is not changed until after the fins are fabricated.

[0145] In another aspect, multi-layer trench isolation regions, which may be referred to as shallow trench isolation (STI) structures, may be implemented between the semiconductor fins. In one embodiment, multi-layer STI structures are formed between silicon fins formed in a bulk silicon substrate to define sub-fin regions of the silicon fins.

[0146] It may be desirable to use bulk silicon for fin or tri-gate based transistors. However, there are concerns that the region below the active silicon fin portion of the device (e.g., gate control region or HSi) (sub-fin) may have weak or no gate control. Therefore, if the source or drain regions are at or below the HSi location, there may be leakage paths through the sub-fin region. For proper device operation, it may be necessary to control the leakage paths in the sub-fin region.

[0147] One approach to address the above issue is to increase the concentration of ZnO in the sub-fin region by increasing the concentration of ZnO in the sub-fin region. 3 This involves the use of a well implant operation, where the fins are doped to a high level (e.g., about 1E18 / cm). This prevents sub-fin leakage, but also leads to significant doping in the fins. The addition of a halo implant further increases the fin doping, thereby causing the edges of the linear fins to be doped to a high level (e.g., about 1E18 / cm). 3 doped to a higher level.

[0148] Another approach involves doping provided through sub-fin doping, which does not necessarily provide the same level of doping to the HSi portion of the fin. The process may involve selectively doping the sub-fin region of a tri-gate or FinFET transistor fabricated on a bulk silicon wafer, for example, through sub-fin out-diffusion of tri-gate doping glass. For example, selectively doping the sub-fin region of a tri-gate or FinFET transistor can mitigate sub-fin leakage while simultaneously maintaining low fin doping. After recessing from the fin sidewalls, solid-state doping sources (e.g., p-type and n-type doped oxides, nitrides, or carbides) can be incorporated into the transistor process flow to provide sufficient doping to the sub-fin region while keeping the fin body relatively undoped.

[0149] Thus, the process scheme may involve the use of a solid-source doping layer (e.g., boron-doped oxide) deposited on the fin following fin etching. Later, after trench fill and polishing, the doping layer is recessed along with the trench fill material to define the device's fin height (HSi). This step removes the doping layer from the fin sidewalls above the HSi. Thus, the doping layer is present only along the fin sidewalls in the sub-fin region, ensuring precise control of doping placement. After a drive-in anneal, the heavy doping is confined to the sub-fin region and rapidly transitions to lighter doping in the adjacent region of the fin above the HSi (which forms the transistor's channel region). Typically, borosilicate glass (BSG) is implemented for NMOS fin doping, while phosphosilicate glass (PSG) or arsenic phosphate glass (AsSG) layers are implemented for PMOS fin doping. In one example, such a P-type solid-state dopant source layer is a BSG layer having a boron concentration in the range of approximately 0.1-10 wt%. In another example, such an N-type solid-state dopant source layer is a PSG layer or an AsSG layer having a phosphorus or arsenic concentration in the range of approximately 0.1-10 wt%. A silicon nitride capping layer may be included in the doping layer, while a silicon dioxide or silicon oxide fill material may be included in the silicon nitride capping layer.

[0150] According to another embodiment of the present disclosure, sub-fin leakage is sufficiently small for relatively thin fins (e.g., fins having a width less than about 20 nanometers) that an undoped or lightly doped silicon oxide or silicon dioxide film is formed directly adjacent to the fin, a silicon nitride layer is formed on the undoped or lightly doped silicon oxide or silicon dioxide film, and a silicon dioxide or silicon oxide fill material is included in the silicon nitride capping layer. It should be understood that doping of the sub-fin region, such as halo doping, can also be implemented in such structures.

[0151] FIG. 5A illustrates a cross-sectional view of a pair of semiconductor fins separated by a triple-layer trench isolation structure according to one embodiment of the present disclosure.

[0152] 5A, an integrated circuit structure includes a fin 502, such as a silicon fin. The fin 502 includes a lower fin portion (sub-fin) 502A and an upper fin portion 502B (H Si ) A first insulating layer 504 is immediately on the sidewalls of the lower fin portion 502A of the fin 502. A second insulating layer 506 is immediately on the first insulating layer 504, which is immediately on the sidewalls of the lower fin portion 502A of the fin 502. A dielectric fill material 508 is immediately adjacent to the second insulating layer 506, which is immediately on the first insulating layer 504, which is immediately on the sidewalls of the lower fin portion 502A of the fin 502.

[0153] In one embodiment, the first insulating layer 504 is an undoped insulating layer comprising silicon and oxygen, such as a silicon oxide or silicon dioxide insulating layer. In one embodiment, the first insulating layer 504 comprises silicon and oxygen and is free of other atomic species having an atomic concentration greater than 1E15 atoms / cubic centimeter. In one embodiment, the thickness of the first insulating layer 504 is in the range of 0.5 to 2 nanometers.

[0154] In one embodiment, the second insulating layer 506 comprises silicon and nitrogen, such as a stoichiometric SiN silicon nitride insulating layer, a silicon-rich silicon nitride insulating layer, or a silicon-poor silicon nitride insulating layer. In one embodiment, the thickness of the second insulating layer 506 is in the range of 2 to 5 nanometers.

[0155] In one embodiment, the dielectric fill material 508 comprises silicon and oxygen, such as a silicon oxide or silicon dioxide insulating layer. In one embodiment, a gate electrode is eventually formed above the top of and laterally adjacent to the sidewall of the upper fin portion 502B of the fin 502.

[0156] It should be understood that during processing, the upper fin portion of the semiconductor fin may be eroded or consumed. Also, the trench isolation structure between the fins may be similarly eroded and have a non-planar topography, or may be formed by non-planar topography-up fabrication. By way of example, FIG. 5B illustrates a cross-sectional view of another pair of semiconductor fins separated by another three-layer trench isolation structure in accordance with another embodiment of the present disclosure.

[0157] 5B , the integrated circuit structure includes a first fin 552, such as a silicon fin. The first fin 552 includes a lower fin portion 552A and an upper fin portion 552B, and a shoulder feature 554 in the region between the lower fin portion 552A and the upper fin portion 552B. A second fin 562, such as a second silicon fin, includes a lower fin portion 562A and an upper fin portion 562B, and a shoulder feature 564 in the region between the lower fin portion 562A and the upper fin portion 562B. A first insulating layer 574 is disposed immediately on the sidewall of the lower fin portion 552A of the first fin 552 and immediately on the sidewall of the lower fin portion 562A of the second fin 562. The first insulating layer 574 has a first end 574A that is substantially flush with the shoulder feature 554 of the first fin 552, and the first insulating layer 574 also has a second end 574B that is substantially flush with the shoulder feature 564 of the second fin 562. The second insulating layer 576 is immediately on top of the first insulating layer 574, which is immediately on the sidewall of the lower fin portion 552A of the first fin 552, and immediately on top of the sidewall of the lower fin portion 562A of the second fin 562.

[0158] The dielectric fill material 578 is immediately adjacent to the second insulating layer 576 immediately above the sidewall of the lower fin portion 552A of the first fin 552 and immediately above the first insulating layer 574 immediately above the sidewall of the lower fin portion 562A of the second fin 562. In one embodiment, the dielectric fill material 578 has a top surface 578A, and a portion of the top surface 578A of the dielectric fill material 578 underlies at least one of the shoulder features 554 of the first fin 552 and underlies at least one of the shoulder features 564 of the second fin 562, as shown in FIG.

[0159] In one embodiment, first insulating layer 574 is an undoped insulating layer comprising silicon and oxygen, such as a silicon oxide or silicon dioxide insulating layer. In one embodiment, first insulating layer 574 comprises silicon and oxygen and does not contain any other atomic species having an atomic concentration greater than 1E15 atoms per cubic centimeter. In one embodiment, first insulating layer 574 has a thickness in the range of 0.5 to 2 nanometers.

[0160] In one embodiment, second insulating layer 576 comprises silicon and nitrogen, such as a stoichiometric SiN silicon nitride insulating layer, a silicon-rich silicon nitride insulating layer, or a silicon-poor silicon nitride insulating layer. In one embodiment, the thickness of second insulating layer 576 is in the range of 2 to 5 nanometers.

[0161] In one embodiment, the dielectric fill material 578 comprises silicon and oxygen, such as a silicon oxide or silicon dioxide insulating layer. In one embodiment, a gate electrode is ultimately formed above the top of and laterally adjacent to the sidewall of the upper fin portion 552B of the first fin 552 and above the top of and laterally adjacent to the sidewall of the upper fin portion 562B of the second fin 562. The gate electrode is also above the dielectric fill material 578 between the first fin 552 and the second fin 562.

[0162] 6A-6D illustrate cross-sectional views of various steps in the fabrication of a triple-layer trench isolation structure according to one embodiment of the present disclosure.

[0163] 6A, a method of fabricating an integrated circuit structure includes forming a fin 602, such as a silicon fin. As shown in FIG. 6B, a first insulating layer 604 is conformally formed immediately over the fin 602. In one embodiment, the first insulating layer 604 includes silicon and oxygen, and is free of other atomic species having an atomic concentration greater than 1E15 atoms per cubic centimeter.

[0164] Referring to Figure 6C, a second insulating layer 606 is conformally formed immediately above the first insulating layer 604. In one embodiment, the second insulating layer 606 comprises silicon and nitrogen. A dielectric fill material 608 is formed immediately above the second insulating layer 606, as shown in Figure 6D.

[0165] In one embodiment, the method further involves recessing the dielectric fill material 608, the first insulating layer 604, and the second insulating layer 606 to provide a fin 602 having an exposed upper fin portion 602A (e.g., upper fin portion 502B, 552B, or 562B of FIGS. 5A and 5B ). The resulting structure may be described with reference to FIG. 5A or 5B . In one embodiment, recessing the dielectric fill material 608, the first insulating layer 604, and the second insulating layer 606 involves using a wet etching process. In another embodiment, recessing the dielectric fill material 608, the first insulating layer 604, and the second insulating layer 606 involves using a plasma etching or a dry etching process.

[0166] In one embodiment, first insulating layer 604 is formed using a chemical vapor deposition process. In one embodiment, second insulating layer 606 is formed using a chemical vapor deposition process. In one embodiment, dielectric fill material 608 is formed using a spin-on process. In one such embodiment, dielectric fill material 608 is a spin-on material that is exposed to a water vapor treatment, for example, either before or after the recess etch process, to provide a hardened material that includes silicon and oxygen. In one embodiment, a gate electrode is ultimately formed above the top of and laterally adjacent to the sidewalls of the upper fin portion of fin 602.

[0167] In another aspect, gate sidewall spacer material may be retained above certain trench isolation regions to protect them from erosion during subsequent processing steps. For example, Figures 7A-7E show perspective three-dimensional cross-sectional views of various steps in a method for fabricating an integrated circuit structure, according to one embodiment of the present disclosure.

[0168] 7A , a method of fabricating an integrated circuit structure includes forming a fin 702, such as a silicon fin. The fin 702 has a lower fin portion 702A and an upper fin portion 702B. An insulating structure 704 is formed directly adjacent a sidewall of the lower fin portion 702A of the fin 702. A gate structure 706 is formed above the upper fin portion 702B and above the insulating structure 704. In one embodiment, the gate structure is a placeholder or dummy gate structure including a sacrificial gate dielectric layer 706A, a sacrificial gate 706B, and a hard mask 706C. A dielectric material 708 is formed conformally to the upper fin portion 702B of the fin 702, conformally to the gate structure 706, and conformally to the insulating structure 704.

[0169] 7B, a hardmask material 710 is formed over the dielectric material 708. In one embodiment, the hardmask material 710 is a carbon-based hardmask material formed using a spin-on process.

[0170] 7C, the hard mask material 710 is recessed to form recessed hard mask material 712, exposing a portion of the dielectric material 708 conformal to the upper fin portion 702B of the fin 702 and conformal to the gate structure 706. The recessed hard mask material 712 covers a portion of the dielectric material 708 conformal to the insulating structure 704. In one embodiment, the hard mask material 710 is recessed using a wet etching process. In another embodiment, the hard mask material 710 is recessed using an ashing, dry etching, or plasma etching process.

[0171] Referring to FIG. 7D, the dielectric material 708 is anisotropically etched to form patterned dielectric material 714 along the sidewalls of the gate structure 706 (as dielectric spacers 714A), along portions of the sidewalls of the upper fin portion 702B of the fin 702, and above the insulating structure 704.

[0172] Referring to Figure 7E, the recessed hard mask material 712 is removed from the structure of Figure 7D. In one embodiment, the gate structure 706 is a dummy gate structure, and subsequent processing includes replacing the gate structure 706 with a permanent gate dielectric and gate electrode stack. In one embodiment, further processing includes forming buried source or drain structures on opposing sides of the gate structure 706, as described in more detail below.

[0173] Referring again to FIG. 7E, in one embodiment, an integrated circuit structure 700 includes a first fin (left 702), such as a first silicon fin, having a lower fin portion 702A and an upper fin portion 702B. The integrated circuit structure further includes a second fin (right 702), such as a second silicon fin, having a lower fin portion 702A and an upper fin portion 702B. An insulating structure 704 is directly adjacent to a sidewall of the lower fin portion 702A of the first fin and directly adjacent to a sidewall of the lower fin portion 702A of the second fin. A gate electrode 706 is above the upper fin portion 702B of the first fin (left 702), above the upper fin portion 702B of the second fin (right 702), and above a first portion 704A of the insulating structure 704. The first dielectric spacer 714A is along the sidewall of the upper fin portion 702B of the first fin (left 702), and the second dielectric spacer 702C is along the sidewall of the upper fin portion 702B of the second fin (right 702). The second dielectric spacer 714C is continuous with the first dielectric spacer 714B above the second portion 704B of the insulating structure 704 between the first fin (left 702) and the second fin (right 702).

[0174] In one embodiment, the first and second dielectric spacers 714B and 714C comprise silicon and nitrogen, such as a stoichiometric Si3N4 silicon nitride material, a silicon-rich silicon nitride material, or a silicon-poor silicon nitride material.

[0175] In one embodiment, the integrated circuit structure 700 further includes buried source or drain structures on opposing sides of the gate electrode 706, the buried source or drain structures having bottom surfaces below the top surfaces of the first and second dielectric spacers 714B and 714C along the sidewalls of the upper fin portions 702B of the first and second fins 702, and the source or drain structures having top surfaces above the top surfaces of the first and second dielectric spacers 714B and 714C along the sidewalls of the upper fin portions 702B of the first and second fins 702. In one embodiment, the isolation structure 704 includes a first isolation layer, a second isolation layer immediately above the first isolation layer, and a dielectric fill material immediately beside the second isolation layer, as also described below in connection with FIG.

[0176] 8A-8F show slightly projected cross-sectional views taken along axis aa' of FIG. 7E for various steps in a method of fabricating an integrated circuit structure according to one embodiment of the present disclosure.

[0177] Referring to FIG. 8A, a method of fabricating an integrated circuit structure includes forming a fin 702, such as a silicon fin. The fin 702 has a lower fin portion (not shown in FIG. 8A) and an upper fin portion 702B. An insulating structure 704 is formed directly adjacent to the sidewall of the lower fin portion 702A of the fin 702. A pair of gate structures 706 are formed above the upper fin portion 702B and above the insulating structure 704. It should be understood that the perspectives shown in FIGS. 8A-8F are slightly projected to show the portion of the gate structure 706 and insulating structure in front of the upper fin portion 702B (off-page), such that the upper fin portion is slightly off-page. In one embodiment, the gate structure 706 is a placeholder or dummy gate structure including a sacrificial gate dielectric layer 706A, a sacrificial gate 706B, and a hard mask 706C.

[0178] Referring to FIG. 8B, which corresponds to the process step described in connection with FIG. 7A, a dielectric material 708 is formed conformally to the upper fin portion 702B of the fin 702, conformally to the gate structure 706, and conformally to the exposed portions of the insulating structure 704.

[0179] 8C, which corresponds to the process step described in connection with Figure 7B, a hard mask material 710 is formed over the dielectric material 708. In one embodiment, the hard mask material 710 is a carbon-based hard mask material formed using a spin-on process.

[0180] 8D, which corresponds to the process step described in connection with FIG. 7C, hard mask material 710 is recessed to form recessed hard mask material 712, exposing a portion of dielectric material 708 conformal to upper fin portion 702B of fin 702 and conformal to gate structure 706. Recessed hard mask material 712 covers a portion of dielectric material 708 conformal to insulating structure 704. In one embodiment, hard mask material 710 is recessed using a wet etching process. In another embodiment, hard mask material 710 is recessed using an ashing, dry etching, or plasma etching process.

[0181] Referring to Figure 8E, which corresponds to the process step described in connection with Figure 7D, dielectric material 708 is anisotropically etched to form patterned dielectric material 714 along the sidewalls of gate structure 706 (as portion 714A), along a portion of the sidewalls of upper fin portion 702B of fin 702, and above insulating structure 704.

[0182] Referring to Figure 8F, which corresponds to the process step described in connection with Figure 7E, the recessed hard mask material 712 is removed from the structure of Figure 8E. In one embodiment, the gate structure 706 is a dummy gate structure, and subsequent processing includes replacing the gate structure 706 with a permanent gate dielectric and gate electrode stack. In one embodiment, further processing includes forming buried source or drain structures on opposing sides of the gate structure 706, as described in more detail below.

[0183] Referring again to FIG. 8F, in one embodiment, integrated circuit structure 700 includes a fin 702, such as a silicon fin, having a lower fin portion (not shown in FIG. 8F) and an upper fin portion 702B. An insulating structure 704 is directly adjacent to a sidewall of the lower fin portion of fin 702. A first gate electrode (left 706) is above the upper fin portion 702B and above a first portion 704A of insulating structure 704. A second gate electrode (right 706) is above the upper fin portion 702B and above a second portion 704A' of insulating structure 704. The first dielectric spacer (right 714A of left 706) is along the sidewall of the first gate electrode (left 706), and the second dielectric spacer (left 714A of right 706) is along the sidewall of the second gate electrode (right 706), and the second dielectric spacer is continuous with the first dielectric spacer above the third portion 704A″ of the insulating structure 704 between the first gate electrode (left 706) and the second gate electrode (right 706).

[0184] Figure 9A shows a slightly projected cross-sectional view along axis a-a' of Figure 7E of an integrated circuit structure including a permanent gate stack and epitaxial source or drain regions according to one embodiment of the present disclosure, and Figure 9B shows a cross-sectional view along axis b-b' of Figure 7E of an integrated circuit structure including epitaxial source or drain regions and a multi-layer trench isolation structure according to one embodiment of the present disclosure.

[0185] 9A and 9B, in one embodiment, an integrated circuit structure includes buried source or drain structures 910 on opposite sides of a gate electrode 706. The buried source or drain structures 910 have bottom surfaces 910A along the sidewalls of the upper fin portions 702B of the first and second fins 702 and below the top surfaces 990 of the first and second dielectric spacers 714B and 714C. The buried source or drain structures 910 have top surfaces 910B along the sidewalls of the upper fin portions 702B of the first and second fins 702 and above the top surfaces of the first and second dielectric spacers 714B and 714C.

[0186] In one embodiment, the gate stack 706 is a permanent gate stack 920. In one such embodiment, the permanent gate stack 920 includes a gate dielectric layer 922, a first gate layer 924, such as a work function gate layer, and a gate fill material 926, as illustrated in Figure 9A. In one embodiment, where the permanent gate structure 920 is above the insulating structure 704, the permanent gate structure 920 is formed on a residual polysilicon portion 930, which may be a remnant of a replacement gate process involving a sacrificial polysilicon gate electrode.

[0187] In one embodiment, the insulating structure 704 includes a first insulating layer 902, a second insulating layer 904 immediately above the first insulating layer 902, and a dielectric fill material 906 immediately adjacent to the second insulating layer 904. In one embodiment, the first insulating layer 902 is an undoped insulating layer including silicon and oxygen. In one embodiment, the second insulating layer 904 includes silicon and nitrogen. In one embodiment, the dielectric fill material 906 includes silicon and oxygen.

[0188] In another aspect, the buried epitaxial source or drain regions are implemented as source or drain structures for the semiconductor fins. By way of example, Figure 10 shows a cross-sectional view of an integrated circuit structure cut at a source or drain location according to one embodiment of the present disclosure.

[0189] 10, an integrated circuit structure 1000 includes a P-type device, such as a P-type metal oxide semiconductor (PMOS) device, and an N-type device, such as an N-type metal oxide semiconductor (PMOS) device.

[0190] The PMOS device of FIG. 10 includes a first plurality of semiconductor fins 1002, such as silicon fins, formed from a bulk silicon substrate 1001. At source or drain locations, the top portions of the fins 1002 are removed and the same or different semiconductor material is grown to form source or drain structures 1004. It should be understood that the source or drain structures 1004 will appear identical in a cross-sectional view taken on either side of the gate electrode. For example, they will appear essentially identical on the source side as on the drain side. In one embodiment, as shown, the source or drain structures 1004 have portions below and above the top surface of the insulating structure 1006. In one embodiment, as shown, the source or drain structures 1004 are strongly faceted. In one embodiment, a conductive contact 1008 is formed above the source or drain structures 1004. However, in such an embodiment, the strong faceting and relatively wide growth of the source or drain structures 1004 at least partially inhibits good coverage by the conductive contact 1008.

[0191] The NMOS device of FIG. 10 includes a second plurality of semiconductor fins 1052, such as silicon fins, formed from a bulk silicon substrate 1001. At the source or drain locations, the top portions of the fins 1052 are removed and the same or different semiconductor material is grown to form source or drain structures 1054. It should be understood that the source or drain structures 1054 will appear identical in a cross-sectional view taken on either side of the gate electrode. For example, they will appear essentially identical on the source side as on the drain side. In one embodiment, as shown, the source or drain structures 1054 include portions below and above the top surface of the insulating structure 1006. In one embodiment, as shown, the source or drain structures 1054 are weakly faceted compared to the source or drain structures 1004. In one embodiment, a conductive contact 1058 is formed above the source or drain structures 1054. In one such embodiment, the relatively weak faceting of source or drain structure 1054 (compared to source or drain structure 1004 ) and the resulting relatively narrow growth promotes good coverage by conductive contact 1058 .

[0192] The shape of the source or drain structure of a PMOS device can be varied to improve the contact area with the overlying contact. For example, Figure 11 shows a cross-sectional view of another integrated circuit structure cut at the source or drain location according to one embodiment of the present disclosure.

[0193] Referring to FIG. 11 , an integrated circuit structure 1100 includes a P-type semiconductor (e.g., PMOS) device. The PMOS device includes a first fin 1102, such as a silicon fin. A first epitaxial source or drain structure 1104 is embedded in the first fin 1102. In one embodiment, although not shown, the first epitaxial source or drain structure 1104 is on a first side of a first gate electrode (which may be formed above an upper fin portion, such as a channel portion of the fin 1102), and a second epitaxial source or drain structure is embedded in the first fin 1102 on a second side of such first gate electrode opposite the first side. In one embodiment, the first and second epitaxial source or drain structures 1104 include silicon and germanium and have a profile 1105. In one embodiment, the profile is a matchstick-shaped profile, as illustrated in FIG. 11 . A first conductive electrode 1108 is above the first epitaxial source or drain structure 1104.

[0194] 11 , in one embodiment, the integrated circuit structure 1100 also includes an N-type semiconductor (e.g., NMOS) device. The NMOS device includes a second fin 1152, such as a silicon fin. A third epitaxial source or drain structure 1154 is embedded in the second fin 1152. In one embodiment, although not shown, the third epitaxial source or drain structure 1154 is on a first side of a second gate electrode (which may be formed above an upper fin portion, such as a channel portion, of the fin 1152), and a fourth epitaxial source or drain structure is embedded in the second fin 1152 on a second side of such second gate electrode opposite the first side. In one embodiment, the third and fourth epitaxial source or drain structures 1154 include silicon and have profiles substantially identical to the profiles 1105 of the first and second epitaxial source or drain structures 1004. A second conductive electrode 1158 overlies the third epitaxial source or drain structure 1154 .

[0195] In one embodiment, the first epitaxial source or drain structure 1104 is weakly faceted. In one embodiment, the height of the first epitaxial source or drain structure 1104 is about 50 nanometers and the width is in the range of 30-35 nanometers. In one such embodiment, the height of the third epitaxial source or drain structure 1154 is about 50 nanometers and the width is in the range of 30-35 nanometers.

[0196] In one embodiment, the first epitaxial source or drain structure 1104 has a graded germanium concentration from about 20% at the bottom 1104A of the first epitaxial source or drain structure 1104 to about 45% at the top 1104B of the first epitaxial source or drain structure 1104. In one embodiment, the first epitaxial source or drain structure 1104 is doped with boron atoms. In one such embodiment, the third epitaxial source or drain structure 1154 is doped with phosphorus or arsenic atoms.

[0197] 12A-12D show cross-sectional views taken at a source or drain location illustrating various steps in the fabrication of an integrated circuit structure according to one embodiment of the present disclosure.

[0198] Referring to FIG. 12A, a method of fabricating an integrated circuit structure includes forming a fin, such as a silicon fin, formed from a silicon substrate 1201. Fin 1202 has a lower fin portion 1202A and an upper fin portion 1202B. In one embodiment, not shown, at a location deep within the page, a gate electrode is formed over a portion of upper fin portion 1202B of fin 1202. Such gate electrode has a first side opposite a second side and defines source or drain locations on the first and second sides. For example, for purposes of illustration, the cross-sectional views of FIGS. 12A-12D are taken through one of the source or drain locations on one of the sides of the gate electrode.

[0199] 12B, the source or drain locations of the fin 1202 are recessed to form a recessed fin portion 1206. The recessed source or drain locations of the fin 1202 can be on a side of the gate electrode and on a second side of the gate electrode. Referring to both FIGS. 12A and 12B, in one embodiment, a dielectric spacer 1204 is formed along a portion of the sidewall of the fin 1202, for example, on a side of the gate structure. In one such embodiment, recessing the fin 1202 involves recessing the fin 1202 below a top surface 1204A of the dielectric spacer 1204.

[0200] 12C, an epitaxial source or drain structure 1208 is formed on the recessed fin 1206, and thus may be formed, for example, on a side of the gate electrode. In one such embodiment, a second epitaxial source or drain structure is formed on a second portion of the recessed fin 1206 on a second side of such gate electrode. In one embodiment, the epitaxial source or drain structure 1208 comprises silicon and germanium and has a matchstick-shaped profile, as illustrated in FIG. 12C. In one embodiment, a dielectric spacer 1204 is included along a lower portion 1208A of the sidewall of the epitaxial source or drain structure 1208, as illustrated.

[0201] 12D, a conductive electrode 1210 is formed on the epitaxial source or drain structure 1208. In one embodiment, the conductive electrode 1210 includes a conductive barrier layer 1210A and a conductive fill material 1201B. In one embodiment, the conductive electrode 1210 follows the profile of the epitaxial source or drain structure 1208, as shown. In other embodiments, the top of the epitaxial source or drain structure 1208 is eroded during the fabrication of the conductive electrode 1210.

[0202] In another aspect, fin trim isolation (FTI) and single gate spacing are described for isolated fins. Non-planar transistors utilizing fins of semiconductor material protruding from the substrate surface utilize gate electrodes that cover two, three, or even all sides of the fin (i.e., dual-gate, tri-gate, nanowire transistors). Source and drain regions are then typically formed on either side of the gate electrode, either within the fin or as regrown portions of the fin. A gap or space may be formed between two adjacent fins to separate the source or drain region of a first non-planar transistor from the source or drain region of an adjacent second non-planar transistor. Such a separation gap generally requires some type of masked etch. Once isolated, gate stacks are then typically patterned above the individual fins, again using some type of masked etch (e.g., a line etch or an open etch, depending on the particular implementation).

[0203] One potential problem with the above-described fin isolation techniques is that the gate is not self-aligned with the edge of the fin; alignment of the gate stack pattern with the semiconductor fin pattern depends on the overlay of these two patterns. Lithographic overlay tolerances are therefore added to the dimensions of the semiconductor fin and isolation gap, requiring the fin to be longer and the isolation gap to be larger than would be required for a given level of transistor functionality. Device architectures and fabrication techniques that reduce such excess dimensions therefore provide highly advantageous improvements in transistor density.

[0204] Another potential problem with the fin isolation techniques described above is that stress in the semiconductor fin, which is desirable for improving carrier mobility, may be lost from the channel region of the transistor if too much of the fin surface remains free during fabrication, allowing for relaxation of fin strain. Thus, device architectures and fabrication techniques that maintain higher levels of desirable fin stress would provide advantageous improvements in non-planar transistor performance.

[0205] Described herein are through-gate fin isolation architectures and techniques according to an embodiment of the present disclosure. In the exemplary embodiment shown, non-planar transistors in a microelectronic device, such as an integrated circuit (IC), are isolated from one another in a manner that is self-aligned with the transistor's gate electrode. While embodiments of the present disclosure apply to virtually any IC that utilizes non-planar transistors, exemplary ICs include, but are not limited to, microprocessor cores including logic and memory (SRAM) portions, RFICs (e.g., radio frequency ICs including digital baseband and analog front-end modules), and power ICs.

[0206] In embodiments, two ends of adjacent semiconductor fins are electrically isolated from each other by an isolation region positioned relative to the gate electrode using only one patterning mask level. In one embodiment, a single mask is employed to form a plurality of sacrificial placeholder stripes with a fixed pitch, where a first subset of the placeholder stripes defines the location or dimensions of the isolation region, while a second subset of the placeholder stripes defines the location or dimensions of the gate electrode. In particular embodiments, the first subset of placeholder stripes are removed and isolation cuts are formed in the semiconductor fin in the openings resulting from the removal of the first subset, while the second subset of placeholder stripes are ultimately replaced with a non-sacrificial gate electrode stack. Because a subset of the placeholders utilized for gate electrode replacement are employed to form the isolation region, the method and resulting architecture are referred to herein as “through-gate” isolation. One or more through-gate isolation embodiments described herein may enable, for example, higher transistor density and higher levels of advantageous transistor channel stress.

[0207] Isolation defined after the placement or definition of the gate electrode allows for greater transistor density because the fin isolation dimension and placement pitch can be perfectly matched to the gate electrode pitch, resulting in both the gate electrode and isolation regions being integer multiples of the minimum feature pitch of a single masking level. In further embodiments in which the semiconductor fin has a lattice mismatch with the substrate on which the fin is placed, a greater degree of strain is maintained by defining the isolation after the placement or definition of the gate electrode. For such embodiments, other features of the transistor (such as the gate electrode and added source or drain material) formed before the edge of the fin is defined help to mechanically retain the fin strain after the isolation cuts are made in the fin.

[0208] To provide further context, transistor scaling can benefit from denser packing of cells within a chip. Currently, most cells are isolated from their surroundings by two or more dummy gates with buried fins. Cells are isolated by etching fins under these two or more dummy gates that connect one cell to another. Scaling could be significantly beneficial if the number of dummy gates isolating neighboring cells could be reduced from two or more to one. As explained above, one solution requires two or more dummy gates. The fins under the two or more dummy gates are etched during fin patterning. A potential problem with such an approach is that the dummy gates consume space on the chip that could be used for cells. In one embodiment, the approach described herein allows for the isolation of neighboring cells using only a single dummy gate.

[0209] In one embodiment, the fin trim isolation approach is implemented as a self-aligned patterning scheme, where the fin under a single gate is etched away. Thus, neighboring cells can be isolated by a single dummy gate. Advantages of such an approach may include saving space on the chip and enabling more computing power for a given area. The approach may also enable fin trimming to be performed at sub-fin pitch distances.

[0210] 13A and 13B show plan views illustrating various steps in a method for patterning fins with multi-gate spacing to form localized isolation structures according to one embodiment of the present disclosure.

[0211] 13A, there is shown a plurality of fins 1302 having a length along a first direction 1304. A grid 1306 having spaces 1307 therebetween is shown along a second direction 1308 orthogonal to the first direction 1304, defining locations for the eventual formation of a plurality of gate lines.

[0212] 13B , portions of the plurality of fins 1302 are cut (e.g., removed by an etching process), leaving fin 1310 with cuts 1312 therein. Thus, the isolation structures ultimately formed at cuts 1312 have dimensions larger than a single gate line (e.g., the dimensions of three gate lines 1306). Thus, the gate structures ultimately formed along the locations of gate lines 1306 will be formed, at least in part, above the isolation structures formed at cuts 1312. Thus, cuts 1312 are relatively wide fin cuts.

[0213] 14A to 14D show plan views illustrating various steps in a method for patterning a fin with a single gate spacing to form a localized isolation structure according to another embodiment of the present disclosure.

[0214] 14A , a method of fabricating an integrated circuit structure includes forming a plurality of fins 1402, each of the plurality of fins 1402 having a longest dimension along a first direction 1404. A plurality of gate structures 1406 overlie the plurality of fins 1402, each of the gate structures 1406 having a longest dimension along a second direction 1408 that is orthogonal to the first direction 1404. In one embodiment, the gate structures 1406 are sacrificial or dummy gate lines and are fabricated from, for example, polycrystalline silicon. In one embodiment, the plurality of fins 1402 are silicon fins and are continuous with a portion of an underlying silicon substrate.

[0215] Referring to FIG. 14B, a dielectric material structure 1410 is formed between adjacent ones of the plurality of gate structures 1406.

[0216] 14C , a portion 1412 of the gate structures 1406 is removed to expose a portion 1414 of each of the fins 1402. In one embodiment, removing the portion 1412 of the gate structures 1406 involves using a lithography window 1416 that is wider than a width 1418 of the portion 1412 of the gate structures 1406.

[0217] 14D , the exposed portion 1414 of each of the multiple fins 1402 is removed to form a cut region 1420. In one embodiment, the exposed portion 1414 of each of the multiple fins 1402 is removed using a dry or plasma etching process. In one embodiment, removing the exposed portion 1414 of each of the multiple fins 1402 involves etching to a depth that is less than the height of the multiple fins 1402. In one such embodiment, the depth is greater than the depth of the source or drain regions in the multiple fins 1402. In one embodiment, the depth is greater than the depth of the active portions of the multiple fins 1402 to provide an isolation margin. In one embodiment, the exposed portion 1414 of each of the multiple fins 1402 is removed without, or substantially without, etching the source or drain regions (e.g., epitaxial source or drain regions) of the multiple fins 1402. In one such embodiment, the exposed portion 1414 of each of the plurality of fins 1402 is removed without laterally etching or substantially laterally etching the source or drain regions (such as epitaxial source or drain regions) of the plurality of fins 1402.

[0218] In one embodiment, the cut region 1420 is eventually filled with an insulating layer, for example, at the location of the removed portion 1414 of each of the multiple fins 1402. Exemplary insulating layer, or "poly cut" or "plug" structures, are described below. However, in other embodiments, the cut region 1420 is only partially filled with an insulating layer upon which conductive structures are then formed. The conductive structures may be used as local interconnects. In one embodiment, prior to filling the cut region 1420 with an insulating layer, or an insulating layer that will house the local interconnect structures, dopants may be implanted or delivered by a solid-source dopant layer through the cut region 1420 and into the locally cut portion of the fin or multiple fins.

[0219] FIG. 15 illustrates a cross-sectional view of an integrated circuit structure with fins having multiple gate spacing for localized isolation according to one embodiment of the present disclosure.

[0220] 15, a silicon fin 1502 has a first fin portion 1504 laterally adjacent to a second fin portion 1506. The first fin portion 1504 is separated from the second fin portion 1506 by a relatively wide cut 1508, as described in connection with FIGS. 13A and 13B, the relatively wide cut 1508 having a width X. A dielectric fill material 1510 is formed in the relatively wide cut 1508 to electrically isolate the first fin portion 1504 from the second fin portion 1506. A plurality of gate lines 1512 are above the silicon fin 1502, and each of the gate lines may include a gate dielectric and gate electrode stack 1514, a dielectric cap layer 1516, and sidewall spacers 1518. Two gate lines (the left two gate lines 1512) occupy the relatively wide cut 1508, so that the first fin portion 1504 is effectively separated from the second fin portion 1506 by two dummy or inactive gates.

[0221] In contrast, the fin portions may be separated by the distance of a single gate. By way of example, Figure 16A shows a cross-sectional view of an integrated circuit structure including fins with a single gate spacing for local isolation, according to another embodiment of the present disclosure.

[0222] 16A , a silicon fin 1602 has a first fin portion 1604 laterally adjacent to a second fin portion 1606. The first fin portion 1604 is separated from the second fin portion 1606 by a relatively narrow cut 1608 as described in connection with FIGS. 14A-14D , the relatively narrow cut 1608 having a width Y, which is less than X in FIG. 15 . A dielectric fill material 1610 is formed in the relatively narrow cut 1608 to electrically isolate the first fin portion 1604 from the second fin portion 1606. A plurality of gate lines 1612 are above the silicon fin 1602, and each of the gate lines may include a gate dielectric and gate electrode stack 1614, a dielectric cap layer 1616, and sidewall spacers 1618. Dielectric fill material 1610 occupies the location where the single gate line was previously located, thus separating first fin portion 1604 from second fin portion 1606 by a single "packed" gate line. In one embodiment, residual spacer material 1620 remains on the sidewalls at the location of the removed gate line portion, as shown. It should be understood that other regions of fin 1602 may be separated from each other by two or more inactive gate lines (region 1622 with three inactive gate lines) fabricated by a previous wide fin cut process, as described below.

[0223] 16A , integrated circuit structure 1600 includes fin 1602, such as a silicon fin. Fin 1602 has a longest dimension along a first direction 1650. Isolation structure 1610 separates a first top portion 1604 of fin 1602 from a second top portion 1606 of fin 1602 along first direction 1650. Isolation structure 1610 has a center 1611 along first direction 1650.

[0224] A first gate structure 1612A is above a first upper portion 1604 of the fin 1602, the first gate structure 1612A having a longest dimension along a second direction 1652 (e.g., into the page) that is orthogonal to the first direction 1650. A center 1613A of the first gate structure 1612A is spaced apart from a center 1611 of the isolation structure 1610 by a pitch along the first direction 1650. A second gate structure 1612B is above a first upper portion 1604 of the fin, the second gate structure 1612B having a longest dimension along the second direction 1652. A center 1613B of the second gate structure 1612B is spaced apart from a center 1613A of the first gate structure 1612A by a pitch along the first direction 1650. The third gate structure 1612C is above the second upper portion 1606 of the fin 1602, and the third gate structure 1612C has a longest dimension along the second direction 1652. The center 1613C of the third gate structure 1612C is spaced apart from the center 1611 of the isolation structure 1610 by the pitch along the first direction 1650. In one embodiment, as shown, the isolation structure 1610 has a top that is substantially flush with the tops of the first gate structure 1612A, the second gate structure 1612B, and the third gate structure 1612C.

[0225] In one embodiment, as shown for exemplary third gate structure 1612C, each of the first gate structure 1612A, second gate structure 1612B, and third gate structure 1612C includes a gate electrode 1660 on and between sidewalls of a high-k gate dielectric layer 1662. In one such embodiment, each of the first gate structure 1612A, second gate structure 1612B, and third gate structure 1612C further includes an insulating cap 1616 on the gate electrode 1660 and on the sidewalls of the high-k gate dielectric layer 1662.

[0226] In one embodiment, integrated circuit structure 1600 further includes a first epitaxial semiconductor region 1664A on a first upper portion 1604 of fin 1602 between first gate structure 1612A and isolation structure 1610. A second epitaxial semiconductor region 1664B on the first upper portion 1604 of fin 1602 between first gate structure 1612A and second gate structure 1612B. A third epitaxial semiconductor region 1664C on a second upper portion 1606 of fin 1602 between third gate structure 1612C and isolation structure 1610. In one embodiment, first epitaxial semiconductor region 1664A, second epitaxial semiconductor region 1664B, and third epitaxial semiconductor region 1664C comprise silicon and germanium. In another embodiment, the first epitaxial semiconductor region 1664A, the second epitaxial semiconductor region 1664B, and the third epitaxial semiconductor region 1664C comprise silicon.

[0227] In one embodiment, the isolation structure 1610 induces stress on the first top portion 1604 of the fin 1602 and the second top portion 1606 of the fin 1602. In one embodiment, the stress is compressive. In another embodiment, the stress is tensile. In another embodiment, the isolation structure 1610 is a partially filled insulating layer onto which conductive structures are then formed. The conductive structures may be used as local interconnects. In one embodiment, dopants are implanted or delivered by a solid-source dopant layer into the locally cut portions of the fin or fins prior to forming the insulating layer or isolation structures 1610 with the insulating layer to house the local interconnect structures.

[0228] It should be appreciated that in another aspect, isolation structures, such as isolation structure 1610 described above, can be formed in place of the active gate electrode at localized locations of the fin cut or at broader locations of the fin cut. Furthermore, the depths of such localized or broader locations of the fin cut can be formed at various depths within the fin relative to one another. In a first example, FIG. 16B illustrates a cross-sectional view showing locations where fin isolation structures can be formed in place of a gate electrode, according to one embodiment of the present disclosure.

[0229] Referring to FIG. 16B , a fin 1680, such as a silicon fin, may be formed above and contiguous with a substrate 1682. The fin 1680 has a fin edge or wide fin cut 1684, which may be formed during fin patterning, such as in the fin-last trim approach described above. The fin 1680 also has a local cut 1686 in which a portion of the fin 1680 is removed, such as using a fin trim isolation approach in which a dummy gate is replaced with a dielectric plug, as described above. An active gate electrode 1688 is formed above the fin and, for purposes of illustration, is shown against the background of the fin 1680 and slightly in front of the fin 1680, with dashed lines representing areas hidden from the front view. A dielectric plug 1690 may be formed at the fin edge or wide fin cut 1684 in lieu of using an active gate at such a location. Additionally or alternatively, a dielectric plug 1692 may be formed at the local cut 1686 in lieu of using an active gate at such a location. It should be understood that epitaxial source or drain regions 1694 are also shown at the location of fin 1680 between active gate electrode 1688 and plug 1690 or 1692. Furthermore, in one embodiment, the surface roughness of the edge of the fin at local cut 1686 is rougher than the edge of the fin at the location of the wider cut, as illustrated in FIG.

[0230] 17A-17C illustrate various possible depths for fin cuts manufactured using a fin trim isolation approach according to one embodiment of the present disclosure.

[0231] 17A , a semiconductor fin 1700, such as a silicon fin, may be formed above and contiguous with an underlying substrate 1702. The fin 1700 has a lower fin portion 1700A and an upper fin portion 1700B, as defined by the height of an isolation structure 1704 relative to the fin 1700. A local fin isolation cut 1706A separates the fin 1700 in a first fin portion 1710 from a second fin portion 1712. In the example of FIG. 17A , the depth of the local fin isolation cut 1706A is the overall depth of the fin 1700 into the substrate 1702, as shown along axis a-a′.

[0232] 17B, ​​in a second example, the depth of the local fin separation cut 1706B, as shown along axis a-a', is deeper than the overall depth of the fin 1700 to the substrate 1702. That is, the cut 1706B extends into the underlying substrate 1702.

[0233] 17C, in a third example, the depth of the local fin isolation cut 1706C, as shown along axis a-a', is less than the overall depth of the fin 1700, but is deeper than the top surface of the isolation structure 1704. Referring again to FIG. 17C, in a fourth example, the depth of the local fin isolation cut 1706D, as shown along axis a-a', is less than the overall depth of the fin 1700, and is generally flush with the top surface of the isolation structure 1704.

[0234] FIG. 18 shows a plan view and corresponding cross-sectional view taken along axis a-a′ illustrating possible options for the depth of local and global locations of fin cuts within a fin according to one embodiment of the present disclosure.

[0235] 18 , a first semiconductor fin 1800 and a second semiconductor fin 1802, such as silicon fins, have upper fin portions 1800B and 1802B that extend above an insulating structure 1804. Both fins 1800 and 1802 have fin ends or wide fin cuts 1806 that may be formed during fin patterning, such as in the fin-last-trim approach described above. Both fins 1800 and 1802 also have local cuts 1808 in which portions of the fins 1800 or 1802 are removed, such as using a fin trim isolation approach in which a dummy gate is replaced with a dielectric plug, as described above. In one embodiment, as shown in FIG. 18 , the surface roughness of the fin ends 1800 and 1802 at the local cuts 1808 is rougher than the fin ends at 1806.

[0236] Referring to the cross-sectional view of FIG. 18 , lower fin portions 1800A and 1802A can be seen below the level of insulating structure 1804. Also visible in the cross-sectional view is fin remnant 1810, which was removed in the final fin trimming process prior to the formation of insulating structure 1804, as described above. While shown protruding above the substrate, remnant 1810 can also be flush with or within the substrate, as illustrated by additional exemplary wide cut depth 1820. It should be understood that wide cut 1806 for fins 1800 and 1802 can also be at the height described for cut depth 1820 in the illustrated example. Local cut 1808, as shown, can have an exemplary depth corresponding to the depth described for FIGS. 17A-17C .

[0237] 16A, 16B, 17A-17C, and 18 collectively, according to one embodiment of the present disclosure, an integrated circuit structure includes a fin including silicon, the fin having a top and sidewalls, the top having a longest dimension along a first direction. A first isolation structure separates a first end of a first portion of the fin from a first end of a second portion of the fin along the first direction. The first isolation structure has a width along the first direction. The first end of the first portion of the fin has a surface roughness. A gate structure includes a gate electrode above the top of the first portion of the fin and laterally adjacent to its sidewall. The gate structure has a width along the first direction, and a center of the gate structure is spaced from the center of the first isolation structure by a pitch along the first direction. A second isolation structure is above a second end of the first portion of the fin, the second end facing the first end. The second isolation structure has a width along the first direction, the second end of the first portion of the fin has a surface roughness that is less than the surface roughness of the first end of the first portion of the fin, and the center of the second isolation structure is spaced from the center of the gate structure by a pitch along the first direction.

[0238] In one embodiment, the first end of the first portion of the fin has a scalloped topography, as illustrated in FIG. 16B. In one embodiment, the first epitaxial semiconductor region is on the first portion of the fin between the gate structure and the first isolation structure. The second epitaxial semiconductor region is on the first portion of the fin between the gate structure and the second isolation structure. In one embodiment, the first and second epitaxial semiconductor regions have a width along a second direction orthogonal to the first direction, the width along the second direction being wider than the width of the first portion of the fin along the second direction underlying the gate structure; for example, the epitaxial features described in connection with FIGS. 11 and 12D have a width wider than the fin portion on which they grow, in the perspectives illustrated in FIGS. 11 and 12D. In one embodiment, the gate structure further includes a high-k dielectric layer along sidewalls of the gate electrode and between the gate electrode and the first portion of the fin.

[0239] 16A, 16B, 17A-17C, and 18 collectively, according to another embodiment of the present disclosure, an integrated circuit structure includes a fin including silicon, the fin having a top and sidewalls, the top having a longest dimension along a direction. A first isolation structure separates a first end of a first portion of the fin from a first end of a second portion of the fin along the direction. The first end of the first portion of the fin has a depth. A gate structure includes a gate electrode above the top of the first portion of the fin and laterally adjacent to its sidewall. A second isolation structure is above the second end of the first portion of the fin, the second end facing the first end. The second end of the first portion of the fin has a depth different from the depth of the first end of the first portion of the fin.

[0240] In one embodiment, a depth of the second end of the first portion of the fin is less than a depth of the first end of the first portion of the fin. In one embodiment, a depth of the second end of the first portion of the fin is greater than a depth of the first end of the first portion of the fin. In one embodiment, the first isolation structure has a width along the direction, and the gate structure has a width along the direction. The second isolation structure has a width along the direction. In one embodiment, a center of the gate structure is spaced apart from a center of the first isolation structure by a pitch along the direction, and a center of the second isolation structure is spaced apart from a center of the gate structure by a pitch along the direction.

[0241] 16A, 16B, 17A-17C, and 18 collectively, according to another embodiment of the present disclosure, an integrated circuit structure includes a first fin including silicon, the first fin having a top and sidewalls, the top having a longest dimension along a direction, and a discontinuity separating a first end of a first portion of the first fin from a first end of a second portion of the fin along the direction. The first portion of the first fin has a second end opposite the first end, and the first end of the first portion of the fin has a depth. The integrated circuit structure also includes a second fin including silicon, the second fin having a top and sidewalls, the top having a longest dimension along the direction. The integrated circuit structure also includes a remaining fin portion between the first fin and the second fin. The remaining fin portion has a top and sidewalls, the top having a longest dimension along the direction, and the top is non-coplanar with the depth of the first end of the first portion of the fin.

[0242] In one embodiment, the depth of the first end of the first portion of the fin is below the apex of the remainder or residual fin portion. In one embodiment, the second end of the first portion of the fin has a depth that is flush with the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth that is below the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth that is above the depth of the first end of the first portion of the fin. In one embodiment, the depth of the first end of the first portion of the fin is above the apex of the remainder or residual fin portion. In one embodiment, the second end of the first portion of the fin has a depth that is flush with the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth that is below the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth that is above the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth that is flush with the apex of the remaining fin portion. In one embodiment, the second end of the first portion of the fin has a depth below the apex of the remaining fin portion. In one embodiment, the second end of the first portion of the fin has a depth above the apex of the remaining fin portion.

[0243] In another aspect, dielectric plugs formed at the locations of local or broad fin cuts can be tailored to provide specific stresses to the fin or fin portion, and in such implementations may be referred to as fin edge stressors.

[0244] One or more embodiments relate to the fabrication of fin-based semiconductor devices. Performance improvements for such devices can be achieved through channel stress induced from a poly plug fill process. Embodiments can include utilizing material properties in the poly plug fill process to induce mechanical stress in a metal-oxide-semiconductor field-effect transistor (MOSFET) channel. As a result, the induced stress can improve transistor mobility and drive current. Furthermore, the plug fill methods described herein can enable the elimination of any seam or void formation during deposition.

[0245] To provide context, stress can be induced in the channel by manipulating the inherent material properties of the plug fill adjacent to the fin. According to one or more embodiments, by adjusting the composition, deposition, and post-processing conditions of the plug fill material, the stress in the channel is tuned to benefit both NMOS and PMOS transistors. Furthermore, such plugs can reside deeper into the fin substrate compared to other common stressor techniques, such as epitaxial source or drain. The nature of the plug fill that achieves such an effect also eliminates seams or voids during deposition, mitigating certain defect modes during processing.

[0246] To provide further context, intentional stress engineering techniques for gate (poly) plugs currently do not exist. Unfortunately, stress enhancement from traditional stressors, such as epitaxial source or drain, dummy poly gate removal, and stress liners, tends to diminish as device pitch shrinks. To address one or more of the above issues, according to one or more embodiments of the present disclosure, additional stress sources are incorporated into the transistor structure. Another potential benefit of such a process may be the elimination of seams or voids in the plug, which can be common in other chemical vapor deposition methods.

[0247] 19A and 19B show cross-sectional views of various steps in a method for selecting fin end stressor locations at the ends of fins having wide cuts as part of a final fin trimming process, such as that described above, according to one embodiment of the present disclosure.

[0248] Referring to FIG. 19A , a fin 1900, such as a silicon fin, may be formed above and continuous with a substrate 1902. The fin 1900 has a fin tip or wide fin cut 1904, which may be formed during fin patterning, such as in the fin-last trimming approach described above. An active gate electrode location 1906 and a dummy gate electrode location 1908 are formed above the fin 1900 and, for purposes of illustration, are shown in the background of the fin 1900 and slightly in front of the fin 1900, with dashed lines representing areas hidden from the front view. It should be understood that an epitaxial source or drain region 1910 is also shown in the fin 1900 between the gate location 1906 and the gate location 1908. Additionally, an interlayer dielectric material 1912 is included in the fin 1900 between the gate location 1906 and the gate location 1908.

[0249] 19B, the gate placeholder structure or dummy gate location 1908 is removed, exposing the fin end or wide fin cut 1904. This removal creates an opening 1920 in which a dielectric plug, such as a fin end stressor dielectric plug, may ultimately be formed.

[0250] 20A and 20B show cross-sectional views of various steps in a method for selecting a fin end stressor location at the end of a fin having a local cut as part of a fin trim isolation process, such as described above, according to one embodiment of the present disclosure.

[0251] Referring to FIG. 20A , a fin 2000, such as a silicon fin, may be formed above and contiguous with a substrate 2002. The fin 2000 has a local cut 2004, where a portion of the fin 2000 is removed using, for example, a fin trim isolation approach, as described above, in which a dummy gate is removed and the fin is etched at a localized location. An active gate electrode location 2006 and a dummy gate electrode location 2008 are formed above the fin 2000 and, for purposes of illustration, are shown in the background of the fin 2000 and slightly in front of the fin 2000, with dashed lines representing areas hidden from the front view. It should be understood that an epitaxial source or drain region 2010 is also shown at a location in the fin 2000 between the gate location 2006 and the gate location 2008. Additionally, an interlayer dielectric material 2012 is included at a location in the fin 2000 between the gate location 2006 and the gate location 2008.

[0252] 20B, the gate placeholder structure or dummy gate electrode location 2008 is removed, exposing the fin edge with the local cut 2004. This removal creates an opening 2020 in which a dielectric plug, such as a fin edge stressor dielectric plug, may ultimately be formed.

[0253] 21A through 21M illustrate cross-sectional views of various steps in a method of fabricating an integrated circuit structure with differentiated fin end dielectric plugs according to one embodiment of the present disclosure.

[0254] Referring to FIG. 21A , initial structure 2100 includes an NMOS region and a PMOS region. The NMOS region of initial structure 2100 includes a first fin 2102, such as a first silicon fin, formed above and which may be continuous with substrate 2104. First fin 2102 has a fin end 2106, which may be formed from a localized or wider fin cut. A first active gate electrode location 2108 and a first dummy gate electrode location 2110 are formed above first fin 2102 and, for purposes of illustration, are shown in the background of first fin 2102 and slightly in front of first fin 2102, with dashed lines representing regions hidden from the front view. Additionally, an epitaxial N-type source or drain region 2112, such as an epitaxial silicon source of a drain structure, is shown in the first fin 2102 at a location between gate location 2108 and gate location 2110. Additionally, interlayer dielectric material 2114 is included in the first fin 2102 at a location between gate location 2108 and gate location 2110 .

[0255] The PMOS region of the initial structure 2100 includes a second fin 2122, such as a second silicon fin, formed above and which may be contiguous with the substrate 2104. The second fin 2122 has a fin end 2126, which may be formed from a localized or wider fin cut. A second active gate electrode location 2128 and a second dummy gate electrode location 2130 are formed above the second fin 2122 and, for purposes of illustration, are shown in the background of and slightly in front of the second fin 2122, with dashed lines representing areas hidden from the front view. Also, an epitaxial P-type source or drain region 2132, such as an epitaxial silicon germanium source of a drain structure, is shown in the second fin 2122 between the gate location 2128 and the gate location 2130. Furthermore, an interlayer dielectric material 2134 is included in the second fin 2122 between the gate location 2128 and the gate location 2130.

[0256] 21B, the first dummy gate electrode at location 2110 and the second dummy gate electrode at location 2130 are removed. The removal exposes fin end 2106 of first fin 2102 and fin end 2126 of second fin 2122. This removal also forms openings 2116 and 2136, respectively, in which a dielectric plug, such as a fin end stressor dielectric plug, may ultimately be formed.

[0257] Referring to Figure 21C, a material liner 2140 is formed that conforms to the structure of Figure 21B. In one embodiment, the material liner comprises silicon and nitrogen, such as a silicon nitride material liner.

[0258] Referring to Figure 21D, a protective capping layer 2142, such as a metal nitride layer, is formed over the structure of Figure 21C.

[0259] 21E, a hard mask material 2144, such as a carbon-based hard mask material, is formed over the structure of FIG. 21D. A lithography mask or mask stack 2146 is formed over the hard mask material 2144.

[0260] Referring to Figure 21F, a portion of the hard mask material 2144 or a portion of the protective crown layer 2142 in the PMOS region has been removed from the structure of Figure 21E. The lithography mask or mask stack 2146 has also been removed.

[0261] 21G, a second material liner 2148 is formed conformal to the structure of FIG. 21F. In one embodiment, the second material liner includes silicon and nitrogen, such as a second silicon nitride material liner. In one embodiment, the second material liner 2148 has different stress states to tailor the stress in the exposed plug.

[0262] Referring to Figure 21H, a second hardmask material 2150, such as a second carbon-based hardmask material, is formed over the structure of Figure 21G and then recessed into opening 2136 in the PMOS region of the structure.

[0263] Referring to Figure 21I, second material liner 2148 is etched from the structure of Figure 21H, thereby removing second material liner 2148 from the NMOS region and recessing second material liner 2148 into the PMOS region of the structure.

[0264] 21J, hard mask material 2144, protective crown layer 2142, and second hard mask material 2150 are removed from the structure of FIG. 21I. This removal leaves two different fill structures in opening 2116, respectively, compared to opening 2136.

[0265] Referring to Figure 21K, an insulating fill material 2152 is formed and planarized in the openings 2116 and 2136 of the structure of Figure 21J. In one embodiment, the insulating fill material 2152 is a flowable oxide material, such as a flowable silicon oxide or silicon dioxide material.

[0266] 21L, insulating fill material 2152 is recessed into openings 2116 and 2136 of the structure of FIG. 21K to form recessed insulating fill material 2154. In one embodiment, a steam oxidation process is performed as part of or after the recessing process to harden recessed insulating fill material 2154. In one such embodiment, recessed insulating fill material 2154 shrinks, inducing tensile stress on fins 2102 and 2122. However, there is relatively less tensile stress-inducing material in the PMOS region than in the NMOS region.

[0267] 21M, a third material liner 2156 overlies the structure of FIG. 21L. In one embodiment, the third material liner 2156 comprises silicon and nitrogen, such as a third silicon nitride material liner. In one embodiment, the third material liner 2156 prevents the recessed insulating fill material 2154 from being etched away during or after the source or drain contact etch.

[0268] 22A-22D illustrate cross-sectional views of an exemplary structure of a PMOS fin edge stressor dielectric plug according to one embodiment of the present disclosure.

[0269] 22A , opening 2136 over the PMOS region of structure 2100 includes material liner 2140 along the sidewalls of opening 2136. Second material liner 2148 is conformal to the bottom of material liner 2140 but recessed relative to the top of material liner 2140. Recessed insulating fill material 2154 is within second material liner 2148 and has a top surface that is flush with the top surface of second material liner 2148. Third material liner 2156 is within the top of material liner 2140 and is on the top surface of insulating fill material 2154 and on the top surface of second material liner 2148. Third material liner 2156 has seam 2157, for example, an artifact of the deposition process used to form third material liner 2156.

[0270] 22B, opening 2136 over the PMOS region of structure 2100 includes material liner 2140 along the sidewalls of opening 2136. Second material liner 2148 is conformal to the bottom of material liner 2140 but recessed relative to the top of material liner 2140. Recessed insulating fill material 2154 is within second material liner 2148 and has a top surface that is flush with the top surface of second material liner 2148. Third material liner 2156 is within the top of material liner 2140 and is on the top surface of insulating fill material 2154 and on the top surface of second material liner 2148. Third material liner 2156 is seam-free.

[0271] 22C , opening 2136 over the PMOS region of structure 2100 includes material liner 2140 along the sidewalls of opening 2136. Second material liner 2148 is conformal to the bottom of material liner 2140 but is recessed relative to the top of material liner 2140. Recessed insulating fill material 2154 is in and above second material liner 2148 and has a top surface that is above the top surface of second material liner 2148. Third material liner 2156 is in the top of material liner 2140 and on the top surface of insulating fill material 2154. Although third material liner 2156 is shown without a seam, in other embodiments, third material liner 2156 has a seam.

[0272] 22D , opening 2136 over the PMOS region of structure 2100 includes material liner 2140 along the sidewalls of opening 2136. Second material liner 2148 is conformal to the bottom of material liner 2140 but recessed relative to the top of material liner 2140. Recessed insulating fill material 2154 is within second material liner 2148 and has a top surface that is recessed below the top surface of second material liner 2148. Third material liner 2156 is within the top of material liner 2140 and is on the top surface of insulating fill material 2154 and on the top surface of second material liner 2148. Although third material liner 2156 is shown without a seam, in other embodiments, third material liner 2156 has a seam.

[0273] 19A, 19B, 20A, 20B, 21A-21M, and 22A-22D collectively, according to one embodiment of the present disclosure, an integrated circuit structure includes a fin, such as silicon, having a top and sidewalls. The top has a longest dimension along the direction. A first isolation structure is above a first end of the fin. A gate structure includes a gate electrode above the top of a region of the fin and laterally adjacent to its sidewalls. The gate structure is spaced apart from the first isolation structure along the direction. A second isolation structure is above a second end of the fin, the second end facing the first end. The second isolation structure is spaced apart from the gate structure along the direction. Both the first isolation structure and the second isolation structure include a first dielectric material (e.g., material liner 2140) laterally surrounding a recessed second dielectric material (e.g., second material liner 2148) that is distinct from the first dielectric material. The recessed second dielectric material laterally surrounds at least a portion of a third dielectric material (eg, recessed insulating fill material 2154) that is different from the first and second dielectric materials.

[0274] In one embodiment, both the first isolation structure and the second isolation structure further include a fourth dielectric material (e.g., third material liner 2156) laterally surrounded by an upper portion of the first dielectric material, the fourth dielectric material being on an upper surface of the third dielectric material. In one such embodiment, the fourth dielectric material is also on an upper surface of the second dielectric material. In another such embodiment, the fourth dielectric material has a generally vertical central seam. In another such embodiment, the fourth dielectric material is seamless.

[0275] In one embodiment, the third dielectric material has a top surface that is coplanar with the top surface of the second dielectric material. In one embodiment, the third dielectric material has a top surface that is below the top surface of the second dielectric material. In one embodiment, the third dielectric material has a top surface that is above the top surface of the second dielectric material, and the third dielectric material is further above the top surface of the second dielectric material. In one embodiment, the first and second isolation structures induce compressive stress on the fin. In one such embodiment, the gate electrode is a P-type gate electrode.

[0276] In one embodiment, the first isolation structure has a width along the direction, the gate structure has a width along the direction, and the second isolation structure has a width along the direction. In one such embodiment, the center of the gate structure is spaced apart from the center of the first isolation structure by a pitch along the direction, and the center of the second isolation structure is spaced apart from the center of the gate structure by a pitch along the direction. In one embodiment, the first and second isolation structures are both in corresponding trenches in the interlayer dielectric layer.

[0277] In one such embodiment, the first source or drain region is between the gate structure and the first isolation structure. The second source or drain region is between the gate structure and the second isolation structure. In one such embodiment, the first and second source or drain regions are embedded in a source or drain region comprising silicon and germanium. In one such embodiment, the gate structure further includes a high-k dielectric layer along sidewalls of the gate electrode and between the gate electrode and the fin.

[0278] In another aspect, the depth of individual dielectric plugs can vary within a semiconductor structure or architecture formed on a common substrate. By way of example, FIG. 23A illustrates a cross-sectional view of another semiconductor structure having fin-edge stress-inducing features in accordance with another embodiment of the present disclosure. Referring to FIG. 23A , a shallow dielectric plug 2308A is included along with a pair of deep dielectric plugs 2308B and 2308C. In one such embodiment, as shown, the shallow dielectric plug 2308C has a depth approximately equal to the depth of the semiconductor fin 2302 within the substrate 2304, while the pair of deep dielectric plugs 2308B and 2308C have a depth below the depth of the semiconductor fin 2302 within the substrate 2304.

[0279] 23A, such a configuration may enable stress amplification on fin trim isolation (FTI) devices in trenches that are etched deeper into the substrate 2304 to provide isolation between adjacent fins 2302. Such an approach may be implemented to increase the density of transistors on a chip. In one embodiment, the stress effects induced on the transistor from the plug fill are magnified in FTI transistors because stress transfer occurs in both the fin and the substrate, or further below the transistor.

[0280] In another aspect, the width or amount of tensile stress-inducing oxide layer included in the dielectric plug can vary within a semiconductor structure or among architectures formed on a common substrate, depending, for example, on whether the device is a PMOS or NMOS device. By way of example, FIG. 23B illustrates a cross-sectional view of another semiconductor structure having fin-edge stress-inducing features in accordance with another embodiment of the present disclosure. Referring to FIG. 23B, in certain embodiments, an NMOS device includes relatively more tensile stress-inducing oxide layer 2350 than a corresponding PMOS device.

[0281] Referring again to FIG. 23B , in one embodiment, differential plug fill is implemented to induce appropriate stress in NMOS and PMOS devices. For example, NMOS plugs 2308D and 2308E have a larger volume and width of tensile stress-inducing oxide layer 2350 than PMOS plugs 2308F and 2308G. The plug fill can be patterned to induce different stresses in NMOS and PMOS devices. For example, lithographic patterning can be used to widen PMOS devices (e.g., widen the dielectric plug trench for PMOS devices), and at this point, different fill options can be implemented to differentiate the plug fill in NMOS and PMOS devices. In an exemplary embodiment, reducing the volume of flowable oxide in the plug over PMOS devices can reduce the induced tensile stress. In such an embodiment, for example, compressive stress from compressive stress source and drain regions can dominate. In other embodiments, the use of different plug liners or different fill materials allows for tunable stress control.

[0282] As discussed above, it should be appreciated that the poly plug stress effect can be beneficial for both NMOS transistors (e.g., tensile channel stress) and PMOS transistors (e.g., compressive channel stress). According to one embodiment of the present disclosure, the semiconductor fin is a uniaxially stressed semiconductor fin. The uniaxially stressed semiconductor fin can be subjected to tensile or compressive uniaxial stress. For example, FIG. 24A illustrates a perspective view of a fin having tensile uniaxial stress, while FIG. 24B illustrates a perspective view of a fin having compressive uniaxial stress, according to one or more embodiments of the present disclosure.

[0283] 24A, a separate channel region (C) is disposed within the semiconductor fin 2400. A source region (S) and a drain region (D) are disposed within the semiconductor fin 2400 on either side of the channel region (C). The separate channel regions of the semiconductor fin 2400 have a direction of current flow from the source region (S) to the drain region (D) along the direction of uniaxial tensile stress (arrows pointing away from each other at the ends 2402 and 2404).

[0284] 24B , a separate channel region (C) is disposed within the semiconductor fin 2450. A source region (S) and a drain region (D) are disposed within the semiconductor fin 2450 on either side of the channel region (C). The separate channel regions of the semiconductor fin 2450 have a direction of current flow from the source region (S) to the drain region (D) along the direction of uniaxial compressive stress (arrows pointing toward each other from ends 2452 and 2454). Accordingly, the embodiments described herein can be implemented to improve transistor mobility and drive current, allowing circuits and chips to perform faster.

[0285] In another aspect, there may be a relationship between the locations where gate line cuts (poly cuts) are made and the locations where fin trim isolation (FTI) local fin cuts are made. In one embodiment, FTI local fin cuts are made only at locations where poly cuts are made. However, in one such embodiment, FTI cuts are not necessarily made at all locations where poly cuts are made.

[0286] 25A and 25B show plan views illustrating various steps in a method for patterning fins at a single gate spacing to form local isolation structures at select gate line cut locations according to one embodiment of the present disclosure.

[0287] 25A , a method of fabricating an integrated circuit structure includes forming a plurality of fins 2502, each of the plurality of fins 2502 having a longest dimension along a first direction 2504. A plurality of gate structures 2506 overlie the plurality of fins 2502, each of the gate structures 2506 having a longest dimension along a second direction 2508 orthogonal to the first direction 2504. In one embodiment, the gate structures 2506 are sacrificial or dummy gate lines and are fabricated from, for example, polycrystalline silicon. In one embodiment, the plurality of fins 2502 are silicon fins and are continuous with a portion of an underlying silicon substrate.

[0288] Referring again to FIG. 25A , a dielectric material structure 2510 is formed between adjacent ones of the plurality of gate structures 2506. Two portions 2512 and 2513 of the plurality of gate structures 2506 are removed, exposing a portion of each of the plurality of fins 2502. In one embodiment, removing the two portions 2512 and 2513 of the gate structures 2506 involves using a lithography window wider than the width of each of the portions 2512 and 2513 of the gate structures 2506. The exposed portion of each of the plurality of fins 2502 at location 2512 is removed to form a cut region 2520. In one embodiment, the exposed portion of each of the plurality of fins 2502 is removed using a dry or plasma etching process. However, the exposed portion of each of the plurality of fins 2502 at location 2513 is masked from being removed. In one embodiment, regions 2512 / 2520 both represent a poly cut and an FTI local fin cut. However, location 2513 represents only a poly cut.

[0289] 25B, the poly cut and FTI local fin cut locations 2512 / 2520 and the poly cut location 2513 are filled with insulating structures 2530, such as dielectric plugs. Exemplary insulating structures, or "poly cut" or "plug" structures, are described below.

[0290] 26A-26C show cross-sectional views of various possibilities for the locations of poly cuts and FTI local fin cuts, as well as dielectric plugs for the locations of poly cuts only, for various regions of the structure of FIG. 25B, according to one embodiment of the present disclosure.

[0291] 26A, a cross-sectional view of portion 2600A of dielectric plug 2530 at location 2513 is shown along axis a-a' of the structure of FIG. 25B. Portion 2600A of dielectric plug 2530 is shown above uncut fins 2502 and between dielectric material structures 2510.

[0292] 26B, a cross-sectional view of portion 2600B of dielectric plug 2530 at location 2512 is shown along axis b-b' of the structure of FIG. 25B. Portion 2600B of dielectric plug 2530 is shown over cut fin location 2520 and between dielectric material structures 2510.

[0293] 26C, a cross-sectional view of portion 2600C of dielectric plug 2530 at location 2512 is shown along axis c-c' of the structure of FIG. 25B. Portion 2600C of dielectric plug 2530 is shown over trench isolation structure 2602 between fins 2502 and between dielectric material structures 2510. In one embodiment of the example described above, trench isolation structure 2602 includes first insulating layer 2602A, second insulating layer 2602B, and insulating fill material 2602C over second insulating layer 2602B.

[0294] 25A, 25B, and 26A-26C collectively, according to one embodiment of the present disclosure, a method of fabricating an integrated circuit structure includes forming a plurality of fins, each of the plurality of fins extending along a first direction. A plurality of gate structures are formed over the plurality of fins, each of the plurality of gate structures extending along a second direction orthogonal to the first direction. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of a first gate structure of the plurality of gate structures is removed to expose a first portion of each of the plurality of fins. A portion of a second gate structure of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed. A first insulating structure is formed at the location of the removed first portion of the plurality of fins. A second insulating structure is formed at the location of the removed portion of the second gate structure of the plurality of gate structures.

[0295] In one embodiment, removing portions of the first and second gate structures of the plurality of gate structures involves using a lithography window wider than a width of each of the first and second gate structures of the plurality of gate structures. In one embodiment, removing the exposed first portion of each of the plurality of fins involves etching to a depth less than a height of the plurality of fins. In one such embodiment, the depth is greater than a depth of a source or drain region in the plurality of fins. In one embodiment, the plurality of fins comprise silicon and are continuous with a portion of the silicon substrate.

[0296] 16A , 25A , 25B , and 26A-26C collectively, according to another embodiment of the present disclosure, an integrated circuit structure includes a fin including silicon, the fin having a longest dimension along a first direction. An isolation structure is above a top portion of the fin, the isolation structure having a center along the first direction. A first gate structure is above a top portion of the fin, the first gate structure having a longest dimension along a second direction perpendicular to the first direction. The center of the first gate structure is spaced apart from the center of the isolation structure by a pitch along the first direction. A second gate structure is above a top portion of the fin, the second gate structure having a longest dimension along the second direction. The center of the second gate structure is spaced apart from the center of the first gate structure by a pitch along the first direction. A third gate structure is above a top portion of the fin, on the opposite side of the isolation structure from the first and second gate structures, the third gate structure having a longest dimension along the second direction. The center of the third gate structure is spaced apart from the center of the isolation structure by a pitch along the first direction.

[0297] In one embodiment, each of the first gate structure, the second gate structure, and the third gate structure includes a gate electrode on and between sidewalls of the high-k gate dielectric layer, and in one such embodiment, each of the first gate structure, the second gate structure, and the third gate structure further includes an insulating cap on the gate electrode and on the sidewalls of the high-k gate dielectric layer.

[0298] In one embodiment, the first epitaxial semiconductor region is on top of the fin between the first gate structure and the isolation structure. The second epitaxial semiconductor region is on top of the fin between the first gate structure and the second gate structure. The third epitaxial semiconductor region is on top of the fin between the third gate structure and the isolation structure. In one such embodiment, the first, second, and third epitaxial semiconductor regions comprise silicon and germanium. In another such embodiment, the first, second, and third epitaxial semiconductor regions comprise silicon.

[0299] 16A , 25A , 25B , and 26A-26C collectively, according to another embodiment of the present disclosure, an integrated circuit structure includes a shallow trench isolation (STI) structure between a pair of semiconductor fins, the STI structure having a longest dimension along a first direction. An isolation structure is on the STI structure, the isolation structure having a center along the first direction. A first gate structure is on the STI structure, the first gate structure having a longest dimension along a second direction perpendicular to the first direction. The center of the first gate structure is spaced apart from the center of the isolation structure by a pitch along the first direction. A second gate structure is on the STI structure, the second gate structure having a longest dimension along the second direction. The center of the second gate structure is spaced apart from the center of the first gate structure by a pitch along the first direction. A third gate structure is on the STI structure on the opposite side of the isolation structure from the first and second gate structures, the third gate structure having a longest dimension along the second direction. The center of the third gate structure is spaced apart from the center of the isolation structure by a pitch along the first direction.

[0300] In one embodiment, the first gate structure, the second gate structure, and the third gate structure each include a gate electrode on and between sidewalls of the high-k gate dielectric layer. In one such embodiment, the first gate structure, the second gate structure, and the third gate structure each further include an insulating cap on the gate electrode and on the sidewalls of the high-k gate dielectric layer. In one embodiment, the pair of semiconductor fins are a pair of silicon fins.

[0301] In another aspect, the insulating structure or dielectric plug used to fill the cut location, whether it be both a poly cut and an FTI localized fin cut, or just a poly cut, may extend laterally into or even beyond the dielectric spacer of the corresponding cut gate line.

[0302] In a first example where the trench contact shape is unaffected by the poly cut dielectric plug, FIG. 27A shows a plan view and corresponding cross-sectional view of an integrated circuit structure including a gate line cut with a dielectric plug extending into the gate line's dielectric spacer in accordance with one embodiment of the present disclosure.

[0303] 27A , integrated circuit structure 2700A includes a first silicon fin 2702 having a longest dimension along a first direction 2703. A second silicon fin 2704 has a longest dimension along the first direction 2703. An insulator material 2706 is between the first silicon fin 2702 and the second silicon fin 2704. A gate line 2708 is above the first silicon fin 2702 and above the second silicon fin 2704 along a second direction 2709, which is perpendicular to the first direction 2703. The gate line 2708 has a first side 2708A and a second side 2708B, and a first end 2708C and a second end 2708D. Gate line 2708 has a discontinuous portion 2710 above insulator material 2706 between first end 2708C and second end 2708D of gate line 2708. Discontinuous portion 2710 is filled with a dielectric plug 2712.

[0304] A trench contact 2714 is located above the first silicon fin 2702 and above the second silicon fin 2704 along a second direction 2709 on a first side 2708A of the gate line 2708. The trench contact 2714 is continuous above the insulator material 2706 at a location 2715 laterally adjacent to the dielectric plug 2712. A dielectric spacer 2716 is located laterally between the trench contact 2714 and the first side 2708A of the gate line 2708. The dielectric spacer 2716 is continuous along the first side 2708A of the gate line 2708 and the dielectric plug 2712. The dielectric spacer 2716 has a width (W2) laterally adjacent to the dielectric plug 2712 that is thinner than a width (W1) laterally adjacent to the first side 2708A of the gate line 2708.

[0305] In one embodiment, a second trench contact 2718 is above the first silicon fin 2702 and above the second silicon fin 2704 at a second side 2708B of the gate line 2708 along a second direction 2709. The second trench contact 2718 is continuous above the insulator material 2706 at a location 2719 laterally adjacent to the dielectric plug 2712. In one such embodiment, a second dielectric spacer 2720 is laterally between the second trench contact 2718 and the second side 2708B of the gate line 2708. The second dielectric spacer 2720 is continuous along the second side 2708B of the gate line 2708 and the dielectric plug 2712. The second dielectric spacer has a width laterally adjacent to the dielectric plug 2712 that is thinner than the width laterally adjacent to the second side 2708B of the gate line 2708.

[0306] In one embodiment, gate line 2708 includes a high-k gate dielectric layer 2722, a gate electrode 2724, and a dielectric cap layer 2726. In one embodiment, dielectric plug 2712 includes the same material as dielectric spacer 2714, but is separate from dielectric spacer 2714. In one embodiment, dielectric plug 2712 includes a different material than dielectric spacer 2714.

[0307] In a second example where trench contact geometry is affected by a poly cut dielectric plug, FIG. 27B shows a plan view and corresponding cross-sectional view of an integrated circuit structure including a gate line cut with a dielectric plug that extends beyond the gate line's dielectric spacer, according to another embodiment of the present disclosure.

[0308] 27B , integrated circuit structure 2700B includes a first silicon fin 2752 having a longest dimension along a first direction 2753. A second silicon fin 2754 has a longest dimension along the first direction 2753. An insulator material 2756 is between the first silicon fin 2752 and the second silicon fin 2754. A gate line 2758 is above the first silicon fin 2752 and above the second silicon fin 2754 along a second direction 2759, where the second direction 2759 is perpendicular to the first direction 2753. The gate line 2758 has a first side 2758A and a second side 2758B, and has a first end 2758C and a second end 2758D. Gate line 2758 has a discontinuous portion 2760 above insulator material 2756 between first end 2758C and second end 2758D of gate line 2758. Discontinuous portion 2760 is filled with a dielectric plug 2762.

[0309] A trench contact 2764 is located above the first silicon fin 2752 and above the second silicon fin 2754, along a first side 2758A of the gate line 2758, in a second direction 2759. The trench contact 2764 is continuous above the insulator material 2756 at a location 2765 laterally adjacent to the dielectric plug 2762. A dielectric spacer 2766 is located laterally between the trench contact 2764 and the first side 2758A of the gate line 2758. The dielectric spacer 2766 is located along the first side 2758A of the gate line 2758, but not along the dielectric plug 2762, resulting in a discontinuous dielectric spacer 2766. The trench contact 2764 has a width (W1) laterally adjacent to the dielectric plug 2762 that is thinner than a width (W2) laterally adjacent to the dielectric spacer 2766.

[0310] In one embodiment, the second trench contact 2768 is above the first silicon fin 2752 and above the second silicon fin 2754, along the second direction 2759, at the second side 2758B of the gate line 2758. The second trench contact 2768 is continuous above the insulator material 2756 at a location 2769 laterally adjacent to the dielectric plug 2762. In one such embodiment, a second dielectric spacer 2770 is laterally between the second trench contact 2768 and the second side 2758B of the gate line 2758. The second dielectric spacer 2770 is along the second side 2758B of the gate line 2758, but not along the dielectric plug 2762, resulting in a discontinuous dielectric spacer 2770. The second trench contact 2768 has a width laterally adjacent to the dielectric plug 2762 that is thinner than the width laterally adjacent to the second dielectric spacer 2770.

[0311] In one embodiment, gate line 2758 includes a high-k gate dielectric layer 2772, a gate electrode 2774, and a dielectric cap layer 2776. In one embodiment, dielectric plug 2762 includes the same material as dielectric spacer 2764, but is separate from dielectric spacer 2764. In one embodiment, dielectric plug 2762 includes a different material than dielectric spacer 2764.

[0312] In a third example where the dielectric plug for the poly cut location is tapered from the top of the plug to the bottom of the plug, Figures 28A-28F show cross-sectional views of various steps in a method of manufacturing an integrated circuit structure with a gate line cut having a dielectric plug with an upper portion that extends beyond the dielectric spacer of the gate line and a lower portion that extends into the dielectric spacer of the gate line, in accordance with another embodiment of the present disclosure.

[0313] Referring to FIG. 28A , multiple gate lines 2802 are formed above structure 2804, such as above trench isolation structures between semiconductor fins. In one embodiment, each of the gate lines 2802 is a sacrificial or dummy gate line, e.g., having a dummy gate electrode 2806 and a dielectric cap 2808. Portions of such sacrificial or dummy gate lines may be replaced later (e.g., after dielectric plug formation, described below) in a replacement gate process. Dielectric spacers 2810 run along the sidewalls of the gate lines 2802. Dielectric material 2812, such as an inter-dielectric layer, is between the gate lines 2802. A mask 2814 is formed and lithographically patterned to expose a portion of one of the gate lines 2802.

[0314] Referring to Figure 28B, with mask 2814 in place, central gate line 2802 is removed in an etching process. Mask 2814 is then removed. In one embodiment, the etching process erodes a portion of dielectric spacer 2810 of the removed gate line 2802, forming reduced dielectric spacer 2816. Additionally, the upper portion of dielectric material 2812 exposed by mask 2814 is eroded in the etching process, forming eroded dielectric material portion 2818. In a particular embodiment, residual dummy gate material 2820, such as residual polysilicon, remains in the structure as an artifact of the uncompleted etching process.

[0315] Referring to Figure 28C, a hard mask 2822 is formed over the structure of Figure 28B. The hard mask 2822 may be conformal to the top of the structure of Figure 2B, and in particular to the eroded dielectric material portions 2818.

[0316] 28D, the remaining dummy gate material 2820 is removed using, for example, an etching process that may be similar in chemistry to the etching process used to remove the middle ones of the gate lines 2802. In one embodiment, a hard mask 2822 protects the eroded dielectric material portions 2818 from further erosion during removal of the remaining dummy gate material 2820.

[0317] 28E, hard mask 2822 is removed. In one embodiment, hard mask 2822 is removed without further erosion of eroded dielectric material portions 2818, or essentially without further erosion.

[0318] Referring to Figure 28F, a dielectric plug 2830 is formed in the opening of the structure of Figure 28E. The top of the dielectric plug 2830 is above the eroded dielectric material portion 2818, e.g., effectively beyond the original spacer 2810. The bottom of the dielectric plug 2830 is adjacent to the reduced dielectric spacer 2816, e.g., effectively within but not beyond the original spacer 2810. As a result, the dielectric plug 2830 has a tapered profile, as illustrated in Figure 28F. It should be understood that the dielectric plug 2830 may be fabricated from the materials and processes described above for other poly cut or FTI plugs or fin end stressors.

[0319] In another aspect, a portion of a placeholder or dummy gate structure may be retained above the trench isolation region beneath the permanent gate structure to protect the trench isolation region from erosion during the replacement gate process. For example, Figures 29A-29C show plan views and corresponding cross-sectional views of an integrated circuit structure with residual dummy gate material at a portion of the bottom of a permanent gate stack, according to one embodiment of the present disclosure.

[0320] 29A-29C, an integrated circuit structure includes a fin 2902, such as a silicon fin, protruding from a semiconductor substrate 2904. The fin 2902 includes a lower fin portion 2902B and an upper fin portion 2902A. The upper fin portion 2902A has a top portion 2902C and sidewalls 2902D. An isolation structure 2906 surrounds the lower fin portion 2902B. The isolation structure 2906 includes an insulator material 2906C having a top surface 2907. A semiconductor material 2908 overlies a portion of the top surface 2907 of the insulator material 2906C. The semiconductor material 2908 is isolated from the fin 2902.

[0321] A gate dielectric layer 2910 overlies a top 2902C of the upper fin portion 2902A and laterally adjacent a sidewall 2902D of the upper fin portion 2902A. The gate dielectric layer 2910 further overlies a semiconductor material 2908 on a portion of a top surface 2907 of the insulator material 2906C. An additional intervening gate dielectric layer 2911, such as an oxidized portion of the fin 2902, may be between the gate dielectric layers 2910 over the top 2902C of the upper fin portion 2902A and laterally adjacent a sidewall 2902D of the upper fin portion 2902A. A gate electrode 2912 overlies the gate dielectric layer 2910 over the top 2902C of the upper fin portion 2902A and laterally adjacent a sidewall 2902D of the upper fin portion 2902A. Gate electrode 2912 further overlies gate dielectric layer 2910 on semiconductor material 2908 over a portion of top surface 2907 of insulator material 2906C. First source or drain region 2916 is adjacent a first side of gate electrode 2912, and second source or drain region 2918 is adjacent a second side of gate electrode 2912, the second side facing the first side. In one embodiment, an example of which is described above, isolation structure 2906 includes first insulating layer 2906A, second insulating layer 2906B, and insulator material 2906C.

[0322] In one embodiment, semiconductor material 2908 over a portion of top surface 2907 of insulator material 2906C is or includes polycrystalline silicon. In one embodiment, top surface 2907 of insulator material 2906C has a concave depression, and semiconductor material 2908 is within the concave depression, as shown. In one embodiment, isolation structure 2906 includes a second insulator material (2906A or 2906B, or both 2906A / 2906B) along the bottom and sidewalls of insulator material 2906C. In one such embodiment, the portion of second insulator material (2906A or 2906B, or both 2906A / 2906B) along the sidewalls of insulator material 2906C has a top surface above the top surface of insulator material 2906C, as shown. In one embodiment, the top surface of the second insulator material (2906A, or 2906B, or both 2906A / 2906B) is above or flush with the top surface of the semiconductor material 2908.

[0323] In one embodiment, the semiconductor material 2908 on a portion of the top surface 2907 of the insulator material 2906C does not extend beyond the gate dielectric layer 2910. That is, from a plan view, the location of the semiconductor material 2908 is limited to the area covered by the gate stack 2912 / 2910. In one embodiment, the first dielectric spacer 2920 is along a first side of the gate electrode 2912. The second dielectric spacer 2922 is along a second side of the gate electrode 2912. In one such embodiment, the gate dielectric layer 2910 further extends along the sidewalls of the first dielectric spacer 2920 and the second dielectric spacer 2922, as shown in FIG. 29B .

[0324] In one embodiment, gate electrode 2912 includes a conformal conductive layer 2912A (e.g., a work function layer). In one such embodiment, work function layer 2912A includes titanium and nitrogen. In another embodiment, work function layer 2912A includes titanium, aluminum, carbon, and nitrogen. In one embodiment, gate electrode 2912 further includes a conductive fill metal layer 2912B above work function layer 2912A. In one such embodiment, conductive fill metal layer 2912B includes tungsten. In a particular embodiment, conductive fill metal layer 2912B includes 95% or more atomic percent tungsten and 0.1-2% atomic percent fluorine. In one embodiment, an insulating cap 2924 is on gate electrode 2912 and can extend above gate dielectric layer 2910, as shown in FIG. 29B.

[0325] 30A-30D show cross-sectional views of various steps in a method of fabricating an integrated circuit structure with residual dummy gate material in a bottom portion of a permanent gate stack according to another embodiment of the present disclosure, the views being taken along a portion of axis a-a' of the structure of FIG.

[0326] Referring to FIG. 30A , a method of fabricating an integrated circuit structure includes forming a fin 3000 from a semiconductor substrate 3002. The fin 3000 has a lower fin portion 3000A and an upper fin portion 3000B. The upper fin portion 3000B has a top portion 3000C and a sidewall 3000D. An isolation structure 3004 surrounds the lower fin portion 3000A. The isolation structure 3004 includes an insulator material 3004C having a top surface 3005. A placeholder gate electrode 3006 is above the top portion 3000C of the upper fin portion 3000B and laterally adjacent to the sidewall 3000D of the upper fin portion 3000B. The placeholder gate electrode 3006 includes a semiconductor material.

[0327] 30A (although its location is shown in FIG. 29C), a first source or drain region may be formed adjacent a first side of the placeholder gate electrode 3006, and a second source or drain region may be formed adjacent a second side of the placeholder gate electrode 3006, the second side facing the first side. Additionally, gate dielectric spacers may be formed along sidewalls of the placeholder gate electrode 3006, and an interlayer dielectric (ILD) layer may be formed laterally adjacent to the placeholder gate electrode 3006.

[0328] In one embodiment, placeholder gate electrode 3006 is or includes polycrystalline silicon. In one embodiment, top surface 3005 of insulator material 3004C of isolation structure 3004 has a concave depression, as shown. A portion of placeholder gate electrode 3006 is within the concave depression. In one embodiment, isolation structure 3004 includes a second insulator material (3004A, or 3004B, or both 3004A and 3004B) along the bottom and sidewalls of insulator material 3004C, as shown. In one such embodiment, the portion of second insulator material (3004A, or 3004B, or both 3004A and 3004B) along the sidewalls of insulator material 3004C has a top surface above at least a portion of top surface 3005 of insulator material 3004C. In one embodiment, the top surface of the second insulator material (3004A, or 3004B, or both 3004A and 3004B) is above the bottom surface of a portion of the placeholder gate electrode 3006.

[0329] 30B, the placeholder gate electrode 3006 is etched from above the top 3000C and sidewalls 3000D of the upper fin portion 3000B, for example, along the direction 3008 of FIG. 30A. The etching process may be referred to as a replacement gate process. In one embodiment, the etching or replacement gate process is incomplete, leaving a portion 3012 of the placeholder gate electrode 3006 on at least a portion of the top surface 3005 of the insulator material 3004C of the isolation structure 3004.

[0330] 30A and 30B, in one embodiment, the oxidized portion 3010 of the upper fin portion 3000B formed prior to the formation of the placeholder gate electrode 3006 is retained as shown during the etching process. However, in another embodiment, a placeholder gate dielectric layer is formed prior to the formation of the placeholder gate electrode 3006, and the placeholder gate dielectric layer is removed after the etching of the placeholder gate electrode.

[0331] 30C , a gate dielectric layer 3014 is formed above the top 3000C of the upper fin portion 3000B and laterally adjacent to the sidewall 3000D of the upper fin portion 3000B. In one embodiment, as shown, the gate dielectric layer 3014 is formed on the oxidized portion 3010 of the upper fin portion 3000B above the top 3000C of the upper fin portion 3000B and laterally adjacent to the sidewall 3000D of the upper fin portion 3000B. In another embodiment, if the oxidized portion 3010 of the upper fin portion 3000B is removed after etching the placeholder gate electrode, the gate dielectric layer 3014 is formed directly above the upper fin portion 3000B above the top 3000C of the upper fin portion 3000B and laterally adjacent to the sidewall 3000D of the upper fin portion 3000B. In either case, in one embodiment, a gate dielectric layer 3014 is further formed over a portion 3012 of the placeholder gate electrode 3006 over a portion of the top surface 3005 of the insulator material 3004C of the isolation structure 3004.

[0332] 30D, a permanent gate electrode 3016 is formed above the top 3000C of the upper fin portion 3000B and laterally adjacent the sidewall 3000D of the upper fin portion 3000B and above the gate dielectric layer 3014. The permanent gate electrode 3016 also overlies the gate dielectric layer 3014 on a portion of the top surface 3005 of the insulator material 3004C and on a portion 3012 of the placeholder gate electrode 3006.

[0333] In one embodiment, forming the permanent gate electrode 3016 includes forming a work function layer 3016A. In one such embodiment, the work function layer 3016A includes titanium and nitrogen. In another such embodiment, the work function layer 3016A includes titanium, aluminum, carbon, and nitrogen. In one embodiment, forming the permanent gate electrode 3016 further includes forming a conductive fill metal layer 3016B formed over the work function layer 3016A. In one such embodiment, forming the conductive fill metal layer 3016B includes forming a tungsten-containing film using atomic layer deposition (ALD) using a tungsten hexafluoride (WF6) precursor. In one embodiment, an insulating gate cap layer 3018 is formed on the permanent gate electrode 3016.

[0334] In another aspect, some embodiments of the present disclosure include an amorphous high-k layer in the gate dielectric structure for the gate electrode. In other embodiments, a partially or fully crystalline high-k layer is included in the gate dielectric structure for the gate electrode. In one embodiment including a partially or fully crystalline high-k layer, the gate dielectric structure is a ferroelectric (FE) gate dielectric structure. In another embodiment including a partially or fully crystalline high-k layer, the gate dielectric structure is an antiferroelectric (AFE) gate dielectric structure.

[0335] In one embodiment, an approach is described herein to increase the charge in the device channel and improve subthreshold behavior by employing ferroelectric or antiferroelectric gate oxides, which allow for increased channel charge for higher currents and sharper turn-on behavior.

[0336] To provide context, hafnium- or zirconium-based (Hf or Zr) ferroelectric and antiferroelectric (FE or AFE) materials are typically much thinner than ferroelectric materials such as lead zirconate titanate (PZT) and are therefore compatible with highly scaled logic technologies. There are two characteristics of FE or AFE materials that can improve logic transistor performance: (1) higher charge in the channel, achieved by the FE or AFE polarization, and (2) a steeper turn-on behavior due to a sharper FE or AFE transition. Such characteristics can improve transistor performance by increasing current and reducing subthreshold swing (SS).

[0337] FIG. 31A shows a cross-sectional view of a semiconductor device having a ferroelectric or antiferroelectric gate dielectric structure according to one embodiment of the present disclosure.

[0338] Referring to FIG. 31A, an integrated circuit structure 3100 includes a gate structure 3102 above a substrate 3104. In one embodiment, the gate structure 3102 is at or above a semiconductor channel structure 3106 comprising a single-crystal material, such as single-crystal silicon. The gate structure 3102 includes the semiconductor channel structure 3106 above the gate dielectric structure and a gate dielectric above a gate electrode. The gate dielectric includes a ferroelectric or antiferroelectric polycrystalline material layer 3102A. The gate electrode has a conductive layer 3102B on the ferroelectric or antiferroelectric polycrystalline material layer 3102A. The conductive layer 3102B includes a metal and may be a barrier layer, work function layer, or template layer that enhances crystallization of the FE or AFE layer. One or more gate fill layers 3102C are on or above the conductive layer 3102B. A source region 3108 and a drain region 3110 are on opposite sides of the gate structure 3102. 31A , the source or drain contact 3112 is electrically connected to the source region 3108 and the drain region 3110 at location 3149 and is spaced apart from the gate structure 3102 by one or both of an interlevel dielectric layer 3114 or a gate dielectric spacer 3116. In the example of FIG. 31A , the source region 3108 and the drain region 3110 are regions of the substrate 3104. In one embodiment, the source or drain contact 3112 includes a barrier layer 3112A and a conductive trench fill material 3112B. In one embodiment, the ferroelectric or antiferroelectric polycrystalline material layer 3102A extends along the dielectric spacer 3116, as shown in FIG. 31A .

[0339] In one embodiment, and as applied throughout this disclosure, the ferroelectric or antiferroelectric polycrystalline material layer 3102A is a ferroelectric polycrystalline material layer. In one embodiment, the ferroelectric polycrystalline material layer is an oxide containing Zr and Hf, with the ratio of Zr to Hf being 50:50 or more in favor of Zr. As the orthorhombic crystallinity increases, the ferroelectric effect can increase. In one embodiment, the ferroelectric polycrystalline material layer has at least 80% orthorhombic crystallinity.

[0340] In one embodiment, and as applied throughout this disclosure, the ferroelectric or antiferroelectric polycrystalline material layer 3102A is an antiferroelectric polycrystalline material layer. In one embodiment, the antiferroelectric polycrystalline material layer is an oxide containing Zr and Hf. The ratio of Zr to Hf is 80:20, i.e., Zr dominates, and may even be 100% Zr, ZrO2. In one embodiment, the antiferroelectric polycrystalline material layer has at least 80% tetragonal crystallinity.

[0341] In one embodiment, and as applied throughout this disclosure, the gate dielectric of the gate stack 3102 further comprises an amorphous dielectric layer 3103, such as a native silicon oxide layer, a high-k dielectric (HfOx, Al2O3, etc.), or a combination of oxide and high-k, between the ferroelectric or antiferroelectric polycrystalline material layer 3102A and the semiconductor channel structure 3106. In one embodiment, and as applied throughout this disclosure, the ferroelectric or antiferroelectric polycrystalline material layer 3102A has a thickness in the range of 1 nanometer to 8 nanometers. In one embodiment, and as applied throughout this disclosure, the crystalline grain size of the ferroelectric or antiferroelectric polycrystalline material layer 3102A is generally in the range of 20 nanometers or greater.

[0342] In one embodiment, following deposition of ferroelectric or antiferroelectric polycrystalline material layer 3102A, for example by atomic layer deposition (ALD), a layer comprising a metal (e.g., a 5-10 nanometer titanium nitride, tantalum nitride, or tungsten layer 3102B) is formed on ferroelectric or antiferroelectric polycrystalline material layer 3102A. An anneal is then performed. In one embodiment, the anneal is performed for a duration ranging from 1 millisecond to 30 minutes. In one embodiment, the anneal is performed at a temperature ranging from 500 to 1100°C.

[0343] FIG. 31B shows a cross-sectional view of another semiconductor device having a ferroelectric or antiferroelectric gate dielectric structure according to another embodiment of the present disclosure.

[0344] Referring to FIG. 31B, integrated circuit structure 3150 includes gate structure 3152 above substrate 3154. In one embodiment, gate structure 3152 is on or above semiconductor channel structure 3156, which includes a single-crystal material, such as single-crystal silicon. Gate structure 3152 includes a gate dielectric above semiconductor channel structure 3156 and a gate electrode above the gate dielectric structure. The gate dielectric includes a ferroelectric or antiferroelectric polycrystalline material layer 3152A and may further include an amorphous oxide layer 3153. The gate electrode has a conductive layer 3152B on ferroelectric or antiferroelectric polycrystalline material layer 3152A. Conductive layer 3152B includes a metal and may be a barrier layer or a work function layer. One or more gate fill layers 3152C are on or above conductive layer 3152B. A raised source region 3158 and a raised drain region 3160, such as regions of semiconductor material different from the semiconductor channel structure 3156, are on opposite sides of the gate structure 3152. A source or drain contact 3162 is electrically connected to the source region 3158 and the drain region 3160 at location 3199 and is spaced from the gate structure 3152 by one or both of an interlayer dielectric layer 3164 or a gate dielectric spacer 3166. In one embodiment, the source or drain contact 3162 includes a barrier layer 3162A and a conductive trench fill material 3162B. In one embodiment, the ferroelectric or antiferroelectric polycrystalline material layer 3152A extends along the dielectric spacer 3166, as shown in FIG.

[0345] FIG. 32A shows a plan view of multiple gate lines above a pair of semiconductor fins according to another embodiment of the present disclosure.

[0346] 32A , a plurality of active gate lines 3204 are formed above a plurality of semiconductor fins 3200. Dummy gate lines 3206 are at the ends of the plurality of semiconductor fins 3200. Spaces 3208 between the gate lines 3204 / 3206 are locations where trench contacts may be placed to provide conductive contact to source or drain regions, such as source or drain regions 3251, 3252, 3253, and 3254. In one embodiment, the patterning of the plurality of gate lines 3204 / 3206 or the patterning of the plurality of semiconductor fins 3200 is described as a grid structure. In one embodiment, the grid-like pattern includes a plurality of gate lines 3204 / 3206, or a pattern of a plurality of semiconductor fins 3200 spaced at a regular pitch and having a regular width, or both.

[0347] FIG. 32B shows a cross-sectional view taken along axis aa' of FIG. 32A according to one embodiment of the present disclosure.

[0348] 32B, a plurality of active gate lines 3264 are formed above a semiconductor fin 3262 formed above a substrate 3260. Dummy gate lines 3266 are at the ends of the semiconductor fin 3262. A dielectric layer 3270 is outside the dummy gate lines 3266. Trench contact material 3297 is between the active gate lines 3264 and between the dummy gate lines 3266 and the active gate lines 3264. Buried source or drain structures 3268 are in the semiconductor fin 3262 between the active gate lines 3264 and between the dummy gate lines 3266 and the active gate lines 3264.

[0349] Active gate line 3264 includes gate dielectric structure 3272, work function gate electrode portion 3274, and filler gate electrode portion 3276, as well as dielectric capping layer 3278. Dielectric spacers 3280 are along the sidewalls of active gate line 3264 and dummy gate line 3266. In one embodiment, gate dielectric structure 3272 includes ferroelectric or antiferroelectric polycrystalline material layer 3298. In one embodiment, gate dielectric structure 3272 further includes amorphous oxide layer 3299.

[0350] In another embodiment, devices of the same conductivity type, e.g., N-type or P-type, may have gate electrode stacks for the same conductivity type that are differentiated. However, for comparison purposes, devices with the same conductivity type may have differentiated voltage thresholds (VT) based on tailored doping.

[0351] FIG. 33A illustrates a cross-sectional view of a pair of NMOS devices with differentiated voltage thresholds based on tailored doping and a pair of PMOS devices with differentiated voltage thresholds based on tailored doping, in accordance with one embodiment of the present disclosure.

[0352] Referring to FIG. 33A , a first NMOS device 3302 is adjacent to a second NMOS device 3304 above a semiconductor active region 3300, such as above a silicon fin or substrate. Both the first NMOS device 3302 and the second NMOS device 3304 include a gate dielectric layer 3306, a first gate electrode conductive layer 3308, such as a work function layer, and a gate electrode conductive filling 3310. In one embodiment, the first gate electrode conductive layers 3308 of the first NMOS device 3302 and the second NMOS device 3304 are of the same material and thickness, and therefore have the same work function. However, the first NMOS device 3302 has a lower VT than the second NMOS device 3304. In one such embodiment, the first NMOS device 3302 is referred to as a “standard VT” device, and the second NMOS device 3304 is referred to as a “high VT” device. In one embodiment, the differentiated V T is achieved by using tailored or differentiated implant doping in the region 3312 of the first NMOS device 3302 and the second NMOS device 3304 .

[0353] Referring again to FIG. 33A , a first PMOS device 3322 is adjacent to a second PMOS device 3324 above a semiconductor active region 3320, such as above a silicon fin or substrate. Both the first PMOS device 3322 and the second PMOS device 3324 include a gate dielectric layer 3326, a first gate electrode conductive layer 3328, such as a work function layer, and a gate electrode conductive filling 3330. In one embodiment, the first gate electrode conductive layers 3328 of the first PMOS device 3322 and the second PMOS device 3324 are of the same material and thickness, and therefore have the same work function. However, the first PMOS device 3322 has a higher VT than the second PMOS device 3324. In one such embodiment, the first PMOS device 3322 is referred to as a “standard VT” device, and the second PMOS device 3324 is referred to as a “low VT” device. In one embodiment, the differentiated V T is achieved by using tailored or differentiated implant doping in the regions 3332 of the first PMOS device 3322 and the second PMOS device 3324 .

[0354] In contrast to FIG. 33A, FIG. 33B illustrates a cross-sectional view of a pair of NMOS devices having differentiated voltage thresholds based on differentiated gate electrode structures and a pair of PMOS devices having differentiated voltage thresholds based on differentiated gate electrode structures, according to another embodiment of the present disclosure.

[0355] Referring to FIG. 33B , a first NMOS device 3352 is adjacent to a second NMOS device 3354 above a semiconductor active region 3350, such as above a silicon fin or substrate. Both the first NMOS device 3352 and the second NMOS device 3354 include a gate dielectric layer 3356. However, the first NMOS device 3352 and the second NMOS device 3354 have structurally different gate electrode stacks. In particular, the first NMOS device 3352 includes a first gate electrode conductive layer 3358, such as a first work function layer, and a gate electrode conductive filling 3360. The second NMOS device 3354 includes a second gate electrode conductive layer 3359, such as a second work function layer, the first gate electrode conductive layer 3358, and a gate electrode conductive filling 3360. The first NMOS device 3352 has a lower V T than the second NMOS device 3354. In one such embodiment, the first NMOS device 3352 is referred to as a "standard VT" device and the second NMOS device 3354 is referred to as a "high VT" device. In one embodiment, the differentiated VT is achieved by using differentiated gate stacks for devices of the same conductivity type.

[0356] Referring again to FIG. 33B , a first PMOS device 3372 is adjacent to a second PMOS device 3374 above a semiconductor active region 3370, such as above a silicon fin or substrate. Both the first PMOS device 3372 and the second PMOS device 3374 include a gate dielectric layer 3376. However, the first PMOS device 3372 and the second PMOS device 3374 have structurally different gate electrode stacks. In particular, the first PMOS device 3372 includes a gate electrode conductive layer 3378A, such as a work function layer, having a first thickness and a gate electrode conductive filling 3380. The second PMOS device 3374 includes a gate electrode conductive layer 3378B having a second thickness and a gate electrode conductive filling 3380. In one embodiment, gate electrode conductive layer 3378A and gate electrode conductive layer 3378B have the same composition, but the thickness (second thickness) of gate electrode conductive layer 3378B is greater than the thickness (first thickness) of gate electrode conductive layer 3378A. First PMOS device 3372 has a higher VT than second PMOS device 3374. In such an embodiment, first PMOS device 3372 is referred to as a "standard VT" device and second PMOS device 3374 is referred to as a "low VT" device. In one embodiment, the differentiated VT is achieved by using differentiated gate stacks for devices of the same conductivity type.

[0357] Referring again to FIG. 33B , according to one embodiment of the present disclosure, an integrated circuit structure includes a fin (e.g., a silicon fin such as 3350). It should be understood that the fin has a top (as shown) and sidewalls (far and near the page). A gate dielectric layer 3356 is above the top of the fin and laterally adjacent the sidewalls of the fin. An N-type gate electrode of device 3354 is above the top of the fin, laterally adjacent the sidewalls of the fin, and above gate dielectric layer 3356. The N-type gate electrode includes a P-type metal layer 3359 on gate dielectric layer 3356 and an N-type metal layer 3358 on P-type metal layer 3359. As should be understood, a first N-type source or drain region may be adjacent to a first side of the gate electrode (e.g., far from the page), and a second N-type source or drain region may be adjacent to a second side of the gate electrode (e.g., near the page), with the second side facing the first side.

[0358] In one embodiment, P-type metal layer 3359 comprises titanium and nitrogen, and N-type metal layer 3358 comprises titanium, aluminum, carbon, and nitrogen. In one embodiment, P-type metal layer 3359 has a thickness in the range of 2-12 angstroms, and in a specific embodiment, P-type metal layer 3359 has a thickness in the range of 2-4 angstroms. In one embodiment, N-type gate electrode further comprises conductive fill metal layer 3360 on N-type metal layer 3358. In one such embodiment, conductive fill metal layer 3360 comprises tungsten. In a specific embodiment, conductive fill metal layer 3360 comprises 95% or more atomic percent tungsten and 0.1-2% atomic percent fluorine.

[0359] 33B, according to another embodiment of the present disclosure, an integrated circuit structure includes a first N-type device 3352 having a voltage threshold (VT), first N-type device 3352 having a first gate dielectric layer 3356, and a first N-type metal layer 3358 on first gate dielectric layer 3356. Also included is a second N-type device 3354 having a voltage threshold (VT), second N-type device 3354 having a second gate dielectric layer 3356, a P-type metal layer 3359 on second gate dielectric layer 3356, and a second N-type metal layer 3358 on P-type metal layer 3359.

[0360] In one embodiment, the VT of second N-type device 3354 is higher than the VT of first N-type device 3352. In one embodiment, first N-type metal layer 3358 and second N-type metal layer 3358 have the same composition. In one embodiment, first N-type metal layer 3358 and second N-type metal layer 3358 have the same thickness. In one embodiment, N-type metal layer 3358 includes titanium, aluminum, carbon, and nitrogen, and P-type metal layer 3359 includes titanium and nitrogen.

[0361] 33B , according to another embodiment of the present disclosure, an integrated circuit structure includes a first P-type device 3372 having a voltage threshold (VT), first P-type device 3372 having a first gate dielectric layer 3376, and a first P-type metal layer 3378A on first gate dielectric layer 3376. First P-type metal layer 3378A has a thickness. Also included is a second P-type device 3374, having a voltage threshold (VT). Second P-type device 3374 has a second gate dielectric layer 3376 and a second P-type metal layer 3378B on second gate dielectric layer 3376. Second P-type metal layer 3378B has a thickness greater than the thickness of first P-type metal layer 3378A.

[0362] In one embodiment, the VT of the second P-type device 3374 is lower than the VT of the first P-type device 3372. In one embodiment, the first P-type metal layer 3378A and the second P-type metal layer 3378B have the same composition. In one embodiment, the first P-type metal layer 3378A and the second P-type metal layer 3378B both include titanium and nitrogen. In one embodiment, the thickness of the first P-type metal layer 3378A is less than the work function saturation thickness of the material of the first P-type metal layer 3378A. In one embodiment, although not shown, the second P-type metal layer 3378B includes a first metal film (e.g., from the second deposition) on a second metal film (e.g., from the first deposition), with a seam between the first and second metal films.

[0363] 33B , according to another embodiment of the present disclosure, an integrated circuit structure includes a first N-type device 3352 having a first gate dielectric layer 3356 and a first N-type metal layer 3358 on first gate dielectric layer 3356. A second N-type device 3354 has a second gate dielectric layer 3356, a first P-type metal layer 3359 on second gate dielectric layer 3356, and a second N-type metal layer 3358 on first P-type metal layer 3359. A first P-type device 3372 has a third gate dielectric layer 3376 and a second P-type metal layer 3378A on third gate dielectric layer 3376. Second P-type metal layer 3378A has a thickness. A second P-type device 3374 has a fourth gate dielectric layer 3376 and a third P-type metal layer 3378B on fourth gate dielectric layer 3376. The third P-type metal layer 3378B has a thickness greater than the thickness of the second P-type metal layer 3378A.

[0364] In one embodiment, the first N-type device 3352 has a voltage threshold (VT) and the second N-type device 3354 has a voltage threshold (VT), where the VT of the second N-type device 3354 is lower than the VT of the first N-type device 3352. In one embodiment, the first P-type device 3372 has a voltage threshold (VT) and the second P-type device 3374 has a voltage threshold (VT), where the VT of the second P-type device 3374 is lower than the VT of the first P-type device 3372. In one embodiment, the third P-type metal layer 3378B includes a first metal film on a second metal film and a seam between the first and second metal films.

[0365] It should be understood that more than two VT devices of the same conductivity type may be included in the same structure, such as on the same die. In a first example, Figure 34A shows a cross-sectional view of a triplet of NMOS devices with differentiated voltage thresholds based on differentiated gate electrode structures and tailored doping, and a triplet of PMOS devices with differentiated voltage thresholds based on differentiated gate electrode structures and tailored doping, according to one embodiment of the present disclosure.

[0366] 34A , a first NMOS device 3402 is adjacent to a second NMOS device 3404 and a third NMOS device 3403 above a semiconductor active region 3400, such as above a silicon fin or substrate. The first NMOS device 3402, the second NMOS device 3404, and the third NMOS device 3403 include a gate dielectric layer 3406. The first NMOS device 3402 and the third NMOS device 3403 have structurally identical or similar gate electrode stacks. However, the second NMOS device 3404 has a structurally different gate electrode stack than the first NMOS device 3402 and the third NMOS device 3403. In particular, the first NMOS device 3402 and the third NMOS device 3403 include a first gate electrode conductive layer 3408, such as a first work function layer, and a gate electrode conductive filling 3410. The second NMOS device 3404 includes a second gate electrode conductive layer 3409, such as a second work function layer, a first gate electrode conductive layer 3408, and a gate electrode conductive filling 3410. The first NMOS device 3402 has a lower VT than the second NMOS device 3404. In one such embodiment, the first NMOS device 3402 is referred to as a “standard VT” device, and the second NMOS device 3404 is referred to as a “high VT” device. In one embodiment, the differentiated VTs are achieved by using differentiated gate stacks for devices of the same conductivity type. In one embodiment, the gate electrode structure of the third NMOS device 3403 is identical to that of the first NMOS device 3402, but the third NMOS device 3403 has a different VT than the VTs of the first NMOS device 3402 and the second NMOS device 3404. In one embodiment, the VT of the third NMOS device 3403 is between the VTs of the first NMOS device 3402 and the second NMOS device 3404. In one embodiment, the differentiated V T between the third NMOS device 3403 and the first NMOS device 3402 is achieved by using tailored or differentiated implant doping in region 3412 of the third NMOS device 3403.In one such embodiment, the third N-type device 3403 has a channel region with a dopant concentration that differs from the dopant concentration of the channel region of the first N-type device 3402 .

[0367] Referring again to FIG. 34A , a first PMOS device 3422 is adjacent to a second PMOS device 3424 and a third PMOS device 3423 above a semiconductor active region 3420, such as above a silicon fin or substrate. The first PMOS device 3422, the second PMOS device 3424, and the third PMOS device 3423 include a gate dielectric layer 3426. The first PMOS device 3422 and the third PMOS device 3423 have structurally identical or similar gate electrode stacks. However, the second PMOS device 3424 has a structurally different gate electrode stack than the first PMOS device 3422 and the third PMOS device 3423. In particular, the first PMOS device 3422 and the third PMOS device 3423 include a gate electrode conductive layer 3428A, such as a work function layer, having a first thickness, and a gate electrode conductive filling 3430. The second PMOS device 3424 includes a gate electrode conductive layer 3428B having a second thickness and a gate electrode conductive filling 3430. In one embodiment, the gate electrode conductive layer 3428A and the gate electrode conductive layer 3428B have the same composition, but the thickness (second thickness) of the gate electrode conductive layer 3428B is greater than the thickness (first thickness) of the gate electrode conductive layer 3428A. In one embodiment, the first PMOS device 3422 has a higher VT than the second PMOS device 3424. In one such embodiment, the first PMOS device 3422 is referred to as a “standard VT” device, and the second PMOS device 3424 is referred to as a “low VT” device. In one embodiment, the differentiated VT is achieved by using differentiated gate stacks for devices of the same conductivity type. In one embodiment, the gate electrode structure of the third PMOS device 3423 is the same as the gate electrode structure of the first PMOS device 3422, but the third PMOS device 3423 has a VT that is different from the VTs of the first PMOS device 3422 and the second PMOS device 3424. In one embodiment, the VT of the third PMOS device 3423 is between the VTs of the first PMOS device 3422 and the second PMOS device 3424.In one embodiment, the differentiated V T between the third PMOS device 3423 and the first PMOS device 3422 is achieved by using tailored or differentiated implant doping in the region 3432 of the third PMOS device 3423. In one such embodiment, the third P-type device 3423 has a channel region with a dopant concentration that differs from the dopant concentration of the channel region of the first P-type device 3422.

[0368] In a second example, FIG. 34B illustrates a cross-sectional view of a triplet of NMOS devices with differentiated voltage thresholds based on differentiated gate electrode structures and tailored doping, and a triplet of PMOS devices with differentiated voltage thresholds based on differentiated gate electrode structures and tailored doping, according to another embodiment of the present disclosure.

[0369] 34B , a first NMOS device 3452 is adjacent to a second NMOS device 3454 and a third NMOS device 3453 above a semiconductor active region 3450, such as above a silicon fin or substrate. The first NMOS device 3452, the second NMOS device 3454, and the third NMOS device 3453 include a gate dielectric layer 3456. The second NMOS device 3454 and the third NMOS device 3453 have structurally identical or similar gate electrode stacks. However, the first NMOS device 3452 has a structurally different gate electrode stack than the second NMOS device 3454 and the third NMOS device 3453. In particular, the first NMOS device 3452 includes a first gate electrode conductive layer 3458, such as a first work function layer, and a gate electrode conductive filling 3460. The second NMOS device 3454 and the third NMOS device 3453 include a second gate electrode conductive layer 3459, such as a second work function layer, a first gate electrode conductive layer 3458, and a gate electrode conductive filling 3460. The first NMOS device 3452 has a lower VT than the second NMOS device 3454. In one such embodiment, the first NMOS device 3452 is referred to as a “standard VT” device, and the second NMOS device 3454 is referred to as a “high VT” device. In one embodiment, the differentiated VTs are achieved by using differentiated gate stacks for devices of the same conductivity type. In one embodiment, the gate electrode structure of the third NMOS device 3453 is identical to the gate electrode structure of the second NMOS device 3454, but the third NMOS device 3453 has a different VT than the VTs of the first NMOS device 3452 and the second NMOS device 3454. In one embodiment, the VT of the third NMOS device 3453 is between the VT of the first NMOS device 3452 and the second NMOS device 3454. In one embodiment, the differentiated VT between the third NMOS device 3453 and the second NMOS device 3454 is achieved by using tailored or differentiated implant doping in the region 3462 of the third NMOS device 3453.In one such embodiment, the third N-type device 3453 has a channel region with a dopant concentration that differs from the dopant concentration of the channel region of the second N-type device 3454 .

[0370] 34B , a first PMOS device 3472 is adjacent to a second PMOS device 3474 and a third PMOS device 3473 above a semiconductor active region 3470, such as above a silicon fin or substrate. The first PMOS device 3472, the second PMOS device 3474, and the third PMOS device 3473 include a gate dielectric layer 3476. The second PMOS device 3474 and the third PMOS device 3473 have structurally identical or similar gate electrode stacks. However, the first PMOS device 3472 has a structurally different gate electrode stack than the second PMOS device 3474 and the third PMOS device 3473. In particular, the first PMOS device 3472 includes a gate electrode conductive layer 3478A, such as a work function layer, having a first thickness, and a gate electrode conductive filling 3480. Second PMOS device 3474 and third PMOS device 3473 include gate electrode conductive layer 3478B having a second thickness and gate electrode conductive filling 3480. In one embodiment, gate electrode conductive layer 3478A and gate electrode conductive layer 3478B have the same composition, but the thickness (second thickness) of gate electrode conductive layer 3478B is greater than the thickness (first thickness) of gate electrode conductive layer 3478A. In one embodiment, first PMOS device 3472 has a higher VT than second PMOS device 3474. In one such embodiment, first PMOS device 3472 is referred to as a “standard VT” device and second PMOS device 3474 is referred to as a “low VT” device. In one embodiment, the differentiated VTs are achieved by using differentiated gate stacks for devices of the same conductivity type. In one embodiment, the gate electrode structure of the third PMOS device 3473 is the same as the gate electrode structure of the second PMOS device 3474, but the third PMOS device 3473 has a VT that is different from the VTs of the first PMOS device 3472 and the second PMOS device 3474. In one embodiment, the VT of the third PMOS device 3473 is between the VTs of the first PMOS device 3472 and the second PMOS device 3474.In one embodiment, a differentiated V T between the third PMOS device 3473 and the first PMOS device 3472 is achieved by using tailored or differentiated implant doping in region 3482 of the third PMOS device 3473. In one such embodiment, the third P-type device 3473 has a channel region with a dopant concentration that differs from the dopant concentration of the channel region of the second P-type device 3474.

[0371] 35A-35D illustrate cross-sectional views of various steps in a method of fabricating NMOS devices with differentiated voltage thresholds based on differentiated gate electrode structures according to another embodiment of the present disclosure.

[0372] 35A , in which a “standard VT NMOS” region (STD VT NMOS) and a “high VT NMOS” region (HIGH VT NMOS) are shown diverging on a common substrate, a method of fabricating an integrated circuit structure includes forming a gate dielectric layer 3506 over a first semiconductor fin 3502 and over a second semiconductor fin 3504, such as over first and second silicon fins. A P-type metal layer 3508 is formed on the gate dielectric layer 3506 over the first semiconductor fin 3502 and over the second semiconductor fin 3504.

[0373] Referring to FIG. 35B, a portion of the P-type metal layer 3508 is removed from the gate dielectric layer 3506 above the first semiconductor fin 3502, while a portion 3509 of the P-type metal layer 3508 is retained on the gate dielectric layer 3506 above the second semiconductor fin 3504.

[0374] 35C, an N-type metal layer 3510 is formed on the gate dielectric layer 3506 above the first semiconductor fin 3502 and on a portion 3509 of the P-type metal layer on the gate dielectric layer 3506 above the second semiconductor fin 3504. In one embodiment, subsequent processing includes forming a first N-type device above the first semiconductor fin 3502 having a voltage threshold (VT) and forming a second N-type device above the second semiconductor fin 3504 having a voltage threshold (VT), the VT of the second N-type device being higher than the VT of the first N-type device.

[0375] 35D, in one embodiment, a conductive fill metal layer 3512 is formed on N-type metal layer 3510. In one such embodiment, forming the conductive fill metal layer 3512 includes forming a tungsten-containing film using atomic layer deposition (ALD) with a tungsten hexafluoride (WF6) precursor.

[0376] 36A-36D illustrate cross-sectional views of various steps in a method of fabricating PMOS devices with differentiated voltage thresholds based on differentiated gate electrode structures according to another embodiment of the present disclosure.

[0377] 36A , in which a “standard VT PMOS” region (STD VT PMOS) and a “low VT PMOS” region (LOW VT PMOS) are shown as diverging on a common substrate, a method of fabricating an integrated circuit structure includes forming a gate dielectric layer 3606 over a first semiconductor fin 3602 and over a second semiconductor fin 3604, such as over first and second silicon fins. A first P-type metal layer 3608 is formed on the gate dielectric layer 3606 over the first semiconductor fin 3602 and over the second semiconductor fin 3604.

[0378] Referring to FIG. 36B, a portion of the first P-type metal layer 3608 is removed from the gate dielectric layer 3606 above the first semiconductor fin 3602, while a portion 3609 of the first P-type metal layer 3608 is retained on the gate dielectric layer 3606 above the second semiconductor fin 3604.

[0379] 36C, a second P-type metal layer 3610 is formed on the gate dielectric layer 3606 above the first semiconductor fin 3602 and on a portion 3609 of the first P-type metal layer on the gate dielectric layer 3606 above the second semiconductor fin 3604. In one embodiment, subsequent processing includes forming a first P-type device above the first semiconductor fin 3602 having a voltage threshold (VT) and forming a second P-type device above the second semiconductor fin 3604 having a voltage threshold (VT), the VT of the second P-type device being lower than the VT of the first P-type device.

[0380] In one embodiment, first P-type metal layer 3608 and second P-type metal layer 3610 have the same composition. In one embodiment, first P-type metal layer 3608 and second P-type metal layer 3610 have the same thickness. In one embodiment, first P-type metal layer 3608 and second P-type metal layer 3610 have the same thickness and the same composition. In one embodiment, as shown, seam 3611 is between first P-type metal layer 3608 and second P-type metal layer 3610.

[0381] 36D , in one embodiment, a conductive fill metal layer 3612 is formed above a P-type metal layer 3610. In one such embodiment, forming the conductive fill metal layer 3612 includes forming a tungsten-containing film using atomic layer deposition (ALD) with a tungsten hexafluoride (WF) precursor. In one embodiment, as shown, an N-type metal layer 3614 is formed on the P-type metal layer 3610 prior to forming the conductive fill metal layer 3612. In one such embodiment, the N-type metal layer 3614 is an artifact of a dual metal gate replacement processing scheme.

[0382] In another aspect, a metal gate structure for a complementary metal oxide semiconductor (CMOS) semiconductor device is described. In one example, Figure 37 shows a cross-sectional view of an integrated circuit structure with a P / N junction according to an embodiment of the present disclosure.

[0383] 37, integrated circuit structure 3700 includes a semiconductor substrate 3702 having an N-well region 3704 with a first semiconductor fin 3706 projecting therefrom and a P-well region 3708 with a second semiconductor fin 3710 projecting therefrom. The first semiconductor fin 3706 is spaced apart from the second semiconductor fin 3710. The N-well region 3704 is directly adjacent to the P-well region 3708 in the semiconductor substrate 3702. A trench isolation structure 3712 is on the semiconductor substrate 3702 between and outside the first semiconductor fin 3706 and the second semiconductor fin 3210. The first semiconductor fin 3706 and the second semiconductor fin 3210 extend above the trench isolation structure 3712.

[0384] A gate dielectric layer 3714 is over the first semiconductor fin 3706 and the second semiconductor fin 3710, as well as over the trench isolation structure 3712. The gate dielectric layer 3714 is continuous between the first semiconductor fin 3706 and the second semiconductor fin 3710. A conductive layer 3716 is over the gate dielectric layer 3714 above the first semiconductor fin 3706, but not over the second semiconductor fin 3710. In one embodiment, the conductive layer 3716 comprises titanium, nitrogen, and oxygen. A P-type metal gate layer 3718 is over the conductive layer 3716 above the first semiconductor fin 3706, but not over the second semiconductor fin 3710. The P-type metal gate layer 3718 also overlies a portion, but not all, of the trench isolation structure 3712 between the first semiconductor fin 3706 and the second semiconductor fin 3710. An n-type metal gate layer 3720 is above the second semiconductor fin 3710, above the trench isolation structure 3712 between the first semiconductor fin 3706 and the second semiconductor fin 3710, and above the p-type metal gate layer 3718.

[0385] In one embodiment, an interlayer dielectric (ILD) layer 3722 is above the trench isolation structure 3712, outside the first semiconductor fin 3706 and the second semiconductor fin 3710. The ILD layer 3722 has an opening 3724, which exposes the first semiconductor fin 3706 and the second semiconductor fin 3710. In one such embodiment, a conductive layer 3716, a p-type metal gate layer 3718, and an n-type metal gate layer 3720 are further formed along sidewalls 3726 of the opening 3724, as shown. In a particular embodiment, the conductive layer 3716 has a top surface 3717 along the sidewalls 3726 of the opening 3724 below a top surface 3719 of the p-type metal gate layer 3718 along the sidewalls 3726 of the opening 3724 and a top surface 3721 of the n-type metal gate layer 3720, as shown.

[0386] In one embodiment, p-type metal gate layer 3718 comprises titanium and nitrogen. In one embodiment, n-type metal gate layer 3720 comprises titanium and aluminum. In one embodiment, conductive fill metal layer 3730 is above n-type metal gate layer 3720, as shown. In one such embodiment, conductive fill metal layer 3730 comprises tungsten. In a particular embodiment, conductive fill metal layer 3730 comprises 95% or higher atomic percent tungsten and 0.1-2% atomic percent fluorine. In one embodiment, gate dielectric layer 3714 comprises a layer comprising hafnium and oxygen. In one embodiment, as shown, a thermal or chemical oxidation layer 3732 is between the top of first semiconductor fin 3706 and the top of second semiconductor fin 3710. In one embodiment, semiconductor substrate 3702 is a bulk silicon semiconductor substrate.

[0387] 37 , in accordance with one embodiment of the present disclosure, an integrated circuit structure includes a semiconductor substrate 3702 including an N-well region 3704 having a semiconductor fin 3706 protruding therefrom. A trench isolation structure 3712 is on the semiconductor substrate 3702 around the semiconductor fin 3706. The semiconductor fin 3706 extends above the trench isolation structure 3712. A gate dielectric layer 3714 is above the semiconductor fin 3706. A conductive layer 3716 is above the gate dielectric layer 3714 above the semiconductor fin 3706. In one embodiment, the conductive layer 3716 comprises titanium, nitrogen, and oxygen. A P-type metal gate layer 3718 is above the conductive layer 3716 above the semiconductor fin 3706.

[0388] In one embodiment, an interlevel dielectric (ILD) layer 3722 is above trench isolation structure 3712. The ILD layer has an opening, the opening exposing semiconductor fin 3706. Furthermore, a conductive layer 3716 and a P-type metal gate layer 3718 are formed along the sidewalls of the opening. In one such embodiment, conductive layer 3716 has a top surface along the sidewalls of the opening that is lower than a top surface of P-type metal gate layer 3718 along the sidewalls of the opening. In one embodiment, P-type metal gate layer 3718 is above conductive layer 3716. In one embodiment, P-type metal gate layer 3718 comprises titanium and nitrogen. In one embodiment, conductive fill metal layer 3730 is above P-type metal gate layer 3718. In one such embodiment, conductive fill metal layer 3730 comprises tungsten. In certain such embodiments, conductive fill metal layer 3730 is composed of 95% or more atomic percent tungsten and 0.1-2% atomic percent fluorine. In one embodiment, the gate dielectric layer 3714 comprises a layer having hafnium and oxygen.

[0389] 38A through 38H illustrate cross-sectional views of various steps in a method of fabricating an integrated circuit structure using a dual metal gate replacement gate process flow according to one embodiment of the present disclosure.

[0390] 38A , which illustrates an NMOS (N-type) region and a PMOS (P-type) region, a method of fabricating an integrated circuit structure includes forming an interlayer dielectric (ILD) layer 3802 above a first semiconductor fin 3804 and a second semiconductor fin 3806 above a substrate 3800. An opening 3808 is formed in the ILD layer 3802, the opening 3808 exposing the first semiconductor fin 3804 and the second semiconductor fin 3806. In one embodiment, the opening 3808 is formed by removing a gate placeholder or dummy gate structure that was originally placed above the first semiconductor fin 3804 and the second semiconductor fin 3806.

[0391] A gate dielectric layer 3810 is formed in the opening 3808, over the first semiconductor fin 3804 and the second semiconductor fin 3806, and on a portion of a trench isolation structure 3812 between the first semiconductor fin 3804 and the second semiconductor fin 3806. In one embodiment, as shown, the gate dielectric layer 3810 is formed on a thermal or chemical oxidation layer 3811, such as a silicon oxide or silicon dioxide layer, formed on the first semiconductor fin 3804 and the second semiconductor fin 3806. In another embodiment, the gate dielectric layer 3810 is formed directly over the first semiconductor fin 3804 and the second semiconductor fin 3806.

[0392] A conductive layer 3814 is formed over the gate dielectric layer 3810 formed over the first semiconductor fin 3804 and the second semiconductor fin 3806. In one embodiment, the conductive layer 3814 comprises titanium, nitrogen, and oxygen. A P-type metal gate layer 3816 is formed over the first semiconductor fin 3804 and the conductive layer 3814 formed over the second semiconductor fin 3806.

[0393] 38B, a dielectric etch stop layer 3818 is formed on the p-type metal gate layer 3816. In one embodiment, the dielectric etch stop layer 3818 includes a first layer of silicon oxide (e.g., SiO), a layer of aluminum oxide (e.g., AlO) on the first layer of silicon oxide, and a second layer of silicon oxide (e.g., SiO) on the layer of aluminum oxide.

[0394] Referring to Figure 38C, a mask 3820 is formed over the structure of Figure 38B. Mask 3820 covers the PMOS regions and exposes the NMOS regions.

[0395] 38D , the dielectric etch stop layer 3818, the p-type metal gate layer 3816, and the conductive layer 3814 are patterned to provide a patterned dielectric etch stop layer 3819 and a patterned p-type metal gate layer 3817 over the patterned conductive layer 3815 over the first semiconductor fin 3804, but not over the second semiconductor fin 3806. In one embodiment, the conductive layer 3814 protects the second semiconductor fin 3806 during patterning.

[0396] Referring to Figure 38E, mask 3820 is removed from the structure of Figure 38D. Referring to Figure 38F, patterned dielectric etch stop layer 3819 is removed from the structure of Figure 38E.

[0397] 38G , an n-type metal gate layer 3822 is formed over the second semiconductor fin 3806, over a portion of the trench isolation structure 3812 between the first semiconductor fin 3804 and the second semiconductor fin 3806, and over the patterned p-type metal gate layer 3817. In one embodiment, the patterned conductive layer 3815, the patterned p-type metal gate layer 3817, and the n-type metal gate layer 3822 are further formed along the sidewalls 3824 of the opening 3808. In one such embodiment, the patterned conductive layer 3815 has a top surface along the sidewalls 3824 of the opening 3808 that is below a top surface of the patterned p-type metal gate layer 3817 and a top surface of the n-type metal gate layer 3822 along the sidewalls 3824 of the opening 3808.

[0398] 38H, a conductive fill metal layer 3826 is formed above n-type metal gate layer 3822. In one embodiment, conductive fill metal layer 3826 is formed by depositing a tungsten-containing film using atomic layer deposition (ALD) with a tungsten hexafluoride (WF6) precursor.

[0399] In another aspect, a dual silicide structure for a complementary metal oxide semiconductor (CMOS) semiconductor device is described. As an exemplary process flow, Figures 39A-39H show cross-sectional views illustrating various steps in a method for fabricating a dual silicide-based integrated circuit according to one embodiment of the present disclosure.

[0400] 39A , in which NMOS and PMOS regions are shown diverging on a common substrate, a method of fabricating an integrated circuit structure includes forming a first gate structure 3902, which may include dielectric sidewall spacers 3903, over a first fin 3904, such as a first silicon fin. A second gate structure 3952, which may include dielectric sidewall spacers 3953, is formed over a second fin 3954, such as a second silicon fin. An insulator material 3906 is formed over the first fin 3904 adjacent to the first gate structure 3902 and over the second fin 3954 adjacent to the second gate structure 3952. In one embodiment, the insulator material 3906 is a sacrificial material and is used as a mask in a dual silicide process.

[0401] 39B , a first portion of insulator material 3906 is removed from above first fin 3904, but not from above second fin 3954, exposing a first source or drain region 3908 and a second source or drain region 3910 of first fin 3904 adjacent first gate structure 3902. In one embodiment, first source or drain region 3908 and second source or drain region 3910 are epitaxial regions formed in a recess in first fin 3904, as shown. In one such embodiment, first source or drain region 3908 and second source or drain region 3910 comprise silicon and germanium.

[0402] 39C, a first metal silicide layer 3912 is formed on the first source or drain region 3908 and the second source or drain region 3910 of the first fin 3904. In one embodiment, the first metal silicide layer 3912 is formed by depositing a layer comprising nickel and platinum on the structure of FIG. 39B, annealing the layer comprising nickel and platinum, and removing unreacted portions of the layer comprising nickel and platinum.

[0403] 39D , after the formation of the first metal silicide layer 3912, the second portion of the insulator material 3906 is removed from above the second fin 3954, exposing a third source or drain region 3958 and a fourth source or drain region 3960 of the second fin 3954 adjacent the second gate structure 3952. In one embodiment, the second source or drain region 3958 and the third source or drain region 3960 are formed in the second fin 3954, such as in a second silicon fin, as shown. However, in another embodiment, the third source or drain region 3958 and the fourth source or drain region 3960 are epitaxial regions formed in a recessed portion of the second fin 3954. In one such embodiment, the third source or drain region 3958 and the fourth source or drain region 3960 comprise silicon.

[0404] 39E, a first metal layer 3914 is formed over the structure of FIG. 39D, i.e., over the first source or drain region 3908, the second source or drain region 3910, the third source or drain region 3958, and the fourth source or drain region 3960. Next, a second metal silicide layer 3962 is formed over the third source or drain region 3958 and the fourth source or drain region 3960 of the second fin 3954. The second metal silicide layer 3962 is formed from the first metal layer 3914 using, for example, an annealing process. In one embodiment, the second metal silicide layer 3962 has a different composition than the first metal silicide layer 3912. In one embodiment, the first metal layer 3914 is or includes a titanium layer. In one embodiment, as shown, the first metal layer 3914 is formed as a conformal metal layer, for example, conformal to the open trench of FIG. 39D.

[0405] Referring to FIG. 39F, in one embodiment, the first metal layer 3914 is recessed to form a U-shaped metal layer 3916 above each of the first source or drain region 3908, the second source or drain region 3910, the third source or drain region 3958, and the fourth source or drain region 3960.

[0406] 39G, in one embodiment, a second metal layer 3918 is formed on the U-shaped metal layer 3916 of the structure of FIG. 39F. In one embodiment, the second metal layer 3918 has a different composition than the U-shaped metal layer 3916.

[0407] 39H, in one embodiment, a third metal layer 3920 is formed on the second metal layer 3918 of the structure of FIG. 39G. In one embodiment, the third metal layer 3920 has the same composition as the U-shaped metal layer 3916.

[0408] Referring again to FIG. 39H, according to one embodiment of the present disclosure, an integrated circuit structure 3900 includes a P-type semiconductor device (PMOS) above a substrate. The P-type semiconductor device includes a first fin 3904, such as a first silicon fin. It should be understood that the first fin has a top (shown as 3904A) and sidewalls (e.g., into and out of the page). A first gate electrode 3902 includes a first gate dielectric layer above the top 3904A of the first fin 3904 and laterally adjacent to the sidewalls of the first fin 3904, and includes a first gate electrode above the first gate dielectric layer above the top 3904A of the first fin 3904 and laterally adjacent to the sidewalls of the first fin 3904. The first gate electrode 3902 has a first side 3902A and a second side 3902B opposite the first side 3902A.

[0409] A first semiconductor source or drain region 3908 and a second semiconductor source or drain region 3910 are adjacent to a first side 3902A and a second side 3902B, respectively, of the first gate electrode 3902. A first trench contact structure 3930 and a second trench contact structure 3932 are respectively above the first semiconductor source or drain region 3908 and the second semiconductor source or drain region 3910 adjacent to the first side 3902A and the second side 3902B of the first gate electrode 3902. A first metal silicide layer 3912 is sandwiched directly between the first trench contact structure 3930 and the first semiconductor source or drain region 3908 and between the second trench contact structure 3932 and the second trench contact structure 3910, respectively.

[0410] The integrated circuit structure 3900 includes an N-type semiconductor device (NMOS) above a substrate. The N-type semiconductor device includes a second fin 3954, such as a second silicon fin. It should be understood that the second fin has a top (shown as 3954A) and sidewalls (e.g., into and out of the page). The second gate electrode 3952 includes a second gate dielectric layer above the top 3954A of the second fin 3954 and laterally adjacent to the sidewalls of the second fin 3954, and includes a second gate electrode above the top 3954A of the second fin 3954 and laterally adjacent to the sidewalls of the second fin 3954. The second gate electrode 3952 has a first side 3952A and a second side 3952B opposite the first side 3952A.

[0411] A third semiconductor source or drain region 3958 and a fourth semiconductor source or drain region 3960 are adjacent a first side 3952A and a second side 3952B, respectively, of the second gate electrode 3952. A third trench contact structure 3970 and a fourth trench contact structure 3972 are above the third semiconductor source or drain region 3958 and the fourth semiconductor source or drain region 3960, which are adjacent the first side 3952A and the second side 3952B, respectively, of the second gate electrode 3952. A second metal silicide layer 3962 is sandwiched directly between the third trench contact structure 3970 and the third semiconductor source or drain region 3958 and directly between the fourth trench contact structure 3972 and the fourth semiconductor source or drain region 3960, respectively. In one embodiment, the first metal silicide layer 3912 includes at least one metal not included in the second metal silicide layer 3962.

[0412] In one embodiment, the second metal silicide layer 3962 includes titanium and silicon. The first metal silicide layer 3912 includes nickel, platinum, and silicon. In one embodiment, the first metal silicide layer 3912 further includes germanium. In one embodiment, the first metal silicide layer 3912 further includes titanium. The titanium is incorporated into the first metal silicide layer 3912, for example, during subsequent formation of the second metal silicide layer 3962 with the first metal layer 3914. In one such embodiment, a silicide layer already formed on the PMOS source or drain region is further modified by the annealing process used to form the silicide region on the NMOS source or drain region. This can result in a silicide layer on the PMOS source or drain region that has only a small percentage of all the silicide metals. However, in other embodiments, such a silicide layer already formed on the PMOS source or drain region is not altered, or is substantially not altered, by the annealing process used to form the silicide region on the NMOS source or drain region.

[0413] In one embodiment, the first semiconductor source or drain region 3908 and the second semiconductor source or drain region 3910 are first and second buried semiconductor source or drain regions comprising silicon and germanium. In one such embodiment, the third semiconductor source or drain region 3958 and the fourth semiconductor source or drain region 3960 are third and fourth buried semiconductor source or drain regions comprising silicon. In another embodiment, the third semiconductor source or drain region 3958 and the fourth semiconductor source or drain region 3960 are formed in the fin 3954 and are not buried epitaxial regions.

[0414] In one embodiment, the first trench contact structure 3930, the second trench contact structure 3932, the third trench contact structure 3970, and the fourth trench contact structure 3972 all include a U-shaped metal layer 3916 and a T-shaped metal layer 3918 over and above the entire U-shaped metal layer 3916. In one embodiment, the U-shaped metal layer 3916 comprises titanium, and the T-shaped metal layer 3918 comprises cobalt. In one embodiment, the first trench contact structure 3930, the second trench contact structure 3932, the third trench contact structure 3970, and the fourth trench contact structure 3972 all further include a third metal layer 3920 over the T-shaped metal layer 3918. In one embodiment, the third metal layer 3920 and the U-shaped metal layer 3916 have the same composition. In a particular embodiment, the third metal layer 3920 and the U-shaped metal layer comprise titanium, and the T-shaped metal layer 3918 comprises cobalt.

[0415] In another aspect, trench contact structures, for example for source or drain regions, are described. In one example, Figure 40A shows a cross-sectional view of an integrated circuit structure with trench contacts for an NMOS device according to one embodiment of the present disclosure. Figure 40B shows a cross-sectional view of an integrated circuit structure with trench contacts for a PMOS device according to another embodiment of the present disclosure.

[0416] Referring to FIG. 40A , an integrated circuit structure 4000 includes a fin 4002, such as a silicon fin. A gate dielectric layer 4004 is over the fin 4002. A gate electrode 4006 is over the gate dielectric layer 4004. In one embodiment, the gate electrode 4006 includes a conformal conductive layer 4008 and a conductive filling 4010. In one embodiment, a dielectric cap 4012 is over the gate electrode 4006 and over the gate dielectric layer 4004. The gate electrode has a first side 4006A and a second side 4006B opposite the first side 4006A. Dielectric spacers 4013 are along the sidewalls of the gate electrode 4006. In one embodiment, as shown, the gate dielectric layer 4004 further resides between a first dielectric spacer 4013 and a first side 4006A of the gate electrode 4006, and between a second dielectric spacer 4013 and a second side 4006B of the gate electrode 4006. In one embodiment, not shown, a thin oxide layer, such as a thermal or chemical silicon oxide or silicon dioxide layer, resides between the fin 4002 and the gate dielectric layer 4004.

[0417] The first semiconductor source or drain region 4014 and the second semiconductor source or drain region 4016 are adjacent to a first side 4006A and a second side 4006B, respectively, of the gate electrode 4006. In one embodiment, as shown, the first semiconductor source or drain region 4014 and the second semiconductor source or drain region 4016 are within the fin 4002. However, in another embodiment, the first semiconductor source or drain region 4014 and the second semiconductor source or drain region 4016 are buried epitaxial regions formed in a recess in the fin 4002.

[0418] The first trench contact structure 4018 and the second trench contact structure 4020 are respectively above the first semiconductor source or drain region 4014 and the second semiconductor source or drain region 4016 adjacent to the first side 4006A and the second side 4006B of the gate electrode 4006. Both the first trench contact structure 4018 and the second trench contact structure 4020 include a U-shaped metal layer 4022 and a T-shaped metal layer 4024 over and above the entire U-shaped metal layer 4022. In one embodiment, the U-shaped metal layer 4022 and the T-shaped metal layer 4024 have different compositions. In one such embodiment, the U-shaped metal layer 4022 includes titanium and the T-shaped metal layer 4024 includes cobalt. In one embodiment, both the first trench contact structure 4018 and the second trench contact structure 4020 further include a third metal layer 4026 on the T-shaped metal layer 4024. In one such embodiment, the third metal layer 4026 and the U-shaped metal layer 4022 have the same composition. In a particular embodiment, the third metal layer 4026 and the U-shaped metal layer 4022 comprise titanium, and the T-shaped metal layer 4024 comprises cobalt.

[0419] The first trench contact via 4028 is electrically connected to the first trench contact 4018. In a particular embodiment, the first trench contact via 4028 is on and coupled to the third metal layer 4026 of the first trench contact 4018. The first trench contact via 4028 is also over and in contact with a portion of one of the dielectric spacers 4013 and over and in contact with a portion of the dielectric cap 4012. The second trench contact via 4030 is electrically connected to the second trench contact 4020. In a particular embodiment, the second trench contact via 4030 is on and coupled to the third metal layer 4026 of the second trench contact 4020. The second trench contact via 4030 is also over and in contact with a portion of another dielectric spacer 4013 and over and in contact with another portion of the dielectric cap 4012.

[0420] In one embodiment, the metal suicide layer 4032 is sandwiched directly between the first trench contact structure 4018 and the first semiconductor source or drain region 4014, and between the second trench contact structure 4020 and the second semiconductor source or drain region 4016, respectively. In one embodiment, the metal suicide layer 4032 comprises titanium and silicon. In certain such embodiments, the first semiconductor source or drain region 4014 and the second semiconductor source or drain region 4016 are first N-type semiconductor source or drain regions and second N-type semiconductor source or drain regions.

[0421] Referring to FIG. 40B, an integrated circuit structure 4050 includes a fin 4052, such as a silicon fin. A gate dielectric layer 4054 is over the fin 4052. A gate electrode 4056 is over the gate dielectric layer 4054. In one embodiment, the gate electrode 4056 includes a conformal conductive layer 4058 and a conductive filling 4060. In one embodiment, a dielectric cap 4062 is over the gate electrode 4056 and over the gate dielectric layer 4054. The gate electrode has a first side 4056A and a second side 4056B opposite the first side 4056A. Dielectric spacers 4063 are along the sidewalls of the gate electrode 4056. In one embodiment, as shown, the gate dielectric layer 4054 further resides between a first dielectric spacer 4063 and a first side 4056A of the gate electrode 4056, and between a second dielectric spacer 4063 and a second side 4056B of the gate electrode 4056. In one embodiment, not shown, a thin oxide layer, such as a thermal or chemical silicon oxide or silicon dioxide layer, resides between the fin 4052 and the gate dielectric layer 4054.

[0422] First semiconductor source or drain region 4064 and second semiconductor source or drain region 4066 are adjacent to a first side 4056A and a second side 4056B, respectively, of gate electrode 4056. In one embodiment, as shown, first semiconductor source or drain region 4064 and second semiconductor source or drain region 4066 are buried epitaxial regions formed in recesses 4065 and 4067, respectively, of fin 4052. However, in another embodiment, first semiconductor source or drain region 4064 and second semiconductor source or drain region 4066 are within fin 4052.

[0423] The first trench contact structure 4068 and the second trench contact structure 4070 are respectively above the first semiconductor source or drain region 4064 and the second semiconductor source or drain region 4066 adjacent the first side 4056A and the second side 4056B of the gate electrode 4056. Both the first trench contact structure 4068 and the second trench contact structure 4070 include a U-shaped metal layer 4072 and a T-shaped metal layer 4074 over and above the entire U-shaped metal layer 4072. In one embodiment, the U-shaped metal layer 4072 and the T-shaped metal layer 4074 have different compositions. In one such embodiment, the U-shaped metal layer 4072 includes titanium and the T-shaped metal layer 4074 includes cobalt. In one embodiment, both the first trench contact structure 4068 and the second trench contact structure 4070 further include a third metal layer 4076 on the T-shaped metal layer 4074. In one such embodiment, the third metal layer 4076 and the U-shaped metal layer 4072 have the same composition. In a particular embodiment, the third metal layer 4076 and the U-shaped metal layer 4072 comprise titanium, and the T-shaped metal layer 4074 comprises cobalt.

[0424] The first trench contact via 4078 is electrically connected to the first trench contact 4068. In a particular embodiment, the first trench contact via 4078 is on and coupled to the third metal layer 4076 of the first trench contact 4068. The first trench contact via 4078 is also over and in contact with a portion of one of the dielectric spacers 4063 and over and in contact with a portion of the dielectric cap 4062. The second trench contact via 4080 is electrically connected to the second trench contact 4070. In a particular embodiment, the second trench contact via 4080 is on and coupled to the third metal layer 4076 of the second trench contact 4070. The second trench contact via 4080 is also over and in contact with a portion of another of the dielectric spacers 4063 and over and in contact with another portion of the dielectric cap 4062.

[0425] In one embodiment, the metal suicide layer 4082 is sandwiched directly between the first trench contact structure 4068 and the first semiconductor source or drain region 4064, and between the second trench contact structure 4070 and the second semiconductor source or drain region 4066, respectively. In one embodiment, the metal suicide layer 4082 comprises nickel, platinum, and silicon. In certain such embodiments, the first semiconductor source or drain region 4064 and the second semiconductor source or drain region 4066 are a first P-type semiconductor source or drain region and a second P-type semiconductor source or drain region. In one embodiment, the metal suicide layer 4082 further comprises germanium. In one embodiment, the metal suicide layer 4082 further comprises titanium.

[0426] One or more embodiments described herein relate to the use of metal chemical vapor deposition for wraparound semiconductor contacts. The embodiments may apply to or include one or more of chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), conductive contact fabrication, or thin films.

[0427] Certain embodiments may include fabricating titanium or similar metal layers using low temperature (e.g., below 500°C or in the range of 400-500°C) chemical vapor deposition of contact metals to provide conformal source or drain contacts. Implementing such conformal source or drain contacts may improve three-dimensional (3D) transistor complementary metal-oxide-semiconductor (CMOS) performance.

[0428] To provide context, metals for semiconductor contact layers can be deposited using sputtering. Sputtering is a line-of-sight process and can be poorly suited for 3D transistor fabrication. Known sputtering solutions result in weak or imperfect metal-semiconductor bonds at the device contact surface and oblique deposition incidence.

[0429] According to one or more embodiments of the present disclosure, a low-temperature chemical vapor deposition process is implemented for the fabrication of contact metals to provide three-dimensional conformality and maximize metal-semiconductor junction contact area. The resulting larger contact area can reduce junction resistance. Embodiments can include deposition on semiconductor surfaces having non-planar topography, where the topography of a region refers to the shape and features of the surface itself, and non-planar topography includes surface shapes and features, or portions of surface shapes and features, that are non-planar, i.e., surface shapes and features that are not entirely flat.

[0430] Embodiments described herein may include the fabrication of wraparound contact structures. In one such embodiment, the use of a pure metal conformally deposited on a transistor source / drain contact by chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or plasma-enhanced atomic layer deposition is described. Such conformal deposition can be used to increase the available area and reduce the resistance of the metal-semiconductor contact to improve transistor device performance. In one embodiment, the relatively low temperature deposition results in minimized junction resistance per unit area.

[0431] It should be appreciated that a variety of integrated circuit structures can be fabricated using integration schemes involving metal layer deposition processes as described herein. According to one embodiment of the present disclosure, a method of fabricating an integrated circuit structure includes providing a substrate in a chemical vapor deposition (CVD) chamber having an RF source, the substrate having features thereon. The method also includes reacting titanium tetrachloride (TiCl4) with hydrogen (H2) to form a titanium (Ti) layer over the features of the substrate.

[0432] In one embodiment, the titanium layer has a total atomic composition including 98% or more titanium and 0.5-2% chlorine. In an alternative embodiment, a similar process is used to produce high-purity metal layers of zirconium (Zr), hafnium (Hf), tantalum (Ta), niobium (NB), or vanadium (V). In one embodiment, the film thickness variation is relatively small, e.g., in one embodiment, greater than 50% on all coated surfaces, with a nominal of 70% or more (i.e., thickness variation of 30% or less). In one embodiment, the thickness is measurably greater on silicon (Si) or silicon germanium (SiGe) surfaces than on other surfaces because the Si or SiGe reacts during deposition, accelerating Ti incorporation. In one embodiment, the film composition includes approximately 0.5% (or less than 1%) Cl as an impurity and is essentially free of other observed impurities. In one embodiment, the deposition process allows for metal coverage on non-line-of-site surfaces, such as surfaces hidden by line-of-site sputter deposition. The embodiments described herein can be implemented to improve transistor device performance by reducing the external resistance of current driven through the source and drain contacts.

[0433] According to one embodiment of the present disclosure, the substrate features are source or drain contact trenches that expose semiconductor source or drain structures. The titanium layer (or other high-purity metal layer) is a conductive contact layer for the semiconductor source or drain structures. Exemplary embodiments of such implementations are described below with reference to Figures 41A, 41B, 42, 43A-43C, and 44.

[0434] FIG. 41A illustrates a cross-sectional view of a semiconductor device having conductive contacts on the source or drain regions according to one embodiment of the present disclosure.

[0435] 41A, a semiconductor structure 4100 includes a gate structure 4102 above a substrate 4104. The gate structure 4102 includes a gate dielectric layer 4102A, a work function layer 4102B, and a gate fill 4102C. A source region 4108 and a drain region 4110 are on opposite sides of the gate structure 4102. A source or drain contact 4112 is electrically connected to the source region 4108 and the drain region 4110 and is spaced apart from the gate structure 4102 by one or both of an interlayer dielectric layer 4114 or a gate dielectric spacer 4116. The source region 4108 and the drain region 4110 are regions of the substrate 4104.

[0436] In one embodiment, source or drain contact 4112 includes high-purity metal layer 4112A, as described above, and conductive trench fill material 4112B. In one embodiment, high-purity metal layer 4112A has a total atomic composition including 98% or more titanium. In one such embodiment, the total atomic composition of high-purity metal layer 4112A further includes 0.5-2% chlorine. In one embodiment, the thickness variation of high-purity metal layer 4112A is 30% or less. In one embodiment, conductive trench fill material 4112B is comprised of a conductive material such as, but not limited to, Cu, Al, W, or alloys thereof.

[0437] FIG. 41B illustrates a cross-sectional view of another semiconductor device having conductive contacts on raised source or drain regions in accordance with an embodiment of the present disclosure.

[0438] Referring to FIG. 41B , semiconductor structure 4150 includes a gate structure 4152 above a substrate 4154. Gate structure 4152 includes a gate dielectric layer 4152A, a work function layer 4152B, and a gate fill 4152C. A source region 4158 and a drain region 4160 are on opposite sides of the gate structure 4152. A source or drain contact 4162 is electrically connected to the source region 4158 and the drain region 4160 and is spaced apart from the gate structure 4152 by one or both of an interlayer dielectric layer 4164 or a gate dielectric spacer 4166. The source region 4158 and the drain region 4160 are epitaxial or buried material regions formed in etched-away areas of the substrate 4154. As shown, in one embodiment, the source region 4158 and the drain region 4160 are raised source and drain regions. In certain such embodiments, the raised source and drain regions are raised silicon source and drain regions or raised silicon germanium source and drain regions.

[0439] In one embodiment, source or drain contact 4162 includes high-purity metal layer 4162A, as described above, and conductive trench fill material 4162B. In one embodiment, high-purity metal layer 4162A has a total atomic composition including 98% or more titanium. In one such embodiment, the total atomic composition of high-purity metal layer 4162A further includes 0.5-2% chlorine. In one embodiment, the thickness variation of high-purity metal layer 4162A is 30% or less. In one embodiment, conductive trench fill material 4162B is comprised of a conductive material such as, but not limited to, Cu, Al, W, or alloys thereof.

[0440] Thus, in one embodiment, referring collectively to FIGS. 41A and 41B , an integrated circuit structure includes a feature (a source or drain contact trench exposing a semiconductor source or drain structure) having a surface. A high-purity metal layer 4112A or 4162A is on the surface of the source or drain contact trench. It is understood that the contact formation process may involve consumption of the exposed silicon or germanium or silicon-germanium material of the source or drain region. Such consumption may degrade device performance. In contrast, according to one embodiment of the present disclosure, the surface (4149 or 4199) of the semiconductor source (4108 or 4158) or drain (4110 or 4160) structure below the source or drain contact trench is not, or is substantially not, eroded or consumed. In one such embodiment, the lack of consumption or erosion results from low-temperature deposition of the high-purity metal contact layer.

[0441] FIG. 42 illustrates a plan view of multiple gate lines above a pair of semiconductor fins according to one embodiment of the present disclosure.

[0442] 42, a plurality of active gate lines 4204 are formed above a plurality of semiconductor fins 4200. Dummy gate lines 4206 are at the ends of the plurality of semiconductor fins 4200. Spaces 4208 between the gate lines 4204 and 4206 are at locations where trench contacts can be formed to make conductive contact to source or drain regions, such as source or drain regions 4251, 4252, 4253, and 4254.

[0443] 43A-43C show cross-sectional views taken along axis aa' of FIG. 42 for various steps in a method of fabricating an integrated circuit structure according to one embodiment of the present disclosure.

[0444] Referring to FIG. 43A , a plurality of active gate lines 4304 are formed above a semiconductor fin 4302 formed above a substrate 4300. Dummy gate lines 4306 are at the ends of the semiconductor fin 4302. Dielectric layers 4310 are between the active gate lines 4304, between the dummy gate lines 4306 and the active gate lines 4304, and outside the dummy gate lines 4306. Buried source or drain structures 4308 are in the semiconductor fin 4302 between the active gate lines 4304 and between the dummy gate lines 4306 and the active gate lines 4304. The active gate lines 4304 include a gate dielectric layer 4312, a work function gate electrode portion 4314, a filler gate electrode portion 4316, and a dielectric capping layer 4318. Dielectric spacers 4320 are along the sidewalls of the active gate lines 4304 and the dummy gate lines 4306.

[0445] 43B, portions of dielectric layer 4310 between the active gate lines 4304 and between dummy gate lines 4306 and active gate lines 4304 are removed to provide openings 4330 where trench contacts are to be formed. Removing portions of dielectric layer 4310 between the active gate lines 4304 and between dummy gate lines 4306 and active gate lines 4304 may result in erosion of buried source or drain structures 4308, thereby providing eroded buried source or drain structures 4332, which may have an upper saddle-shaped topography, as illustrated in FIG.

[0446] 43C, trench contacts 4334 are formed in the openings 4330 between the active gate lines 4304 and between the dummy gate lines 4306 and the active gate lines 4304. Each of the trench contacts 4334 may include a metal contact layer 4336 and a conductive fill material 4338.

[0447] FIG. 44 illustrates a cross-sectional view of an integrated circuit structure taken along axis bb' of FIG. 42, according to one embodiment of the present disclosure.

[0448] Referring to FIG. 44 , fin 4402 is shown above substrate 4404. The bottom of fin 4402 is surrounded by trench isolation material 4404. The top of fin 4402 has been removed to allow for the growth of buried source and drain structures 4406. Trench contacts 4408 are formed in openings in dielectric layer 4410, which expose buried source and drain structures 4406. The trench contacts include a metal contact layer 4412 and a conductive fill material 4414. It should be understood that according to one embodiment, metal contact layer 4412 extends to the top of trench contact 4408 as illustrated in FIG. 44 . However, in another embodiment, metal contact layer 4412 does not extend to the top of trench contact 4408 but is somewhat recessed into trench contact 4408, for example, similar to the illustration of metal contact layer 4336 in FIG. 43C .

[0449] 42, 43A-43C, and 44 collectively, according to one embodiment of the present disclosure, an integrated circuit structure includes semiconductor fins (4200, 4302, 4402) above a substrate (4300, 4400). The semiconductor fins (4200, 4302, 4402) have tops and sidewalls. A gate electrode (4204, 4304) is above the tops of the semiconductor fins (4200, 4302, 4402) and adjacent to a portion of the sidewalls. The gate electrode (4204, 4304) defines a channel region in the semiconductor fin (4200, 4302, 4402). The first semiconductor source or drain structure (4251, 4332, 4406) is at a first end of the channel region on a first side of the gate electrode (4204, 4304), the first semiconductor source or drain structure (4251, 4332, 4406) having a non-planar topography. The second semiconductor source or drain structure (4252, 4332, 4406) is at a second end of the channel region on a second side of the gate electrode (4204, 4304), the second end facing the first end and the second side facing the first side. The second semiconductor source or drain structure (4252, 4332, 4406) has a non-planar topography. The metal contact material (4336, 4412) is immediately above the first semiconductor source or drain structure (4251, 4332, 4406) and immediately above the second semiconductor source or drain structure (4252, 4332, 4406). The metal contact material (4336, 4412) is conformal to the non-planar topography of the first semiconductor source or drain structure (4251, 4332, 4406) and is conformal to the non-planar topography of the second semiconductor source or drain structure (4252, 4332, 4406).

[0450] In one embodiment, the metal contact material (4336, 4412) has a total atomic composition containing 95% or more of a single metal species. In one such embodiment, the metal contact material (4336, 4412) has a total atomic composition containing 98% or more of titanium. In a particular such embodiment, the total atomic composition of the metal contact material (4336, 4412) further includes 0.5-2% chlorine. In one embodiment, the thickness of the metal contact material (4336, 4412) varies by 30% or less along the non-planar topography of the first semiconductor source or drain structure (4251, 4332, 4406) and along the non-planar topography of the second semiconductor source or drain structure (4252, 4332, 4406).

[0451] In one embodiment, the non-planar topography of the first semiconductor source or drain structure (4251, 4332, 4406) and the non-planar topography of the second semiconductor source or drain structure (4252, 4332, 4406) both include a raised central portion and lower side portions, for example, as illustrated in Figure 44. In one embodiment, the non-planar topography of the first semiconductor source or drain structure (4251, 4332, 4406) and the non-planar topography of the second semiconductor source or drain structure (4252, 4332, 4406) both include a saddle-shaped portion, for example, as illustrated in Figure 43C.

[0452] In one embodiment, the first semiconductor source or drain structure (4251, 4332, 4406) and the second semiconductor source or drain structure (4252, 4332, 4406) both comprise silicon, hi one embodiment, the first semiconductor source or drain structure (4251, 4332, 4406) and the second semiconductor source or drain structure (4252, 4332, 4406) both further comprise germanium, for example, in the form of silicon germanium.

[0453] In one embodiment, the metal contact material (4336, 4412) immediately above the first semiconductor source or drain structures (4251, 4332, 4406) also extends along the sidewalls of trenches in the dielectric layer (4320, 4410) above the first semiconductor source or drain structures (4251, 4332, 4406), the trenches exposing portions of the first semiconductor source or drain structures (4251, 4332, 4406). In one such embodiment, the thickness of the metal contact material (4336) along the sidewalls of the trench decreases from 4336A in the first semiconductor source or drain structure (4332) to a position (4336B) above the first semiconductor source or drain structure (4332), an example of which is shown in Figure 43C. In one embodiment, the conductive fill material (4338, 4414) is over the metal contact material (4336, 4412) in the trench, as shown in Figures 43C and 44.

[0454] In one embodiment, the integrated circuit structure further includes a second semiconductor fin (e.g., top fin 4200, 4302, 4402 of FIG. 42) having a top and sidewalls. A gate electrode (4204, 4304) further overlies the top of the second semiconductor fin and abuts a portion of a sidewall thereof, the gate electrode defining a channel region in the second semiconductor fin. A third semiconductor source or drain structure (4253, 4332, 4406) is at a first end of the channel region of the second semiconductor fin on a first side of the gate electrode (4204, 4304), the third semiconductor source or drain structure having a non-planar topography. A fourth semiconductor source or drain structure (4254, 4332, 4406) is at a second end of the channel region of the second semiconductor fin on a second side of the gate electrode (4204, 4304), the second end facing the first end, and the fourth semiconductor source or drain structure (4254, 4332, 4406) has a non-planar topography. Metal contact material (4336, 4412) is immediately on top of the third semiconductor source or drain structure (4253, 4332, 4406) and is immediately on top of the fourth semiconductor source or drain structure (4254, 4332, 4406), and the metal contact material (4336, 4412) is conformal to the non-planar topography of the third semiconductor source or drain structure (4253, 4332, 4406) and is conformal to the non-planar topography of the fourth semiconductor source or drain structure (4254, 4332, 4406). In one embodiment, the metal contact material (4336, 4412) is continuous between the first semiconductor source or drain structure (4251, 4332, left side 4406) and the third semiconductor source or drain structure (4253, 4332, right side 4406), and is continuous between the second semiconductor source or drain structure (4252) and the fourth semiconductor source or drain structure (4254).

[0455] In another aspect, a hard mask material can be used to protect (inhibit erosion of) and retain over the dielectric material at trench line locations where the conductive trench contact is interrupted (e.g., contact plug locations). For example, Figures 45A and 45B show a plan view and corresponding cross-sectional view, respectively, of an integrated circuit structure including a trench contact plug having a hard mask material thereon, according to one embodiment of the present disclosure.

[0456] 45A and 45B, in one embodiment, an integrated circuit structure 4500 includes a fin 4502A, such as a silicon fin. A plurality of gate structures 4506 are above the fin 4502A. Each of the gate structures 4506 is oriented along a direction 4508 perpendicular to the fin 4502A and includes a pair of dielectric sidewall spacers 4510. A trench contact structure 4512 is above the fin 4502A and is sandwiched directly between the dielectric sidewall spacers 4510 of a first pair 4506A / 4506B of the gate structures 4506. A contact plug 4514B is above the fin 4502A and is sandwiched directly between the dielectric sidewall spacers 4510 of a second pair 4506B / 4506C of the gate structures 4506. The contact plug 4514B includes a lower dielectric material 4516 and an upper hard mask material 4518.

[0457] In one embodiment, the lower dielectric material 4516 of the contact plug 4516B includes silicon and oxygen, such as, for example, a silicon oxide or silicon dioxide material, and the upper hard mask material 4518 of the contact plug 4516B includes silicon and nitrogen, such as, for example, a silicon nitride, silicon-rich nitride, or silicon-poor nitride material.

[0458] In one embodiment, trench contact structure 4512 includes a lower conductive structure 4520 and a dielectric cap 4522 over lower conductive structure 4520. In one embodiment, dielectric cap 4522 of trench contact structure 4512 has an upper surface that is coplanar with an upper surface of upper hard mask material 4518 of contact plug 4514B, as shown.

[0459] In one embodiment, each of the plurality of gate structures 4506 includes a gate electrode 4524 on a gate dielectric layer 4526. A dielectric cap 4528 overlies the gate electrode 4524. In one embodiment, the dielectric cap 4528 of each of the plurality of gate structures 4506 has an upper surface that is coplanar with an upper surface of the upper hard mask material 4518 of the contact plug 4514B, as shown. In one embodiment, although not shown, a thin oxide layer, such as a thermal or chemical silicon oxide or silicon dioxide layer, is between the fin 4502A and the gate dielectric layer 4526.

[0460] Referring again to Figures 45A and 45B, in one embodiment, an integrated circuit structure 4500 includes a plurality of fins 4502, such as a plurality of silicon fins. Each of the fins 4502 extends along a first direction 4504. A plurality of gate structures 4506 are above the fins 4502. Each of the gate structures 4506 extends along a second direction 4508 that is orthogonal to the first direction 4504. Each of the gate structures 4506 has a pair of dielectric sidewall spacers 4510. A trench contact structure 4512 is above a first fin 4502A of the fins 4502 and is directly sandwiched between the dielectric sidewall spacers 4510 of the pair of gate structures 4506. A contact plug 4514A is above a second fin 4502B of the fins 4502 and is directly sandwiched between the dielectric sidewall spacers 4510 of the pair of gate structures 4506. Similar to the cross-sectional view of contact plug 4514B, contact plug 4514A includes a lower dielectric material 4516 and an upper hard mask material 4518.

[0461] In one embodiment, the lower dielectric material 4516 of the contact plug 4516A includes silicon and oxygen, such as, for example, a silicon oxide or silicon dioxide material, and the upper hard mask material 4518 of the contact plug 4516A includes silicon and nitrogen, such as, for example, a silicon nitride, silicon-rich nitride, or silicon-poor nitride material.

[0462] In one embodiment, trench contact structure 4512 includes a lower conductive structure 4520 and a dielectric cap 4522 over lower conductive structure 4520. In one embodiment, dielectric cap 4522 of trench contact structure 4512 has an upper surface that is coplanar with an upper surface of upper hard mask material 4518 of contact plug 4514A or 4514B, as shown.

[0463] In one embodiment, each of the plurality of gate structures 4506 includes a gate electrode 4524 on a gate dielectric layer 4526. A dielectric cap 4528 overlies the gate electrode 4524. In one embodiment, the dielectric cap 4528 of each of the plurality of gate structures 4506 has an upper surface that is coplanar with the upper surface of the upper hard mask material 4518 of contact plug 4514A or 4514B, as shown. In one embodiment, although not shown, a thin oxide layer, such as a thermal or chemical silicon oxide or silicon dioxide layer, is between fin 4502A and gate dielectric layer 4526.

[0464] One or more embodiments of the present disclosure relate to a gate-aligned contact process. Such a process can be implemented to form contact structures for the fabrication of semiconductor structures, such as integrated circuits. In one embodiment, a contact pattern is formed to align with an existing gate pattern. In contrast, other approaches typically involve additional lithography processes with critical alignment of the lithographic contact pattern to the existing gate pattern, combined with selective contact etching. For example, another process can include patterning a poly(gate) grid along with patterning of separate contacts and contact plugs.

[0465] According to one or more embodiments described herein, a method of contact formation involves forming a contact pattern that is essentially perfectly aligned to an existing gate pattern, while eliminating the use of lithography steps with very tight alignment tolerances. In one such embodiment, this approach inherently enables the use of highly selective wet etching (e.g., relative to dry etching or plasma etching) to create the contact openings. In one embodiment, the contact pattern is formed by utilizing the existing gate pattern in combination with a contact plug lithography step. In one such embodiment, this approach enables the elimination of the need for an otherwise significant lithography step to create the contact pattern, as used in other approaches. In one embodiment, the trench contact grid is formed between poly (gate) lines rather than being separately patterned. For example, in one such embodiment, the trench contact grid is formed after gate grid patterning but before the gate grid cut.

[0466] 46A-46D show cross-sectional views illustrating various steps in a method of fabricating an integrated circuit structure including trench contact plugs having hard mask material thereon in accordance with one embodiment of the present disclosure.

[0467] Referring to FIG. 46A , a method of fabricating an integrated circuit structure includes forming a plurality of fins, where each of the plurality of fins 4602 is aligned along a first direction 4604. Each of the plurality of fins 4602 may include a diffusion region 4606. A plurality of gate structures 4608 are formed above the plurality of fins. Each of the plurality of gate structures 4508 is aligned along a second direction 4610 that is orthogonal to the first direction 4604 (e.g., direction 4610 is into and out of the page). A sacrificial material structure 4612 is formed between a first pair of gate structures 4608. A contact plug 4614 is between a second pair of gate structures 4608. The contact plug includes an underlying dielectric material 4616. A hard mask material 4618 is on the underlying dielectric material 4616.

[0468] In one embodiment, gate structure 4608 includes a sacrificial or dummy gate stack and a dielectric spacer 4609. The sacrificial or dummy gate stack may be composed of polysilicon or silicon nitride pillars or some other sacrificial material, which may be referred to as a gate dummy material.

[0469] Referring to FIG. 46B, the sacrificial material structure 4612 is removed from the structure of FIG. 46A, forming an opening 4620 between the first pair of gate structures 4608.

[0470] 46C, a trench contact structure 4622 is formed in the opening 4620 between the first pair of gate structures 4608. Additionally, in one embodiment, the hard mask 4618 of FIGS. 46A and 46B is planarized as part of forming the trench contact structure 4622. The final finished contact plug 4614′ includes a lower dielectric material 4616 and an upper hard mask material 4624 formed from the hard mask material 4618.

[0471] In one embodiment, the lower dielectric material 4616 of each of the contact plugs 4614' comprises silicon and oxygen, and the upper hard mask material 4624 of each of the contact plugs 4614' comprises silicon and nitrogen. In one embodiment, each of the trench contact structures 4622 includes a lower conductive structure 4626 and a dielectric cap 4628 over the lower conductive structure 4626. In one embodiment, the dielectric cap 4628 of the trench contact structure 4622 has an upper surface that is coplanar with the upper surface of the upper hard mask material 4624 of the contact plugs 4614'.

[0472] Referring to Figure 46D, the sacrificial or dummy gate stack of gate structure 4608 is replaced in a replacement gate process scheme. In such a scheme, the dummy gate material, such as polysilicon or silicon nitride pillar material, is removed and replaced with a permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process, rather than being carried over from previous processing.

[0473] Thus, permanent gate structure 4630 includes permanent gate dielectric layer 4632 and permanent gate electrode layer or stack 4634. Further, in one embodiment, the top portion of permanent gate structure 4630 is removed, for example by an etching process, and replaced with dielectric cap 4636. In one embodiment, dielectric cap 4636 of each permanent gate structure 4630 has a top surface that is coplanar with the top surface of upper hard mask material 4624 of contact plug 4614'.

[0474] 46A-46D, in one embodiment, the replacement gate process is performed after the formation of trench contact structure 4622 as shown. However, according to other embodiments, the replacement gate process is performed before the formation of trench contact structure 4622.

[0475] In another aspect, contact-over-active-gate (COAG) structures and processes are described. One or more embodiments of the present disclosure relate to a semiconductor structure or device having one or more gate contact structures (e.g., gate contact vias) disposed above an active portion of a gate electrode of the semiconductor structure or device. One or more embodiments of the present disclosure relate to a method of fabricating a semiconductor structure or device having one or more gate contact structures formed above an active portion of a gate electrode of the semiconductor structure or device. The approaches described herein can be used to reduce standard cell area by enabling gate contact formation above the active gate region. In one or more embodiments, the gate contact structures fabricated to contact the gate electrode are self-aligned via structures.

[0476] In technologies with somewhat relaxed space and layout constraints compared to those of current generations, contact to the gate structure may be made by contacting a portion of the gate electrode that is disposed above the isolation region. As an example, Figure 47A shows a plan view of a semiconductor device having a gate contact disposed above an inactive portion of the gate electrode.

[0477] Referring to FIG. 47A, semiconductor structure or device 4700A includes a diffusion or active region 4704 disposed in a substrate 4702 or within an isolation region 4706. One or more gate lines (also known as poly lines), such as gate lines 4708A, 4708B, and 4708C, are disposed over the diffusion or active region 4704 as well as over portions of the isolation region 4706. Source or drain contacts (also known as trench contacts), such as contacts 4710A and 4710B, are disposed over the source and drain regions of semiconductor structure or device 4700A. Trench contact vias 4712A and 4712B provide contact to trench contacts 4710A and 4710B, respectively. An isolation gate contact 4714 and an overlying gate contact via 4716 provide contact to gate line 4708B. In contrast to source or drain trench contacts 4710A or 4710B, gate contact 4714 is, from a plan view perspective, positioned above isolation region 4706 but not above diffusion or active region 4704. Furthermore, neither gate contact 4714 nor gate contact via 4716 is positioned between source or drain trench contacts 4710A and 4710B.

[0478] Figure 47B shows a cross-sectional view of a non-planar semiconductor device having a gate contact disposed over an inactive portion of a gate electrode. Referring to Figure 47B, a semiconductor structure or device 4700B (e.g., a non-planar version of device 4700A of Figure 47A) includes a non-planar diffusion or active region 4704C (e.g., a fin structure) formed from a substrate 4702 within an isolation region 4706. A gate line 4708B is disposed over the non-planar diffusion or active region 4704B as well as over a portion of the isolation region 4706. As shown, gate line 4708B includes a gate electrode 4750 and a gate dielectric layer 4752 along with a dielectric cap layer 4754. A gate contact 4714 and an overlying gate contact via 4716 are also seen from this perspective, along with an overlying metal interconnect 4760, all of which are disposed within an interlayer dielectric stack or layer 4770. Also, from the perspective of Figure 47B, gate contact 4714 is located above isolation region 4706, but not above non-planar diffusion or active region 4704B.

[0479] Referring again to Figures 47A and 47B, semiconductor structures or devices 4700A and 4700B, respectively, have configurations in which the gate contact is placed above the isolation region. Such configurations waste layout space. However, placing the gate contact above the active region requires very tight alignment tolerances or the gate dimensions must be increased to provide sufficient space for the gate contact to land. Furthermore, contacting a gate above a diffusion region has traditionally been avoided due to the risk of drilling through other gate material (e.g., polysilicon) to contact the underlying active region. One or more embodiments described herein address the above problems by providing a feasible approach to fabricating a contact structure, and resulting structure, that contacts a portion of a gate electrode formed above a diffusion or active region.

[0480] 48A illustrates a plan view of a semiconductor device having a gate contact via disposed over an active portion of a gate electrode, according to one embodiment of the present disclosure. Referring to FIG. 48A, semiconductor structure or device 4800A includes a diffusion or active region 4804 disposed in a substrate 4802 and within an isolation region 4806. One or more gate lines, such as gate lines 4808A, 4808B, and 4808C, are disposed over the diffusion or active region 4804 as well as over portions of isolation region 4806. Source or drain trench contacts, such as trench contacts 4810A and 4810B, are disposed over the source and drain regions of semiconductor structure or device 4800A. Trench contact vias 4812A and 4812B provide contact to trench contacts 4810A and 4810B, respectively. Gate contact via 4816, without an intervening isolation gate contact layer, provides contact to gate line 4808B. In contrast to Figure 47A, gate contact 4816 is located, from a plan view perspective, above diffusion or active region 4804 and between source or drain contacts 4810A and 4810B.

[0481] Figure 48B shows a cross-sectional view of a non-planar semiconductor device having a gate contact via disposed over an active portion of a gate electrode according to one embodiment of the present disclosure. Referring to Figure 48B, a semiconductor structure or device 4800B (e.g., a non-planar version of device 4800A of Figure 48A) includes a non-planar diffusion or active region 4804B (e.g., a fin structure) formed from a substrate 4802 and located within an isolation region 4806. A gate line 4808B is disposed over the non-planar diffusion or active region 4804B as well as over a portion of the isolation region 4806. As shown, the gate line 4808B includes a gate electrode 4850 and a gate dielectric layer 4852, along with a dielectric cap layer 4854. A gate contact via 4816 is also seen from this perspective, along with an overlying metal interconnect 4860, both of which are disposed within an interlayer dielectric stack or layer 4870. Also, as seen from the perspective of Figure 48B, gate contact via 4816 is located above non-planar diffusion or active area 4804B.

[0482] Thus, referring again to FIGS. 48A and 48B , in one embodiment, trench contact vias 4812A, 4812B and gate contact via 4816 are formed in the same layer and are essentially coplanar. Compared to FIGS. 47A and 47B , contact to the gate lines would otherwise include an additional gate contact layer (e.g., which may extend perpendicular to the corresponding gate line). However, in the structures described in connection with FIGS. 48A and 48B , fabrication of structures 4800A and 4800B, respectively, allows for landing contacts directly from the metal interconnect layer on the active gate portion without shorting to adjacent source-drain regions. In one embodiment, such a configuration provides a significant reduction in area in the circuit layout by eliminating the need to extend a separate transistor gate to form a reliable contact. In one embodiment, as used throughout, reference to the active portion of the gate refers to the portion of the gate line or structure that is disposed (from a plan view perspective) above the active or diffusion region of the underlying substrate. In one embodiment, reference to a non-active portion of a gate refers to a portion of a gate line or structure that is disposed (from a plan view perspective) above an isolation region of the underlying substrate.

[0483] In one embodiment, semiconductor structure or device 4800 is a non-planar device, such as, but not limited to, a FinFET or a Tri-Gate device. In such an embodiment, the channel region of the corresponding semiconductor is comprised of or formed in a three-dimensional object. In one such embodiment, the gate electrode stacks of gate lines 4808A-4808C surround at least a top surface of the three-dimensional object and a pair of its sidewalls. In another embodiment, at least the channel region is fabricated as a separate three-dimensional object, such as in a gate-all-around device. In one such embodiment, each of the gate electrode stacks of gate lines 4808A-4808C completely surrounds the channel region.

[0484] More generally, one or more embodiments relate to approaches for landing gate contact vias directly above active transistor gates, and structures formed therefrom. Such an approach may eliminate the need for extending a separate gate line for contact purposes. Such an approach may also eliminate the need for a separate gate contact (GCN) layer to conduct signals from the gate line or structure. In one embodiment, removal of the upper feature is achieved by recessing contact metal into the trench contact (TCN) and introducing an additional dielectric material (e.g., TILA) in the process flow. The additional dielectric material is included as a trench contact dielectric cap layer with different etch characteristics than the gate dielectric material cap layer (e.g., GILA) already used for trench contact alignment in a gate alignment contact process (GAP) processing scheme.

[0485] As an exemplary fabrication scheme, Figures 49A-49D show cross-sectional views illustrating various steps in a method for fabricating a semiconductor structure having a gate contact structure disposed above an active portion of the gate, according to one embodiment of the present disclosure.

[0486] Referring to FIG. 49A, a semiconductor structure 4900 is provided following trench contact (TCN) formation. It should be understood that the particular configuration of structure 4900 is used for illustrative purposes only, and that a variety of possible layouts can benefit from the embodiments of the present disclosure described herein. Semiconductor structure 4900 includes one or more gate stack structures, such as gate stack structures 4908A-4908E, disposed above a substrate 4902. The gate stack structures may include a gate dielectric layer and a gate electrode. Trench contacts, such as trench contacts 4910A-4910C, e.g., contacts to diffusion regions of substrate 4902, are also included in structure 4900 and are spaced from gate stack structures 4908A-4908E by dielectric spacers 4920. An insulating cap layer 4922 may be disposed on gate stack structures 4908A-4908E (e.g., GILA), as also shown in FIG. 49A. As also shown in FIG. 49A, contact obstruction regions or "contact plugs," such as region 4923 fabricated from interlevel dielectric material, can be included in areas where contact formation is to be inhibited.

[0487] In one embodiment, providing structure 4900 involves forming a contact pattern that is essentially perfectly aligned with an e...

Claims

1. a nanowire comprising a semiconductor material, the nanowire having a channel region; a gate electrode surrounding the channel region of the nanowire, the gate electrode having a first side and a second side opposite the first side; a first semiconductor source or drain region adjacent to the first side of the gate electrode, and a second semiconductor source or drain region adjacent to the second side of the gate electrode; a trench contact structure over one of the first semiconductor source or drain region and the second semiconductor source or drain region, the trench contact structure having a T-shaped metal layer overlying a U-shaped metal layer, the U-shaped metal layer having a lateral width; a dielectric layer between the gate electrode and the trench contact structure, the dielectric layer having a top surface; an insulating cap layer over the T-shaped metal layer of the trench contact structure, the insulating cap layer having a lateral width greater than a lateral width of the U-shaped metal layer, the insulating cap layer having a top surface that is coplanar with a top surface of the dielectric layer; 1. An integrated circuit structure comprising:

2. The integrated circuit structure of claim 1 , wherein the U-shaped metal layer and the T-shaped metal layer are of different composition.

3. 3. The integrated circuit structure of claim 1, wherein said U-shaped metal layer comprises titanium.

4. 4. The integrated circuit structure of claim 1, wherein the T-shaped metal layer comprises cobalt.

5. 5. The integrated circuit structure of claim 1, wherein the trench contact structure further comprises a third metal layer above the T-shaped metal layer and below the insulating cap layer.

6. 6. The integrated circuit structure of claim 5, wherein said third metal layer and said U-shaped metal layer have the same composition.

7. 7. The integrated circuit structure of claim 1 further comprising a metal silicide layer sandwiched between the trench contact structure and the one of the first and second semiconductor source or drain regions.

8. 8. The integrated circuit structure of claim 7, wherein said metal suicide layer comprises titanium and silicon.

9. 9. The integrated circuit structure of claim 8, wherein said first semiconductor source or drain region is a first N-type semiconductor source or drain region and said second semiconductor source or drain region is a second N-type semiconductor source or drain region.

10. 8. The integrated circuit structure of claim 7, wherein said metal suicide layer comprises nickel, platinum and silicon.

11. a nanowire comprising a semiconductor material, the nanowire having a channel region; a gate electrode surrounding the channel region of the nanowire, the gate electrode having a first side and a second side opposite the first side; a first semiconductor source or drain region adjacent to the first side of the gate electrode, and a second semiconductor source or drain region adjacent to the second side of the gate electrode; a trench contact structure over one of the first semiconductor source or drain region and the second semiconductor source or drain region, the trench contact structure having a U-shaped metal layer and a T-shaped metal layer over and above the entire U-shaped metal layer; a dielectric layer between the gate electrode and the trench contact structure, the dielectric layer having an upper surface above an upper surface of the T-shaped metal layer of the trench contact structure; 1. An integrated circuit structure comprising:

12. The integrated circuit structure of claim 11 , wherein the U-shaped metal layer and the T-shaped metal layer are of different composition.

13. 13. The integrated circuit structure of claim 11 or 12, wherein the U-shaped metal layer comprises titanium.

14. 14. The integrated circuit structure of claim 11, wherein the T-shaped metal layer comprises cobalt.

15. 15. The integrated circuit structure of claim 11, wherein the trench contact structure further comprises a third metal layer over the T-shaped metal layer.

16. 16. The integrated circuit structure of claim 15, wherein the third metal layer and the U-shaped metal layer have the same composition.

17. 17. The integrated circuit structure of claim 11, further comprising a metal silicide layer sandwiched between the trench contact structure and the one of the first and second semiconductor source or drain regions.

18. 20. The integrated circuit structure of claim 17, wherein said metal suicide layer comprises titanium and silicon.

19. 20. The integrated circuit structure of claim 18, wherein said first semiconductor source or drain region is a first N-type semiconductor source or drain region and said second semiconductor source or drain region is a second N-type semiconductor source or drain region.

20. 20. The integrated circuit structure of claim 17, wherein said metal suicide layer comprises nickel, platinum and silicon.

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