Drive circuit

Abstract

To provide an upper arm drive circuit that can drive and control CGs of CG-IGBTs of upper arm side upper arm output elements and can make a power conversion device smaller and more efficient, and a control method for the same, in the power conversion device having a bridge circuit composed of a lower arm.SOLUTION: In a drive circuit for a power conversion device, a gate driver 25 for driving a collector gate CG of a CG-IGBT 28 as an upper arm output element has a charge accumulation circuit 33 including a capacitor 35 and a reverse current prevention element 34, and a charge charge / discharge control circuit 32 including a switching element 36 and a resistor 37. One terminal of the capacitor 35 is connected to a main power supply 31 of the power conversion device via the reverse current prevention element 34 and is connected to the collector gate CG of the CG-IGBT 28. The other terminal of the capacitor 35 is connected to a reference potential of the power conversion device via the switching element 36, and is connected to the main power supply 31 of the power conversion device via the resistor 37.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a drive circuit for a power conversion device. [Background technology]

[0002] With the rise in awareness of environmental conservation worldwide, the demand for energy conservation has increased, and power conversion devices are being widely adopted in various fields. For power conversion devices installed in the drive systems of railway vehicles, air conditioners, etc., important issues include not only high performance and efficiency, but also miniaturization, weight reduction, and high reliability.

[0003] Insulated gate bipolar transistors (IGBTs) are used, for example, in inverter circuits with inductive loads. A typical IGBT has a collector terminal and an emitter terminal that block voltage or conduct current, and a gate terminal that controls the blocking and conducting states of the IGBT. In order to reduce the resistance when the IGBT is conducting, it is effective to inject carriers into the drift layer at a high density to promote conductivity modulation.

[0004] On the other hand, when high density carriers are injected into the drift layer, the speed of the turn-off switching operation of the IGBT, which transitions from the conductive state to the cut-off state, slows down, and the turn-off loss increases, so there is a trade-off between reducing the conductive loss and the turn-off loss. In recent years, as one means for improving this trade-off relationship, there is the collector gate controlled IGBT (CG-IGBT), which adds an N-type MOSFET structure to the collector section and further has a collector gate terminal (CG) for controlling the N-type MOSFET in the collector section, and Patent Document 1 discloses a drive circuit that drives and controls the CG of the CG-IGBT.

[0005] Patent Document 1 discloses an example of a drive circuit for controlling the CG of a CG-IGBT, which generates a power supply voltage for driving the CG using a bootstrap circuit. Patent Document 2 discloses a drive circuit for controlling the drive of a conventional emitter-side gate of an upper-arm output element, and discloses a configuration in which the emitter-side gate of the upper-arm output element is charged from the main power supply of a power conversion device.

[0006] In this specification, the CG-IGBT is described as a concept indicating an IGBT having an emitter, a collector, an emitter gate (conventional gate) which is a gate on the emitter side, and a collector gate (CG) which is a gate on the collector side. Also, the description will be made assuming that a collector-gate-controlled reverse conducting IGBT (CG-RC-IGBT) is included as one type of CG-IGBT. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2023-35478 A [Patent Document 2] Patent Publication No. 2022-24572 Summary of the Invention [Problem to be solved by the invention]

[0008] Since the collector potential of the CG-IGBT of the upper arm output element on the upper arm side of the power converter is equal to the potential of the main power supply of the power converter, when turning on the CG, the potential of the CG needs to be higher than the main power supply of the power converter. Therefore, there is a problem that the drive control of the CG of the CG-IGBT of the upper arm output element on the upper arm side of the power converter cannot be applied to the power generation using the bootstrap circuit disclosed in Patent Document 1 or the method of charging directly from the main power supply of the power converter disclosed in Patent Document 2.

[0009] Therefore, an object of the present invention is to provide an upper arm drive circuit and a control method thereof that can drive and control the CG of the CG-IGBT of the upper arm output element on the upper arm side in a power conversion device having a bridge circuit composed of upper and lower arms, and that can make the power conversion device smaller and more efficient. [Means for solving the problem]

[0010] A drive circuit for a power conversion device according to one embodiment of the present invention is characterized in that a gate driver for driving a collector gate of a CG-IGBT, which is an upper arm output element, has a charge storage circuit having a capacitor and a backflow prevention element, and a charge charge / discharge control circuit having a switching element and a resistor, one terminal of the capacitor being connected to a main power supply of the power conversion device via the backflow prevention element and connected to the collector gate of the CG-IGBT, which is the upper arm output element, and the other terminal of the capacitor being connected to a reference potential of the power conversion device via a switching element and connected to the main power supply of the power conversion device via a resistor. Effect of the Invention

[0011] According to the present invention, in a power conversion device having a bridge circuit composed of upper and lower arms, it is possible to realize an upper arm drive circuit and a control method thereof that can drive and control the CG of the CG-IGBT of the upper arm output element on the upper arm side, thereby making the power conversion device smaller and more efficient. [Brief description of the drawings]

[0012] [Figure 1] 1 is a partial cross-sectional view showing a part of a CG-IGBT according to a first embodiment of the present invention. [Diagram 2] 1A is an equivalent circuit diagram of a CG-(RC-)IGBT according to a first embodiment of the present invention; FIG. 1B is a symbol of a CG-(RC-)IGBT; [Diagram 3] 2 is a diagram showing a specific example of an upper arm driver circuit according to the first embodiment of the present invention; FIG. [Figure 4] 4 is a timing chart showing an operation of the upper arm driver circuit according to the first embodiment of the present invention. [Diagram 5] FIG. 4 is a diagram showing a modified example of the upper arm driver circuit according to the first embodiment of the present invention. [Figure 6] FIG. 11 is a diagram showing a specific example of an upper arm driver circuit according to a second embodiment of the present invention. [Figure 7] FIG. 11 is a diagram showing a modified example of an upper arm driver circuit according to the second embodiment of the present invention. [Figure 8] 10 is a timing chart showing the operation of the upper arm driver circuit according to the second embodiment of the present invention. [Figure 9] FIG. 11 is a diagram showing a specific example of an upper arm driver circuit according to a third embodiment of the present invention. [Figure 10] FIG. 11 is a diagram showing a modified example of an upper arm driver circuit according to the third embodiment of the present invention. [Figure 11] FIG. 11 is a diagram showing a specific example of an upper arm driver circuit according to a fourth embodiment of the present invention. [Figure 12] 10 is a timing chart showing the operation of the upper arm driver circuit according to Example 4 of the present invention. [Figure 13] 13 is a diagram showing a specific example of an upper arm drive circuit and a lower arm drive circuit according to Example 5 of the present invention. FIG. [Figure 14] 13 is a timing chart showing the operation of an upper arm drive circuit and a lower arm drive circuit according to Example 5 of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same components are designated by the same reference numerals, and detailed description of overlapping parts will be omitted. EXAMPLES

[0014] Fig. 1 is a partial cross-sectional structural diagram showing a part of the CG-IGBT of Example 1. As shown in Fig. 1, a buried oxide film 2 is formed on a support substrate 1 made of silicon (Si), a p-type base region 4 is selectively formed in the surface layer of an n-type semiconductor layer 3, an n-emitter region 5 is formed in a part of the surface layer of the p-type base region 4, and a p-anode region 6 is formed adjacent to the n-emitter region 5. In addition, an n-type buffer region 7 is selectively formed in a different region of the surface layer of the n-type semiconductor layer 3, a p-type base region 8 is formed in a part of the surface layer of the n-type buffer region 7, an n-cathode region 9 is formed in a part of the surface layer of the p-type base region, and a p-collector region 10 is formed in another part of the surface layer of the p-type base region.

[0015] A gate electrode 13 connected to a gate terminal (G) via a gate oxide film 12 is provided on the surface of a channel region 11 in the surface layer of the p base region 4, and a collector gate electrode 16 connected to a collector gate terminal (CG) via a gate oxide film 15 is provided on the surface of a channel region 14 in the surface layer of the p base region 8. An emitter electrode 17 is provided in common contact with the surfaces of the n emitter region 5 and the p anode region 6, and a collector electrode 18 is provided in common contact with the surfaces of the p collector region 10 and the n cathode region 9, and is connected to the emitter terminal (E) and the collector terminal (C), respectively.

[0016] Here, a CG-RC-IGBT is used as an example of a CG-IGBT for explanation, but the present invention is not limited to this, and a CG-IGBT other than a reverse conducting IGBT (RC-IGBT) may be used.

[0017] Fig. 2(a) is an equivalent circuit diagram of the CG-(RC-)IGBT of Example 1, and Fig. 2(b) is a symbol showing the CG-(RC-)IGBT of Example 1. As shown in Fig. 2(a), the CG-(RC-)IGBT of the present invention is characterized in comparison with a general IGBT in that it includes an N-type MOSFET 19 and a built-in diode 21. The N-type MOSFET 19 is a normally-off type, and its on / off is controlled by the collector gate CG.

[0018] When the collector gate CG is off (the N-type MOSFET 19 is off), it operates in the same way as a typical IGBT. When the collector gate CG is off and gate G (also called the emitter gate, which is the gate on the emitter side, but since it corresponds to a conventional gate, it will be simply called the "gate") is off, a forward cut-off state is established between collector C and emitter E. When the collector gate CG is off and gate G is on, it conducts in bipolar operation like a typical IGBT.

[0019] When gate G is on and collector gate CG is on (N-type MOSFET 19 is on), the base and emitter of pnp transistor 20 are shorted and pnp transistor 20 is turned off, so that the CG-(RC-)IGBT operates as a unipolar element in which only electron current flows through channel region 11, n-type semiconductor layer 3, and channel region 14. When the conduction current increases and the voltage drop between the drain and source of N-type MOSFET 19 increases, a voltage is generated between the base and emitter of pnp transistor 20, turning pnp transistor 20 on and enabling bipolar operation.

[0020] In the case of a CG-RC-IGBT, when the collector gate CG is on, the gate G is off, and the N-type MOSFET 19 is on, a reverse conducting current can flow through the built-in diode 21 and the N-type MOSFET 19. If the collector gate CG is on and the gate G is on when a reverse conducting current flows, the anode and cathode of the built-in diode 21 are shorted, no current flows through the built-in diode 21, and a unipolar operation is performed in which only an electron current flows through the channel region 11, the n-type semiconductor layer 3, and the channel region 14. In the following of this embodiment, the CG-(RC-)IGBT is represented by the symbol shown in FIG. 2(b).

[0021] Fig. 3 is a diagram showing a schematic configuration of an upper arm drive circuit of a power conversion device according to a first embodiment of the present invention, and Fig. 4 is a timing chart showing its operation. Note that in the following explanation, an example of a half-bridge circuit having only one leg with upper and lower arms each composed of a CG-IGBT and a freewheeling diode as an output element will be explained, but the subject of the present invention is not limited to this, and can also be applied to a power conversion device of a three-phase full-bridge circuit configured by connecting another leg of the half-bridge circuit to form a full-bridge configuration and connecting each output terminal (U phase, V phase, W phase) of a three-phase AC to the neutral point of each leg.

[0022] In Fig. 3, the CG-IGBT 28 and the freewheel diode 29 are upper arm output elements of the power converter, and the CG-IGBT 26 and the freewheel diode 27 are lower arm output elements of the power converter. As shown in Fig. 3, in the power converter of the first embodiment of the present invention, a load (coil) 30 is connected to the output terminal VOUT (emitter E of the CG-IGBT 28, collector C of the CG-IGBT 26), the collector C of the CG-IGBT 28 is connected to a main power supply 31, the upper arm drive circuit is made up of a gate driver 24 that drives the gate G of the CG-IGBT 28 and a gate driver 25 that drives the collector gate CG, and the lower arm drive circuit is made up of a gate driver 22 that drives the gate G of the CG-IGBT 26 and a gate driver 23 that drives the collector gate CG.

[0023] The gate driver 25 comprises a charge storage circuit 33 having a reverse current prevention element (diode) 34 and a capacitor 35, a charge charge / discharge control circuit 32 having a resistor 37 and a switching element 36, and a gate delay circuit (resistor) 38. The charge charge / discharge control circuit 32 is provided between a main power supply 31 of the power conversion device and a reference potential (ground) of the power conversion device, and the charge storage circuit 33 is connected in parallel with the resistor 37 of the charge charge / discharge control circuit 32.

[0024] Furthermore, one terminal of the capacitor 35 is connected to the main power supply 31 of the power conversion device via a reverse current prevention element (diode) 34, and is also connected to the collector gate CG of the CG-IGBT 28 via a gate delay circuit (resistance) 38, and the other terminal of the capacitor 35 is connected to the main power supply 31 of the power conversion device via a resistor 37, and is also connected to the reference potential (ground) of the power conversion device via a switching element 36. Furthermore, the main power supply 31 of the power conversion device and the collector gate CG of the CG-IGBT 28 are connected via the reverse current prevention element (diode) 34 and the gate delay circuit (resistance) 38.

[0025] 4, in the upper arm drive circuit of the power conversion device of the first embodiment of the present invention, first, the main power supply 31 is turned on and the collector voltage of the CG-IGBT 28 rises to the voltage VS of the main power supply 31. Next, the gate voltage VGE rises due to an upper arm on command signal input to the gate driver 24, turning on the CG-IGBT 28 and causing the output terminal VOUT to rise to the voltage VS of the main power supply 31 of the power conversion device.

[0026] At this time, by turning on the switching element 36, a positive voltage V37 is generated across the resistor 37, and charge is stored in the capacitor 35. Thereafter, when the switching element 36 is turned off, no current flows through the resistor 37, the voltage V37 across the resistor 37 drops to 0 V, and the potential at the junction between the resistor 37, the switching element 36, and the other terminal of the capacitor 35 becomes equal to the voltage VS of the main power supply 31 of the power conversion device. Then, the charge stored in the capacitor 35 is injected into the collector gate CG of the CG-IGBT 28 via the gate delay circuit (resistor) 38, the voltage of the collector gate CG rises, the collector gate of the CG-IGBT 28 is turned on, and the carrier density in the CG-IGBT 28 decreases.

[0027] Thereafter, the gate voltage VGE decreases due to an upper arm off command signal input to the gate driver 24, the CG-IGBT 28 turns off, and the output terminal VOUT decreases to the reference potential (ground) of the power conversion device.

[0028] As described above, according to the upper arm driver circuit and its control method of the first embodiment of the present invention, the collector gate CG of the CG-IGBT 28 is turned on prior to turning off the CG-IGBT 28, thereby reducing the carrier density in the CG-IGBT 28 and, as a result, reducing the turn-off loss of the CG-IGBT 28. As a modification of the first embodiment of the present invention, as shown in Fig. 5, the resistor 37 may be replaced with a switching element 39, and the switching element 39 may be controlled to be turned off during the period when the switching element 36 is turned on and to be turned off during the period when the switching element 36 is off. EXAMPLES

[0029] Next, the configuration and control method of the upper arm drive circuit of the second embodiment of the present invention will be described with reference to Figures 6 to 8. The difference between Figure 6 and Figure 3 is that in Figure 6, a switching element 40 for turning off the collector gate CG is connected between the collector gate CG and collector C of the CG-IGBT 28. In the configuration of Figure 3, it was necessary to maintain the switching element 36 in the on state in order to maintain the collector gate CG in the off state, as shown in the timing chart of Figure 4.

[0030] In the second embodiment of the present invention shown in FIG. 6, by turning on switching element 40 while switching element 36 is in the off state, collector gate CG and collector C of CG-IGBT 28 are short-circuited, and the charge stored in capacitor 35 is discharged, making it possible to maintain collector gate CG of CG-IGBT 28 in the off state.

[0031] 8 shows a timing chart illustrating the operation of the upper arm driver circuit according to the second embodiment of the present invention. When the CG-IGBT28 is turned on, the switching element 40 is turned on to maintain the collector gate CG of the CG-IGBT28 in the off state, and prior to the turn-off of the CG-IGBT28, the switching element 36 is turned on to store charge in the capacitor 35, and then the switching element 36 is turned off to inject the charge stored in the capacitor 35 into the collector gate CG of the CG-IGBT28, thereby turning on the collector gate CG.

[0032] As described above, according to the upper arm driver circuit and the control method thereof in the second embodiment of the present invention, the period during which the switching element 36 is turned on can be reduced, thereby reducing the power consumption of the charge / discharge control circuit 32. As a modification of the second embodiment of the present invention, a switching element 41 may be connected between the collector gate CG of the CG-IGBT 28 and the reference potential (ground) of the power conversion device, instead of the switching element 40, as shown in FIG. EXAMPLES

[0033] Next, the configuration of an upper arm driver circuit according to a third embodiment of the present invention will be described with reference to Figures 9 and 10. The difference between Figures 3 and 9 is that a voltage limiting element (Zener diode) 42 is connected in parallel to the capacitor 35 in Figure 9.

[0034] 9, the voltage applied to the capacitor 35 when the switching element 36 is turned on can be limited by the voltage limiting element (Zener diode) 42, and therefore it is possible to prevent an overvoltage from being applied to the collector gate CG when the switching element 36 is turned off to inject charge into the collector gate CG of the CG-IGBT 28, thereby improving the reliability of the CG-IGBT 28. As a modification of the third embodiment of the present invention, a voltage limiting element (Zener diode) 43 may be connected in parallel to the resistor 37 as shown in FIG. EXAMPLES

[0035] Next, the configuration and control method of an upper arm driver circuit according to a fourth embodiment of the present invention will be described with reference to Figures 11 and 12. In the fourth embodiment, a specific example of the gate driver 24 that drives the gate G of the CG-IGBT 28 will be described. The gate driver 24 is composed of a switching element 44, a backflow prevention element (diode) 45, a voltage limiting element (Zener diode) 46, a capacitor 47, a gate delay circuit (resistor) 48, and a switching element 49.

[0036] The gate G of the CG-IGBT28, which is the upper arm output element, is connected to the main power supply 31 of the power conversion device via a switching element 44, a backflow prevention element (diode) 45, and a gate delay circuit (resistor) 48, and is also connected to the reference potential (ground) of the power conversion device via a switching element 49 and a gate delay circuit (resistor) 48.

[0037] One terminal of the capacitor 47 is connected to the main power supply 31 of the power conversion device via a switching element 44 and a reverse current prevention element (diode) 45, is connected to the reference potential (ground) of the power conversion device via a switching element 49, and is also connected to the gate G of the CG-IGBT 28 which is the upper arm output element via a gate delay circuit (resistor) 48. The other terminal of the capacitor 47 is connected to the output terminal VOUT of the power conversion device, and further, a voltage limiting element (Zener diode) 46 is connected in parallel to both terminals of the capacitor 47.

[0038] As shown in FIG. 12, in the upper arm drive circuit of the power conversion device of the fourth embodiment of the present invention, first, the main power supply 31 is turned on, and the collector potential of the CG-IGBT 28 rises to the voltage VS of the main power supply 31. Next, the switching element 44 is turned on, and charge is injected from the main power supply 31 of the power conversion device to the capacitor 47 via the switching element 44 and the backflow prevention element (diode) 45, and the capacitor 47 is charged. The voltage applied between both terminals of the capacitor 47 is limited by the voltage limiting element (Zener diode) 46, so there is no risk of destruction due to overvoltage. The charge charged in the capacitor 47 is injected into the gate G of the CG-IGBT 28 via the gate delay circuit (resistor) 48, and the gate voltage VGE rises, the CG-IGBT 28 is turned on, and the potential of the output terminal VOUT rises to the voltage VS of the main power supply 31 of the power conversion device.

[0039] At this time, by turning on the switching element 36, a positive voltage V37 is generated across the resistor 37, and charge is stored in the capacitor 35. Thereafter, when the switching element 36 is turned off, no current flows through the resistor 37, the voltage V37 across the resistor 37 drops to 0 V, and the potential at the junction between the resistor 37, the switching element 36, and the other terminal of the capacitor 35 becomes equal to the voltage VS of the main power supply 31 of the power conversion device. Then, the charge stored in the capacitor 35 is injected into the collector gate CG of the CG-IGBT 28 via the gate delay circuit (resistor) 38, the voltage of the collector gate CG rises, the collector gate of the CG-IGBT 28 is turned on, and the carrier density in the CG-IGBT 28 decreases.

[0040] Thereafter, by turning off switching element 44 and turning on switching element 49, the charge stored in gate G of CG-IGBT 28 is discharged to the reference potential (ground) of the power conversion device via gate delay circuit (resistor) 48 and switching element 49, the gate voltage VGE of CG-IGBT 28 drops, CG-IGBT 28 turns off, and the output terminal VOUT drops to the reference potential (ground) of the power conversion device.

[0041] As described above, according to the upper arm drive circuit and its control method of the fourth embodiment of the present invention, the collector gate CG of the CG-IGBT28 is turned on prior to turning off the CG-IGBT28, thereby reducing the carrier density in the CG-IGBT28, and as a result, the turn-off loss of the CG-IGBT28 can be reduced. EXAMPLES

[0042] Next, the configuration and control method of an upper arm drive circuit and a lower arm drive circuit of embodiment 5 of the present invention will be described with reference to Figures 13 and 14. In embodiment 5, a specific example of a gate driver 23 that drives a collector gate CG of a CG-IGBT 26 that is a lower arm output element will be described. The gate driver 23 is composed of a switching element 50, a backflow prevention element (diode) 51, a voltage limiting element (Zener diode) 52, a capacitor 53, a gate delay circuit (resistor) 54, and a switching element 55.

[0043] The collector gate CG of the CG-IGBT 26, which is the lower arm output element, is connected to the main power supply 31 of the power conversion device via a switching element 50, a backflow prevention element (diode) 51, and a gate delay circuit (resistor) 54, and is also connected to the reference potential (ground) of the power conversion device via a switching element 55 and a gate delay circuit (resistor) 54.

[0044] One terminal of the capacitor 53 is connected to the main power supply 31 of the power conversion device via a switching element 50 and a reverse current prevention element (diode) 51, is connected to the reference potential (ground) of the power conversion device via a switching element 55, and is also connected to the collector gate CG of the CG-IGBT 28 which is the lower arm output element via a gate delay circuit (resistor) 54. The other terminal of the capacitor 53 is connected to the output terminal VOUT of the power conversion device, and a voltage limiting element (Zener diode) 52 is connected in parallel to both terminals of the capacitor 53.

[0045] As shown in Figure 14, in the upper arm drive circuit and lower arm drive circuit of the power conversion device of Example 5 of the present invention, when the main power supply 31 is turned on and the collector voltage of the upper arm output element CG-IGBT28 rises to the voltage VS of the main power supply 31 and the gate voltage VGE of the upper arm output element CG-IGBT28 is off (0 V), a lower arm on command signal input to the gate driver 22 of the lower arm drive circuit increases the gate voltage VGEL of the lower arm output element CG-IGBT26, turning on the CG-IGBT26 and causing the potential of the output terminal VOUT to fall to the reference potential (ground) of the power conversion device.

[0046] At this time, by turning on the switching element 55, the collector gate CG of the CG-IGBT 26 is electrically connected to the reference potential (ground) of the power conversion device, and the collector gate CG of the CG-IGBT 26 is fixed in the OFF state. After that, by turning off the switching element 55 and turning on the switching element 50, charge is injected from the main power supply 31 of the power conversion device via the switching element 50, the backflow prevention element (diode) 51, and the gate delay circuit (resistor) 54 into the collector gate CG of the CG-IGBT 26, the potential of the collector gate CG rises, and the collector gate CG turns on. At this time, even if an excessive current flows instantaneously through the switching element 50, the voltage limiting element (Zener diode) 52 and the capacitor 53 can prevent an excessive voltage from being applied to the collector gate CG of the CG-IGBT 26. When the collector gate CG turns on, the carrier density in the CG-IGBT 26 decreases.

[0047] Thereafter, the gate voltage VGEL of the lower arm output element CG-IGBT26 is reduced by the lower arm off command signal input to the gate driver 22, turning off the CG-IGBT26 and causing the potential of the output terminal VOUT to rise to the voltage VS of the main power supply 31 of the power conversion device.

[0048] As described above, according to the upper arm drive circuit and lower arm drive circuit of the power conversion device of embodiment 5 of the present invention and the control method thereof, the carrier density in the CG-IGBT26 of the lower arm is reduced by turning on the collector gate CG of the CG-IGBT26 prior to turning off the CG-IGBT26, and as a result, the turn-off loss of the CG-IGBT26 is reduced. [Explanation of symbols]

[0049] 1…Support substrate 2...Buried oxide film 3...n-type semiconductor layer 4...p base region 5...n emitter region 6...p anode region 7...n buffer area 8...p base region 9...n cathode region 10...p collector region 11…Channel region 12...Gate oxide film 13...Gate electrode 14…Channel region 15...Gate oxide film 16...Collector gate electrode 17…Emitter electrode 18…Collector electrode 19...N-type MOSFET 20...pnp transistor 21…Built-in diode 22…Gate driver 23...Gate driver 24…Gate driver 25…Gate driver 26...CG-IGBT (lower arm output element) 27...Freewheeling diode (lower arm output element) 28...CG-IGBT (upper arm output element) 29...Freewheeling diode (upper arm output element) 30...Load (coil) 31…Main power supply 32...Charge and discharge control circuit 33...Charge storage circuit 34...Reverse current prevention element (diode) 35…Capacitor 36...Switching element 37…Resistor 38…Gate delay circuit (resistor) 39...Switching element 40...Switching element 41...Switching element 42...Voltage limiting element (Zener diode) 43...Voltage limiting element (Zener diode) 44...Switching element 45...Reverse current prevention element (diode) 46...Voltage limiting element (Zener diode) 47…Capacitor 48…Gate delay circuit (resistor) 49...Switching element 50...Switching element 51...Reverse current prevention element (diode) 52...Voltage limiting element (Zener diode) 53…Capacitor 54…Gate delay circuit (resistor) 55...Switching element

Claims

1. A drive circuit for a power conversion device including a first CG-IGBT as an upper arm output element and a second CG-IGBT as a lower arm output element, an upper arm drive circuit that drives the first CG-IGBT and a lower arm drive circuit that drives the second CG-IGBT; the upper arm drive circuit has a first gate driver that drives a collector gate of the first CG-IGBT and a second gate driver that drives a gate of the first CG-IGBT; the lower arm drive circuit has a third gate driver that drives a collector gate of the second CG-IGBT and a fourth gate driver that drives a gate of the second CG-IGBT; the first gate driver has a charge storage circuit including a first capacitor and a first reverse current prevention element, and a charge charge / discharge control circuit including a first switching element and a first resistor; one terminal of the first capacitor is connected to a main power supply of the power conversion device via the first reverse current prevention element and to a collector gate of the first CG-IGBT; The other terminal of the first capacitor is connected to a reference potential of the power conversion device via the first switching element and to a main power supply of the power conversion device via the first resistor.

2. 2. The drive circuit according to claim 1, wherein the first reverse current prevention element prevents a reverse current flow from one terminal of the first capacitor to a main power supply of the power conversion device.

3. A drive circuit for a power conversion device including a first CG-IGBT as an upper arm output element and a second CG-IGBT as a lower arm output element, an upper arm drive circuit that drives the first CG-IGBT and a lower arm drive circuit that drives the second CG-IGBT; the upper arm drive circuit has a first gate driver that drives a collector gate of the first CG-IGBT and a second gate driver that drives a gate of the first CG-IGBT; the lower arm drive circuit has a third gate driver that drives a collector gate of the second CG-IGBT and a fourth gate driver that drives a gate of the second CG-IGBT; the first gate driver has a charge storage circuit including a first capacitor and a first reverse current prevention element, and a charge charge / discharge control circuit including a first switching element and a second switching element; one terminal of the first capacitor is connected to a main power supply of the power conversion device via the first reverse current prevention element and to a collector gate of the first CG-IGBT; A drive circuit characterized in that the other terminal of the first capacitor is connected to a reference potential of the power conversion device via the first switching element and is connected to a main power supply of the power conversion device via the second switching element.

4. 4. The drive circuit according to claim 3, wherein the first reverse current prevention element prevents a reverse current flow from one terminal of the first capacitor to a main power supply of the power conversion device.

5. 5. The drive circuit according to claim 1, further comprising a first gate delay circuit provided between the one terminal of the first capacitor and a collector gate of the first CG-IGBT.

6. 5. The drive circuit according to claim 1, further comprising a third switching element provided in parallel with the first reverse current prevention element between the one terminal of the first capacitor and a main power supply of the power conversion device.

7. 5. The drive circuit according to claim 1, further comprising a third switching element provided between the one terminal of the first capacitor and a reference potential of the power conversion device.

8. 5. The drive circuit according to claim 1, wherein a first voltage limiting element is connected in parallel to the first capacitor.

9. 3. The drive circuit according to claim 1, wherein a first voltage limiting element is connected in parallel to the first resistor.

10. the second gate driver includes a third switching element, a second reverse current prevention element, a second voltage limiting element, a second capacitor, a first gate delay circuit, and a fourth switching element; one terminal of the second capacitor is connected to a main power supply of the power conversion device via the third switching element and the second reverse current prevention element, is connected to a reference potential of the power conversion device via the fourth switching element, and is connected to a gate of the first CG-IGBT via the first gate delay circuit; the other terminal of the second capacitor is connected to an output terminal of the power conversion device; the second voltage limiting element is connected in parallel to the second capacitor; the third gate driver includes a fifth switching element, a third reverse current prevention element, a third voltage limiting element, a third capacitor, a second gate delay circuit, and a sixth switching element; one terminal of the third capacitor is connected to a main power supply of the power conversion device via the fifth switching element and the third reverse current prevention element, is connected to a reference potential of the power conversion device via the sixth switching element, and is connected to a collector gate of the second CG-IGBT via the second gate delay circuit; the other terminal of the third capacitor is connected to an output terminal of the power conversion device; 5. The drive circuit according to claim 1, wherein the third voltage limiting element is connected in parallel to the third capacitor.

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