PFC network circuit

Abstract

To provide a network circuit that does not include a step-up or step-down circuit downstream and a method for directly converting a rectified voltage to a lower intermediate circuit DC voltage and a higher intermediate circuit DC voltage.SOLUTION: A PFC network circuit includes: a rectifier having three phases and three input units; first and second transistors controlled by a control unit; an intermediate point arranged between the first and second transistors; a star point having three star capacitors; and a capacitor connected to the intermediate point and a reference potential. The reference potential can be either a zero potential of a network circuit or the star point of the star capacitor. The control unit is configured to control the first transistor and the second transistor so that an AC power supply voltage is converted to a DC output voltage that is stepped up or down depending on the polarity of a string voltage. The first and second transistors are controlled by the control unit through positive control and negative control.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] [CROSS REFERENCE TO RELATED APPLICATIONS] This application claims priority to Luxembourg patent application LU504159, filed May 8, 2023. The entire contents of Luxembourg patent application LU504159 are incorporated herein by reference in their entirety.

[0002] The present invention relates to a network circuit and a method for supplying direct current from a three-phase power supply network to an electrical load, in order to modulate the string voltage from the three-phase power supply network, the rectified voltage being both step-up and step-down. The network circuit ensures that the phase currents at the input of the rectifier are approximately sinusoidal, regardless of the load. Thus, a network circuit is provided which, through the target control of the control elements, allows the AC mains voltage to be set high or low in compliance with the PFC standard. [Background technology]

[0003] Network circuits are known from the prior art. They have the task of rectifying an AC mains voltage applied to their input and increasing it to a value greater than the amplitude of the associated AC mains voltage (step-up converter or boost converter) or decreasing it to a value less than the amplitude of the associated AC mains voltage (step-down converter or buck converter).

[0004] It is known that there is a certain physical relationship between the AC mains voltage and the intermediate circuit voltage, as shown in Figure 1. Electronic converter systems in the form of boost and buck converters make it possible to convert the AC mains voltage into a higher or lower intermediate circuit voltage UZK or into a DC output voltage. Known electronic converter systems try to achieve sinusoidal phase currents. They are called PFC boost converters or PFC buck converters with PFC for power factor correction (PFC).

[0005] It is known that many loads connected to the public power supply network extract pulsating network currents through simple bridge rectifiers, which are accompanied by large harmonic currents and therefore high reactive power consumption. To utilize these pulsating currents, the public power supply network must be made large. Furthermore, there are short-term voltage dips and voltage peaks, which lead to increased problems for sensitive loads. For this reason, there are corresponding (PFC) standards (see, for example, DIN EN IEC 61000-3-2 (VDE 0838-2), December 2019 and DIN EN 61000-3-12 (VDE 0838-12), June 2012), which require the use of so-called power factor correction (PFC) above a certain power level. Passive system components require a large installation space and supply currents with a shape that deviates from a sine wave, which consequently requires the use of active circuit solutions.

[0006] For example, EP 3068024 A1 discloses a three-phase pulse rectifier system with relatively low reverse voltage stress on switchable high power density power semiconductors and low system feedback. Such three-phase three-point pulse rectifiers, also known as Vienna rectifiers, are known to be characterized by a significantly lower harmonic content on the AC voltage side compared to conventional six-pulse bridge circuits used for rectifying three-phase currents.

[0007] US2013 / 0194838A1 discloses a three-phase boost rectifier with low input current and low harmonics, comprising an input stage for receiving a three-phase input voltage with respect to a neutral point and an output stage suitable for coupling to at least one load.

[0008] US5933336A discloses a boost converter with first, second and third phase inputs and outputs. The boost converter further comprises first and second switches or transistors connected between corresponding lines of the output. The boost converter also comprises first, second and third capacitors forming first, second and third LC series paths with a first inductor, respectively. The first, second and third LC series paths are respectively coupled between the first, second and third phase inputs and a node between the first and second switches. The first and second switches cooperate in a stepwise manner using the line-to-line voltage minus the voltage across the first, second and third capacitors to discharge the current through the first inductor, thereby reducing the total harmonic distortion (THD) of the input current in all three phase inputs.

[0009] EP0973245A2 discloses a circuit in which an inductor is coupled to the three phase inputs. Two switches are connected between the output terminals. Three capacitors are connected in a star configuration to the three phase inputs, with the star point connected to the node between the switches. A rectifier with diodes is inserted between the inductor and the switches. The output is connected to the switches via the output capacitors. The phase inputs are fed through electromagnetic interference suppression filters. The inductor is operated in gapped mode (discontinuous current modem DCM). A control loop controls the switches. The switches are operated in stages, with a voltage across the output section lower than the voltage across the capacitors, to discharge the current through the inductor and reduce the total input current distortion at all phase inputs.

[0010] According to WO 93 / 12576 A1, a circuit is known for generating a current having a selected amplitude and phase that is a harmonic of the frequency of a power supply system in order to reduce the total harmonic distortion of a system converting AC to DC or vice versa. A DC signal is sampled and a sinusoidal current containing the desired harmonics is generated by controlling a switch and fed to an impedance network which feeds this current into a polyphase AC system of a power supply. The impedance network comprises a single inductor and a capacitor connected in series with each phase of the power supply and includes a current signal having an amplitude selected to substantially eliminate the harmonics that cause significant distortion in the supplied signal.

[0011] CN102130572A discloses a three-phase rectifier bridge DC side parallel circuit type active power filter. The active power filter has a coupling element on the AC side of the three-phase rectifier bridge, which is a low-frequency bidirectional power switch, and the coupling element is an impedance. The active power filter improves the prior art in which two capacitors and four high-frequency power switching tubes used in two boost bidirectional power converters are connected in series with each other, so that only one capacitor and three high-frequency power are required. Therefore, compared with the prior art, the active power filter presents better harmonic suppression because it does not need to equalize the voltage between the two original capacitors.

[0012] Thus, network circuits capable of converting an AC mains voltage into a rectified intermediate circuit voltage are known from the prior art. However, in order to be able to both step up and step down the AC mains voltage, the known network circuits are usually configured as PFC boost converters and comprise a separate downstream step-down converter circuit. Converter systems with transformers are also used for this purpose.

[0013] Such a network circuit requires a large number of components to step up or increase the AC mains voltage, as is the case for example with the Vienna rectifier, making it very expensive and requiring a very complex control. To obtain a lower intermediate circuit voltage from the previously increased voltage, in addition to this circuit a buck converter circuit must be connected downstream, which also requires additional components. In addition to the increased costs, the efficiency is also significantly reduced when two converter systems are connected in series (by multiplying the efficiency of the individual converter systems). The efficiency reduction can be generalized to all PFC boost converter topologies that require a buck converter circuit to be connected downstream.

[0014] An example of a PFC boost converter topology without a downstream converter circuit is known, for example, from WO2021 / 260222A1. As shown in FIG. 2, this discloses a network circuit N for providing an intermediate circuit DC voltage UZK and a load-dependent intermediate circuit current IZK at an output OUT from a three-phase power supply network VN. The network circuit N comprises a capacitor CS in the midpoint network, which serves as an adjustable voltage source for setting a voltage difference via storage chokes LL1, LL2, LL3 as energy stores on the rectifier GR. By selectively controlling the control element ST, the AC mains voltage can be boosted while complying with the PFC standard. However, a disadvantage of this network circuit is that only one boost is possible.

[0015] Considering PFC buck converters, there are also various well-known buck converter topologies with a downstream boost converter circuit. Also, the high number of components significantly reduces the efficiency of this type of circuit. It also requires complex control.

[0016] Another example of a downstream converter in a PFC circuit is known as a CUK or SEPIC converter. However, because CUK or SEPIC converters can only function at a certain input voltage due to their control law, the network circuit combining CUK or SEPIC converters is very complex and requires additional components. Also, the efficiency of this type of circuit decreases significantly with the number of components.

[0017] It is therefore an object of the present application to provide a network circuit without downstream step-up or step-down circuits and a method for directly converting an AC mains voltage and the resulting rectified voltage into both a lower intermediate circuit DC voltage and a higher intermediate circuit DC voltage while complying with PFC standards, thereby overcoming the above-mentioned disadvantages of known network circuits. Summary of the Invention

[0018] This object is solved by a PFC network circuit with a half bridge and a method for converting an AC mains voltage to both a lower and a higher DC output voltage while complying with PFC standards.

[0019] The PFC network circuit includes a rectifier having three phases and three inputs, a first and a second transistor or switch controlled by a control unit, a midpoint disposed between the first and the second transistors, a star point having three star capacitors, and a capacitor connected to the midpoint and a reference potential, which may be either the zero potential of the network circuit or the star point of the star capacitors. The network circuit further includes an output capacitor, an output coil, a diode, and a string capacitor, the output capacitor, the output coil, the diode, and the string capacitor being provided in an output region of the network circuit. The network circuit also includes three storage chokes, each connected to one of the three phases and one of the three inputs of the rectifier. The capacitor functions as an adjustable voltage source by selectively charging and discharging by controlling the first and second transistors, and is configured to adjust the voltage difference between the three storage chokes to meet the PFC standard. The control unit is configured to control the first and second transistors such that the AC source voltage is converted to a stepped-up or stepped-down DC output voltage depending on the polarity of the string voltage. The control of the first and second transistors is performed by a control unit through positive control and negative control.

[0020] In this way, a network circuit is provided that allows converting an AC power supply voltage into lower and higher DC output voltages while complying with the PFC standard by controlling only the first and second transistors. Thus, with the same control element, a sinusoidal current is obtained from the power supply network according to the control in order to meet the PFC standard. The network circuit improves effectiveness and energy efficiency by eliminating unnecessary downstream topologies, and reduces the number of components, thereby reducing costs.

[0021] According to one embodiment, the diodes include at least one of a positive diode in the positive path, a negative diode in the negative path, or a positive diode and a negative diode in the positive path.

[0022] The diode allows the output of the network circuit to be completely electrically isolated from the rest of the network circuit. Furthermore, the network circuit is made symmetrical with respect to earth, which provides further advantages in terms of EMC (electromagnetic compatibility) and leakage currents. This reduces the electrical load on the individual components of the network circuit.

[0023] According to a further aspect, the string capacitor includes at least one of a positive strand capacitor in the positive string, a negative strand capacitor in the negative string, or a positive strand capacitor in the positive string and a negative strand capacitor in the negative string.

[0024] If the string capacitors contain only positive or only negative string capacitors, the volume of the installation space can be reduced. If the string capacitors contain positive and negative string capacitors, the output of the network circuit can be completely capacitively decoupled from the rest of the network circuit. Furthermore, the network circuit is ground balanced, which provides further advantages in terms of EMC (electromagnetic compatibility) and leakage currents. This reduces the electrical load of the individual components of the network circuit. Even if a component in the network circuit fails, there is no breakdown of the input voltage at the output.

[0025] According to a further aspect, the output coil includes at least one of a positive output coil in the positive path, a negative output coil in the negative path, or a positive output coil and a negative output coil in the positive path.

[0026] If the output coils include a positive output coil and a negative output coil, the output of the network circuit can be completely inductively decoupled from the rest of the network circuit. Furthermore, the network circuit is ground symmetrical, which provides further advantages in terms of EMC (electromagnetic compatibility) and leakage currents. This reduces the electrical load on the individual components of the network circuit.

[0027] According to a further aspect, the network circuit further comprises a positive decoupling diode provided in an output region of the positive path network circuit, and a negative decoupling diode provided in an output region of the negative path network circuit.

[0028] Positive and negative decoupling diodes improve the inductive decoupling of the output of the network circuit and allow unidirectional current flow. Furthermore, the network circuit is made symmetrical with respect to ground, which provides further advantages in terms of EMC (electromagnetic compatibility) and leakage currents. This reduces the electrical load on the individual components of the network circuit.

[0029] According to a further aspect, the network circuit is multi-channel.

[0030] Thanks to the multi-channel design, the network circuit can be used over a wider power range.

[0031] According to a further aspect, each channel of the multi-channel network circuit operates synchronously or offset according to an interleaving principle.

[0032] Using the interleaving principle, the energy supply to the components of the network circuit can be divided and the load on the components can be reduced. In addition, the ripple of the output voltage can be reduced, so that the capacitance of the output capacitor can be selected lower (smoothing capacitance).

[0033] The object is further solved by a method for converting an AC mains voltage to a lower or higher DC output voltage while complying with the PFC standard on the network circuit. The method includes controlling the first and second transistors, charging and discharging a capacitor in response to the control, generating a capacitor voltage in the capacitor, influencing a voltage difference on three storage chokes by the capacitor voltage of the capacitor, and extracting a sinusoidal phase current from the power supply network in compliance with the limit values ​​of harmonic currents of the PFC standard. The control includes positive and negative control, taking into account the polarity of the string voltage. The coil voltage of the storage choke corresponds to the voltage difference between the capacitor voltage and the AC mains voltage resulting from the charging and discharging. The DC output voltage is stepped up or down with respect to the AC mains voltage in response to the control.

[0034] By controlling only the first and second transistors of the network circuit, the DC output voltage can be increased or decreased while complying with the PFC standard, which improves effectiveness and energy efficiency and reduces the number of components, thus reducing costs.

[0035] According to one embodiment, the first transistor and the second transistor are controlled such that the DC output voltage is regulated to a desired value depending on the load, and at least one of the switch-on period, the short circuit period, and the switch-off period of the first and second transistors serves as a degree of freedom.

[0036] According to a further aspect, the control is performed to comply with the harmonic current limits of the PFC standard. [Brief description of the drawings]

[0037] The invention will now be explained in more detail with reference to the drawings in which:

[0038] FIG. 1 illustrates the known, fixed physical relationship between the AC mains voltage and the intermediate circuit voltage.

[0039] FIG. 2 shows a known PFC boost converter topology without a downstream converter circuit.

[0040] FIG. 3 shows a network circuit according to a first example embodiment.

[0041] FIG. 4 shows a rectifier of the network circuit of FIG.

[0042] FIG. 5 shows a network circuit according to the second embodiment.

[0043] FIG. 6 shows a first variant of the output area of ​​the network circuit.

[0044] 7A and 7B show a second variant of the output area of ​​the network circuit.

[0045] FIG. 8 shows a third variant of the output area of ​​the network circuit.

[0046] FIG. 9 shows a fourth variant of the output area of ​​the network circuit.

[0047] 10 and 11 show a multi-channel configuration of a network circuit.

[0048] FIG. 12 shows the flow of control signals in positive control.

[0049] FIG. 13 shows the flow of control signals in negative control.

[0050] FIG. 14 shows different characteristic curves in positive control in the boost operation of the network circuit of FIG.

[0051] FIG. 15 shows different characteristic curves in negative control in the boost operation of the network circuit of FIG.

[0052] FIG. 16 shows different characteristic curves in positive control in the step-down operation of the network circuit of FIG.

[0053] FIG. 17 shows different characteristic curves in negative control in the step-down operation of the network circuit of FIG.

[0054] FIG. 18 shows different characteristic curves in positive control in the boost operation of the network circuit of FIG.

[0055] FIG. 19 shows different characteristic curves in negative control in the boost operation of the network circuit of FIG.

[0056] FIG. 20 shows different characteristic curves in positive control in the step-down operation of the network circuit of FIG.

[0057] FIG. 21 shows different characteristic curves in negative control in the step-down operation of the network circuit of FIG.

[0058] 22A and 22B show method steps for positive and negative control of a network circuit.

[0059] 24A to 25C show transitions of network variables in the step-up and step-down operations of the network circuit of FIG.

[0060] 26A to 27C show transitions of network variables in the step-up and step-down operations of the network circuit of FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0061] [Description of Specific Embodiments of the Invention]

[0062] FIG. 3 shows the general structure of a single-channel network circuit 100 according to a first example embodiment for providing a stepped-up or stepped-down DC output voltage UA at the output of the network circuit 100 from an AC power supply voltage uN (u1, u2, u3) from a three-phase power supply network VN.

[0063] The network circuit 100 comprises a number of interconnected components: in the input domain B1, the network circuit 100 comprises an input IN, an EMI filter or a filter for electromagnetic interference, a network detector NE, a control unit SE optionally comprising an output detector AE, a coupling circuit KS, a rectifier GR, at least one control element ST or a first transistor T1 and a second transistor T2, a midpoint M arranged between the first transistor T1 and the second transistor T2, and a capacitor CS, and in the output domain B2, an output capacitor CA, an output coil LA, a diode D, a string capacitor C and an output OUT.

[0064] The first transistor T1 and the second transistor T2 are each transistors with a control input AN and a body diode (not shown) or a freewheeling diode (not shown) connected in parallel with the transistors T1, T2. The control input AN is connected to a control unit SE, and the first transistor T1 and the second transistor T2 are each controlled via the control input AN via the control unit SE. The capacitor CS is connected to a midpoint M of the network circuit 100 and to a zero potential NP. The first transistor T1, the midpoint M and the second transistor T2 form a half-bridge or electronic half-bridge circuit.

[0065] At the input IN, the network circuit 100 is connected to a power supply network VN via phases L1, L2, and L3. The phases L1, L2, and L3 have network variables NG. The network variables NG have at least one of the phase position PL, the string voltage UN (string voltages u1, u2, and u3), and the phase currents iNL1, iNL2, and iNL3.

[0066] The input IN is followed by an EMI filter EMI, which is used in a known manner to filter electromagnetic interference, for this reason and for the sake of brevity, the EMI filter will not be described in detail here.

[0067] The network variables NG of each of the phases L1, L2, L3 are detected by a network detector NE in the various circuit paths and passed to the control unit SE. The network detector NE is located between the EMI filter and the coupling circuit KS. Here, the circuit paths have a positive path pZ and a negative path nZ.

[0068] If the power supply network VN is a four-wire three-phase system with a neutral conductor, a symmetrical neutral point is created in the power supply network VN (not shown).

[0069] The control unit SE can optionally extend the output detection part AE to detect voltage and current variables at different locations, in particular at the output OUT of the network circuit 100. The output detection part thus detects at least one of the DC output voltage UA and the output current IA at the output OUT.

[0070] The coupling circuit KS is followed by a rectifier GR, which in the illustrated example has three inputs e1, e2, e3 and is composed of rectifier diodes D1, D2, D3, D4, D5, D6 as energy storages. The inputs e1, e2, e3 connect the rectifier GR to the phases L1, L2, L3. Between the coupling circuit KS and the rectifier GR, storage chokes LL1, LL2, LL3 are provided. However, the rectifier GR is not limited to this example embodiment. The rectifier GR can also be composed of controllable and / or non-controllable components and / or a combination thereof. The rectifier GR can thus be a rectifier and an inverter allowing a feedback option to the power supply network VN.

[0071] As shown in Fig. 4, the rectifier GR rectifies the phase currents iNL1, iNL2, and iNL3 of the phases L1, L2, and L3 to generate a rectified current IG. The rectified current IG is divided into a first rectified current IG1 and a second rectified current IG2 depending on the clock state of the first transistor T1. The second rectified current IG2 passes through the first transistor T1. The first rectified current IG1 is supplied to the output OUT of the network circuit 100 via the positive path pZ.

[0072] In the network circuit 100, the control inputs AN of the first transistor T1 and the second transistor T2 are controlled by a control unit SE. The second rectified current IG2 is converted into a clock signal GS by controlling the control inputs AN by the control unit SE. The clock signal GS corresponds to the capacitor current iCS through the capacitor CS.

[0073] The clock signal GS is transferred from the first transistor T1 to the phases L1, L2, L3 via the intermediate point M and the capacitor CS, as shown in Figure 3. The capacitor CS is charged in particular by the clock signal GS. The voltage to which the capacitor CS is charged corresponds to the integrated capacitor current iCS divided by the capacitance value of the capacitor CS.

[0074] The difference between the respective string voltages and the voltage values ​​of the capacitances measures the currents through the storage chokes LL1, LL2, LL3, ensuring sinusoidally modulated phase currents iNL1, iNL2, iNL3.

[0075] Thus, the capacitor CS acts as a voltage source and provides an adjustable voltage difference through the storage chokes LL1, LL2, LL3 by controlling the first transistor T1 or the second transistor T2. In this way, the network circuit 100 ensures a sinusoidal current extraction from the power supply network VN in order to meet the PFC standards.

[0076] The coupling circuit KS is provided between the EMI filter or network detector NE and the rectifier GR and is connected to the midpoint M. The coupling circuit KS removes high-frequency current components generated by the clocking of the transistors from the phase currents. In other words, the coupling circuit KS ensures that high-frequency currents generated by the clocking of the first transistor T1 and / or the second transistor T2 do not appear in the phase currents iNL1, iNL2, iNL3.

[0077] The coupling circuit KS is a capacitor star circuit with three star capacitors CYL1, CYL2, CYL3 forming a star point SP. The midpoint M is connected to the star point SP of the capacitor star circuit via a capacitor CS. The phase currents iNL1, iNL2, iNL3 are modulated by means of the forwarded clock signal GS of the phases L1, L2, L3 via the capacitor star circuit KS. The forwarded clock signal GS is thus fed back to the star point SP of the coupling circuit KS.

[0078] In order to capacitively isolate the output OUT from the input IN, in the first embodiment of the network circuit 100, a string capacitor C is provided in the positive path pZ after the first transistor T1. After the string capacitor C towards the output OUT, an output coil LA is provided between the positive path pZ and the negative path nZ. The output coil LA performs the function of an output-side storage choke (energy storage body) necessary for the circuit function (boost and buck). In order to isolate the output area B2 from the network circuit 100 so that the DC output voltage UA is maintained at the ground symmetric potential regardless of the clock, in the first embodiment of the network circuit 100, a diode is provided in the positive path pZ downstream of the string capacitor C and the output coil LA. Finally, an output capacitor CA is provided between the positive path pZ and the negative path nZ of the output OUT. Due to this particular arrangement of the aforementioned components in the output area B2, the network circuit 100 according to the first embodiment corresponds to a non-inverting three-phase buck-boost converter topology.

[0079] FIG. 5 shows the general structure of a single-channel network circuit 100 according to a second embodiment example, which supplies a stepped-up or stepped-down DC output voltage UA to an output OUT of the network circuit 100 from an AC power supply voltage uN from a three-phase power supply network VN.

[0080] The network circuit 100 according to the second embodiment differs from the first embodiment in that the arrangement of the output coil LA and the diode D in the output area B2 is different. The components in the input area B1 are the same as those in the first embodiment and are arranged similarly. Therefore, for the sake of brevity, these components will not be described in detail again.

[0081] In the network circuit 100 according to the second embodiment, a diode D is provided between the positive path pZ and the negative path nZ in the output region B2 downstream of the string capacitor C in the positive path pZ in the output OUT direction. Furthermore, an output coil LA is provided in the positive path pZ after the string capacitor C and the diode.

[0082] Due to the different arrangement of the output coil LA and the diode D in the output region B2 of the network circuit 100 according to the second embodiment, the DC output voltage UA and the output current IA are correspondingly inverted compared to the first embodiment of the network circuit 100. Thus, the network circuit 100 according to the second embodiment corresponds to an inverting three-phase buck-boost converter topology.

[0083] 6 shows an output region B2 of the network circuit 100 according to a first output example corresponding to the first modified example. According to the first modified example, the diode D includes at least one of a positive diode Dp of the positive path pZ and a negative diode Dn of the negative path nZ. The diode D may include only the positive diode Dp of the positive path pZ, only the negative diode Dn of the negative path nZ, or both the positive diode Dp and the negative diode Dn.

[0084] By using two diodes, a positive diode Dp in the positive path pZ and a negative diode Dn in the negative path nZ, the output area B2 of the network circuit 100 can be separated so that the DC output voltage UA is kept at the ground symmetric potential regardless of the clock. Active diodes in the form of transistors can also be used to improve efficiency. Thus, the network circuit 100 according to the first variant can be realized using only the positive diode Dp in the positive path pZ, only the negative diode Dn in the negative path nZ, or both the positive diode Dp and the negative diode Dn.

[0085] 7A and 7B show an output region B2 (FIG. 7A) of the network circuit 100 according to the first output example and an output region B2 (FIG. 7B) of the network circuit 100 according to the second embodiment example corresponding to the second modified example. According to the second modified example, the string capacitor C includes at least one of the positive string capacitor Cp of the positive path pZ and the negative string capacitor Cn of the negative path nZ. The string capacitor C may include only the positive strand capacitor Cp of the positive path pZ, only the negative strand capacitor Cn of the negative path nZ, or both the positive strand capacitor Cp and the negative strand capacitor Cn.

[0086] The advantage of splitting the string capacitor C is that the output OUT is capacitively isolated from the input IN of the network circuit 100. During operation, a high voltage is generated across the string capacitor C. By splitting the string capacitor C into a positive string capacitor Cp and a negative string capacitor Cn, the voltage is halved, allowing the use of capacitors with lower dielectric strength. It should be noted that the positive terminal capacitor Cp and the negative terminal capacitor Cn correspond to a series connection. To obtain the same total capacitance with the positive string capacitor Cp and the negative string capacitor Cn as a single string capacitor C, the positive string capacitor Cp and the negative string capacitor Cn must be twice as large as the string capacitor C.

[0087] 8 shows an output region B2 of the network circuit 100 according to a second output example corresponding to the third modified example. According to the third modified example, the output coil LA includes at least one of the positive output coil LAP of the positive path pZ and the negative output coil LAn of the negative path nZ. The output coil LA may include only the positive output coil LAP of the positive path pZ, only the negative output coil LAn of the negative path nZ, or both the positive output coil LAP and the negative output coil LAn.

[0088] FIG. 9 shows the output area B2 of the network circuit 100 according to a second output example corresponding to the fourth variant. The fourth variant can be considered as a further variant of the third variant according to FIG. 8. According to the fourth variant, the output area B2 of the network circuit 100 according to FIG. 8 is extended by a positive decoupling diode EDp and a negative decoupling diode EDn. The positive decoupling diode EDp is provided downstream of the positive output coil LAp to the output OUT of the positive path pZ. The negative decoupling diode EDn is provided downstream of the negative output coil LAn to the output OUT of the negative path nZ.

[0089] 10 and 11 show a multi-channel structure of a network circuit 100 according to a first example embodiment (FIG. 10) and a multi-channel structure of a network circuit 100 according to a second example embodiment (FIG. 11) for providing a boosted or stepped-down DC output voltage UA for use in a larger power range.

[0090] As shown, the structure of the network circuit 100 between the coupling circuit KS and the output capacitor CA is connected in multiple channels or multiple parallel connections.

[0091] The multi-channel structures of the network circuit 100 shown in Figures 10 and 11 can be operated synchronously or according to the well-known interleaving principle, in which the individual structures offset their clocks from each other. For example, in a two structure or two channel design, the clocking is typically offset by half a period. For example, in n structures, the clocking is offset by n shifts within one period. The clocking or control is performed via a control unit SE.

[0092] The star point SP, realised by the three star capacitors CYL1, CYL2, CYL3, serves as a common reference point for all capacitors CS of the structures. The neutral conductor present in a four-wire three-phase system can also be used as a reference point. Alternatively, each structure can provide an independent midpoint M or star point SP to the capacitor CS via a capacitor, i.e. three separate star capacitors are provided for each structure upstream of the storage chokes LL1, LL2, LL3.

[0093] The capacitor CS at the midpoint M is particularly charged by a special type of control of the control input AN of at least one of the first transistor T1 and the second transistor T2 by the control unit SE. The charging of the capacitor CS corresponds to at least one of precharging, charging, recharging and discharging. The type of charging of the capacitor CS depends on the network variables detected by the network detection part NE and the output detection part AE.

[0094] The capacitor voltage uCS of the capacitor CS modulates the coil voltages uLL1, uLL2, uLL3 so that sinusoidal phase currents iNL1, iNL2, iNL3 are extracted from the phases L1, L2, L3 of the power supply network VN. In other words, the capacitor voltage uCS of the capacitor CS, specially adjusted to the network variables, is used to dynamically compensate the deviations of the coil voltages uLL1, uLL2, uLL3 of the storage chokes LL1, LL2, LL3 so that sinusoidal phase currents iNL1, iNL2, iNL3 are extracted from the phases L1, L2, L3 of the power supply network VN in order to comply with the PFC standard. The compensation is dynamic, since the level of the capacitor voltage uCS depends on the control of the first transistor T1 and the second transistor T2 by the control unit SE, which control depends on the network variables detected by the network detection unit NE and the output detection unit AE.

[0095] The level of the capacitor voltage uCS therefore depends on the pulse duty factor or duty cycle TV, as explained below. Due to the modulation, the phase currents iNL1, iNL2, iNL3 are essentially sinusoidal currents or have an essentially sinusoidal progression, corresponding to the PFC standard in all power ranges. The modulation corresponds to pulse width modulation, pulse frequency modulation or other known modulation methods. A sinusoidal current is extracted from the power supply network VN at the input of the network circuit 100.

[0096] By charging the capacitor CS according to a special control type, the capacitor CS acts as an adjustable voltage source for generating a voltage difference between the storage chokes LL1, LL2, LL3. The voltage difference between the storage chokes LL1, LL2, LL3 can be influenced by the charging of the capacitor CS in the corresponding time periods as shown in Fig. 12 to Fig. 26C, and a larger coil voltage uLL1, uLL2, uLL3 is applied to the storage chokes LL1, LL2, LL3 than is physically provided by the power supply network VN. As a result, in all phases L1, L2, L3, an essentially sinusoidal current is extracted from the power supply network VN, which allows compliance with the limit values ​​of the PFC standard in the corresponding power class.

[0097] For this purpose, the first transistor T1 and the second transistor T2 receive control signals ST1, ST2 from the control unit SE, respectively, depending on the detected network variables, by which the first transistor T1 and the second transistor T2 are clocked. Due to the clocking resulting from the control of the transistors T1, T2 by the control unit SE, different time intervals are determined, such as the switch-on period TE of the first transistor T1, the switch-on period TE of the second transistor T2, and the short-circuit period TK, which defines the short-circuit range in which both transistors T1, T2 are simultaneously switched on or conducted. The remaining time, during which the first transistor T1 or the second transistor T2 is not switched on or conducted, is defined as the switch-off period TA. The sum of the switch-on period TE and the switch-off period TA forms the period TS. Depending on the order of the time intervals, a distinction is made between positive and negative control. This special timing is explained in more detail below with reference to figures 12 and 13. The control unit SE adjusts the modulation by the length of the time intervals. At the same time, the length of the time intervals and the short-circuit period TK are used to control the level of the DC output voltage UA. The capacitor CS is charged during a time interval. The charging is performed relative to the star point SP.

[0098] In one example, one of the time intervals (switch-on period TE, switch-off period TA) can be shorter than the other one of the time intervals. This allows the network circuit 100 to be set for a nicely regulated DC output voltage UA or for PFC-compliant sinusoidal current extraction. This allows a first clock period TS1 to be set in which the network currents iNL1, iNL2, iNL3 are sufficiently compliant with the PFC limits by reducing the harmonics, or to reduce the harmonics. The DC output voltage UA can be kept stable in the subsequent second clock period TS2. In a further non-limiting example, a third clock period TS3 can be added to achieve further improvement. Furthermore, all clock periods can be set such that the network circuit 100 is set only for a nicely regulated DC output voltage UA or for PFC-compliant sinusoidal current extraction.

[0099] FIG. 12 shows the progression of a first control signal ST1 for the first transistor T1 and a second control signal ST2 for the second transistor T2 based on positive control of the first transistor T1 and the second transistor T2 over time t.

[0100] In the positive control, the control inputs AN of the first and second transistors T1, T2 are controlled by the control unit SE in such a way that the first transistor T1 is conductive during a switch-on period TE between the first time point t1 and the third time point t3, and then the second transistor T2 is conductive during a switch-on period TE between the second time point t2 and the fourth time point t4. During the short-circuit period TK between the second time point t2 and the third time point t3, the first and second transistors T1, T2 are simultaneously conductive. While the first control signal ST1 is zero, the first transistor T1 is non-conductive. The first transistor T1 is non-conductive during a switch-off period TA from the third time point t3 of the current period TS consisting of the sum of the switch-on period TE and the switch-off period TA to the first time point t1 of the next period, during which the first transistor T1 is not controlled by the control unit SE. While the second control signal ST2 is zero, the second transistor T2 is non-conductive. The second transistor T2 is non-conducting in a switch-off period TA from a fourth time point t4 of the current cycle period TS to a second time point t2 of the next cycle period, during which the second transistor T2 is not controlled by the control unit SE.

[0101] The reciprocal of the cycle duration TS is the clock frequency fS, i.e. fS=1 / TS, at which the first transistor T1 and the second transistor T2 are clocked through the control of the control unit SE. It should be noted that the clocking must be performed at a clock frequency fS that is sufficiently high compared to the network frequency fN in order to minimize the effort required to filter harmonics generated by the clocking.

[0102] FIG. 13 shows the progression of the first control signal ST1 for the first transistor T1 and the progression of the second control signal ST2 for the second transistor T2 based on the negative control of the first transistor T1 and the second transistor T2 over time t.

[0103] In negative control, the switch-on period TE, the switch-off period TA, the short circuit period TK and the switching period TS correspond to those of positive control with the difference that they start and end at different times, i.e. the switch-on period TE, the switch-off period TA, the short circuit period TK and the switching period TS are the same as those of positive control.

[0104] In the negative control, the control inputs AN of the first and second transistors T1, T2 are controlled by the control unit SE such that the second transistor T2 is conductive during a switch-on period TE between the first time point t1 and the third time point t3, and then the first transistor T1 is conductive during a switch-on period TE between the second time point t2 and the fourth time point t4. In the short-circuit period TK between the second time point t2 and the third time point t3, the first and second transistors T1, T2 are simultaneously conductive. The first transistor T1 is non-conductive during a switch-off period TA from the fourth time point t4 of the current period TS to the second time point t2 of the next period, during which the first transistor T1 is not controlled by the control unit SE. The second transistor T2 is non-conductive during a switch-off period TA from the third time point t3 of the current period TS to the first time point t1 of the next period, during which the second transistor T2 is not controlled by the control unit SE.

[0105] In negative control, it is also important to ensure that the clock frequency fS is sufficiently high compared to the network frequency fN.

[0106] The DC output voltage UA can be arbitrarily controlled via the duty cycle TV or period TS from the switch-on period TE to the switch-off period TA of the first and second transistors T1, T2 and in combination with the short-circuit period TK.

[0107] Through special positive and negative controls with the network circuit 100, a DC output voltage UA that is lower (step-down) or higher (step-up) than the standard three-phase rectification can be generated from the AC power supply voltage uN. This means that during step-up, the DC output voltage UA becomes higher than the AC power supply voltage uN, and during step-down, the DC output voltage UA becomes lower than the AC power supply voltage uN. The level of the DC output voltage UA depends on the clocking, and the change between step-up and step-down is continuously possible. Not only are the step-up and step-down of the DC output voltage UA caused by the clocking, but also the sinusoidal phase currents iNL1, iNL2, iNL3 are simultaneously extracted from the power network VN by coupling. Using the network circuit 100 enables a smooth transition between step-down (UA < uN) and step-up (UA > uN), and while complying with the PFC standard, the DC output voltage UA can be appropriately adjusted within a wide voltage range such as from 0 volts to 1000 volts.

[0108] The step-up and step-down in the network circuit 100 are determined by the length of the switch-on period TE or the short-circuit period TK. Due to the physical relationships within the network circuit 100 in the control laws shown in FIGS. 12 and 13, when the short-circuit period TK is short, the DC output voltage UA becomes low and step-down occurs. Furthermore, when the short-circuit period TK is short, the sinusoidal shape of the phase currents iNL1, iNL2, iNL3 is improved and complies with the PFC standard. The transition of the sine wave of the minimum harmonic of the phase currents iNL1, iNL2, iNL3 is almost achieved when the short-circuit period TK is less than 0.1 of the switch-on period TE, that is, TK < 0.1 × TE. When the short-circuit period TK is slightly changed with the same switch-on period TE, a large change occurs in the DC output voltage UA, but by changing the switch-on period TE with the same ratio of the short-circuit period TK, the DC output voltage UA can be finely adjusted or adjusted.

[0109] A longer short circuit period TK is required for boosting. With a longer short circuit period TK, the phase currents iNL1, iNL2, iNL3 will have a sinusoidal shape that deviates from the optimal sinusoidal shape. The minimum harmonic sinusoidal course of the phase currents iNL1, iNL2, iNL3 is approximately achieved when the short circuit period TK is 0.2-0.3 of the switch-on period TE, i.e. TK=0.2···0.3×TE. The longer the short circuit period TK, the higher the DC output voltage UA. In the case of boosting as well, a small change in the short circuit period TK with the same switch-on period TE will result in a large change in the DC output voltage UA. Moreover, by changing the switch-on period TE with the same percentage of the short circuit period TK, the DC output voltage UA can be fine-tuned or adjusted.

[0110] It should be noted that the load connected to the output OUT also influences the switch-on period TE and the short-circuit period TK, which therefore typically depend on the desired DC output voltage UA, the AC mains voltage uN and the associated dimensions of the network circuit 100.

[0111] Figures 14 to 17 show various characteristic curves based on the control laws according to Figures 12 and 13 for controlling the first and second transistors T1 and T2 of the network circuit 100 in steady state according to the first embodiment example of Figure 3. For better understanding, the progressions of the control signals ST1, ST2 in Figures 12 and 13 are also shown so that the time points of the respective time intervals can be determined. The progressions of the first and second control signals ST1 and ST2 are not repeated below for the sake of brevity.

[0112] 14 to 17 show the output current IA, the output capacitor current iCA, the diode current iD of the diode D including at least one of the positive diode Dp and the negative diode Dn, the output coil current iLA, the output coil voltage uLA, the string capacitor current iC, the string capacitor voltage uC, the coil current iLL1, the coil current iLL23 corresponding to the sum of the coil currents iLL2 and iLL3, the coil voltage uLL1, the overlapping coil voltages uLL2 and uLL3, the capacitor voltage uCS, and the capacitor current iCS over time t. The output current IA is kept constant over the entire period TS at a value greater than zero amperes.

[0113] 14 and 15 show various characteristic curves resulting from positive control and negative control for boosting in the network circuit 100 according to the first embodiment.

[0114] FIG. 14 shows basic characteristic curves in positive control as a function of the clocking of the first and second transistors T1, T2 of the network circuit 100 during boosting over time t. An exemplary assumption is that the string voltages u2 and u3 at phases L2 and L3 are equal in magnitude and greater than 0 volts, while the string voltage u1 at phase L1 is less than 0 volts. The storage chokes LL2 and LL3 are therefore connected to the first transistor T1 via the positive path pZ of the rectifier GR. The rectifier diodes D3 and D5 are conducting. Meanwhile, the storage choke LL1 is connected to the second transistor T2 via the negative path nZ of the rectifier GR. The rectifier diode D2 is conducting. These assumptions are exemplary and apply to the characteristic curves described below with a two-phase AC mains voltage greater than zero. The selected assumptions are not intended to limit the scope of the invention and can be made in other ways.

[0115] 22A, at the beginning of step S0A of the cycle period TS at a first time point t1, the capacitor CS is negatively charged (uCS<0) and the string capacitor C is positively charged (uC>0). At the first time point t1, in step S1A, the first transistor T1 is turned on or turned on. As a result, the voltage difference resulting from the AC source voltage uN and the capacitor voltage uCS of each phase appears as coil voltages uLL2 and uLL3 at the storage chokes LL2 and LL3. The values ​​of the coil voltages uLL2 and uLL3 are correspondingly quantitatively greater than the value of the AC source voltage uN of the phases L2 and L3 relative to zero potential. As a result, in step S2A, current begins to accumulate in the storage chokes LL2 and LL3, and the coil currents iLL2 and iLL3 increase positively. The positively increased capacitor current iCS discharges the capacitor CS to the capacitor voltage uCS=0V. The coil current iLL23, which is the sum of the coil currents iLL2 and iLL3 of the storage chokes LL2 and LL3, increases positively in response to the capacitor current iCS until a second time point t2.

[0116] At a second time t2, in step S3A, the second transistor T2 is turned on and the first transistor T1 is also turned on. The second transistor T2 is triggered to be turned on by the control unit SE when a set time has elapsed or when the capacitor voltage uCS is equal to zero volts. As a result, the rectifier GR is short-circuited for a short-circuit period TK, which corresponds to the short-circuit range shown in Figs. 12 and 13. From this second time t2, in step S4A, the capacitor CS is positively charged from a discharged state, and the capacitor current iCS decreases (towards zero) quantitatively from the second time t2. Meanwhile, the coil currents iLL2 and iLL3 of the storage chokes LL2 and LL3 continue to be positively stored or to increase positively during the short-circuit period TK.

[0117] When the second transistor T2 is controlled, the voltage difference between the AC power supply voltage uN of phase L1 and the current value of the capacitor voltage uCS is applied to the storage choke LL1 as the coil voltage uLL1. The value of the coil voltage uLL1 is correspondingly quantitatively larger (more negative) than the value of the AC power supply voltage uN of phase L1 relative to zero potential. Thus, from this point on, negative current accumulation of the coil current iLL1 begins in the storage choke LL1.

[0118] Due to the short circuit caused by the transistors T1 and T2, a negative output coil voltage uLA is applied to the output coil LA. Therefore, a negative output coil current iLA is accumulated in the output coil LA during the short circuit period TK. The quantitative negative increase in the output coil current iLA generates a positive flow of the string capacitor current iC to the string capacitor C, which starts discharging the string capacitor C from the second time point t2. Therefore, the string capacitor voltage uC of the string capacitor C is quantitatively decreased.

[0119] During this period, the main part of the energy input to the network circuit 100 occurs. The second transistor T2 is controlled when the capacitor voltage uCS goes to zero volts, or alternatively, is controlled.

[0120] At a third time t3, in step S5A, the first transistor T1, which is conductive at time t1, is switched off or made non-conductive again by the control unit SE after the switch-on period TE. The second transistor T2 remains conductive. From the third time t3, the storage chokes LL2 and LL3, in which positive coil currents iLL2, iLL3 have been stored during the switch-on period TE of the first transistor T1, control these coil currents iLL2, iLL3 on the input side via the rectifier diodes D3, D5, the string capacitor C, and on the output side via the diodes D, which include at least one of the positive diode Dp and the negative diode Dn, and the load path or output OUT. Thus, in step S6A, the coil currents iLL2 and iLL3 of the storage chokes LL2 and LL3 are reduced again. Since the second transistor T2 is still conducting at this point, the sum of the coil currents iLL2, iLL3 through the load path is temporarily divided at the node below the second transistor T2 between the storage choke LL1, in which the coil current iLL1 continues to accumulate, and the capacitor CS. The capacitor current iCS further decreases significantly from the time t3.

[0121] When the first transistor T1 is turned off, the output coil voltage uLA (uLA<0V) of the output coil LA, which had been negative up until then, suddenly changes to positive (uLA>0V). Therefore, the negative output coil current iLA stored in the output coil LA starts decreasing again in the direction of zero amperes.

[0122] The string capacitor current iC of the string capacitor C changes suddenly from a value greater than zero amperes (iC>0) to a value less than zero amperes (iC<0) due to a decrease in the output coil current iLA of the output coil LA, and decreases quantitatively from the third time point t3 to the time point t3L. Therefore, the string capacitor voltage uC increases quantitatively from the third time point t3.

[0123] At time t3', the maximum positive capacitor voltage uCS is reached when the capacitor current iCS is at zero amperes, iCS=0A. From this time t3', in step S7A, a negative flow of the capacitor current iCS through the capacitor CS is established. From time t3', the capacitor CS is discharged until a fifth time t5, at which it is charged negatively again. From time t3', the negative capacitor current iCS is added to the flow to the storage choke LL1 of the sum of the coil currents iLL2, iLL3 of the storage chokes LL2 and LL3.

[0124] The output capacitor CA is charged with energy after the first transistor T1 is turned off at time t3 until time t5L, when the energy stored in the storage chokes LL1, LL2, LL3 is completely consumed. During the remaining time period TS, the energy stored in the output capacitor CA is transferred to the load connected to the output OUT.

[0125] Due to step S8A at time t3L, the coil currents iLL2 and iLL3 of the storage chokes LL2 and LL3 are completely consumed. The coil currents iLL2 and iLL3 correspond to zero amperes at time t3L. The output coil current iLA in the output area B2 of the network circuit 100 is completely controlled by the output coil LA from time t3L, and the negative output coil current iLA continues to decrease in amount. As a result, no current flows between the input IN and the output OUT of the network circuit 100, and therefore no further current flows in the string capacitor C. The string capacitor voltage uC remains constant until time t4. The total negative capacitor current iCS continues to flow through the storage choke LL1 from time t3L, and as a result, the coil current iLL1 continues to increase negative in amount.

[0126] At the fourth time t4, the second transistor T2, which is still conducting, is controlled by the switching unit SE after the switch-on period TE, so that the second transistor T2 becomes non-conductive. From the fourth time t4, the storage choke LL1 again controls the coil current iLL1 via the string capacitor C, the diode D, which includes at least one of the positive diode Dp and the negative diode Dn, and the load connected to the output of the network circuit 100, and the coil current iLL1 is added to the output coil current iLA of the output coil LA, which continues to decay. From the fourth time t4, the capacitor current iCS flows via the only remaining current path in the form of the body diode of the first transistor T1 (or a freewheeling diode connected in parallel thereto) and is quantitatively reduced again from the fourth time t4. As a result, the capacitor voltage uCS of the capacitor CS is charged to its original negative value, as before the first time t1. At the same time, the positive coil currents iLL2 and iLL3 start to accumulate again in the two storage chokes LL2 and LL3.

[0127] Due to the coil current iLL1 controlled by the storage choke LL1 via the output OUT, a current again flows between the input IN and the output OUT of the network circuit 100 in step S10A, and as a result, a current flows through the string capacitor C. The string capacitor current iC jumps from a value of 0 amperes to a negative value (iC<0A) at the fourth time point t4 and decreases quantitatively from the fourth time point t4. The capacitor voltage uC therefore increases quantitatively from the fourth time point t4.

[0128] At the fifth time t5, in step S11A, the value of the coil current iLL1 of the storage choke LL1 corresponds to the sum of the values ​​of the coil currents iLL2 and iLL3 of the storage chokes LL2 and LL3. This results in a zero ampere capacitor current iCS, i.e. iCS=0A. As a result, from the fifth time t5, no current flows through the freewheeling diode of the first transistor T1. From this fifth time t5, in step S12A, the capacitor CS is fully charged to the negative initial value of the capacitor voltage uCS and is available again for the next period TS. The storage chokes LL1, LL2, LL3 continue to control the current through the output OUT, which is added to the output coil current iLA of the output coil LA until the time t5'. The remaining coil currents iLL1, iLL2, iLL3 decrease linearly with time until the time t5L.

[0129] At time t5L, the output coil current iLA of the output coil LA is completely consumed, and the coil currents iLL1, iLL2, and iLL3 of the storage chokes LL1, LL2, and LL3 are also consumed. As a result, no current flows between the input IN and the output OUT of the network circuit 100, and therefore no string capacitor current iC flows through the string capacitor C. From time t5L, the string capacitor voltage uC is fully charged to a positive value that can be used again in the next period TS.

[0130] The value of the coil current iLL1=iLL2=iLL3=0 at time t5L can be reached before the end of the cycle period TS in the discontinuous conduction mode, or at the end of the cycle period TS in the boundary conduction mode. The value of the output coil current iLA=0 at time t5' can also be reached before the end of the cycle period TS, or at the end of the cycle period TS. This does not affect the operation of the network circuit 100 with respect to the boundary conduction mode or the discontinuous conduction mode.

[0131] In boundary conduction mode, the inductor current iLL1, iLL2, or iLL3 goes to exactly zero amps at the end of the period TS. In discontinuous conduction mode, a pause is inserted (the current is "interrupted" or discontinuous) between the decrease in current and the start of the new period TS. Discontinuous conduction mode and boundary conduction mode are standard when using boost converters.

[0132] FIG. 15 shows the basic characteristic curves of the negative control as a function of the clocking of the first and second transistors T1, T2 of the network circuit 100 during boosting over time t. An exemplary assumption is that the string voltage u1 of the phase L1 is greater than zero volts, and the string voltages u2 and u3 of the phases L2 and L3 are quantitatively equal and less than zero volts. The storage choke LL1 is therefore connected to the first transistor T1 via the positive path pZ of the rectifier GR. The rectifier diode D1 is conducting. Meanwhile, the storage chokes LL2 and LL3 are connected to the second transistor T2 via the negative path nZ of the rectifier GR. The rectifier diodes D4 and D6 are conducting. These assumptions are exemplary and apply to the characteristic curves described below with two-phase network voltages less than zero. The selected assumptions are not intended to limit the scope of the invention and can be made in other ways.

[0133] 22B, at the beginning of step S0B, the capacitor CS is positively charged (uCS>0), and the string capacitor C is also positively charged (uC>0). At a first time t1, in step S1B, the second transistor T2 is turned on or turned on. As a result, the voltage difference resulting from the AC supply voltage uN of each phase and the capacitor voltage uCS is applied to the storage chokes LL2 and LL3 as coil voltages uLL2 and uLL3. The values ​​of the coil voltages uLL2 and uLL3 are correspondingly quantitatively greater than the value of the AC supply voltage uN of the phases L2 and L3 relative to zero potential. As a result, in step S2B, current begins to accumulate in the storage chokes LL2 and LL3, and the coil currents iLL2 and iLL3 increase negatively. The capacitor CS is discharged by the negatively increasing capacitor current iCS to the capacitor voltage uCS=0V. The coil currents iLL2 and iLL3 of the storage chokes LL2 and LL3 increase negatively in response to the capacitor current iCS until a second time point t2.

[0134] At a second time point t2, in step S3B, the first transistor T1 is turned on and the second transistor T2 is turned on as well. As a result, the rectifier GR is short-circuited for a short-circuit period TK corresponding to the short-circuit range shown in Figures 12 and 13. In step S4B, from this second time point t2, the capacitor CS is negatively charged from a discharged state, and the capacitor current iCS decreases (towards zero) from the second time point t2.

[0135] By controlling the first transistor T1, the voltage difference resulting from the AC power supply voltage uN of phase L1 and the current value of the capacitor voltage uCS is applied to the storage choke LL1 as a coil voltage uLL1.

[0136] Therefore, the value of the coil voltage uLL1 becomes quantitatively larger (more positive) than the value of the AC supply voltage uN of phase L1 relative to zero potential. Therefore, from this point on, a positive current accumulation of the coil current iLL1 begins in the storage choke LL1.

[0137] Due to the short circuit through the transistors T1 and T2, a negative output coil voltage uLA is applied to the output coil LA. Thus, a negative output coil current iLA is accumulated in the output coil LA during the short circuit period TK. As the magnitude of the output coil current iLA increases negatively, a positive flow of the string capacitor current iC to the string capacitor C occurs, which causes the string capacitor C to start discharging from the second time point t2. Thus, the string capacitor voltage uC of the string capacitor C decreases quantitatively.

[0138] During this period, the main part of the energy input to the network circuit 100 takes place. The control of the first transistor T1 can be controlled arbitrarily or can take place when the capacitor voltage uCS becomes zero volts.

[0139] At a third time t3, in step S5B, the second transistor T2, which is conducting at time t1, is switched off again by the control unit SE after a switch-on period TE. The first transistor T1 remains conducting. From the third time t3, the storage chokes LL2 and LL3, in which negative coil currents iLL2 and iLL3 have been stored during the switch-on period TE of the second transistor T2, control these coil currents iLL2 and iLL3 on the input side via the rectifier diodes D4, D6 and the string capacitor C, and on the output side via the diode D and the load path, which includes at least one of the positive diode Dp and the negative diode Dn. Thus, in step S6B, the coil currents iLL2 and iLL3 of the storage chokes LL2 and LL3 are reduced again. Since the first transistor T1 is still conducting at this point, the negative flow of the capacitor current iCS through the capacitor CS temporarily adds a positive current to the sum of the coil currents from iLL2 and iLL3 at the nodes upstream of the first transistor T1. The capacitor current iCS increases further rapidly from time t3.

[0140] When the second transistor T2 is turned off, the output coil voltage uLA (uLA<0 V) of the output coil LA, which had been negative up until then, suddenly changes to positive (uLA>0 V). In response to this, the negative output coil current iLA stored in the output coil LA starts to decrease again in the direction of zero amperes.

[0141] The string capacitor current iC of the string capacitor C abruptly changes from a value greater than zero amperes (iC>0) to a value less than zero amperes (iC<0) due to a decrease in the output coil current iLA of the output coil LA, and decreases from the third time point t3 to the time point t3L. Therefore, the string capacitor voltage uC increases quantitatively from the third time point t3.

[0142] The maximum positive capacitor voltage uCS is reached at time t3' when the capacitor current iCS is zero amperes, iCS=0A. From this time t3', in step S7B, a positive capacitor current iCS is established through the capacitor CS. The capacitor CS is discharged again. From time t3', the positive capacitor current iCS in the capacitor CS is subtracted from the coil current iLL1 of the storage choke LL1. The remaining current flows through the coils LL2 and LL3.

[0143] Due to step S8B at time t3L, the coil currents iLL2 and iLL3 of the storage chokes LL2 and LL3 are completely decreased. The coil current iLL23 corresponds to zero amperes at time t3L. The output coil current iLA of the output area B2 of the network circuit 100 is completely controlled by the output coil LA from time t3L, and the negative output coil current iLA continues to decrease in amount. As a result, no current flows between the input IN and the output OUT of the network circuit 100, and therefore no further current flows in the string capacitor C. The string capacitor voltage uC remains constant until time t4. The total positive capacitor current iCS continues to flow through the storage choke LL1 from time t3L, and as a result, the coil current iLL1 continues to increase in amount to be positive.

[0144] At the fourth time t4, in step S9B, the still conducting first transistor T1 is controlled by the switching unit SE so that after the switch-on period TE the first transistor T1 is made non-conductive. From the fourth time t4, the storage choke LL1 again controls the coil current iLL1 via the string capacitor C, the diode D including at least one of the positive diode Dp and the negative diode Dn and the load connected to the output of the network circuit 100, which coil current iLL1 is added to the output coil current iLA of the output coil LA, which continues to decay. From the fourth time t4, the capacitor current iCS flows via the only remaining current path in the form of the body diode of the second transistor T2, which is initially switched off (or a freewheeling diode connected in parallel thereto), and its value is quantitatively reduced again from the fourth time t4. As a result, the capacitor voltage uCS of the capacitor CS is charged to its original positive value, as before the first time t1. At the same time, the negative coil currents iLL2 and iLL3 start to accumulate again in the two storage chokes LL2 and LL3.

[0145] Due to the coil current iLL1 controlled by the storage choke LL1 via the output OUT, in step S10B, a current flows again between the input IN and the output OUT of the network circuit 100, and a current flows through the string capacitor C. The string capacitor current iC abruptly changes from a value of 0 amperes to a negative value (iC<0A) at the fourth time point t4 and decreases quantitatively from the fourth time point t4. The capacitor voltage uC therefore increases quantitatively from the fourth time point t4.

[0146] At the fifth time t5, in step S11B, the amount of the coil current iLL1 of the storage choke LL1 corresponds to the sum of the amounts of the coil currents iLL2 and iLL3 of the storage chokes LL2 and LL3. This results in a zero ampere capacitor current iCS, i.e. iCS=0A. As a result, from the fifth time t5, no current flows through the freewheeling diode of the second transistor T2. From this fifth time t5, in step S12B, the capacitor CS is fully charged to the positive initial value of the capacitor voltage uCS and is available again for the next period TS. The storage chokes LL1, LL2, LL3 continue to control the current through the output OUT, which is added to the output coil current iLA of the output coil LA until the time t5'. The remaining coil currents iLL1, iLL2, iLL3 decrease linearly with time until the time t5L.

[0147] At time t5L, the output coil current iLA of the output coil LA is completely consumed, and the coil currents iLL1, iLL2, and iLL3 of the storage chokes LL1, LL2, and LL3 are also consumed. As a result, no current flows between the input IN and the output OUT of the network circuit 100, and therefore no string capacitor current iC flows through the string capacitor C. The string capacitor voltage uC is fully charged to a positive value from time t5L and becomes available again in the next period TS.

[0148] The value of the coil current iLL1=iLL2=iLL3=0 at time t5L can be reached before the end of the cycle period TS in the discontinuous conduction mode, or at the end of the cycle period TS in the boundary conduction mode. The value of the output coil current iLA=0 at time t5' can also be reached before the end of the cycle period TS, or at the end of the cycle period TS. This does not affect the operation of the network circuit 100 with respect to the boundary conduction mode or the discontinuous conduction mode.

[0149] 16 and 17 show different characteristic curves obtained by positive control and negative control for step-down in the network circuit 100 according to the first embodiment.

[0150] The progression of the step-down characteristic curves in Figures 16 and 17 differs from the progression of the step-up characteristic curves in Figures 14 and 15 only in that the length of the individual time intervals between the individual times t1, t2, t3, t3', t3L, t4, t5, t5', t5L is different, due to the different ratios between the short-circuit period TK and the switch-on period TE.

[0151] Since the ratio between the short circuit period TK and the switch-on period TE during positive control and negative control of the first transistor T1 and the second transistor T2 of the network circuit 100 according to the first embodiment example is different during voltage step-up (TK=0.2...0.3×TE) and voltage step-down (TK<0.1×TE), the network circuit 100 can generate a larger or smaller DC output voltage UA from the AC power supply voltage uN without any additional or downstream circuitry.

[0152] The positive and negative controls for boosting and lowering the voltage of the network circuit 100 according to the first embodiment shown in Figures 14 to 17 can be similarly used for the positive and negative controls for boosting and lowering the voltage of the network circuit 100 according to the second embodiment.

[0153] Figures 18 to 21 show different characteristic curves based on the control laws according to Figures 12 and 13 for controlling the first and second transistors T1 and T2 of the network circuit 100 in steady state according to the second embodiment example of Figure 5. For better understanding, the progression of the control signals ST1, ST2 in Figures 12 and 13 are also shown so that the time points of the respective time intervals can be determined.

[0154] Furthermore, Figures 18 to 21 show the changes in the output current IA, the changes in the output capacitor current iCA, the changes in the diode current iD of the diode D including at least one of the positive diode Dp and the negative diode Dn, the changes in the output coil current iLA, the changes in the output coil voltage uLA, the changes in the string capacitor current iC, the changes in the string capacitor voltage uC, the changes in the coil current iLL1, the changes in the coil currents iLL2 and iLL3, the changes in the coil voltage uLL1, the changes in the coil voltages uLL2 and uLL3, the changes in the capacitor voltage uCS, and the changes in the capacitor current iCS over time t.

[0155] 18 and 19 show different characteristic curves obtained by the network circuit 100 according to the second embodiment example by positive and negative control for boosting. The progression of all characteristic curves except for the output current IA and the output capacitor current iCA is the same as that of the network circuit 100 according to the first embodiment example shown in FIGS. 14 and 15, and will not be repeated for the sake of brevity.

[0156] The output current IA is held constant at less than zero amperes for the entire period TS.

[0157] Figures 20 and 21 show different characteristic curves obtained by the network circuit 100 according to the second embodiment example by positive and negative control for step-down. The progression of all characteristic curves except for the output current IA and the output capacitor current iCA is the same as that of the network circuit 100 according to the first embodiment example shown in Figures 16 and 17, and will not be repeated again for the sake of brevity.

[0158] 22A and 22B show a method of positive control (FIG. 22A) and a method of negative control (FIG. 22B) of the first transistor T1 and the second transistor T2 of the network circuit 100. These methods are based on the above-mentioned control or clocking, and accordingly apply equally to the boost and buck of the network circuit 100 (non-inverting) according to the first embodiment and the network circuit 100 (inverting) according to the first embodiment, respectively.

[0159] 23 shows the power supply network VN as a three-phase system with string voltages u1, u2, and u3 and time intervals A and B. The polarity of the capacitor charge on the capacitor CS and the capacitor voltage uCS must be taken into consideration so that the network circuit 100 can achieve step-up and step-down functions as required while complying with the PFC standard.

[0160] Looking at the progression of string voltages u1, u2, u3 of a three-phase system, there is a positive time interval A where two string voltages are greater than zero and one string voltage is less than zero, and a negative time interval B where one string voltage is greater than zero and two string voltages are less than zero. If two of the string voltages u1, u2, u3 are greater than zero, then in this positive time interval A, positive control (see FIG. 12) is used. If two of the string voltages u1, u2, u3 are less than zero, then in this negative time interval B, negative control (see FIG. 13) is used. Over time, we obtain a voltage curve SK (dashed line) that is an approximation of a triangular sinusoidal segment bounded by the time intervals A and B and moving around the zero line.

[0161] During time intervals A and B, i.e. the time when the positive or negative control is active, the string voltages u1, u2, u3 are always in the same state, i.e. greater than or less than zero, so for time intervals A and B, we can define time interval A = time interval B based on a symmetrical three-phase system.

[0162] At each zero point of the approximate triangular voltage curve SK, there is a change from positive control to negative control or from negative control to positive control. When the approximate triangular voltage curve SK moves from a negative time interval B (i.e., value less than zero) to a positive time interval A (i.e., value greater than zero), the control changes from negative control to positive control. The transition from positive / negative control to negative / positive control may occur abruptly, for example, as shown in Figure 22. However, the transition may also be smooth (not shown).

[0163] The duration of the time intervals A, B depends on the network frequency fN. In a European power supply network with a network frequency fN=50 Hz, a zero point occurs every 3.33 milliseconds in a three-phase system. This means that the system switches between positive and negative control every 3.33 milliseconds. However, the network circuit 100 is not limited to European power supply networks. In fact, the network circuit 100 can be operated with all international network voltages and frequencies.

[0164] By charging the capacitor voltage uCS, the voltage difference between the string voltage u1, u2, u3 and the capacitor voltage uCS at the storage choke LL1, LL2, LL3 can be influenced such that a larger coil voltage uLL1, uLL2, uLL3 is applied to the storage choke LL1, LL2, LL3 depending on the control of the first and second switching transistors T1, T2 by the control unit SE than is physically available from the power supply network VN. In other words, the phase currents iNL1, iNL2, iNL3 are modulated by the coil voltages uLL1, uLL2, uLL3, which are influenced by the adjustable voltage applied to the capacitor CS. This generates sinusoidal network currents iNL1, iNL2, iNL3, which are fed to the input of the rectifier GR to meet the limit values ​​of the PFC standard of the corresponding power class, as shown in Figures 25B and 27B.

[0165] In all described embodiments, the first transistor T1 and the second transistor T2 are controlled in such a way that at least one of the switch-on period TE, the short-circuit period TK and the off period TA of the first and second transistors T1, T2 acts as a degree of freedom and adjusts the DC output voltage UA to the desired value depending on the load. As a result, the DC output voltage UA is not only lowered or raised by the control but also complies with the harmonic current limit values ​​of the PFC standard, thus improving the effectiveness and energy efficiency of the network circuit and reducing the number of components, thereby reducing costs.

[0166] Figures 24A, 24B and 24C show the measured progression of the network variables of the network circuit 100 according to the first example embodiment during boost. Figure 24A shows the progression of the DC output voltage UA, Figure 24B shows the progression of the sinusoidal phase currents iNL1, iNL2, iNL3 and Figure 24C shows the progression of the AC source voltage uN including the string voltages u1, u2, u3. Boosting to a positive DC output voltage UA is achieved by sinusoidal PFC compliant current extraction.

[0167] Figures 25A, 25B and 25C show the measured progression of the network variables of the network circuit 100 according to the first example embodiment during step-down. Figure 25A shows the progression of the DC output voltage UA, Figure 25B shows the progression of the sinusoidal phase currents iNL1, iNL2, iNL3 and Figure 25C shows the progression of the AC source voltage uN including the string voltages u1, u2, u3. Step-down to the positive DC output voltage UA is achieved by sinusoidal PFC compliant current extraction.

[0168] Figures 26A-27C show the measured network variables of the network circuit 100 according to the second example embodiment for step-up and step-down, as well as the progression of the network variables in Figures 24A-25C. Figure 26A shows step-up to a negative DC output voltage UA with sinusoidal PFC compliant current extraction. Figure 27A shows step-down to a positive DC output voltage UA with sinusoidal PFC compliant current extraction. [Explanation of symbols]

[0169] 100 Network Circuit A,B Time Interval AE output detector ON control input C String Capacitor CA Output Capacitor CS Capacitor CYL1, CYL2, CYL3 Star Capacitor D Diode D1-D6 Rectifier diode Dn Negative diode Dp Positive diode e1, e2, e3 input EMI Electromagnetic Filter (Electromagnetic Interference Prevention Filter) fN Network frequency GR rectifier IA Output Current iC String Capacitor Current iCS Capacitor current iNL1,iNL2,iNL3 phase current KS coupling circuit KS coupling circuit L1, L2, L3 phase LL1, LL2, LL3 storage choke M midpoint NE Network Detector SE control unit SK voltage curve SP Star Point T1 First transistor T2 Second transistor TE Switch-On Period TC Short circuit period TS cycle period u1,u2,u3 string voltage UA DC Output Voltage uCS Capacitor voltage VN Power supply network

Claims

1. A PFC network circuit having a half bridge for converting a PFC compliant AC power supply voltage to both a lower DC output voltage and a higher DC output voltage, The three phases, a rectifier having three inputs; first and second transistors controlled by a control unit; a midpoint located between the first and second transistors; a star point having three star capacitors; a capacitor connected to the midpoint and to a reference potential, which may be either the zero potential of the network circuit or the star point of the star capacitor; an output capacitor, an output coil, a diode, and a string capacitor provided in an output region of the network circuit; three storage chokes each connected to one of the three phases and to one of the three inputs of the rectifier; the capacitor is configured to function as an adjustable voltage source by selectively charging and discharging the capacitor by controlling the first and second transistors to adjust the voltage difference between the three storage chokes to meet PFC standards; the control unit is configured to control the first transistor and the second transistor to convert an AC power supply voltage into a stepped-up or stepped-down DC output voltage according to a polarity of a string voltage; 13. A PFC network circuit, comprising: a first transistor and a second transistor, the first transistor and the second transistor being controlled by the control unit through positive control and negative control.

2. 2. The PFC network circuit according to claim 1, The PFC network circuit, wherein the diode includes at least one of a positive diode in a positive path, a negative diode in a negative path, or a positive diode and a negative diode in a positive path.

3. 3. The PFC network circuit according to claim 1, 11. The PFC network circuit, wherein the string capacitors include at least one of a positive strand capacitor in a positive string, a negative strand capacitor in a negative string, or a positive strand capacitor in a positive string and a negative strand capacitor in a negative string.

4. 4. The PFC network circuit according to claim 3, The PFC network circuit, wherein the output coil includes at least one of a positive output coil in a positive path, a negative output coil in a negative path, or a positive output coil and a negative output coil in a positive path.

5. 5. The PFC network circuit according to claim 4, A PFC network circuit, further comprising: a positive decoupling diode provided in an output region in the network circuit of a positive path; and a negative decoupling diode provided in an output region in the network circuit of a negative path.

6. 2. The PFC network circuit according to claim 1, A PFC network circuit, wherein the network circuit is formed as a multi-channel.

7. 7. The PFC network circuit according to claim 6, A PFC network circuit, characterized in that each channel of the multi-channel network circuit can operate synchronously or offset according to an interleaving principle.

8. 1. A method for converting an AC power supply voltage to both a lower DC output voltage and a higher DC output voltage while complying with PFC standards on a network circuit, comprising: controlling first and second transistors; charging and discharging a capacitor in response to said control; generating a capacitor voltage in the capacitor; affecting a voltage difference across three storage chokes by the capacitor voltage of said capacitor; Extracting sinusoidal phase currents from the power supply network in compliance with the harmonic current limits of the PFC standard, The control includes positive control and negative control, taking into account the polarity of the string voltage; the coil voltage of the storage choke corresponds to the voltage difference between the resulting capacitor voltage and the respective AC power supply voltage as a result of charging and discharging; The method of claim 1, wherein the DC output voltage is stepped up or down relative to the AC supply voltage in response to said control.

9. 9. The method of claim 8, The method according to claim 1, wherein the first transistor and the second transistor are controlled such that the DC output voltage is regulated to a desired value depending on the load, and at least one of the switch-on period, the short circuit period, and the switch-off period of the first and second transistors acts as a degree of freedom.

10. The method according to claim 8 or claim 9, The method according to claim 1, wherein the control is performed so as to comply with the harmonic current limits of the PFC standard.

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