Manufacturing method for display device

Abstract

To provide a flexible display device with high display quality and a high yield.SOLUTION: A manufacturing method includes: a first separating step including forming a first organic resin layer on a first substrate, forming a first insulating film on the first organic resin layer, forming a first element layer on the first insulating film, forming a second organic resin layer on a second substrate, forming a second insulating film on the second organic resin layer, forming a second element layer on the second insulating film, attaching the first substrate and the second substrate together so that the first element layer and the second element layer are sealed, and separating the first substrate by reducing adhesion between the first organic resin layer and the first substrate; a second separating step including bonding the first organic resin layer and the first flexible substrate together with a first adhesive layer interposed therebetween, and separating the second substrate by reducing adhesion between the second organic resin layer and the second substrate; and bonding the second organic resin layer and the second flexible substrate together with a second adhesive layer interposed therebetween.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention is a semiconductor device including an oxide semiconductor, a display device including the semiconductor device, And the present invention relates to a method for producing the same.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one aspect relates to an article, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition. Therefore, the present invention more specifically disclosed herein The technical field of one embodiment of the present invention is a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, As examples of the present invention, the present invention relates to a device, a power storage device, a storage device, a driving method thereof, or a manufacturing method thereof. Some examples include:

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. A display device or an electronic device may include a semiconductor device. [Background technology]

[0004] The technology of constructing transistors using semiconductor films formed on substrates with insulating surfaces is attracting attention. The transistor is expected to be used in devices such as integrated circuits (ICs) and image display devices (display devices). Silicon is widely used as a semiconductor thin film that can be applied to transistors. Silicon-based semiconductor materials are widely known, but oxide semiconductors are also attracting attention as other materials. There are.

[0005] For example, indium (In), gallium (Ga), and A transistor using an amorphous oxide semiconductor containing zinc (Zn) is disclosed in Patent Document 1. There are.

[0006] In addition to being thin and lightweight, displays are also desired to have improved flexibility and impact resistance. For example, Patent Document 2 discloses a film substrate on which a transistor, which is a switching element, is mounted. and a flexible active matrix type light emitting device equipped with an organic EL element. There are. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2006-165528 A [Patent Document 2] JP 2003-174153 A Summary of the Invention [Problem to be solved by the invention]

[0008] The manufacturing process for flexible displays does not seem to pose a problem when using rigid substrates. Small defects can expand during processing, resulting in a decrease in product yield. In addition, after the display device is completed, the defective area may expand due to bending or warping, resulting in deterioration of display quality and signal quality. This may reduce reliability.

[0009] Therefore, in the manufacturing method of a flexible display device, the combination of materials and appropriate processing are important. It is desirable to use a process that does not cause minute defects in the product during the process. .

[0010] Therefore, one object of one embodiment of the present invention is to provide a display device with high display quality. Another object of the present invention is to provide a highly reliable display device. One of the objects of the present invention is to provide a new display device. Another object of the present invention is to provide a method for manufacturing the display device. It shall be one.

[0011] The description of these problems does not preclude the existence of other problems. It is not necessary for the embodiment to solve all of these problems. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0012] One embodiment of the present invention is a flexible display device including a transistor using an oxide semiconductor layer, and a method for producing the same.

[0013] One embodiment of the present invention includes a first element layer and a second element layer. One of the element layers is a pixel including a first transistor having an oxide semiconductor layer and a display element. a circuit portion including a first transistor and a second transistor having an oxide semiconductor layer, The other of the second element layer and the second element layer has a colored layer and a light-shielding layer. A first organic resin layer is formed on the first substrate, and a first insulating film is formed on the first organic resin layer. A first element layer is formed on the first insulating film, and a second organic resin layer is formed on the second substrate. A second insulating film is formed on the second organic resin layer, and a second element layer is formed on the second insulating film. and bonding the first substrate and the second substrate together so that the first element layer and the second element layer are sealed. The adhesiveness between the first organic resin layer and the first substrate is reduced, and the first substrate is separated. A first separation step is performed, and the first organic resin layer and the first flexible substrate are bonded via a first adhesive layer. and a second organic resin layer is attached to the second substrate, thereby reducing adhesion between the second organic resin layer and the second substrate, thereby separating the second substrate. The second organic resin layer and the second flexible substrate are bonded to each other via a second adhesive layer. The present invention relates to a method for manufacturing a display device.

[0014] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components. It should be noted that the numbers are added for the purpose of illustration only and are not intended to be limiting.

[0015] The first organic resin layer and the second organic resin layer are made of an epoxy resin, an acrylic resin, or a polyimide. It can be made of a material selected from the group consisting of resin, polyamide resin, and polyamide-imide resin. can.

[0016] A decrease in adhesion between the first organic resin layer and the first substrate, and a decrease in adhesion between the second organic resin layer and the first substrate The reduction in adhesion between the first substrate and the second substrate is preferably performed by irradiating a linear excimer laser beam. stomach.

[0017] The excimer laser light is a laser light obtained by synthesizing laser light output from a plurality of oscillators. Preferably it is light.

[0018] The second separation step is to separate the first flexible substrate by contacting the first flexible substrate with a curved surface of a roller. It is preferable to do so.

[0019] The first insulating film and the second insulating film may be a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a silicon nitride film. It is preferable that the insulating layer includes a silicon oxide film or a silicon oxynitride film.

[0020] The oxide semiconductor layer is In-M-Zn oxide (M is Al, Ti, Ga, Y, Zr, La, C In addition, the oxide semiconductor layer is oriented along the c-axis. It is preferable to have crystals that

[0021] The display element may be an organic EL element.

[0022] Another aspect of the present invention is a liquid crystal display device comprising: a first flexible substrate; a first adhesive layer; a first organic resin layer; A pixel including a first transistor having a first insulating film, an oxide semiconductor layer, and a display element a first element having a circuit portion including a second transistor having an oxide semiconductor layer; a second element layer having a colored layer and a light-shielding layer; a second insulating film; and a second organic resin. a first adhesive layer, a second adhesive layer, and a second flexible substrate are laminated in the above order. The display device is as follows.

[0023] The oxide semiconductor layer of the first transistor is a single layer, and the oxide semiconductor layer of the second transistor is a single layer. The compound semiconductor layer may be multi-layered.

[0024] The oxide semiconductor layer of the first transistor is a second transistor having an oxide semiconductor layer. It is preferable that the composition of the layer be the same as that of the layer in contact with the gate insulating film of the transistor. Effect of the Invention

[0025] By using one embodiment of the present invention, a display device with high display quality can be provided. Alternatively, a highly reliable display device can be provided. Alternatively, a novel display device, etc. Alternatively, a manufacturing method of the display device can be provided. Alternatively, a manufacturing method for a display device with high yield can be provided.

[0026] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. Effects other than these may also be included. The above is self-evident from the description, drawings, claims, etc. Other effects can be extracted from the claims and other descriptions. [Brief description of the drawings]

[0027] [Figure 1] FIG. [Diagram 2] FIG. 1 is a cross-sectional view illustrating a display device. [Diagram 3] FIG. 1 is a cross-sectional view illustrating a display device. [Figure 4] 1A to 1C are cross-sectional views illustrating a method for manufacturing a display device. [Diagram 5] 1A to 1C are cross-sectional views illustrating a method for manufacturing a display device. [Figure 6] FIG. 1 is a diagram for explaining an example of a processing device using an excimer laser. [Figure 7] FIG. [Figure 8] FIG. [Figure 9] FIG. [Figure 10] FIG. [Figure 11] FIG. 2 is a diagram showing an example of a peeling device. [Figure 12] FIG. [Figure 13] FIG. [Figure 14] FIG. [Figure 15] FIG. [Figure 16] FIG. [Figure 17] 1A and 1B are a block diagram and a circuit diagram illustrating a display device. [Figure 18] FIG. 2 is a diagram illustrating a display module. [Figure 19] 1 is a cross-sectional view illustrating a transistor. [Figure 20] 1 is a cross-sectional view illustrating a transistor. [Figure 21] Cs-corrected high-resolution TEM image of a cross section of CAAC-OS, and a schematic cross-sectional diagram of CAAC-OS. [Figure 22] Cs-corrected high-resolution TEM image of the CAAC-OS in the plane. [Diagram 23] 13A to 13C show structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. [Figure 24] 1A to 1C are diagrams illustrating electronic devices. [Diagram 25] 1 is a cross-sectional view illustrating a transistor. [Figure 26] 1 is a cross-sectional view illustrating a transistor. [Figure 27] 1 is a cross-sectional view illustrating a transistor. [Figure 28] 1 is a cross-sectional view illustrating a transistor. [Figure 29] 1 is a cross-sectional view illustrating a transistor. [Diagram 30] FIG. 1 is a cross-sectional view illustrating a display device. [Diagram 31] FIG. 1 is a cross-sectional view illustrating a display device. [Diagram 32] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor. [Diagram 33] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor. [Diagram 34] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor. [Diagram 35] 1 is a cross-sectional view illustrating a transistor. [Diagram 36] FIG. 4 is a diagram illustrating the temperature dependence of resistivity. [Figure 37] 1 is a cross-sectional view illustrating a transistor. [Figure 38] 1 is a cross-sectional view illustrating a transistor. [Figure 39] 1 is a cross-sectional view illustrating a transistor. [Diagram 40] Electron diffraction pattern of CAAC-OS. [Diagram 41] FIG. 1 shows the change in the crystal part of an In-Ga-Zn oxide due to electron irradiation. [Diagram 42] Schematic diagram explaining the film formation model of CAAC-OS and nc-OS. [Diagram 43] A diagram explaining InGaZnO4 crystals and pellets. [Diagram 44] Schematic diagram explaining a film formation model of CAAC-OS. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various ways in form and detail without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be modified in various ways. The present invention is not limited to the above-mentioned embodiments. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. In addition, the same elements constituting the figures are used in the same way, and their repeated explanations may be omitted. In some cases, the patterns may be omitted or changed as appropriate between different drawings.

[0029] For example, in the present specification, when it is explicitly stated that X and Y are connected, In this case, X and Y are electrically connected, and X and Y are functionally connected. The case where X and Y are directly connected is also considered to be disclosed in the present specification. Therefore, the present invention is not limited to a specific connection relationship, for example, a connection relationship shown in a drawing or a sentence. Any connections other than those shown in the drawings or text shall be deemed to be included in the drawings or text. do.

[0030] Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). , etc.).

[0031] An example of a direct connection between X and Y is a circuit that allows electrical connection between X and Y. The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, When a resistor (such as an electrode, display element, light-emitting element, or load) is not connected between X and Y, The elements that allow electrical connection between X and Y (e.g., switches, transistors, capacitors, etc.) elements, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc.) , X and Y are connected.

[0032] An example of a case where X and Y are electrically connected is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more elements (such as an electrode, a display element, a light-emitting element, or a load) can be connected between X and Y. It is possible. The switch has a function that allows it to be turned on and off. A switch can be in a conductive state (on state) or a non-conductive state (off state) and can either pass current or not. The switch has the function of controlling whether or not current flows. When X and Y are electrically connected, This includes the case where Y is directly connected.

[0033] An example of a case where X and Y are functionally connected is a case where a functional connection between X and Y is possible. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits ( power supply circuits (voltage boost circuits, voltage drop circuits, etc.), level shifter circuits that change the potential level of signals, etc.) , voltage sources, current sources, switching circuits, amplifier circuits (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more devices (such as a memory circuit, a control circuit, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X If X is transmitted to Y, then X and Y are considered to be functionally connected. When X and Y are functionally connected, there is a direct connection between X and Y and a direct connection between X and Y. and the like are electrically connected to each other.

[0034] In addition, if it is explicitly stated that X and Y are electrically connected, are electrically connected (i.e., there is another element or circuit between X and Y) When X and Y are functionally connected (i.e., when X and Y are connected), (When there is a functional connection between X and Y via another circuit in between) and when X and Y are directly connected (i.e., when X and Y are connected without any other element or circuit between them) is deemed to be disclosed in the present specification. If it is explicitly stated that it is connected, The same contents are deemed to be disclosed in the present specification and the like.

[0035] For example, the source (or the first terminal, etc.) of the transistor is connected via Z1 (or The drain (or second terminal, etc.) of the transistor is electrically connected to Z 2 (or not), it may be electrically connected to Y, or the source of the transistor (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. and another part of Z2 is directly connected to Y, It is possible to do so.

[0036] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor The terminals of the transistor (or the first terminal, etc.) are electrically connected to each other, and X, the source of the transistor (or the first terminal, etc.) 1 terminal, etc.), the drain (or second terminal, etc.) of the transistor, and Y. "The source (or the third) of the transistor is connected to the The drain (or second terminal, etc.) of the transistor is electrically connected to X. The transistor source (or first terminal, etc.) is electrically connected to Y, and the transistor source (or first terminal, etc.) is electrically connected to X. The drain (or second terminal, etc.) of the transistor, Y, is electrically connected in this order. " Alternatively, "X is the source (or first terminal, etc.) of a transistor. The transistor is electrically connected to Y via a drain (or a second terminal, etc.) and a transistor is electrically connected to X via a drain (or a second terminal, etc.). The source (or first terminal, etc.) of a resistor, the drain (or second terminal, etc.) of a transistor ), Y is provided in this connection order. By using a simple expression method and specifying the order of connections in the circuit configuration, Distinguish between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of a transistor. The technical scope can be determined based on the above.

[0037] Or, as another way of expressing it, for example, "the source (or first terminal, etc.) of a transistor is electrically connected to X through at least a first connection path, and the first connection path is , the second connection path does not have a second connection path, and the second connection path is a transistor The source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) of the transistor The first connection path is a path via Z1, and the second connection path is a path between the transistor The drain (or second terminal, etc.) of the capacitor is electrically connected to Y through at least a third connection path. The third connection path does not include the second connection path, and the third connection path The connection path is the path through Z2. The source (or the first terminal, etc.) of the resistor is connected to the resistor via Z1 by at least the first connection path. and X is electrically connected to the first connection path, and the first connection path does not have a second connection path; The second connection path includes a connection path through a transistor, and the second connection path includes a drain of the transistor. (or the second terminal, etc.) is connected to Y via Z2 by at least a third connection path. The third connection path does not have the second connection path. Alternatively, the source (or the first terminal, etc.) of the transistor may be at least The first electrical path is electrically connected to X through Z1, and the first electrical path is The primary path does not have a second electrical path, and the second electrical path is a From the source (or first terminal, etc.) to the drain (or second terminal, etc.) of the transistor The drain (or second terminal, etc.) of the transistor is connected to at least a third The third electrical path is electrically connected to Y through Z2. , the fourth electrical path is not included, and the fourth electrical path is a drain of the transistor (or second terminal, etc.) to the source (or first terminal, etc.) of the transistor. Using the same expression as these examples, the circuit configuration By defining the connection path in Distinguish between the first terminal (or the second terminal, etc.) and the drain (or the second terminal, etc.) to determine the technical scope. can be done.

[0038] Note that these expression methods are merely examples, and the present invention is not limited to these expression methods. , Y, Z1, and Z2 are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layer, etc.).

[0039] In addition, the circuit diagram shows independent components as if they are electrically connected to each other. Even if the components are the same, one component may have the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film has the function of the wiring and The electrode functions as both components. The term "electrochemically connected" refers to a case where one conductive film has the functions of multiple components. This also falls within the scope of the above.

[0040] The words "membrane" and "layer" may be interchangeable depending on the situation. For example, the term "conductive layer" can be used interchangeably with the term "conductive film." ". Alternatively, for example, the term "insulating film" may be used. It may be possible to change the term to "insulating layer."

[0041] (Embodiment 1) In this embodiment, a display device of one embodiment of the present invention and a manufacturing method thereof will be described with reference to drawings. explain.

[0042] In this specification, the display device refers to an image display device or a light source (such as a lighting device). Also refers to connectors such as FPC and TCP (Tape Carrier). The module has a printed wiring board at the end of the TCP. or a module in which the driver circuit is directly mounted on the display element using the COG method. All of the above are considered to be included in the display device.

[0043] The display device according to one embodiment of the present invention has flexibility. Flexibility also means that the final product can be In some cases, they are used during the manufacturing process, while in other cases they are used as final products. In some cases, the flexibility may be limited.

[0044] FIG. 1 is a top view of a display device 300 according to one embodiment of the present invention. Note that in FIG. 1, for clarity of illustration, For convenience, some elements may be enlarged, reduced, transparent, or omitted.

[0045] The display device 300 includes a pixel section 302 provided on a first flexible substrate 301 and a A first circuit portion 304 and a second circuit portion 305 for driving the pixel portion 302 and the first a sealant 312 disposed to surround the first circuit portion 304 and the second circuit portion 305; and a second flexible substrate 307 disposed opposite the first flexible substrate 301. The first circuit portion 304 may be, for example, a signal line driver circuit (source driver), The circuit section 305 may include, for example, a scanning line driver circuit (gate driver). Cut.

[0046] The first flexible substrate 301 and the second flexible substrate 307 are bonded with a sealant 312. Although not shown in FIG. 1, the first flexible substrate 301 and the second flexible substrate 30 A display element is provided between the pixel portion 302, the first circuit portion 304, the second The circuit portion 305 and the display element are formed by a first flexible substrate 301, a sealant 312, and a second It is sealed by a flexible substrate 307 .

[0047] The display device 300 is surrounded by a sealant 312 on the first flexible substrate 301. The pixel section 302, the first circuit section 304, and the second circuit section 305 are disposed in a region different from the region where the pixel section 302 is disposed. 5 and an FPC terminal portion 308 (FPC: Flexible Printer d circuit).

[0048] In addition, an FPC 316 is connected to the FPC terminal portion 308. Various signals are supplied to the first circuit section 302, the first circuit section 304 and the second circuit section 305. , a pixel section 302, a first circuit section 304, a second circuit section 305, and an FPC terminal section 308 A signal line 310 is connected to each of the FPC 316. , the pixel section 302, the first circuit section 304, and the second circuit section 305 through a signal line 310. is given to.

[0049] In addition, in FIG. 1, a configuration in which a circuit for driving the pixel portion 302 is arranged in two regions is illustrated. However, the configuration of the circuit is not limited to this. For example, the circuit may be integrated into one area. The circuit may be divided into three or more parts. Only one of the path portion 304 and the second circuit portion 305 is provided on the first flexible substrate 301. The other circuit may be externally provided.

[0050] In addition, the circuit for driving the pixel portion 302 is the same as the transistor included in the pixel portion 302. Alternatively, the semiconductor device may be formed on the first flexible substrate 301 in the same manner as above, or may be formed on a COG (chip on glass) substrate. The IC chip may be mounted on a PC using a USB cable or a USB cable. The configuration may be such that the electrodes are connected to each other.

[0051] The display device 300 includes a pixel section 302, a first circuit section 304, and a second circuit section 305. 05 has a plurality of transistors in which a channel formation region is formed using an oxide semiconductor layer. do.

[0052] A transistor using an oxide semiconductor layer has high mobility and therefore occupies a small area. The aperture ratio can be improved by using the transistor. A first circuit section 304 and a second circuit section 305 are formed on the same substrate as the pixel section 302. In addition, the off-state current of the transistor is extremely small, and the retention time of an image signal or the like is short. Since the time can be increased, the frame frequency can be lowered, and the power consumption of the display device can be reduced. Power consumption can be reduced.

[0053] In addition, the oxide semiconductor layer preferably has crystals oriented in the c-axis direction. When an oxide semiconductor layer having such crystals is used in a channel formation region of a display device, When the device 300 is bent, cracks or the like are less likely to occur in the oxide semiconductor layer, and therefore reliability is improved. It can be improved.

[0054] Therefore, by using a transistor including an oxide semiconductor layer, This allows for the formation of displays that are superior to those using silicon or polysilicon layers.

[0055] The display device 300 typically uses a liquid crystal element or a light emitting element as a display element. can be done.

[0056] Next, a display device 300a using a liquid crystal element will be described. 2 is a cross-sectional view taken along dashed dotted line A1-A2 shown in FIG. 1 in the case where a liquid crystal element is used.

[0057] The display device 300a includes a first flexible substrate 301, a first adhesive layer 318a, and a first organic A resin layer 320a, a first insulating film 321a, a first element layer, a second element layer, and a second The insulating film 321b, the second organic resin layer 320b, the second adhesive layer 318b, and the second flexible The conductive substrates 307 are laminated in the above order.

[0058] In FIG. 2, the first element layer includes transistors 350 and 352, insulating films 364 and 366, 368, a planarization insulating film 370, a connection electrode 360, a conductive film 372, and the like. The second element layer is a conductive film 374, an insulating film 334, and a coloring layer 336 (color filter). and a light-shielding layer 338 (black matrix). In the device layer, some of the above elements may not be included. may also be included.

[0059] Here, the first element layer and the second element layer are sealed by a liquid crystal layer 376 and a sealant 312. This forms a liquid crystal element 375 .

[0060] The first flexible substrate 301 and the second flexible substrate 307 may be, for example, a flexible substrate. thickness glass, polyethylene terephthalate (PET), polyethylene naphthalate Polyester resins such as PEN, polyacrylonitrile resins, polyimide resins, poly Methyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (P ES) resin, polyamide resin, cycloolefin resin, polystyrene resin, polyamide resin Examples include amide resin, polyvinyl chloride resin, and polyether ether ketone (PEEK) resin. In particular, it is preferable to use a material with a low thermal expansion coefficient, such as polyamide. Suitable materials for use include amide resin, polyimide resin, and PET. Substrates impregnated with organic resin or substrates with a lower thermal expansion coefficient by mixing inorganic fillers into organic resin. It can also be used.

[0061] The adhesive layers 318a and 318b are made of a hardening resin that hardens at room temperature, such as a two-part mixed resin. Resins such as epoxy, photocurable resins, and thermosetting resins can be used. Examples of the resin include epoxy resin, acrylic resin, silicone resin, and phenol resin. A material with low moisture permeability, such as silicone resin, is preferred.

[0062] The first organic resin layer 320a and the second organic resin layer 320b may be made of, for example, epoxy. Resin, aramid resin, acrylic resin, polyimide resin, polyamide resin, or polyamide The insulating layer 11 can be made of a material selected from the group consisting of dimethyl ether and diphenyl ether.

[0063] The first insulating film 321a and the second insulating film 321b may be a silicon oxide film, a silicon oxynitride film, or the like. A single layer of a silicon film, a silicon nitride film, or a silicon oxynitride film, or a laminate of these films is used. In particular, the first flexible substrate 301 and the first adhesive layer 318a may include In order to prevent impurities from diffusing into transistors, etc., a highly blocking nitride is used. It is preferable to use a film containing an element.

[0064] The display device 300a includes a wiring portion 311, a pixel portion 302, and a first circuit portion 304. , and an FPC terminal section 308. The wiring section 311 includes a signal line 310. do.

[0065] In the display device 300a, a transistor 350 is provided in the pixel portion 302, and a first circuit portion 3 illustrates a configuration in which a transistor 352 is provided in each of the first and second transistors 304 .

[0066] In FIG. 2, transistors 350 and 352 are configured to be the same size. The transistors 350 and 352 may be of any suitable size. The number of channels (channel length, channel width, etc.) can be changed. In this case, the second circuit unit 305 is not shown, but the connection destination or the connection method, etc. are changed. In this way, the same configuration as the first circuit portion 304 can be achieved.

[0067] The signal line 310 of the lead wiring portion 311 is connected to the source electrode layer of the transistor 350 and The insulating layer 12 can be formed in the step of forming the drain electrode layer.

[0068] The FPC terminal portion 308 includes a connection electrode 360, an anisotropic conductive film 380, and an FPC 316. The connection electrode 360 ​​is connected to the source electrode layer and the drain electrode layer of the transistor 350. The connection electrode 360 ​​can be formed in the process of forming the layer. The terminal is electrically connected to the corresponding terminal via an anisotropic conductive film 380.

[0069] In addition, a signal connected to a transistor in a pixel portion and a transistor used in a driver circuit portion It is preferable to use wiring containing copper as the wire. By using wiring containing copper, This can reduce signal delays and other issues caused by wiring resistance.

[0070] 2, an insulating film 364 is formed on the transistor 350 and the transistor 352. , 366, 368, and a planarizing insulating film 370 are provided.

[0071] The insulating films 364 and 366 can be made of the same material, for example, silicon oxide. The insulating film 364 has a small number of defects and can be made of silicon oxide nitride. The insulating film 366 is an oxide insulating film containing more oxygen than the oxygen that satisfies the stoichiometric composition. It is preferable to form the insulating films 364 and 366 using a single layer of the same material. The insulating film 368 may be formed of a bromine such as oxygen, hydrogen, water, an alkali metal, or an alkaline earth metal. For example, it is preferable to use a nitride insulating film.

[0072] The planarization insulating film 370 may be made of polyimide resin, acrylic resin, or polyimide amide. Resin, benzocyclobutene resin, polyamide resin, epoxy resin, and other heat-resistant organic In addition, it is possible to laminate multiple insulating films made of these materials. In this manner, the planarization insulating film 370 may be formed. It is also possible to use the following.

[0073] In addition, one of the source electrode layer and the drain electrode layer of the transistor 350 has a conductive The conductive film 372 is formed on the planarization insulating film 370. The conductive film 372 functions as an electrode, that is, one of the electrodes of the liquid crystal element. In the above, it is preferable to use a light-transmitting conductive film. It is preferable to use a material containing one selected from the group consisting of In, zinc (Zn) and tin (Sn).

[0074] The liquid crystal element 375 includes a conductive film 372, a conductive film 374, and a liquid crystal layer 376. 374 is provided on the second flexible substrate 307 side and functions as a counter electrode. In the display device 300a shown in FIG. By changing the orientation of the crystal layer 376, the light transmission or non-transmission is controlled to display an image. It is possible.

[0075] Although not shown in FIG. 2, the conductive films 372 and 374 are provided on the side in contact with the liquid crystal layer 376. In addition, a polarizing member, a phase difference member, an anti-reflection member, etc. may be used. Optical members (optical substrates) such as members may be provided as appropriate. For example, a polarizing substrate and a phase A circularly polarized light source such as a backlight or a sidelight may be used as the light source. may also be used.

[0076] In addition, a spacer 378 is provided between the first flexible substrate 301 and the second flexible substrate 307. The spacers 378 are columnar spacers obtained by selectively etching an insulating film. It is a spacer, and is provided to control the film thickness (cell gap) of the liquid crystal layer 376. The spacer 378 may be a spherical spacer.

[0077] The liquid crystal material constituting the liquid crystal layer 376 may be a thermotropic liquid crystal, a low molecular weight liquid crystal, or a high molecular weight liquid crystal. Liquid crystal, polymer dispersed liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. These liquid crystal materials can exhibit cholesteric, smectic, cubic, and chromatic phases depending on the conditions. It shows an isotropic phase, an isotropic phase, etc.

[0078] In addition, when the in-plane switching system is adopted, liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of a cholesteric liquid crystal is increased, the cholesteric The blue phase appears just before the transition from the crystalline phase to the isotropic phase. In order to improve the temperature range, a liquid crystal composition containing a chiral agent of several weight percent or more is used. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent is used in the liquid crystal layer. It has a short response time, is optically isotropic so no alignment treatment is required, and has little viewing angle dependency. In addition, since there is no need to provide an alignment film, rubbing treatment is also unnecessary. This can prevent electrostatic damage caused by electrostatic discharge, and can prevent defects and damage to liquid crystal display devices during the manufacturing process. The loss can be reduced.

[0079] When liquid crystal elements are used as display elements, TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fring e Field Switching) mode, ASM (Axially Symmet ric aligned Micro-cell) mode, OCB (Optical C ompensated birefringence mode, FLC (Ferroel etric Liquid Crystal) mode, AFLC (AntiFerro You can use modes such as electric Liquid Crystal.

[0080] In addition, normally black type liquid crystal display devices, for example, transparent liquid crystal display devices using a vertical alignment (VA) mode, The liquid crystal display device may be a vertical alignment mode liquid crystal display device. For example, the MVA (Multi-Domain Vertical Alignment) model mode, PVA (Patterned Vertical Alignment) mode, ASV mode, etc. can be used.

[0081] The display method in the pixel unit 302 may be a progressive method, an interlace method, or the like. In addition, the color elements controlled by pixels when displaying colors are RGB. (R stands for red, G stands for green, and B stands for blue). For example, R pixels and G pixels It may be composed of four pixels: a pixel of B and a pixel of W (white). Or, In this way, two colors from RGB compose one color element, and two different colors are selected depending on the color element. Or you can add one or more colors such as yellow, cyan, magenta, etc. to RGB. The size of the display area may be different for each dot of the color element. However, the disclosed invention is not limited to a color display device, and may be used for a monochrome display device. It can also be applied to a display device.

[0082] Next, a display device 300b using a light-emitting element will be described. FIG. 2 is a cross-sectional view taken along dashed line A1-A2 in FIG. 1 when a light-emitting element is used. Description overlapping with the display device 300a using the above-mentioned liquid crystal element will be omitted.

[0083] The display device 300b includes a first flexible substrate 301, a first adhesive layer 318a, and a first organic The resin layer 320a, the first insulating film 321a, the first element layer 410, and the second element layer 41 1, a second insulating film 321b, a second organic resin layer 320b, and a second adhesive layer 318b. , and a second flexible substrate 307 are laminated in the above order.

[0084] In FIG. 3, the first element layer 410 includes transistors 350 and 352, insulating films 364, 66, 368, a planarization insulating film 370, a light emitting element 480, an insulating film 430, and a signal line 3 10 and a connection electrode 360. The second element layer 411 includes an insulating film 334 and a colored The first element layer 410 and the second element layer 41 The first element layer 41 is sealed by the sealing layer 432 and the sealant 312. The zeroth and second element layers 411 may not include some of the above elements. It may also include elements other than those mentioned above.

[0085] The light-emitting element 480 includes a conductive film 444, an EL layer 446, and a conductive film 448. The device 300b displays an image by emitting light from the EL layer 446 of the light emitting element 480. It can be shown.

[0086] An insulating film 430 is provided on the conductive film 444 on the planarization insulating film 370. The conductive film 444 is provided with a conductive layer having a high reflectance with respect to light emitted from the EL layer. A conductive film having high light-transmitting properties with respect to light emitted from the EL layer is used as the conductive film 448. As a result, the light-emitting element 480 can have a top emission structure. A conductive film having a high light-transmitting property is used for the conductive film 448. By using a highly conductive film, the light emitting element 480 can have a bottom emission structure. In addition, both the conductive film 444 and the conductive film 448 are made of a conductive film having a high light-transmitting property. By using this, a dual emission structure can be achieved.

[0087] In addition, a coloring layer 336 is provided at a position overlapping the light emitting element 480, and a coloring layer 336 is provided at a position overlapping the insulating film 430. A light shielding layer 338 is provided on the position, the lead wiring section 311, and the first circuit section 304. The colored layer 336 and the light-shielding layer 338 are covered with a third insulating film 334. Light-emitting element The space between the insulating film 480 and the third insulating film 334 is filled with a sealing layer 432. In the embodiment 0b, the colored layer 336 is provided, but the present invention is not limited to this. For example, when the EL layer 446 is formed by coloring, the colored layer 336 is not provided. Alternatively, a different configuration may be used.

[0088] In the display device 300b, the adhesive layers 318a and 318b may contain a desiccant. For example, chemical adsorption occurs when the oxides of alkaline earth metals (calcium oxide, barium oxide, etc.) Alternatively, a material that adsorbs moisture by absorbing the moisture can be used, such as zeolite or silica gel. A substance that adsorbs moisture by physical adsorption may be used, such as This can prevent impurities such as moisture from entering the light emitting element 480, improving the reliability of the display device. It can be improved.

[0089] In addition, by mixing a filler with a high refractive index (such as titanium oxide) into the sealing layer 432, The light extraction efficiency from the optical element 480 can be improved.

[0090] The adhesive layers 318a and 318b may also include a scattering material that scatters light. For example, the adhesive layers 318a and 318b may be formed by mixing the sealing layer 432 with particles having different refractive indexes. The particles can also be used as a light scattering material. The difference in refractive index between the particles is preferably 0.1 or more, and more preferably 0.3 or more. As the particles, titanium oxide, barium oxide, zeolite, etc. can be used. Titanium oxide and barium oxide particles are preferred because they have a strong light scattering property. When fluorite is used, water contained in the sealing layer 432 etc. can be adsorbed, and the reliability of the light-emitting element can be improved. It is possible to improve the performance.

[0091] The first flexible substrate 301 and the second flexible substrate 307 are each made of a highly tough material. This makes it possible to realize a light emitting device that is highly resistant to impact and is less likely to break. For example, the first flexible substrate 301 and the second flexible substrate 307 may be organic resin substrates. This makes the display lighter and less susceptible to breakage than when a glass substrate is used as the base material. This makes it possible to realize this position.

[0092] In addition, if a material with high thermal emissivity is used for the first flexible substrate 301, the surface temperature of the display device Therefore, damage to the display device and deterioration of its reliability can be suppressed. The flexible substrate 301 is made of a metal substrate and a layer with high thermal emissivity (e.g., a metal oxide or a ceramic material). A laminated structure of the above-mentioned materials may be used.

[0093] Next, a method for manufacturing the display device 300b shown in FIG. 3 will be described with reference to FIGS. In order to avoid complication of the drawings, the first element layer 4 shown in FIG. 10 and the second element layer 411 are illustrated in a simplified manner.

[0094] First, a first organic resin layer 320a, a first insulating film 321a, and A stack of a first element layer 410 and a second element layer 411 is formed (see FIG. 4A).

[0095] In addition, a second organic resin layer 320b, a second insulating film 321b, and A stack of a second element layer 411 and a second element layer 412 is formed in this order (see FIG. 4B).

[0096] The first substrate 462 and the second substrate 463 are at least made of a material that can withstand the subsequent heat treatment. For example, glass substrates, ceramic substrates, and quartz substrates. , a sapphire substrate, etc. can be used.

[0097] The first organic resin layer 320a and the second organic resin layer 320b are made of, for example, an epoxy resin. , aramid resin, acrylic resin, polyimide resin, polyamide resin, polyamideimide resin An organic resin film such as grease can be used. Among them, polyimide resin has high heat resistance. In the case where a polyimide resin is used, the thickness of the polyimide resin is preferably 3 nm or more. The thickness of the polyimide resin is preferably 500 nm or more and 2 μm or less. The layer can be formed by a coating method, a dip coating method, a doctor blade method, or the like.

[0098] The first insulating film 321a and the second insulating film 321b may be a silicon oxide film, an oxynitride film, or the like. Silicon film, silicon nitride film, silicon oxide nitride film, etc. can be used. The first insulating film 321a can be formed by a CVD method or the like. Diffusion of impurities from the first substrate 462 or the first organic resin layer 320a to the first element layer 410 can be suppressed.

[0099] When forming the first element layer 410, the formation temperature of all components including the transistor 350 The temperature is preferably from room temperature to 300° C. For example, the inorganic The insulating film or conductive film formed from the material is preferably formed at a film formation temperature of 150° C. or higher and 300° C. or lower. The temperature is preferably 200° C. or more and 270° C. or less. The insulating film formed by the method is preferably formed at a temperature between room temperature and 100° C. In addition, in the process of forming the transistor 350, for example, a heating step may be omitted. It is also possible.

[0100] The insulating film 430, the conductive film 444, the EL layer 446, and the The conductive film 448 can be formed by the following method.

[0101] The insulating film 430 may be made of, for example, an organic resin or an inorganic insulating material. Examples of the organic resin include polyimide resin, polyamide resin, acrylic resin, and siloxane. Resin, epoxy resin, phenol resin, etc. can be used as the inorganic insulating material. For example, silicon oxide, silicon oxynitride, etc. can be used for the insulating film 430. The method for forming the layer is not particularly limited, and may be, for example, a lithography method, a sputtering method, a vapor deposition method, a droplet ejection method, or the like. Printing methods (inkjet printing, etc.), printing methods (screen printing, offset printing, etc.) In the case of using the lithography method, if a photosensitive resin is used, the process of forming the insulating film 430 can be performed in a short time. can be simplified.

[0102] The conductive film 444 is preferably a metal film having high reflectivity in visible light. The metal film may be made of, for example, aluminum, silver, or an alloy thereof. The conductive film 444 can be formed by, for example, a sputtering method. do.

[0103] The EL layer 446 is formed by recombining holes and electrons injected from the conductive film 444 and the conductive film 448. In addition to the light-emitting material, a hole injection layer, a hole transport layer, Functional layers such as an electron transport layer, an electron injection layer, etc. may be formed as necessary. The layer 446 can be formed by, for example, a vapor deposition method or a coating method.

[0104] The conductive film 448 is preferably a conductive film that transmits visible light, for example. The conductive film may be made of, for example, indium (In), zinc (Zn), or tin (Sn). The conductive film 448 may be made of a material containing one of the selected species. Indium oxide containing tungsten, indium zinc oxide containing tungsten oxide, Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin Oxide (ITO), Indium Zinc Oxide, Indium Tin Oxide doped with Silicon, etc. In the display device of one embodiment of the present invention, a conductive material having a light-transmitting property can be used. It is preferable to use silicon-added indium tin oxide for the conductive film 448. When indium tin oxide containing ruthenium is used, the resistance of the conductive film 448 to bending is improved. The conductive film 448 is formed by using, for example, a sputtering method. It is possible.

[0105] The colored layer 336 of the second element layer 411 is a layer that transmits light of a specific wavelength band. For example, a red (R) color filter that transmits light in the red wavelength band may be used. A green (G) color filter transmits light in the green wavelength range, and a blue (B) color filter transmits light in the blue wavelength range. A blue (B) color filter that transmits light can be used. A color filter having a color of 0.1 to 0.5 μm may be used. Each color filter may be made of various materials. The printing method, the inkjet method, the etching method using lithography technology, etc. Each is formed at a desired position.

[0106] The light shielding layer 338 of the second element layer 411 is a layer that blocks light of a specific wavelength range. It is sufficient that the insulating film has the function of blocking the black pigment. This can be done.

[0107] The third insulating film 434 of the second element layer 411 is made of, for example, an acrylic resin. The third insulating film 434 is not necessarily formed. It is not necessary, and a structure in which the third insulating film 434 is not formed may be used.

[0108] Next, the first element layer 410 and the second element layer 411 are bonded together via the sealing layer 432 ( See FIG. 4(C). Note that the sealant 312 is not shown.

[0109] The sealing layer 432 can be made of a flexible solid sealing material. Glass materials such as glass frit, two-part resins that harden at room temperature, and light Resin materials such as hardening resins and thermosetting resins can be used.

[0110] Next, the first substrate 462 is peeled off from the structure shown in Fig. 4(C) (see Fig. 4(D)). Note that the step of peeling off the second substrate 463 may be performed first.

[0111] In addition, various methods can be used as appropriate for the peeling step. For example, The first organic resin layer 320a is irradiated with ultraviolet light 468 through the first organic resin layer 320a. The layer 320a is weakened or the adhesion between the first organic resin layer 320a and the first substrate 462 is reduced. By lowering the substrate 462, the first substrate 462 can be peeled off. By adjusting the energy density, the adhesion between the first substrate 462 and the first organic resin layer 320a can be improved. The first substrate 462 and the first organic resin layer 320a are provided with a region having high adhesion and a region having low adhesion. The ultraviolet light source may be, for example, a 308 nm ultraviolet light source. It is possible to use an excimer laser that outputs external light. It is also possible to use a high-pressure mercury lamp or UV LEDs and the like may also be used.

[0112] Excimer lasers are high-power pulsed lasers, and the beam is shaped into a linear form by an optical system. By moving the substrate at the irradiation position of the linear laser beam, the entire substrate can be The linear beam can be irradiated to a portion of the substrate to be used. If the length is equal to or greater than the side, the entire substrate can be irradiated with laser light by simply moving the substrate in one direction. It is possible.

[0113] Excimer laser devices include devices equipped with one laser oscillator as well as devices equipped with two or more laser oscillators. In the case of an apparatus equipped with a plurality of laser oscillators, The laser beams output from each laser oscillator are synchronized and combined by an optical system. By combining the two, it is possible to obtain a laser beam with a high energy density. For applications in this form, the size of the 8th generation glass substrate (2160mm x 2460mm) or more is In addition, in a device equipped with multiple laser oscillators, each The laser beams output from each laser oscillator complement each other's output variations, so This reduces the variation in strength between individual pieces, enabling processing with a high yield. Instead of the oscillator, a plurality of excimer laser devices may be used.

[0114] Figure 6 shows an example of a processing device using an excimer laser. Laser beams 610a and 610b outputted from a sigma laser device 600 are combined by an optical system 630. The laser beam 610c expanded laterally by the optical system 630 is reflected by a mirror 650. The linear beam is then incident on the lens 670 and reduced to become the linear beam 610d. The beam 610d is irradiated onto the processing area 710 of the workpiece 700 through the substrate 720. Make it so.

[0115] In this embodiment, the workpiece 700 has the structure shown in FIG. 4(C) or FIG. In the processing region 710, the first organic resin layer 320a or the second organic resin layer 320b, The substrate 720 corresponds to the first substrate 462 or the second substrate 463 .

[0116] Then, by moving the workpiece 700 in the direction of the arrow in the figure, a linear pattern is formed over the entire processing area 710. The excimer laser can emit a beam 610d. It is preferable to use a wavelength of 308 nm or longer. For example, even if a glass substrate is used as the substrate 720, the laser light required for processing can be sufficiently transmitted. It can be done.

[0117] In this embodiment, at the interface between the first substrate 462 and the first organic resin layer 320a, The peeling method is described above as an example, but is not limited to this. For example, when peeled, the first The organic resin layer 320a may be separated so that a part of the organic resin layer 320a remains on the first substrate 462. Peeling may occur at the interface between the organic resin layer 320 a and the first element layer 410 .

[0118] In addition, the liquid is allowed to penetrate into the interface between the first substrate 462 and the organic resin layer 320a. Alternatively, the first organic resin layer 320a may be peeled off from the substrate 62. A liquid is allowed to penetrate into the interface between the first organic resin layer 320a and the first element layer 410 to form the first The element layer 410 may be peeled off. The liquid may be, for example, water, a polar solvent, or the like. By using this liquid, static electricity that occurs during peeling can be suppressed. Therefore, electrostatic damage to a transistor or the like included in the first element layer 410 can be suppressed. do.

[0119] Next, the first organic resin layer 320a and the first flexible substrate 301 are bonded together using the first adhesive layer 318a. (See Figure 5(A)).

[0120] Next, the second substrate 463 is peeled off using the same method as above, and the second organic resin layer 320b is and the second flexible substrate 307 are bonded to each other using a second adhesive layer 318b (see FIG. 5(B)). .

[0121] Then, the FPC 316 is attached to the connection electrode 360 ​​via the anisotropic conductive film 380. If necessary, an IC chip or the like may be mounted.

[0122] In this manner, the display device 300b shown in FIG. 3 can be manufactured.

[0123] When peeling is performed at the interface between the first organic resin layer 320a and the first element layer 410, The configuration shown in FIG. 5(C) is obtained. At this time, the display devices 300a and 300b shown in FIG. In the case of 0b, the organic resin layer 320a is not present.

[0124] In one embodiment of the present invention, a device including a transistor using an oxide semiconductor layer over an organic resin layer A layer is formed, weakening the organic resin layer or reducing the adhesive strength between the organic resin layer and the substrate. In the case of a transistor using polycrystalline silicon, The method includes a laser irradiation step for crystallizing the amorphous silicon. In some cases, a region will be generated that is hot enough to melt silicon, even if only for a moment. When an organic resin layer is used as in one embodiment of the present invention, heat is also transferred to the organic resin layer, and degassing is performed. Cracks and chips may occur in the inorganic film formed between the transistor and the substrate due to thermal expansion or other factors. In addition, energy is used to suppress the cracks and peeling. - With laser irradiation with reduced density, it became impossible to obtain polycrystalline silicon with sufficient crystallinity. It ends up like this.

[0125] On the other hand, a manufacturing process of a transistor using an oxide semiconductor layer does not require a high-temperature process. Stable processes can be carried out without weakening the organic resin layer until transistors, etc. are completed. This makes it possible to fabricate transistors with high yield and reliability.

[0126] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0127] (Embodiment 2) In this embodiment, a separation apparatus according to one embodiment of the present invention will be described with reference to FIGS. The following description will be given with reference to Figs. 1, 12, 13, and 14. One embodiment of the present invention is a first part of a processed member. a structure capable of holding a first member of the workpiece and a stage capable of holding a second member of the workpiece. and a second member is wound up, and the processed member between the structure and the stage is wound up. For example, the first member is a peeling device shown in FIG. A) is applied to the second substrate 463 of the laminate other than the second substrate 463 shown in A) and the second member. It is possible.

[0128] By using the peeling device according to one aspect of the present invention, the processed member can be separated into the first member and the second member with a high yield. The peeling device according to one embodiment of the present invention does not have a complicated configuration, It can handle peeling of a wide range of processed parts.

[0129] The configuration and operation of the peeling device and a peeling method using the peeling device will be described below.

[0130] <Configuration example 1> 7, 8, and 9, the first member 103a is peeled off from the processed member 103, An example of separating the first member 103a and the second member 103b will be shown.

[0131] First, FIG. 7(A) shows a perspective view of the peeling device immediately before peeling, and FIG. 7(B) shows a front view. A side view is shown in FIG. 7(D).

[0132] The peeling apparatus shown in FIG. 7(A), FIG. 7(B), FIG. 7(C), and FIG. 7(D) is a structure 101 and The structure 101 has a convex surface. The stage 105 is The support surface faces the support member.

[0133] In Fig. 7(A), Fig. 7(B), Fig. 7(C), and Fig. 7(D), the convex surface of the peeling device and the supporting surface A workpiece 103 is disposed therebetween.

[0134] FIG. 7C shows a processed member 103 for the structure 101. 7A shows a top view of a case where the arrangement of the processed member 103 is different from that of the processed member 103. As shown in the top view of FIG. 7(C), the peeling starts from the corner of the processed member 103. When peeling is started from the side of the processed member 103, peeling is started from the short side. In this case, it is preferable to perform peeling in the long side direction. This makes it possible to control conditions such as the rotation speed of the structure. This makes it easier to control, and the yield of peeling can be increased.

[0135] The processed member 103 is in a sheet shape, and includes a sheet-shaped first member 103a and a sheet-shaped second member 103b. The first member 103a and the second member 103b are The processed member 103 may be a single layer or a multi-layer. This prevents peeling at the interface between the first member 103a and the second member 103b. This makes it easier to separate.

[0136] When the peeling device has a conveying means, the conveying means conveys the processed member onto the stage 105. 103 may be arranged.

[0137] As shown in the enlarged view of the area surrounded by the two-dot chain line in FIG. 7(D), the convex surface of the structure 101 is processed. A point-like or linear (including solid line, dashed line, and frame-like) peeling starting point 102 formed on a member 103 Then, the structure 101 rotates, so that the first member 103a is placed on the processed member 103. A force is applied to peel the first member 103a away from the vicinity of the peeling starting point 102. Then, the processed member 103 is separated into a first member 103a and a second member 103b.

[0138] The structure 101 may have a convex surface, and may be, for example, a cylindrical shape (a circular cylinder, a right circular cylinder, an elliptical cylinder, etc.). It can be a part of a cylinder, a sphere, a part of a sphere, etc. For example, a roller such as a drum roller can be used.

[0139] The materials of the structure include metals, alloys, organic resins, etc. The structure has spaces or voids inside. It may have a cavity.

[0140] 10(C) and 10(D) show structures 151 and 152, some of which include convex surfaces. Each of the structure 151 and the structure 152 has a partial cylindrical structure.

[0141] The radius of curvature of the convex surface of the structure is smaller than the radius of curvature of the support surface of the stage 105. The radius of curvature of the can be, for example, 0.5 mm or more and 1000 mm or less. For example, When peeling off the film, the radius of curvature of the convex surface may be 0.5 mm or more and 500 mm or less. Specific examples include 150 mm, 225 mm, and 300 mm. The structure having such a convex surface may be, for example, a structure having a diameter of 300 mm, 450 mm, or 600 mm. The radius of curvature of the convex surface may vary depending on the thickness and size of the workpiece. The preferred range of varies. Therefore, without being limited thereto, in one embodiment of the present invention, The radius of curvature of the convex surface of the structure needs to be smaller than the radius of curvature of the support surface of the stage 105 .

[0142] When the processed member 103 includes a laminated structure with low adhesion, peeling may occur at the interface with low adhesion. For example, if the processed member 103 is not attached to the organic EL element, the peeling yield may decrease. In the case where the first layer contains the EL layer, the EL layer is peeled off at the interface between the two layers constituting the EL layer or at the interface between the EL layer and the electrode. In some cases, it may be difficult to separate the first member 103a from the second member 103b at the interface. The radius of curvature of the convex surface is set so that the first member 103a and the second member 103b can be peeled off at the interface. In addition, the rotation speed of the structure 101 may be controlled.

[0143] Furthermore, if the radius of curvature of the convex surface is too small, the first member 103a wound around the convex surface may be damaged. Therefore, the radius of curvature of the convex surface must be 0.5 mm or more. preferable.

[0144] In addition, if the radius of curvature of the convex surface is large, the flexibility of glass, sapphire, quartz, silicon, etc. is low. Therefore, the radius of curvature of the convex surface is, for example, For example, it is preferable that the distance is 300 mm or more.

[0145] In addition, if the radius of curvature of the convex surface is large, the size of the peeling device will increase, which will limit the installation location. Therefore, the radius of curvature of the convex surface should be, for example, 1000 mm or less. It is preferable that the distance is 500 mm or less, and more preferable that the distance is 500 mm or less.

[0146] At least a portion of the convex surface may be adhesive. For example, a portion or the entirety of the convex surface may be adhesive. Adhesive tape or the like may be attached. Also, as shown in FIG. 10(E), at least a part of the convex surface may be In addition, the first member 103a may be provided with an adhesive portion 104. The member 101 may have a suction mechanism, and the convex surface may be capable of suctioning the first member 103a.

[0147] The structure 101 and the stage 105 can move in at least one of the directions: forward / backward, left / right, and up / down. The distance between the convex surface of the structure 101 and the support surface of the stage 105 may be variable. This is preferable because it is possible to peel off processed members of various thicknesses. An example in which the stage 105 is movable in the longitudinal direction is shown.

[0148] A member or the like (for example, a processed member 103 or a second member 103b) placed on the stage 105 The means for holding the object are a suction chuck, an electrostatic chuck, a mechanical chuck, etc. For example, a porous chuck may be used. The member may be fixed to a cable, a heater table, a spinner table, etc.

[0149] Next, FIG. 8(A) shows a perspective view of the peeling device during peeling, FIG. 8(B) shows a front view, and FIG. FIG. 8(C) shows a side view of the peeling device after peeling. FIG. 9(A) shows a perspective view of the peeling device after peeling. is shown in FIG. 9(B) and a side view is shown in FIG. 9(C).

[0150] The structure 101 has a rotation axis 109 at its center. The direction in which the structure 101 rotates is shown in FIG. As shown in (C) and the like, the structure 101 may be able to rotate in the opposite direction. The rotation shaft 109 moves along the groove of the stage 105, so that the structure moves in the longitudinal direction of the stage 105. The body 101 can move (left and right directions in FIG. 8(C) and FIG. 9(C)).

[0151] As the structure 101 rotates, the first member 103a overlapping the convex surface of the structure 101 is peeled off. The second part is peeled off from the processed member 103 near the starting point of the separation and wound around the convex surface. The first member 103a is held by the convex surface of the structure 101, and the stay A second member 103b is held on the base 105.

[0152] In the peeling apparatus according to one embodiment of the present invention, at least one of the stage 105 or the structure 101 By moving the stage 105, the position of the center of rotation of the structure 101 relative to the stage 105 can be moved. In the configuration example 1, an example in which the rotation center of the structure 101 itself moves is shown. Specifically, In the state where the stage 105 is stationary (or fixed), the structure 101 is While winding up the processed member 103a, the processed member 103 is wound from one end side to the other end side. Here is an example of how the object can be moved (rotated) by the arrow.

[0153] The linear velocity of the convex surface of the structure 101 is the movement of the center of rotation of the structure 101 relative to the stage 105. It's more than speed.

[0154] While applying tension to the first member 103a or the second member 103b, the first member 103a And the second member 103b may be separated.

[0155] As shown by arrow 108 in FIG. 8(C), the first member 103a and the second member 103b are separated. The liquid supply mechanism may be provided to supply liquid to the surface.

[0156] The static electricity generated during the peeling may adversely affect the elements and the like included in the first member 103a ( It is possible to prevent damage to semiconductor elements caused by static electricity. The liquid may be pure water or an organic solvent, and the liquid may be neutral. Alternatively, an aqueous solution having an alkaline or acidic acidic acid or an aqueous solution having a dissolved salt may be used.

[0157] If the peeling device has a transport means, the peeling device transports the wafer onto the stage 105 after peeling. The second member 103b and the first member 103a wound around the structure 101 are transported. You may put it out.

[0158] In addition, as shown in FIGS. 10(A) and 10(B), the structure 101 is rotated to Even if the sheet-like member 111 arranged on the surface 105 is bonded to the first member 103a, good.

[0159] The member 111 may be a single layer or a multilayer. At least a part of the surface in contact with the member 103a has adhesion to the member 103a. For example, an adhesive layer may be formed.

[0160] During one rotation of the structure 101, the convex surface may take up the entire first member 103a. This prevents the first member 103a from touching the stage 105 and the first member 103a from This is preferable because pressure applied by the structure 101 can be suppressed.

[0161] In addition, the first member 103a wound on the convex surface does not come into contact with the stage 105. It is preferable that the substrate is laminated to 111.

[0162] For example, the structure 101 is rotated by a quarter turn to wind up the first member 103a so that all of the convex surfaces are wound up. , the structure 101 is rotated 3 / 4 times, and the structure 101 moves to the vicinity of the end of the member 111, The structure 101 is then rotated by a quarter turn to bond the first member 103a onto the member 111. This may be allowed.

[0163] Alternatively, after the peeling is completed, the first member 103a wound around the structure 101 is moved to the stage. The distance between the structure 101 and the stage 105 may be adjusted so that the structure 101 does not come into contact with the stage 105 .

[0164] <Configuration example 2> In configuration example 2, the stage moves, and the position of the center of rotation of the structure relative to the stage changes. An example of a structure moving is shown below. Specifically, the position of the rotation center of the structure does not move, and the stage moves in the direction of the processing. An example in which a member can move from one end side to the opposing other end side will be shown.

[0165] 11, 12, and 13, the first member 153a is peeled off from the processed member 153. 13 shows an example of separating the first member 153a and the second member 153b.

[0166] First, FIG. 11(A) shows a perspective view of the peeling device immediately before peeling, and FIG. 11(B) shows a front view. and a side view is shown in FIG. 11(C).

[0167] The peeling apparatus shown in FIG. 11(A), FIG. 11(B), and FIG. 11(C) includes a structure 151, a stage The structure 151 has a convex surface. The stage 155 has a support surface facing the convex surface. The support 157 supports the structure 15 Support 1.

[0168] In Fig. 11(A), Fig. 11(B), and Fig. 11(C), a pressurized layer is formed between the convex surface and the support surface of the peeling device. A construction member 153 is arranged.

[0169] FIG. 11A shows a case where peeling starts from the side of the processed member 153. Similarly, peeling may start from a corner of the processed member 153.

[0170] The structure 151, the workpiece 153, and the stage 155 are the same as those in the structure 101 and the workpiece 102 in the configuration example 1. Since the same configuration as the workpiece 103 and the stage 105 can be applied, The processed member 153 has a peeling starting point 162 formed therein.

[0171] The support 157 supports a rotation axis 159 of the structure 151. 51. This allows the convex surface of the structure 151 and the stage 155 The distance between the support surfaces can be variable.

[0172] The transport rollers 158 can move the stage 155. Movement of the stage 155 There is no particular limitation on the means, and a belt conveyor or a transport robot may be used.

[0173] When the peeling device has a conveying means, the conveying means conveys the processed member onto the stage 155. 153 may be placed.

[0174] Next, FIG. 12(A) shows a perspective view of the peeling device in the middle of peeling, and FIG. 12(B) shows a front view. A side view is shown in FIG. 12(C). A perspective view of the peeling device after peeling is shown in FIG. 13(A). A front view is shown in FIG. 13(B) and a side view is shown in FIG. 13(C).

[0175] A rotation shaft 159 is located at the center of the structure 151. The structure 151 and the conveying roller 158 rotate. The direction of the structure 151 and the conveying roller 158 is shown in FIG. The conveying roller 158 may be capable of rotating in the opposite direction. The position of the stage 155 and the workpiece 153 on the stage 155 relative to the center of rotation of (Specifically, it can move left and right in Fig. 12(C) and Fig. 13(C).)

[0176] The first member 153a held by the structure 151 is peeled off from the processed member 153 and formed into a convex surface. While being wound, the second member 153b is separated from the second member 153b. 153b is retained.

[0177] The convex surface of the structure 151 is placed over the peeling starting point 162 formed on the processed member 153. The rotation of the structure 151 generates a force to peel off the first member 153a from the processed member 153. As a result, the first member 153a is peeled off from the vicinity of the peeling starting point 162. The first member 153a peeled off from the convex surface is wound around the convex surface and is then joined to the second member 103b. The first member 153a is held by the convex surface of the structure 151 and is placed on the stage 155. The second member 153b is held by the second member 153a.

[0178] If the peeling device has a transport means, the peeling device transports the wafer onto the stage 155 after peeling. The second member 153b and the first member 153a wound around the structure 151 are carried by the You may put it out.

[0179] As shown in FIGS. 14(A) and 14(B), a structure 151 and a conveying roller 158 As the stage 156 rotates, the sheet-like member 161 and the first member 1 53a may be attached to the stage 155 on which the processed member 153 was placed. A member 161 may be disposed in the space between the first and second electrodes 161 .

[0180] <Configuration example 3> Another configuration of a peeling device according to an embodiment of the present invention will be described with reference to FIG. 1A to 1C are diagrams illustrating a configuration and operation of a peeling device according to one embodiment of the present invention.

[0181] FIG. 15(A-1), FIG. 15(B-1) and FIG. 15(C-1) show a peeling device according to one embodiment of the present invention. 15(A-2), 15(B-2) and 15(C-3) are schematic diagrams illustrating the side surface of the device. 15(C-2) is a schematic diagram illustrating the top surface.

[0182] FIG. 15(A-1) and FIG. 15(A-2) show a peeling device according to one embodiment of the present invention. 1A and 1B are diagrams illustrating a state in which a process of separating a first member 103a from a base material 103 is started.

[0183] FIG. 15(B-1) and FIG. 15(B-2) show a peeling apparatus according to an embodiment of the present invention for peeling a processed member 10. 1 is a diagram illustrating a state in which the first member 103a is being separated from the first member 103a.

[0184] FIG. 15(C-1) and FIG. 15(C-2) show a peeling apparatus according to an embodiment of the present invention for peeling a processed member 10. 1 is a diagram illustrating a state in which the first member 103a has been completely separated from the first member 103a.

[0185] The peeling device described in the third configuration of the present embodiment has a cylindrical structure 101. The cylindrical structure 101 is in contact with the inner wall of the cylindrical structure 101 and rotates in synchronization with the rotation of the structure 101. The rotating body 101a is different from the peeling device described with reference to FIGS. The different configurations are described in detail here, and similar configurations can be used. The above description is incorporated herein by reference.

[0186] The structure 101 has a cylindrical shape. The structure 101 has a member 101b on its outer periphery. (See FIG. 15(A-1) and FIG. 15(A-2)).

[0187] The member 101b can modify the physical properties of the surface of the structure 101. For example, the adhesiveness can be improved. It can be given to the surface of the structure 101. Or, it can have elasticity that can disperse stress concentrated in the uneven parts. can be applied to the surface of the structure 101.

[0188] For example, rubber, silicone rubber, resin, or natural materials can be used for the member 101b.

[0189] In addition, when a joint is formed in the member 101b arranged in the structure 101, The workpiece is fed between the stage 105 and the structure 101 so that the workpiece 3 does not come into contact with the joint portion. do.

[0190] The rotor 101a is in contact with the inner circumference of the cylindrical structure 101 and is in contact with the outer circumference of the structure 101 and the stage. 105 so as to sandwich the processed member 103 therebetween.

[0191] The rotating body 101a is provided so as to be rotatable about a central axis. For example, the rotating body 101a may be provided with a cylindrical roller or a gear on its outer periphery.

[0192] When using a rotating body 101a having a gear on its outer periphery, the gear that meshes with the gear is placed in the structure 1. According to this configuration, the rotor 101a is driven by a driving mechanism, for example. Then, the rotation can be transmitted to the structure 101.

[0193] In the first step, a processed member 103 on which a peeling starting point 102 is formed is placed on a stage 10. 5 and the structure 101 (see FIG. 15(A-1) and FIG. 15(A-2)). In the case where the processed member 103 has a short side and a long side, the peeling starting point 102 is provided at the corner, and the rotating body It is advisable to insert the wire 101a from the corner at an angle of θ from the direction perpendicular to the central axis of the wire 101a. The peeling starts at the peeling starting point 102, and gradually spreads out, so that the first member 103a and the second member 103b are peeled off. can be separated.

[0194] In the second step, the separation of the first member 103a and the second member 103b is advanced. (See Figures 15(B-1) and 15(B-2)).

[0195] A liquid supply mechanism indicated by an arrow 108 is used to supply liquid to the first member 103a and the second member 103b. For example, the liquid is permeated into the separation surface of the separator 103b. Or liquid may be sprayed on it.

[0196] The liquid to be permeated or sprayed can be water, polar solvent, etc. By allowing the film to penetrate, the effects of static electricity and the like that occur with peeling can be suppressed. Alternatively, the peeling layer may be peeled off while being melted.

[0197] In the third step, the first member 103a and the second member 103b are separated (FIG. 15 (C-1) and Figure 15 (C-2)).

[0198] <Configuration Example 4> Another configuration of a peeling device according to an embodiment of the present invention will be described with reference to FIG. 1A to 1C are diagrams illustrating a configuration and operation of a peeling device according to one embodiment of the present invention.

[0199] 16(A-1), 16(B-1) and 16(C-1) show a peeling device according to one embodiment of the present invention. 16(A-2), 16(B-2) and 16(C-3) are schematic diagrams illustrating the side surface of the device. 16(C-2) is a schematic diagram illustrating the top surface.

[0200] FIG. 16(A-1) and FIG. 16(A-2) show a peeling device according to one embodiment of the present invention. 13 is a diagram illustrating a state in which a process of separating a first member 153a from a material 153 is started.

[0201] FIG. 16(B-1) and FIG. 16(B-2) show a peeling apparatus according to an embodiment of the present invention for peeling a processed member 15. 13 is a diagram illustrating a state in which a first member 153a is being separated from the first member 153a.

[0202] 16(C-1) and 16(C-2) show a peeling apparatus according to an embodiment of the present invention for peeling a processed member 15. 14 is a diagram illustrating a state in which the first member 153a has been completely separated from the first member 153a.

[0203] In addition, the peeling device described in the configuration example 4 of this embodiment is a cylindrical structure 101. The point that is provided in place of the structure 151 is in contact with the inner wall of the cylindrical structure 101 and is The fact that the rotating body 101a that can rotate in synchronization with the rotation of the This differs from the stripping device described with reference thereto.

[0204] Also, the point where the structure 101 is fixed and the stage 155 moves is shown in FIG. This is different from the stripping device described.

[0205] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0206] (Embodiment 3) In this embodiment, a structure of a display device and a display element according to one embodiment of the present invention will be described. .

[0207] The display device shown in FIG. 17A has a region having pixels of a display element (hereinafter, referred to as a pixel portion 502). 502) and a circuit section (hereinafter referred to as a pixel section) that is disposed outside the pixel section 502 and has a circuit for driving the pixel. A circuit having a function of protecting the element (hereinafter, a protection circuit 506) The protection circuit 506 may be omitted. good.

[0208] A part or the whole of the driver circuit portion 504 is formed on the same substrate as the pixel portion 502. This makes it possible to reduce the number of parts and terminals. When the pixel portion 502 and the entire portion are not formed on the same substrate, the COG or TAB (Tape Automated Bonding) is used to mount IC chips. good.

[0209] The pixel section 502 is arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more). A driving circuit (hereinafter referred to as a pixel circuit 501) for driving a plurality of display elements The gate driver 504 is a circuit for outputting a signal (scanning signal) for selecting a pixel. 04a), for supplying a signal (data signal) for driving the display element of the pixel. The pixel circuit 504 includes a driver circuit such as a source driver 504b.

[0210] The gate driver 504a includes a shift register and the like. A signal for driving the shift register is input via the slave unit 507, and a signal is output. For example, the gate driver 504a receives a start pulse signal, a clock signal, etc. The gate driver 504a outputs a pulse signal to a wiring to which a scanning signal (hereinafter , GL_1 to GL_X). A plurality of gate drivers 504a are provided, and the scanning lines GL_1 to Alternatively, the gate driver 504a may control the GL_X separately. However, the gate driver 504 has a function of supplying the a may also supply another signal.

[0211] The source driver 504b includes a shift register and the like. Through the slave unit 507, in addition to the signal for driving the shift register, the source of the data signal is also transmitted. The source driver 504b outputs a pixel circuit 5 based on the image signal. The source driver 504b has a function of generating a data signal to be written to the data buffer 501. A data signal is generated according to a pulse signal obtained by inputting a start pulse, a clock signal, etc. The source driver 504b has a function of controlling the output of the data signal. The potential of the wiring (hereinafter referred to as data lines DL_1 to DL_Y) connected to the data line Alternatively, the source driver 504b may have a function of supplying an initialization signal. However, the present invention is not limited to this, and the source driver 504b may supply other signals. It is Noh.

[0212] The source driver 504b is configured using, for example, a plurality of analog switches. The source driver 504b sequentially turns on a number of analog switches to generate a pixel pixel. The image signal can be time-division-multiplexed and output as a data signal. The source driver 504b may be configured as follows.

[0213] Each of the plurality of pixel circuits 501 is connected to one of the plurality of scanning lines GL through which a scanning signal is applied. A pulse signal is input to the data line DL, and a data signal is given through one of the data lines DL. A data signal is input to each of the pixel circuits 501. 04a controls the writing and holding of data of the data signal. For example, The second pixel circuit 501 is connected to a gate driver GL_m (where m is a natural number equal to or smaller than X) via a scanning line GL_m. A pulse signal is input from 504a, and the data line DL_n ( A data signal is input from the source driver 504b via a source driver 504c (n is a natural number equal to or smaller than Y).

[0214] The protection circuit 506 shown in FIG. 17A is, for example, a gate driver 504a and a pixel circuit 50 1. Alternatively, the protection circuit 506 is connected to the scanning line GL, which is the wiring between the source driver The data line DL is connected between the protection circuit 504b and the pixel circuit 501. The circuit 506 can be connected to a wiring between the gate driver 504a and the terminal unit 507. Alternatively, the protection circuit 506 may be a wiring between the source driver 504b and the terminal unit 507. The terminal unit 507 can be connected to the display device from an external circuit. This refers to the part provided with terminals for inputting control signals and image signals.

[0215] When a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected, the protection circuit It is a circuit that brings a line into electrical contact with another wiring.

[0216] As shown in FIG. 17A, a pixel section 502 and a driver circuit section 504 are provided with a protection circuit 506. By providing a This can improve the resistance of the display device to overcurrents caused by electrical discharges, etc. However, the configuration of the protection circuit 506 is not limited to this. For example, A configuration in which a protection circuit 506 is connected, or a configuration in which a protection circuit 506 is connected to the source driver 504b Alternatively, a protection circuit 506 may be connected to the terminal section 507. It is also possible.

[0217] In FIG. 17A, the gate driver 504a and the source driver 504b However, the present invention is not limited to this configuration. For example, only the gate driver 504a is formed, and a source driver circuit (IC chip) that is separately prepared is not formed. The configuration may also include a device that implements a

[0218] Note that a display element, a display device which is a device having a display element, a light-emitting element, and a A light-emitting device, which is a device for performing light emission, can have various forms or include various elements. An example of a display element, a display device, a light-emitting element, or a light-emitting device is an electroluminescent (EL) device. EL elements (including organic and inorganic EL elements, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (transistors that emit light in response to electric current), electron emitters, liquid crystal elements, electronic ink, Electrophoretic elements, Grating Light Valves (GLV), Plasma Displays (PDP), Display elements using MEMS (Micro-Electro-Mechanical Systems), digital Micromirror Device (DMD), DMS (Digital Micro Shutter), MI RASOL (registered trademark), IMOD (Interference Modulation) element, Shutter-type MEMS display element, optical interference-type MEMS display element, electrowet Electromagnetic devices such as piezoelectric ceramic displays and carbon nanotubes. Those having a display medium whose contrast, brightness, reflectance, transmittance, etc. change depending on the action An example of a display device using an EL element is an EL display. An example of a display device using emission elements is a field emission display (FE D) or SED type flat panel display (SED: Surface-conductive LCDs are used in LCD displays. An example of a display device that has been used is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, etc.). LCD, reflective LCD, direct-view LCD, projection LCD Display devices using electronic ink, electronic powder, or electrophoretic elements. An example is electronic paper. When realizing a display, a part or all of the pixel electrodes are used as reflective electrodes. For example, a part or the whole of the pixel electrode may be made of aluminum. In this case, the SRAM may be formed under the reflective electrode. It is also possible to provide a memory circuit such as a memory cell. This can further reduce power consumption. This can be done.

[0219] The pixel circuits 501 shown in FIG. 17(A) may be configured as shown in FIG. 17(B), for example. This can be done.

[0220] The pixel circuit 501 shown in FIG. 17B includes a liquid crystal element 570, a transistor 550, and a capacitor. Element 560.

[0221] The potential of one of the pair of electrodes of the liquid crystal element 570 is appropriately set according to the specifications of the pixel circuit 501. The alignment state of the liquid crystal element 570 is set by the written data. A common potential ( A common potential may be applied to the pair of electrodes of the liquid crystal element 570 of the pixel circuit 501 in each row. One of the poles may be given a different potential.

[0222] For example, the display device including the liquid crystal element 570 can be driven in a TN mode, an STN mode, or the like. mode, VA mode, ASM (Axially Symmetric Aligned Mi cro-cell mode, OCB (Optically Compensated B irefringence mode, FLC (Ferroelectric Liqui d Crystal) mode, AFLC (AntiFerroelectric Liq. uid Crystal) mode, MVA mode, PVA (Patterned Ver (Artificial Alignment) mode, IPS mode, FFS mode, or TBA (Transverse Bend Alignment) mode, etc. may also be used. In addition to the above-mentioned driving method, the display device can be driven by an ECB (Electric Carrier Bipolar Transistor) or the like. Ally Controlled Birefringence mode, PDLC(P Oligomeric Dispersed Liquid Crystal (PNLC) mode (Polymer Network Liquid Crystal) mode, guest hole However, the liquid crystal element and its driving method are not limited to these. A variety of different ones can be used.

[0223] In the pixel circuit 501 in the mth row and the nth column, One of the electrodes is electrically connected to the data line DL_n, and the other is a pair of electrodes of the liquid crystal element 570. The gate electrode of the transistor 550 is electrically connected to the other of the scanning lines GL _m. The transistor 550 is electrically connected to the on-state or the off-state. This has the function of controlling the writing of data of the data signal.

[0224] One of a pair of electrodes of the capacitor 560 is a wiring to which a potential is supplied (hereinafter, a potential supply line VL). and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. The value of the potential of the potential supply line VL is set appropriately according to the specifications of the pixel circuit 501. The capacitor 560 functions as a storage capacitor for storing written data.

[0225] For example, in a display device having the pixel circuit 501 shown in FIG. 17(B), The pixel circuits 501 in each row are sequentially selected by the gate driver 504a shown in FIG. 50 is turned on to write data of the data signal.

[0226] The pixel circuit 501 in which the data has been written is held by turning off the transistor 550. By performing this process for each row in sequence, an image can be displayed.

[0227] In addition, the pixel circuits 501 shown in FIG. 17(A) may have a configuration shown in FIG. 17(C), for example. It is possible.

[0228] The pixel circuit 501 shown in FIG. 17C includes transistors 552 and 554 and a capacitor element 562 and a light-emitting element 572.

[0229] One of the source and drain electrodes of the transistor 552 is supplied with a data signal. The transistor 55 is electrically connected to a wiring (hereinafter, referred to as a signal line DL_n). The gate electrode of 2 is electrically connected to the wiring (hereinafter referred to as the scanning line GL_m) to which the gate signal is applied. are connected to the network.

[0230] The transistor 552 is turned on or off to transmit the data of the data signal. It has the function of controlling writing.

[0231] One of a pair of electrodes of the capacitor 562 is connected to a wiring to which a potential is applied (hereinafter, a potential supply line VL a) and the other is electrically connected to the source electrode and drain electrode of the transistor 552. The second electrode is electrically connected to the other of the first and second electrodes.

[0232] The capacitor 562 functions as a storage capacitor for storing written data.

[0233] One of the source electrode and the drain electrode of the transistor 554 is connected to the potential supply line VL_a. In addition, the gate electrode of the transistor 554 is electrically connected to the It is electrically connected to the other of the source electrode and the drain electrode.

[0234] One of the anode and the cathode of the light-emitting element 572 is electrically connected to the potential supply line VL_b. The other one is electrically connected to the other of the source electrode and drain electrode of the transistor 554. To be continued.

[0235] The light-emitting element 572 may be, for example, an organic electroluminescence element (also called an organic EL element). However, the light-emitting element 572 is not limited to this. An inorganic EL element made of an inorganic material may also be used.

[0236] A high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b. and the other is supplied with a low power supply potential VSS.

[0237] In a display device having the pixel circuit 501 of FIG. 17(C), for example, The pixel circuits 501 in each row are sequentially selected by the gate driver 504a, and the transistors 552 are turned on. The data signal is written into the ON state.

[0238] The pixel circuit 501 in which the data has been written is held by turning off the transistor 552. Furthermore, the transistor 554 is turned on and off in response to the potential of the written data signal. The amount of current flowing between the source electrode and the drain electrode is controlled, and the light emitting element 572 is By performing this process row by row, an image can be displayed.

[0239] For example, in this specification, transistors having various structures are used as transistors. Therefore, there is no limitation on the type of transistor to be used. Examples of such transistors include transistors having single crystal silicon, or transistors having amorphous silicon or polycrystalline silicon. Amorphous silicon, microcrystalline (also called microcrystal, nanocrystal, or semi-amorphous) A transistor having a non-single crystal semiconductor film, such as a single crystal semiconductor film, can be used. Alternatively, thin-film transistors (TFTs) made from these semiconductors can be used. There are various advantages to using TFTs. For example, they are smaller than single crystal silicon. This allows the production to be carried out at a very low temperature, reducing production costs and enabling the use of larger production equipment. Since the manufacturing equipment can be made larger, it is possible to manufacture on large substrates. Since a large number of display devices can be manufactured, the manufacturing cost can be reduced. Therefore, a substrate with low heat resistance can be used. Alternatively, a display element can be manufactured using a transistor on a light-transmitting substrate. The light transmission of the transistor can be controlled. A part of the film that forms the star can transmit light. This improves the aperture ratio. It is possible.

[0240] In addition, when manufacturing polycrystalline silicon, a catalyst (such as nickel) is used to form the crystals. This will enable the manufacture of transistors with improved crystallinity and good electrical characteristics. As a result, the gate driver circuit (scanning line driver circuit) and the source driver circuit (signal line driver circuit) and signal processing circuits (signal generation circuits, gamma correction circuits, DA conversion circuits, etc.) on the board. It can be integrally formed.

[0241] In addition, when manufacturing microcrystalline silicon, a catalyst (such as nickel) is used to form the crystal. This makes it possible to further improve the crystallinity and manufacture transistors with good electrical characteristics. In some cases, the crystallinity can be improved by simply applying heat treatment without laser irradiation. As a result, part of the source driver circuit (analog switches, etc.) and the gate The gate driver circuit (scanning line driving circuit) can be formed integrally on the substrate. Therefore, if laser irradiation is not performed, the unevenness of the silicon crystallinity can be suppressed. Therefore, it is possible to display images with improved quality. However, the use of catalysts (such as nickel) It is possible to produce polycrystalline or microcrystalline silicon without the use of .

[0242] In addition, improving the crystallinity of silicon to polycrystalline or microcrystalline can improve the overall panel quality. It is preferable to perform the process in a region other than the region of the panel, but it is not limited to this. The crystallinity of the contact may be improved. The crystallinity can be improved by selectively applying a laser beam. For example, the peripheral circuit area, which is an area other than the pixels, can be selectively irradiated. Only in the gate driver circuit and the source driver circuit, or only in the source Laser light is irradiated only on a part of the driver circuit (e.g., analog switch). As a result, silicon crystallization is limited to areas where high-speed circuitry is required. Since there is little need for high-speed operation in the pixel region, the crystallinity is Even if the pixel circuit is not improved, it can still operate without problems. Since the region in which the crystallinity needs to be improved is small, the manufacturing process can be shortened. This improves throughput and reduces manufacturing costs. Since only a small number of manufacturing devices are required, manufacturing costs can be reduced.

[0243] An example of a transistor is a compound semiconductor (e.g., SiGe, GaAs, etc.). , or oxide semiconductors (e.g., Zn-O, In-Ga-Zn-O, In-Zn-O, I n-Sn-O, Sn-O, Ti-O, Al-Zn-Sn-O, In-Sn-Zn-O, etc. ) or the like. Alternatively, a transistor having these compound semiconductors or Alternatively, a thin film transistor in which these oxide semiconductors are thinned can be used. These allow the manufacturing temperature to be lowered, so that, for example, transistors can be manufactured at room temperature. As a result, it is possible to form a substrate having low heat resistance, such as a plastic substrate or a film substrate. It is possible to form transistors directly on the substrate. Oxide semiconductors are not only used for the channel portion of transistors, but are also used for other purposes. For example, these compound semiconductors or oxide semiconductors can be used as wiring, resistor elements, etc. They can be used as a transistor, a pixel electrode, or a light-transmitting electrode. Since it is possible to deposit or form the film at the same time as the transistor, costs can be reduced.

[0244] Note that an example of a transistor is a transistor formed by an ink-jet method or a printing method. These can be used for manufacturing at room temperature, low vacuum, or It can be manufactured on a large substrate without using a mask (reticle). This allows the transistor layout to be easily changed. Alternatively, it can be manufactured without using resist, which reduces material costs and the number of processes. It is also possible to apply the film only to the necessary parts, so the cost of applying the film to the entire surface can be reduced. This method wastes less material and is less costly than a method that involves etching afterwards.

[0245] An example of a transistor is a transistor having an organic semiconductor or a carbon nanotube. These can be used to fabricate transistors on a flexible substrate. It is possible to form transistors using organic semiconductors and carbon nanotubes. The device used can be shock resistant.

[0246] Note that as the transistor, transistors having various other structures can also be used. For example, transistors include MOS transistors, junction transistors, and bipolar transistors. A MOS transistor is used as the transistor. This allows the size of the transistors to be reduced. It is possible to mount a bipolar transistor as a transistor. This allows a large current to flow, which allows the circuit to operate at high speed. It is also possible to mix MOS transistors and bipolar transistors on a single substrate. This can realize low power consumption, small size, high speed operation, etc. come.

[0247] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0248] (Embodiment 4) In this embodiment, a display module in which the display device of one embodiment of the present invention can be used will be described. Explanations will be given.

[0249] The display module 8000 shown in FIG. 18 is made up of an upper cover 8001 and a lower cover 8002. In between, touch panel 8004 is connected to FPC8003, and touch panel 8005 is connected to FPC8005. Display panel 8006, backlight 8007, frame 8009, printed circuit board 8010 , and battery 8011.

[0250] The display device of one embodiment of the present invention can be used for the display panel 8006, for example.

[0251] The upper cover 8001 and the lower cover 8002 are connected to the touch panel 8004 and the display panel. The shape and dimensions can be changed as appropriate to fit the size of the upper cover 8006. The bar 8001 and the lower cover 8002 may be flexible.

[0252] The touch panel 8004 is a resistive or capacitive touch panel, and the display panel 8 8006. In addition, the opposing substrate (sealing substrate) of the display panel 8006 It is also possible to provide the display panel 80 with a touch panel function. It is also possible to provide an optical sensor in each pixel of the touch panel to make it an optical touch panel. , the touch panel 8004 may be flexible.

[0253] The backlight 8007 has a light source 8008. In FIG. Although the configuration in which the light source 8008 is disposed on the 8007 has been illustrated, the present invention is not limited to this. For example, a light source 8008 is arranged at the end of a backlight 8007, and a light diffusion plate is further used. In addition, when a self-luminous light-emitting element such as an organic EL element is used, or when a reflective In the case of a panel or the like, the backlight 8007 may not be provided. The backlight 8007 may be flexible.

[0254] The frame 8009 protects the display panel 8006 and also functions to stabilize the operation of the printed circuit board 8010. It also functions as an electromagnetic shield to block electromagnetic waves generated by the frame. The frame 8009 may have a function as a heat sink. The material may be flexible.

[0255] The printed circuit board 8010 includes a power supply circuit, a signal circuit for outputting a video signal, and a clock signal. The power supply circuit is provided with a signal processing circuit. Alternatively, the power source may be a battery 8011 provided separately. 1 can be omitted when using a commercial power source. The printed circuit board 8010 is FPC. It's fine.

[0256] In addition, the display module 8000 includes additional components such as a polarizing plate, a retardation plate, and a prism sheet. It may also be provided as such.

[0257] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0258] (Embodiment 5) In this embodiment, a transistor and a display device that can be used in one embodiment of the present invention will be described. The materials constituting the transistor will be described. The transistors 350, 352, 550, 552, 554, etc. described in the previous embodiments are Note that the transistor described in this embodiment can be transferred onto a flexible substrate. This is the configuration before installation.

[0259] FIG. 19A illustrates an example of a transistor that can be used in a display device according to one embodiment of the present invention. The transistor includes an organic resin layer 910 formed on a substrate 900. , an insulating film 915, a gate electrode layer 920, an insulating film 931, and an insulating film 932 are formed in this order. The gate insulating film 930 and the oxide semiconductor layer 940 are connected to a part of the oxide semiconductor layer. The source electrode layer 950 and the drain electrode layer 960 are connected to each other. A gate insulating film 930, an oxide semiconductor layer 940, a source electrode layer 950 and a drain electrode layer An insulating film 970 , an insulating film 980 , and an insulating film 990 may be formed on the pole layer 960 .

[0260] In addition, in the transistor of one embodiment of the present invention, as shown in FIG. The conductive layer is formed on the insulating film 990 so as to overlap the gate electrode layer 920 and the oxide semiconductor layer 940. The conductive film may be used as a second gate electrode layer (back gate). By using this, it is possible to increase the on-current and control the threshold voltage. In order to increase the capacitance, for example, the gate electrode layer 920 and the conductive film 921 are set to the same potential, and a double gate In order to control the threshold voltage, the gate A constant potential different from that of the electrode layer 920 may be supplied to the conductive film 921 .

[0261] In addition, the transistor of one embodiment of the present invention has a channel protection layer as shown in FIGS. Here, the insulating film 933 protects the channel region. Therefore, the insulating film 933 is disposed only in a region overlapping with the channel region. As shown in Figs. 25(A) and (B), the slits may be arranged in other areas. It may be possible.

[0262] In addition, the transistor of one embodiment of the present invention has a self-alignment function as shown in FIGS. In the structure of FIG. 26(A), the source region 9 51 and the drain region 961 are the connections of the source electrode layer 950 and the drain electrode layer 960. The generation of oxygen defects by etching, and the gate electrode layer 920 is used as a mask to ionize boron, phosphorus, and aluminum. It can be formed by doping impurities such as fluorine. In the structure of B), the source region 951 and the drain region 961 are doped as described above. Instead, a hydrogen-containing insulating film 9 such as a silicon nitride film is formed so as to be in contact with a part of the oxide semiconductor layer 940. 75 and diffusing hydrogen into part of the oxide semiconductor layer 940. Cut.

[0263] Further, the transistor of one embodiment of the present invention may have a self-aligned structure as shown in FIG. In the structure of FIG. 27(A), the source region 951 and The source electrode layer 950 and the drain electrode layer 960 are in contact with each other. The generation of oxygen defects and the ion implantation of boron, phosphorus, argon, etc. using the gate insulating film 930 as a mask. In the structure of FIG. The source electrode layer 950, the drain electrode layer 960 and the gate electrode layer 920 are formed in the same process. It can be formed in a process.

[0264] Further, the transistor of one embodiment of the present invention may have a self-aligned structure as shown in FIG. In the structure of FIG. 27(B), the source region 951 and The drain region 961 is formed by ion implantation of boron, phosphorus, argon, etc. using the gate insulating film 930 as a mask. In addition to doping with impurities, a nitride semiconductor layer is formed in contact with part of the oxide semiconductor layer 940. An insulating film 975 containing hydrogen, such as a silicon oxide film, is formed to absorb hydrogen into part of the oxide semiconductor layer 940. In this configuration, the lower resistance source region 951 A drain region 961 can be formed without doping with the above impurities. Alternatively, the insulating film 975 may not be formed.

[0265] Note that an element which forms oxygen vacancies in the oxide semiconductor layer is used as an impurity (an impurity element). Representative examples of impurity elements are boron, carbon, nitrogen, fluorine, aluminum, Silicon, phosphorus, chlorine, and rare gas elements. Representative examples of rare gas elements are helium, Neon, argon, krypton and xenon.

[0266] When hydrogen is added to an oxide semiconductor in which oxygen vacancies have been formed by the addition of an impurity element, the oxygen vacancies Hydrogen enters the loss site and a donor level is formed near the conduction band. As a result, the oxide semiconductor The conductivity of the oxide semiconductor increases and it becomes a conductor. An oxide semiconductor that has become a conductor is called an oxide conductor. In general, oxide semiconductors have a large energy gap and are therefore highly resistant to visible light. On the other hand, an oxide conductor is an oxide semiconductor having a donor level near the conduction band. Therefore, the effect of absorption due to the donor level is small, and it is oxidized by visible light. It has the same level of transparency as a semiconductor.

[0267] Here, the resistance of a film formed of an oxide conductor (hereinafter referred to as an oxide conductor layer) The temperature dependency of the rate will be explained with reference to FIG.

[0268] Here, a sample having an oxide conductor layer was prepared. The oxide conductor layer (OC_SiN x ), In a doping apparatus, argon is added to the oxide semiconductor layer and the oxide semiconductor layer is in contact with the silicon nitride film. The oxide conductor layer (OC_Ar doped + SiN x ), or Pla In the plasma processing apparatus, the oxide semiconductor layer is exposed to argon plasma, and the silicon nitride film is The oxide conductor layer formed by contacting with the plasma (OC_Ar+SiNx ) The silicon nitride film contains hydrogen.

[0269] Oxide conductor layer (OC_SiN x The method for preparing a sample containing the ZnO film is as follows. A silicon oxynitride film with a thickness of 400 nm was formed by plasma CVD, and then the oxygen plasma was By exposing the silicon oxynitride film to a plasma and adding oxygen ions to it, oxygen is released by heating. Next, a silicon oxynitride film that releases oxygen when heated was formed. A sputtering target with an atomic ratio of In:Ga:Zn=5:5:6 was used on the film. A 100 nm thick In-Ga-Zn oxide film was formed by sputtering, and then heated at 450°C in nitrogen. After heat treatment in a nitrogen and oxygen mixed gas atmosphere at 450°C, Next, a silicon nitride film with a thickness of 100 nm was formed by plasma CVD. The heat treatment was carried out in a mixed gas atmosphere of nitrogen and oxygen at 0°C.

[0270] Oxide conductor layer (OC_Ar doped+SiN x The method for preparing the sample containing A 400 nm thick silicon oxynitride film is formed on a glass substrate by plasma CVD. After that, it is exposed to oxygen plasma to add oxygen ions to the silicon oxynitride film, A silicon oxynitride film that releases oxygen by heating was formed. On the silicon oxynitride film, a sputtering tantalum with an atomic ratio of In:Ga:Zn=5:5:6 was deposited. A 100 nm thick In-Ga-Zn oxide film was formed by sputtering using a target. After heat treatment in a nitrogen atmosphere at 450°C, the specimen was placed in a nitrogen and oxygen mixed gas atmosphere at 450°C. Next, the In-Ga-Zn oxide film was doped with an accelerated The voltage was 10 kV and the dose was 5 × 10 14 / cm 2 Add argon to the In-G The oxygen vacancies were created in the a-Zn oxide film. Next, a 100 nm thick film was formed by plasma CVD. A silicon nitride film was formed. Next, the substrate was heated at 350°C in a mixed gas atmosphere of nitrogen and oxygen. I understood.

[0271] Oxide conductor layer (OC_Ar plasma+SiN x The preparation method of the sample including A silicon oxynitride film with a thickness of 400 nm was formed on a glass substrate by plasma CVD. A silicon oxynitride film that releases oxygen when heated by exposing it to oxygen plasma after formation. Next, a silicon oxynitride film having an atomic ratio of In was formed on the silicon oxynitride film which releases oxygen by heating. The thickness was determined by sputtering using a sputtering target with a Ga:Zn ratio of 5:5:6. A 100 nm In-Ga-Zn oxide film was formed and heat-treated in a nitrogen atmosphere at 450°C. After that, it was heat-treated at 450°C in a mixed gas atmosphere of nitrogen and oxygen. In the device, argon plasma is generated and accelerated argon ions are injected into the In-Ga-Z Next, a 1 mm thick film was prepared by plasma CVD. A silicon nitride film with a thickness of 0.1 nm was then formed. Next, the substrate was placed in a nitrogen and oxygen mixed gas atmosphere at 350° C. It was heat treated in air.

[0272] Next, the resistivity of each sample was measured and the results are shown in Figure 36. Here, the resistivity was measured using a four-terminal The van der Pauw method was used. In FIG. 36, the horizontal axis indicates the measurement temperature, and the vertical axis indicates The resistivity of the oxide conductor layer (OC_SiNx The measurement results of ) are shown with square marks, and Compound conductor layer (OC_Ar dope+SiN x The measurement results of oxide conductors are shown by triangles. Electric layer (OC_Ar plasma+SiN x ) The measurement results are indicated by circles.

[0273] Although not shown, the oxide semiconductor layer not in contact with the silicon nitride film has a high resistivity. Therefore, the oxide conductor layer has a lower resistivity than the oxide semiconductor layer. It is clear that...

[0274] As can be seen from FIG. 36, the oxide conductor layer (OC_Ar doped+SiN x ) and acid Compound conductor layer (OC_Ar plasma+SiN x ) contains oxygen vacancies and hydrogen In the case of 80K or more and 290K or less, the resistivity change is small. The variability is less than ±20%. Or, the change in resistivity is less than ±20% at temperatures between 150K and 250K. The mobility is less than ±10%. In other words, oxide conductors are degenerate semiconductors, and the conduction band edge and the full band It is estimated that the electric potential of the oxide conductor layer is equal to or approximately equal to the Elmi level. By using it as the source and drain regions of a transistor, the oxide conductor layer and the source The contact with the conductive film that functions as the source electrode and the drain electrode is an ohmic contact, and the oxide The contact resistance between the conductive layer and the conductive film that functions as the source electrode and the drain electrode can be reduced. In addition, the resistivity of the oxide conductor has low temperature dependence, so that the oxide conductor layer and the source The variation in contact resistance with the conductive film that functions as the electrode and drain electrode is small, resulting in high reliability. It is possible to fabricate a transistor having a low resistance.

[0275] In addition, as shown in FIGS. 28A and 28B, the transistor of one embodiment of the present invention has a gate insulator. A conductive film 921 may be provided so as to overlap with the oxide semiconductor layer 940 with an insulating film 935 interposed therebetween. In addition, in FIG. 28(A) and (B), the transistor shown in FIG. 26(A) and (B) is 27A and 27B. It can also have 1.

[0276] In the display device which is one embodiment of the present invention, an oxide semiconductor is used for an active layer as described above. Transistors using a carbide semiconductor layer have higher mobility than transistors using amorphous silicon. Because of the high resistance, it is easy to make the transistors smaller, and the pixels can be made smaller. In addition, a transistor including an oxide semiconductor layer has excellent reliability and can be used in a flexible display device. However, one aspect of the present invention is not limited to this. Depending on the circumstances, the active layer may include a semiconductor other than an oxide semiconductor.

[0277] As shown in FIGS. 19A and 19B, the width of the gate electrode layer 920 is It is preferable that the width of the layer 940 is larger than that of the layer 940. The gate electrode layer serves as a light-shielding layer, and the electrical characteristics of the oxide semiconductor layer 940 are reduced when light is irradiated thereon. In addition, in EL display devices, top-gate transistors are used. By using a transistor, the gate electrode layer can be used as a light shielding layer.

[0278] Components of a transistor according to one embodiment of the present invention will be described in detail below.

[0279] The substrate 900 is preferably a rigid substrate in order to facilitate the transfer process to a flexible substrate. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, a metal substrate, etc. The substrate 900 corresponds to the first substrate 462 shown in Embodiment 1. do.

[0280] The organic resin layer 910 may be made of, for example, epoxy resin, aramid resin, acrylic resin, polyimide resin, or the like. For example, an organic resin film such as an organic resin film of polyamide resin, polyamideimide resin, or the like can be used. The organic resin layer 910 corresponds to the organic resin layer 320a shown in the first embodiment.

[0281] The insulating film 915 may be, for example, a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or A single layer of a silicon nitride oxide film or a laminate of these films can be used. The film 915 corresponds to the first insulating film 321a shown in the first embodiment.

[0282] The gate electrode layer 920 and the conductive film 921 are made of chromium (Cr), copper (Cu), aluminum (Al), or the like. Aluminum (Al), gold (Au), silver (Ag), zinc (Zn), molybdenum (Mo), tantalum ( Ta), titanium (Ti), tungsten (W), manganese (Mn), nickel (Ni), A metal element selected from iron (Fe) and cobalt (Co), or a material containing the above-mentioned metal elements as components. The metal elements may be alloys of the above metal elements or alloys of the above metal elements. In addition, the gate electrode layer 920 may have a single-layer structure or a stacked structure of two or more layers.

[0283] The gate electrode layer 920 and the conductive film 921 are formed of indium tin oxide and tungsten oxide. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide A conductive material having light transmission properties, such as an indium tin oxide material or an indium tin oxide material containing silicon oxide, is used. In addition, the conductive material having the light-transmitting property and the metal element may be laminated. It is also possible.

[0284] In addition, an In-Ga-Zn-based oxynitride semiconductor is provided between the gate electrode layer 920 and the insulating film 932. film, In-Sn-based oxynitride semiconductor film, In-Ga-based oxynitride semiconductor film, In-Zn-based oxynitride semiconductor film Semiconductor film, Sn-based oxynitride semiconductor film, In-based oxynitride semiconductor film, metal nitride film (InN ZnN, etc.) may be provided.

[0285] The insulating films 931 and 932 functioning as the gate insulating film 930 are formed by plasma chemical vapor deposition. Product(PECVD:(Plasma Enhanced Chemical Vapor Silicon oxide film, silicon oxynitride film, etc. are formed by deposition, sputtering, etc. film, silicon oxynitride film, silicon nitride film, aluminum oxide film, hafnium oxide film, oxide Yttrium oxide film, zirconium oxide film, gallium oxide film, tantalum oxide film, magnesium oxide film An insulating layer containing one or more of aluminium oxide, lanthanum oxide, cerium oxide and neodymium oxide films. The gate insulating film 930 can be formed by using insulating films 931 and 932. A single-layer insulating film selected from the above materials, or an insulating film having three or more layers, without using a laminated structure. may also be used.

[0286] Note that the insulating layer in contact with the oxide semiconductor layer 940 which functions as a channel formation region of the transistor The insulating film 932 is preferably an oxide insulating film, and contains oxygen in excess of the stoichiometric composition. It is more preferable that the insulating film 932 has a region containing oxygen (an oxygen excess region). The insulating film 932 is an insulating film capable of releasing oxygen. To prevent this, for example, the insulating film 932 may be formed in an oxygen atmosphere. Oxygen may be introduced into the insulating film 932 to form an oxygen excess region. Ion implantation, ion doping, plasma immersion ion implantation, plasma Processing methods, etc. can be used.

[0287] Furthermore, when hafnium oxide is used for the insulating films 931 and 932, the following effects are obtained. Hafnium oxide has a higher dielectric constant than silicon oxide and silicon oxynitride. Therefore, the physical thickness can be made larger than the equivalent oxide thickness, so the equivalent oxide thickness is set to 10 nm. Even if the thickness is reduced to 5 nm or less, the leakage current due to the tunnel current is reduced. That is, a transistor with a small off-state current can be realized. Hafnium oxide with a crystalline structure has a higher specific resistance than hafnium oxide with an amorphous structure. Therefore, in order to make a transistor with a small off-current, the crystal structure It is preferable to use hafnium oxide having a crystal structure of monoclinic or cubic. However, one embodiment of the present invention is not limited to these.

[0288] In this embodiment, a silicon nitride film is formed as the insulating film 931, and a silicon nitride film is formed as the insulating film 932. The silicon nitride film has a lower dielectric constant than the silicon oxide film. The thickness required to obtain the same capacitance as a silicon oxide film is large, so The gate insulating film 930 of the sta- tor is made physically thick by including a silicon nitride film. Therefore, the dielectric strength of the transistor can be improved, and the static electricity of the transistor can be reduced. Destruction can be suppressed.

[0289] The oxide semiconductor layer 940 is typically made of In-Ga oxide, In-Zn oxide, In-Mn oxide, or In-Zn oxide. -Zn oxide (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, Sn or Hf In particular, the oxide semiconductor layer 940 may be an In-M-Zn oxide (wherein M is Al , Ti, Ga, Y, Zr, La, Ce, Nd, Sn or Hf) are preferably used.

[0290] The oxide semiconductor layer 940 is an In-M-Zn oxide (wherein M is Al, Ti, Ga, Y, Zr, L a, Ce, Nd, Sn or Hf) are used to deposit In-M-Zn oxide. The atomic ratio of the metal elements in the sputtering target preferably satisfies In≧M and Zn≧M. The atomic ratio of the metal elements in such a sputtering target is In:M:Z. n=1:1:1, In:M:Zn=5:5:6, In:M:Zn=3:1:2 are preferred The atomic ratio of the oxide semiconductor layer 940 to be formed is determined by the above-mentioned sputtering method as an error. The atomic ratio of metal elements contained in the target varies by ±40%. nothing.

[0291] When the oxide semiconductor layer 940 is an In-M-Zn oxide, the The atomic ratio of In and M is preferably 25 atomic % or more of In and 75 atomic % or more of M. mic%, more preferably In is 34 atomic % or more and M is 66 atomic % or more. % or less.

[0292] The oxide semiconductor layer 940 has an energy gap of 2 eV or more, preferably 2.5 e V or more, and more preferably 3 eV or more. By using a semiconductor, the off-state current of a transistor can be reduced.

[0293] The thickness of the oxide semiconductor layer 940 is 3 nm or more and 200 nm or less, preferably 3 nm or more. The thickness is set to at most 100 nm, and more preferably at least 3 nm and at most 50 nm.

[0294] In addition, an oxide semiconductor layer with low carrier density is used as the oxide semiconductor layer 940. For example, the oxide semiconductor layer 940 has a carrier density of 1×10 17 pieces / cm 3 The following is preferably is 1×10 15 pieces / cm 3 Less than 1×10, more preferably 13 pieces / cm 3 The following is better Preferably 1×10 11 pieces / cm 3 The following applies.

[0295] In addition, the semiconductor characteristics and electrical characteristics (field effect) of the required transistors are not limited to these. It is sufficient to use a material with an appropriate composition according to the required properties (e.g., the resultant mobility, threshold voltage, etc.). In order to obtain semiconductor characteristics of a transistor, the carrier density and impurity of the oxide semiconductor layer 940 are The concentration of metals, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc. are appropriately adjusted. It is preferable.

[0296] In the oxide semiconductor layer, hydrogen, nitrogen, carbon, silicon, and metal elements other than the main component are For example, hydrogen and nitrogen contribute to the formation of donor levels and increase the carrier density. In addition, silicon forms an impurity level in the oxide semiconductor layer. The impurity levels can become traps and degrade the electrical characteristics of a transistor. It is preferable to reduce the impurity concentration in the semiconductor layer and at the interface with other layers.

[0297] In order to provide stable electrical characteristics to a transistor having an oxide semiconductor layer as a channel, The present invention relates to a method for manufacturing an oxide semiconductor layer, comprising: reducing an impurity concentration in the oxide semiconductor layer to make the oxide semiconductor layer intrinsic or substantially intrinsic; Here, the term "substantially intrinsic" means that the carrier density of the oxide semiconductor layer is But 1×10 17 / cm 3 Preferably less than 1 x 10 15 / cm 3 is less than More preferably, 1×10 13 / cm 3 Less than 8×10 11 / cm 3 less than 1×10 11 / cm 3 less than 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 It means that it is more than this.

[0298] In order to make the oxide semiconductor layer intrinsic or substantially intrinsic, a secondary ion beam (SIMS) In the case of oxide semiconductors, for example, The silicon concentration at a certain depth in the semiconductor layer or in a certain region of the oxide semiconductor layer is 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 less than , and more preferably 1×1018 atoms / cm 3 The portion shall be less than The hydrogen concentration may vary depending on the depth of the oxide semiconductor layer or the thickness of the oxide semiconductor layer. In a region of the body layer, 2×10 20 atoms / cm 3 Less than or equal to 5×10 1 9 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 The following is further Preferably 5 x 10 18 atoms / cm 3 The following parts are included: The nitrogen concentration is, for example, at a certain depth in the oxide semiconductor layer or at In a certain area, 5×10 19 atoms / cm 3 Less than 5 x 10 18 at oms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 The following are more preferred Or 5×10 17 atoms / cm 3 It shall have the following parts:

[0299] In addition, when the oxide semiconductor layer contains crystals and contains silicon or carbon at a high concentration, the oxide In order to prevent the crystallinity of the oxide semiconductor layer from being reduced, For example, at a certain depth in the oxide semiconductor layer or in a certain region of the oxide semiconductor layer In this case, the silicon concentration is 1×10 19 atoms / cm 3 Less than 5 x 10 1 8 atoms / cm 3 less than 1×1018 atoms / cm 3 Less than In addition, for example, at a certain depth of the oxide semiconductor layer, In a region of the oxide semiconductor layer, the carbon concentration is set to 1×10 19 atoms / cm 3 less than , preferably 5 x 10 18 atoms / cm 3 less than 1×10 18 at oms / cm 3 It shall have a part that is less than

[0300] Specifically, a transistor in which a highly purified oxide semiconductor layer is used for a channel formation region can be The low f-current can be verified by various experiments. For example, 6 Even if the device has a channel length of 10 μm, the voltage between the source and drain electrodes ( In the drain voltage range of 1V to 10V, the off-state current is Below the measurement limit of Isa, that is, 1×10 -13 A characteristic of less than A can be obtained. In this case, the off-state current normalized by the channel width of the transistor is 100 zA / μm or less. In addition, by connecting the capacitance element and the transistor, The off-state current is measured using a circuit that controls the charge flowing out of the capacitance element with the transistor. In the measurement, a highly purified oxide semiconductor layer was used as a channel type transistor. The off-state voltage of the transistor is calculated from the change in the charge amount per unit time of the capacitance element. The current was measured when the voltage between the source and drain electrodes of the transistor was 3 V. It was found that an even lower off-current of several tens of yA / μm can be obtained when In addition, a transistor in which a highly purified oxide semiconductor layer is used for a channel formation region has an off-state current The current is significantly lower than that of a transistor using crystalline silicon.

[0301] The source electrode layer 950 and the drain electrode layer 960 are formed of a material that extracts oxygen from the oxide semiconductor layer. It is preferable to use a conductive film that has good electrical conductivity. For example, Al, Cr, Cu, Ta, Ti, M O, W, Ni, Mn, Nd, Sc, etc. can be used. In addition, alloys and tops of the above materials can be used. Conductive nitrides of the above materials may also be used. The material may be a laminate of a plurality of materials selected from the group consisting of conductive nitrides of materials such as oxygen, The high melting point of Ti is a good candidate for this purpose, as it can be easily bonded to other metals and the subsequent process temperatures can be relatively high. It is more preferable to use W. In addition, low-resistance Cu or Cu-X alloy (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) or the above materials and Cu or Cu-X alloy A gold lamination may also be used.

[0302] Cu-X alloy (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) In the case of the insulating film, the covering film is formed in a region in contact with the oxide semiconductor layer or in contact with the insulating film by heat treatment. The coating film may be formed from a compound containing X. An example of a compound containing X is Examples include X oxide, In-X oxide, Ga-X oxide, In-Ga-X oxide, In -Ga-Zn-X oxide, etc. The coating film is formed, and the coating film acts as a blocking film. As a result, it is possible to suppress the Cu in the Cu-X alloy film from penetrating into the oxide semiconductor layer. Cut.

[0303] The conductive film has a property of extracting oxygen from the oxide semiconductor layer. The oxygen is released from the oxide semiconductor layer, and oxygen vacancies are formed in the oxide semiconductor layer. The oxygen vacancies combine with the corresponding regions to significantly change the region to n-type. The resulting region can act as the source or drain of a transistor.

[0304] The insulating films 970, 980, and 990 function as protective insulating films. Reference numeral 70 denotes an insulating film that is permeable to oxygen. Note that the insulating film 970 is a film that is formed later. The insulating film 980 also functions as a film for reducing damage to the oxide semiconductor layer 940 when the insulating film 980 is formed. do.

[0305] The insulating film 970 has a thickness of 5 nm to 150 nm, preferably 5 nm to 50 nm. Silicon oxide, silicon oxynitride, etc. having a thickness of 100 nm or less can be used. In this case, the silicon oxynitride film is a film whose composition contains more oxygen than nitrogen. A silicon nitride oxide film is a film whose composition contains more nitrogen than oxygen. vinegar.

[0306] In addition, it is preferable that the insulating film 970 has a small amount of defects. Typically, the insulating film 970 has a small amount of defects as determined by ESR measurement. , the spin density of the signal at g=2.001 originating from the silicon dangling bond is 3×10 17 spins / cm 3 This is because the insulating film 970 is preferably If the density of defects is high, oxygen will be bonded to the defects, and the amount of oxygen in the insulating film 970 will increase. This is because the amount of transmission decreases.

[0307] The insulating film 980 is an oxide insulating film containing more oxygen than the oxygen that satisfies the stoichiometric composition. The oxide insulating film containing more oxygen than the stoichiometric composition is formed by heating. Heat causes some of the oxygen to be released. Acids that contain more oxygen than is required for the stoichiometric composition The oxide insulating film had a desorption of oxygen of 1.0×10 18 a toms / cm 3 More than 3.0×10 20 atoms / cm 3 Oxidation is more than The surface temperature of the film during the TDS analysis was 100°C or higher for 7 00°C or lower, or in the range of 100°C to 500°C is preferred.

[0308] The insulating film 980 has a thickness of 30 nm to 500 nm, preferably 50 nm to 400 nm. Silicon oxide, silicon oxynitride, etc. having a thickness of 00 nm or less can be used.

[0309] In addition, it is preferable that the insulating film 980 has a small amount of defects. Typically, the insulating film 980 has a small amount of defects as determined by ESR measurement. , the spin density of the signal at g=2.001 originating from the silicon dangling bond is 1.5×10 18 spins / cm 3 Less than or even 1×10 18 spins / cm 3 Below Note that the insulating film 980 is preferably made of an oxide semiconductor, as compared with the insulating film 970. Since it is farther away from layer 940 , it may have a higher defect density than insulating film 970 .

[0310] In addition, since the insulating films 970 and 980 can be made of the same material, In some cases, it may be difficult to clearly confirm the interface between the insulating film 970 and the insulating film 980. In this embodiment, the interface between the insulating film 970 and the insulating film 980 is shown by a dashed line. In the embodiment, the two-layer structure of the insulating film 970 and the insulating film 980 has been described. For example, the insulating film 970 may have a single layer structure, the insulating film 980 may have a single layer structure, or the insulating film 980 may have a three-layer structure. A laminated structure of more than one layer may also be used.

[0311] The insulating film 990 is a blocking material for oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc. By providing the insulating film 990, oxygen from the oxide semiconductor layer 940 can be prevented from being generated. In addition, it is possible to prevent hydrogen, water, and the like from entering the oxide semiconductor layer 940 from the outside. The insulating film 990 may be, for example, a nitride insulating film. The insulating film may be silicon nitride, silicon oxynitride, aluminum nitride, or aluminum oxynitride. In addition, blocking elements such as oxygen, hydrogen, water, alkali metals, and alkaline earth metals are Instead of a nitride insulating film that has a blocking effect, a silicon oxide film that has a blocking effect against oxygen, hydrogen, water, etc. An oxide insulating film having a blocking effect against oxygen, hydrogen, water, and the like may be provided. The films include aluminum oxide, aluminum oxynitride, gallium oxide, and gallium oxynitride. yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, etc. There is.

[0312] The oxide semiconductor layer 940 may have a structure in which a plurality of oxide semiconductor layers are stacked. For example, as in the transistor illustrated in FIG. 20A, the oxide semiconductor layer 940 may be a first oxide semiconductor layer. The first oxide semiconductor layer 941a and the second oxide semiconductor layer 941b may be stacked. The first oxide semiconductor layer 941a and the second oxide semiconductor layer 941b are formed of metal oxides having different atomic ratios. It may be used. For example, one of the oxide semiconductors containing two types of metals, three types of metals, or four types of metals may be used for one oxide semiconductor layer, and an oxide semiconductor containing two types of metals different from those of the one oxide semiconductor layer, three types of metals, or four types of metals may be used for the other oxide semiconductor layer.

[0313] Also, the constituent elements of the first oxide semiconductor layer 941a and the second oxide semiconductor layer 941b may be the same, and the atomic ratios of both may be made different. For example, the atomic ratio of one oxide semiconductor layer may be In:Ga:Zn = 1:1:1, 5:5:6, or 3:1:2, and the atomic ratio of the other oxide semiconductor layer may be In:Ga:Zn = 1:3:2, 1:3:4, 1:3:6, 1:4:5, 1:6:4, or 1:9:6. The atomic ratio of each oxide semiconductor layer includes a variation of plus or minus 20% of the above atomic ratio as an error.

[0314] At this time, among one oxide semiconductor layer and the other oxide semiconductor layer, the atomic ratio of In and Ga in the oxide semiconductor layer closer to the gate electrode (channel side) is set to In ≧ Ga (In is greater than or equal to Ga), and the atomic ratio of In and Ga in the oxide semiconductor layer farther from the gate electrode (back channel side) is set to In < Ga, whereby a transistor with high field-effect mobility can be manufactured. On the other hand, by setting the atomic ratio of In and Ga in the oxide semiconductor layer on the channel side to In < Ga and the atomic ratio of In and Ga in the oxide semiconductor layer on the back channel side to In ≧ Ga (In is greater than or equal to Ga), the amount of variation in the threshold voltage due to the change over time of the transistor and the reliability test can be reduced.

[0315] ​​​​​​​​​​​​​​​In addition, the semiconductor film of the transistor is formed of a first oxide semiconductor layer, a second oxide semiconductor layer, a third oxide semiconductor layer, and a third oxide semiconductor layer. In this case, the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer may have a three-layer structure. The constituent elements may be the same, but the atomic ratio of each may be different. The structure of the transistor is shown in FIG. 20(B) and FIG. 29(A) and (B). The multi-layered structure of the semiconductor film is similar to that of the other transistors shown in this embodiment. This can also be applied to the

[0316] In the transistor type shown in FIG. 20(B) and FIG. 29(A) and (B), the third oxide semiconductor The oxide semiconductor layer 942a, the second oxide semiconductor layer 942b, and the first oxide semiconductor layer 942c are They are laminated in order from the gate insulating film side.

[0317] The first oxide semiconductor layer 942c and the third oxide semiconductor layer 942a are made of the following material: InM 1x Zinc y O z (x≧1 (x is 1 or more), y>1, z>0, M1=Ga, Hf, etc.) The second oxide semiconductor layer 942b is made of a material that can be expressed as I nM 2x Zinc y O z (x≧1 (x is 1 or more), y≧x (y is x or more), z>0, M2=G Use materials that can be expressed as the formula (a, Sn, etc.).

[0318] The conduction band minimum of the first oxide semiconductor layer 942c and the conduction band minimum of the third oxide semiconductor layer 942a The conduction band minimum of the second oxide semiconductor layer 942b is the deepest from the vacuum level compared to the band minimum. The materials of the first, second and third oxide semiconductor layers are arranged so as to form such a well-type structure. Choose appropriately.

[0319] For example, the first oxide semiconductor layer 942c and the third oxide semiconductor layer 942a are formed in an atomic ratio of In:Ga:Zn=1:1:1, 1:3:2, 1:3:4, 1:3:6, 1:4:5, The second oxide semiconductor layer 9 is formed of an oxide semiconductor layer having a ratio of 1:6:4 or 1:9:6. The atomic ratio of 42b is In:Ga:Zn=1:1:1, 5:5:6, or 3:1:2. The insulating film can be formed using an oxide semiconductor layer.

[0320] The first to third oxide semiconductor layers 942c to 942a contain the same elements. Therefore, the second oxide semiconductor layer 942b has a low conductivity at the interface with the third oxide semiconductor layer 942a. In particular, the defect level (trap level) is The defect levels are fewer than those at the interface between the gate insulating film and the third oxide semiconductor layer 942a. For this reason, when oxide semiconductor layers are stacked as described above, the deterioration of the transistor over time is reduced. This makes it possible to reduce the amount of variation in threshold voltage due to fabrication and reliability testing.

[0321] In addition, the conduction band minimum of the first oxide semiconductor layer 942a and the third oxide semiconductor layer 942c The conduction band minimum of the second oxide semiconductor layer 942b is the deepest from the vacuum level compared to the conduction band minimum of the first oxide semiconductor layer 942b. The first, second and third oxide semiconductor layers are arranged to form a well structure such that By selecting the appropriate materials, it is possible to increase the field-effect mobility of transistors. In addition, the aim is to reduce the amount of variation in threshold voltage caused by aging and reliability testing of transistors. can be done.

[0322] In addition, the first to third oxide semiconductor layers 942a to 942c have different crystallinity. Note that at least the second oxide semiconductor that can be a channel formation region may be used. The oxide semiconductor layer 942b is preferably a film having crystallinity, and the oxide semiconductor layer 942b has a crystallinity perpendicular to the surface. It is more preferable that the film be c-axis oriented in the direction.

[0323] In addition, in the channel formation region of the top-gate transistor shown in FIG. The cross section in the channel width direction is preferably configured as shown in FIG. The gate electrode layer 920 electrically surrounds the oxide semiconductor layer 940 in the channel width direction. The on-current is increased by the above-mentioned structure of the transistor. This is called the channel (s-channel) structure.

[0324] In addition, in a structure having a conductive film 921 as shown in FIGS. When the conductive film 921 and the conductive layer 920 are at the same potential, as shown in FIG. The two may be connected via a contact hole.

[0325] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0326] (Embodiment 6) In this embodiment, a transistor included in a display device according to one embodiment of the present invention will be described. do.

[0327] The transistors included in the display device of one embodiment of the present invention do not necessarily have the same structure. For example, a transistor included in a pixel portion of a display device and a driving circuit for driving the pixel portion By using transistors with different configurations for the path, appropriate electrical characteristics can be given to each. In addition, the reliability of the display device can be improved.

[0328] In addition, the transistors included in the driver circuit section have a double gate structure, so that It is also possible to provide a transistor with high effective mobility.

[0329] The channel lengths of the transistors included in the driver circuit portion and the pixel portion may be different. In particular, the channel length of the transistor 194 included in the driving circuit section is set to less than 2.5 μm. The thickness of the transistor included in the pixel portion can be set to 1.45 μm or more and 2.2 μm or less. The channel length of the resistor 190 is set to 2.5 μm or more, or 2.5 μm or more and 20 μm or less. It is possible.

[0330] The channel length of the transistor included in the driving circuit section is set to less than 2.5 μm, preferably less than 1.4 By making the size of the transistor larger than 5 μm and smaller than 2.2 μm, the current is reduced compared to the transistors included in the pixel area. It is possible to increase the field effect mobility and increase the on-current. A driver circuit portion capable of high speed operation can be manufactured.

[0331] In addition, the high field effect mobility of the transistors in the driver circuit section allows the number of input terminals to be reduced. It can be reduced.

[0332] FIG. 30 shows a transistor shown in FIG. 26(A) as a transistor included in the pixel portion of the liquid crystal display device shown in FIG. The transistor shown in FIG. 29(A) is used as a transistor included in the driver circuit portion. FIG. 31 shows an example of applying a transistor to the EL display device shown in FIG. This is an example in which different transistors are used in the pixel section and the driver circuit section. As the transistor, the transistors shown in FIG. 26(B), FIG. 27(A), and FIG. 27(B) are used. As a transistor included in the driver circuit portion, the transistor shown in FIG. 27(A) and (B), and the transistor having a multilayer structure including oxide semiconductor layers shown in FIG. can also be applied.

[0333] The transistors in the pixel area detect light emitted from the backlight or EL element. For example, the atomic ratio of In:Ga:Zn=1:1:1 is required for a highly reliable transistor. The oxide semiconductor layer formed by sputtering using the material as a target is used as the channel formation region. By using this in the region, a transistor with high reliability against light irradiation can be formed.

[0334] On the other hand, the transistors included in the driver circuit section are preferably transistors with high field effect mobility. In addition to the above-mentioned configuration, for example, a material having an atomic ratio of In:Ga:Zn=3:1:2 may be used. The oxide semiconductor layer formed by sputtering using a material as a target is used for the channel formation region. By this, a transistor with high field effect mobility can be formed.

[0335] In this embodiment, the oxide semiconductor layer of one of the transistors has a stacked structure. A method for easily fabricating two types of transistors on the same substrate is shown in Figures 32 and 33. 33 is used as a transistor for use in the pixel portion. 1 illustrates a cross section in the channel length direction of a transistor A having a similar configuration to the transistor in (A). Also, on the right side of the drawing, the transistor shown in FIG. 29(A) is used as a driver circuit. 1 shows a cross section in the channel length direction of a transistor B having a similar structure to that of the transistor B. The symbols common to transistors A and B are attached to only one of them. The method for manufacturing a transistor described in this embodiment includes the steps of forming a transistor on a flexible substrate described in Embodiment 1. This includes a method for preparing the elements (such as organic resin layers) for transposition.

[0336] The substrate 900 may be a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like. In addition, a single crystal semiconductor substrate such as silicon or silicon carbide, or a polycrystalline semiconductor substrate can be used. Substrates, compound semiconductor substrates such as silicon germanium, SOI (Silicon On In It is also possible to use a quartz crystal integrator substrate, on which semiconductor elements are mounted. The one provided may be used.

[0337] The organic resin layer 910 may be made of, for example, epoxy resin, aramid resin, acrylic resin, polyimide resin, or the like. For example, an organic resin film such as an organic resin film of polyamide resin, polyamideimide resin, or the like can be used. Among them, polyimide resin is preferable because of its high heat resistance. In this case, the thickness of the polyimide resin is 3 nm or more and 20 μm or less, preferably 500 nm or more and 200 μm or less. The polyimide resin can be applied by spin coating, dip coating, doctor blade coating, etc. The lamination can be formed by a lamination method or the like.

[0338] The insulating film 915 may be a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a nitride oxide film. A silicon carbide film or the like can be used, and the film can be formed by a sputtering method, a CVD method or the like.

[0339] The insulating layer 935 is formed by a method such as plasma CVD or sputtering, using aluminum oxide, oxide Magnesium, silicon oxide, silicon oxynitride, gallium oxide, germanium oxide, oxide Yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and oxide insulating films such as tantalum oxide, silicon nitride, silicon nitride oxide, aluminum nitride, etc. The insulating film is made of a nitride such as aluminum oxide or a mixture of the above materials. Alternatively, the insulating film may be a stack of the above materials, and may include at least an oxide semiconductor layer. The upper layer in contact with the oxide semiconductor layer is formed of a material containing excess oxygen that can supply oxygen to the oxide semiconductor layer. It is preferable to do so.

[0340] The insulating layer 935 is also formed by ion implantation, ion doping, plasma immersion ion implantation, or the like. Oxygen may be added by implantation, plasma treatment, or the like. By adding the insulating layer 935, oxygen can be more easily supplied to the oxide semiconductor layer. It is possible.

[0341] Note that the surface of the substrate 900 is an insulator, and therefore the influence of impurity diffusion into an oxide semiconductor layer to be formed later may occur. In the case where there is no effect, the insulating layer 935 may not be provided. As shown in FIG. 1B, a conductive film 921 is formed on an insulating film 915, and an insulating film is formed on the conductive film. An edge layer 935 may be formed.

[0342] Next, a first oxide semiconductor layer 942 of the driver circuit transistor is formed over the insulating layer 935. a first oxide semiconductor film 940c which is to become a second oxide semiconductor layer 942b; The compound semiconductor film 940b is formed by sputtering, CVD, MBE or the like.

[0343] Next, a resist mask 801 is formed in the driver circuit region by using a lithography method (FIG. 32 Then, the first oxide semiconductor film 940c and the The second oxide semiconductor film 940b is selectively etched to form the first oxide semiconductor layer 942c. A stack of the first oxide semiconductor layer and a second oxide semiconductor layer 942b is formed (see FIG. 32B).

[0344] Next, a third oxide semiconductor film to be a third oxide semiconductor layer 942a was formed so as to cover the stack. A film 940a is formed.

[0345] The first oxide semiconductor film 940c, the second oxide semiconductor film 940b, and the third oxide semiconductor film The conductive film 940a may be made of the material described in the fifth embodiment. In the above, for example, the first oxide semiconductor film 940c and the third oxide semiconductor film 940 a) In-Ga-Zn oxide with In:Ga:Zn=1:1:1 [atomic ratio], b) The semiconductor film 940b is made of In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn=3:1:2. Note that the first oxide semiconductor film 940c, the second oxide semiconductor film 940b, The atomic ratios of the third oxide semiconductor film 940a and the third oxide semiconductor film 940b are each calculated by subtracting the above atomic ratios from the atomic ratios of the first oxide semiconductor film 940a as an error. In addition, if sputtering is used for deposition, the above The material can be used as a target to form a film.

[0346] In addition, the first oxide semiconductor film 940c, the second oxide semiconductor film 940b, and the third oxide semiconductor film The oxide semiconductor that can be used for the oxide semiconductor film 940a is at least indium It is preferable that the material contains In or zinc (Zn). Alternatively, the material contains both In and Zn. In addition, it is preferable to reduce variations in electrical characteristics of a transistor using the oxide semiconductor. It is preferable to include a stabilizer therewith to reduce the strain on the load.

[0347] The stabilizers are gallium (Ga), tin (Sn), hafnium (Hf), and aluminum. Aluminum (Al) or zirconium (Zr). Also, with other stabilizers The lanthanides lanthanum (La), cerium (Ce), and praseodymium (P r), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium ( Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium Er, Thulium, Ytterbium, Lutetium, etc. .

[0348] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and In-Zn oxide. , Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In- Mg oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al-Zn oxide, I n-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al -Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm-Zn oxide, I n-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy -Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide oxide, In-Yb-Zn oxide, In-Lu-Zn ​​oxide, In-Sn-Ga-Zn oxide In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al -Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al-Zn oxide It is possible.

[0349] In addition, for example, In-Ga-Zn oxide is a material with In, Ga, and Zn as the main components. It means that the oxide contains metal elements other than In, Ga, and Zn. In this specification, a film made of In-Ga-Zn oxide is referred to as an IGZO film. Also called.

[0350] In addition, InMO3(ZnO) m (m>0 and m is not an integer) M may be one selected from Ga, Y, Zr, La, Ce, or Nd. It denotes a metal element or elements. Also, In2SnO5(ZnO) n (n>0, and and n is an integer) may be used.

[0351] However, the second oxide semiconductor film 940b is a first oxide semiconductor film 940c and a third oxide semiconductor film 940b. A material having a larger electron affinity than the compound semiconductor film 940a is selected.

[0352] Note that the oxide semiconductor film is preferably formed by a sputtering method. For this purpose, RF sputtering, DC sputtering, AC sputtering, etc. can be used. The uniformity of the film thickness distribution, the film composition distribution, or the crystallinity distribution of the oxide semiconductor film is improved. For this purpose, it is preferable to use DC sputtering or AC sputtering rather than RF sputtering. stomach.

[0353] The second oxide semiconductor film 940b is a first oxide semiconductor film 940c and a third oxide semiconductor film 940b. The indium content of the oxide semiconductor film 940a is preferably larger than that of the oxide semiconductor film 940b. The s orbital of the heavy metal contributes to carrier conduction, and by increasing the In content, Therefore, more s orbitals overlap, and therefore oxides with a composition in which In is more abundant than Ga are The mobility is higher than that of oxides with a composition equal to or less than a. By using oxides with a high indium content in the transistor formation region, a high mobility transistor can be realized. This makes it possible to realize

[0354] After the third oxide semiconductor film 940a is formed, first heat treatment may be performed. The treatment is carried out at a temperature of 250° C. to 650° C., preferably 300° C. to 500° C. This can be done in an active gas atmosphere, an atmosphere containing 10 ppm or more of oxidizing gas, or under reduced pressure. In addition, the atmosphere of the first heat treatment is an inert gas atmosphere, and the desorbed oxygen is removed after the heat treatment. In order to supplement the oxygen, the first heat treatment may be performed in an atmosphere containing 10 ppm or more of an oxidizing gas. As a result, the crystallinity of the first to third oxide semiconductor films 940c to 940a can be improved. In addition, the insulating layer 935 and the first to third oxide semiconductor films 940c to 940d are Impurities such as hydrogen and water can be removed from the solid film 940a. This may be performed after etching the third oxide semiconductor film 940a, which will be described later.

[0355] Next, a resist mask 802 is formed in the pixel region by using a lithography method. The mask 803 is applied to the first oxide semiconductor layer 942c and the second oxide semiconductor layer 942b in the driver circuit region. The insulating layer 942 is formed on a stack of the organic semiconductor layer 942b (see FIG. 32(C)).

[0356] Next, the third oxide semiconductor film 940a is selectively etched using the resist mask. The first oxide semiconductor layer 943a is formed in the pixel region. The oxide semiconductor layer 942c, the second oxide semiconductor layer 942b, and the third oxide semiconductor layer 942 A laminate consisting of a is formed (see FIG. 32(D)).

[0357] Next, a first conductive film is formed over the oxide semiconductor layer 943a and the above stack. The films are made of Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc, and A single layer or a laminate of a material selected from the group consisting of the above metallic materials and alloys of the above metallic materials can be used.

[0358] Next, a resist mask is formed on the first conductive film, and the first conductive film is The source electrode layer 950 and the drain electrode layer 960 are formed by selectively etching the conductive film. At this time, the oxide semiconductor layer 943a and the first oxide Part of the stack including the semiconductor layer 942c to the third oxide semiconductor layer 942a becomes n-type.

[0359] Next, a gate insulating film 930 is formed so as to cover the pixel region and the driving circuit region (FIG. 33 The gate insulating film 930 is made of aluminum oxide, magnesium oxide, silicon oxide, etc. Silicon, silicon oxide nitride, silicon nitride oxide, silicon nitride, gallium oxide, gallium oxide Al, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, halide oxide The gate insulating film 930 may be made of fluorine, tantalum oxide, or the like. The gate insulating film 930 may be a laminate of the above materials. The method can be used to form the insulating layer.

[0360] Next, a second conductive film that is to become a gate electrode layer 920 is formed on the gate insulating film 930. Conductive films include Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ru, and Ag. , Mn, Nd, Sc, Ta and W can be used as single layers, laminates or alloys. The conductive film can be formed by a sputtering method, a CVD method, or the like. The film may be a conductive film containing nitrogen. Layers may also be used.

[0361] Next, a resist mask is formed over the second conductive film, and the second The conductive film is selectively etched to form a gate electrode layer 920 .

[0362] Next, the oxide semiconductor layer 943a and the first to third oxide semiconductor layers 942c to 942d are The semiconductor layer 942a is a stack of a source electrode layer 950, a drain electrode layer 960, and a gate electrode layer 970. The region not covered with the electrode layer 920 is doped with impurities 810 to make it n-type, and the source region 95 1 and drain region 961 are formed (see FIG. 33(C)).

[0363] The method of adding the impurity includes ion implantation, ion doping, plasma imaging, etc. The deposition method may be a deposition ion implantation method, a plasma treatment method, or the like. The impurity is added by selectively etching the gate insulating film 930 using the gate electrode layer 920 as a mask. This may be done after chipping.

[0364] Examples of impurities that increase the electrical conductivity of the oxide semiconductor layer include phosphorus, arsenic, antimony, and fluorine. Uranium, aluminum, silicon, nitrogen, helium, neon, argon, krypton, xenon Selected from the group consisting of non, indium, fluorine, chlorine, titanium, zinc, and carbon. One or more may be used.

[0365] When a rare gas is added to an oxide semiconductor layer as an impurity element, the metal element in the oxide semiconductor layer The bond between oxygen and the oxide semiconductor film is broken, and oxygen vacancies are formed. The vacancies interact with hydrogen that remains in the oxide semiconductor layer or is added later, causing the oxide semiconductor layer to The conductivity of the conductor layer is increased. Specifically, hydrogen enters the oxygen vacancies in the oxide semiconductor film. This generates electrons, which act as carriers, resulting in high electrical conductivity.

[0366] In FIG. 33C, the gate electrode layer 920 and the source electrode The width of the region that does not overlap with the drain electrode layer and the drain electrode layer, that is, the offset region, is less than 0.1 μm. In this case, the doping of the above impurities is not necessary. When the thickness is less than 1 μm, the difference in the on-current of a transistor with and without impurity doping is becomes extremely small.

[0367] Next, an insulating film 970, an insulating film 980, and a gate electrode layer 920 are formed on the gate insulating film 930 and the gate electrode layer 920. Then, an insulating film 990 is formed (see FIG. 33(D)).

[0368] In addition, the insulating film 970 and / or the insulating film 980 may be subjected to ion implantation, ion doping, Using plasma immersion ion implantation and plasma treatment methods, etc. By adding oxygen, the insulating film 970 and / or the insulating film 9 80 to the oxide semiconductor layer 943a and the first to third oxide semiconductor layers 942c to 942d. This makes it easier to supply oxygen to the stack of the compound semiconductor layers 942a.

[0369] Next, a second heat treatment may be performed under the same conditions as the first heat treatment. By the second heat treatment, the insulating layer 935, the insulating film 970, and the insulating film 98 are Excess oxygen is easily released from the oxide semiconductor layer 943a and the first oxide semiconductor layer 943b. By reducing oxygen vacancies in the stack including the conductor layer 942c to the third oxide semiconductor layer 942a, This can be done.

[0370] In addition, a transistor having the same structure as that of the transistor in FIG. 26(B) is used as a transistor in a pixel portion. The transistor C is used as the transistor for the driver circuit. A manufacturing method of a transistor D having a similar structure is shown in FIG.

[0371] First, the same steps as in the above-mentioned method for manufacturing a transistor are performed up to the step shown in FIG. Then, a gate electrode layer 920 is formed (see FIG. 34A).

[0372] Next, the gate insulating film 930 is etched using the gate electrode layer 920 as a mask (FIG. 34). (See (B)).

[0373] Next, a film of silicon nitride, aluminum nitride, or the like is formed so as to be in contact with part of the oxide semiconductor layer 940. An insulating film 975 containing hydrogen is formed, and hydrogen is diffused into part of the oxide semiconductor layer 940 (FIG. The diffused hydrogen is bonded to oxygen vacancies in the oxide semiconductor layer 940 to form a doped oxide semiconductor layer. Since the source region 951 and the drain region 961 are formed as a low resistance, In the structure of FIG. 34C, the oxide semiconductor layer is doped with the above-described impurities. You may also use the

[0374] Next, insulating films 970, 980, and 990 are formed on the insulating film 975 (FIG. 34(D)).

[0375] Through the above steps, a transistor having an oxide semiconductor layer with a stacked structure and a transistor having a single-layer structure A transistor including an oxide semiconductor layer can be easily formed over the same substrate. The pixel section has excellent display quality, is capable of high-speed operation, and is less susceptible to deterioration due to light irradiation. A display device can be fabricated.

[0376] The various films described in this embodiment, such as a metal film, a semiconductor film, and an inorganic insulating film, are representatively The can be formed by sputtering or plasma CVD, but other methods, such as thermal It may be formed by a CVD (Chemical Vapor Deposition) method. An example of the thermal CVD method is MOCVD (Metal Organic Chemical Vapor Deposition). Al Vapor Deposition (ALD) method and Atomic Layer Deposition (ALD) method. eposition method.

[0377] Thermal CVD is a film formation method that does not use plasma, so defects can occur due to plasma damage. This has the advantage that the

[0378] In the thermal CVD method, the source gas and the oxidizing agent are fed into the chamber at the same time, and the inside of the chamber is By reacting near or on the substrate under atmospheric or reduced pressure, the material is deposited on the substrate. Film formation may also be performed.

[0379] In the ALD method, the pressure inside the chamber is set to atmospheric pressure or reduced pressure, and the source gases for the reaction are sequentially The gas may be introduced into the chamber and the film may be formed by repeating the gas introduction sequence. For example, By switching between the switching valves (also called high-speed valves), two or more types of raw materials can be mixed. The gases are supplied to the chamber in order, and the first source gas is supplied to the chamber in order to prevent the mixture of the multiple source gases. At the same time or after this, an inert gas (argon, nitrogen, etc.) is introduced to If an inert gas is introduced at the same time, the inert gas acts as a carrier gas. In addition, an inert gas may be introduced at the same time as the second raw material gas is introduced. In addition, instead of introducing an inert gas, the first source gas is discharged by evacuation, and then the second source gas is introduced. The first source gas may be adsorbed on the surface of the substrate to form a first layer. The second layer is deposited on the first layer by reacting with the second source gas introduced later, forming a thin film. This process is repeated several times while controlling the gas introduction sequence until the desired thickness is formed. The thickness of the thin film can be adjusted by repeating the gas introduction sequence. The thickness can be precisely adjusted by changing the number of times the film is repeated. This is suitable for producing ET.

[0380] The thermal CVD method such as the MOCVD method or the ALD method may be used in the above-described embodiments. It can form various films such as metal films, semiconductor films, and inorganic insulating films. For example, In-Ga -ZnO X When forming a (X>0) film, trimethylindium, trimethylgallium In addition, the chemical formula of trimethylindium is The chemical formula for trimethylgallium is Ga(CH3)3. The chemical formula for dimethylzinc is Zn(CH3)2. The combination is not limited to the above, and triethylgallium (chemical formula Ga(C2 H5)3) can be used instead of dimethyl zinc, and diethyl zinc (chemical formula Zn(C2 H5)2) can also be used.

[0381] For example, when forming a hafnium oxide film using a deposition system that uses ALD, the solvent and A liquid containing a hafnium precursor compound (hafnium alkoxide solution, typically tetrakis The raw material gas was vaporized with trimethylsilyl dimethylamide hafnium (TDMAH) as an oxidizing agent. Two types of gases are used: tetrakisdimethylamidohafnium (O3) and tetrakisdimethylamidohafnium (TDMHA). The chemical formula is Hf[N(CH3)2]4. Other material liquids include tetrakis(ethy) (dimethylamido) hafnium.

[0382] For example, when forming an aluminum oxide film using a film forming apparatus that uses ALD, a solvent A liquid containing an aluminum precursor compound (e.g., trimethylaluminum (TMA)) is vaporized. Two types of gases are used: the source gas and H2O as an oxidizing agent. The chemical formula for nium is Al(CH3)3. Other materials include tris(dimethylamino) Aluminum tris(2,2,3-triisobutylaluminum), aluminum tris(2,2,3-triisobutylaluminum), 6,6-tetramethyl-3,5-heptanedionate).

[0383] For example, when forming a silicon oxide film using a deposition system that uses ALD, The chlorine contained in the adsorbed material is removed, and the oxidizing gas (O2 , nitrous oxide) radicals are supplied to react with the adsorbate.

[0384] For example, when forming a tungsten film using a deposition system that uses ALD, WF6 gas is used. The initial tungsten film is formed by repeatedly introducing B2H6 gas and WF6 Gas and H2 gas are introduced simultaneously to form a tungsten film. Note that instead of B2H6 gas, Alternatively, SiH4 gas may be used.

[0385] For example, an oxide semiconductor film, such as In-Ga-ZnO, can be formed by a film formation apparatus using ALD. X When forming a (X>0) film, In(CH3)3 gas and O3 gas are introduced in sequence. Then, Ga(CH3)3 gas and O3 gas are introduced simultaneously to form an In-O layer. Then, Zn(CH3)2 and O3 gases are introduced simultaneously to form a ZnO layer. The order of these layers is not limited to this example. A mixed compound layer such as a Ga-O layer, an In-Zn-O layer, or a Ga-Zn-O layer may be formed. In addition, H2O gas obtained by bubbling an inert gas such as Ar instead of O3 gas was used. However, it is preferable to use O3 gas that does not contain H. In(CH3) Instead of the gas In(C2H5)3, gas Ga(CH3)3 may be used. Alternatively, Ga(C2H5)3 gas may be used. Zn(CH3)2 gas may also be used. That's fine.

[0386] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0387] (Embodiment 7) In this embodiment, an oxide semiconductor that can be used for a transistor according to one embodiment of the present invention will be described. The conductive film will now be described.

[0388] <Structure of oxide semiconductors> The structure of an oxide semiconductor will be described below.

[0389] In this specification, "parallel" means that the angle between two straight lines is between -10° and 10°. Therefore, it includes the case where the angle is between -5° and 5°. "Approximately parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. "Perpendicular" means that two straight lines are arranged at an angle of 80° to 100°. Therefore, it includes the case where the angle is between 85° and 95°. refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0390] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. .

[0391] Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor, polycrystalline oxide semiconductor Examples of the oxide semiconductor include a conductor, a microcrystalline oxide semiconductor, and an amorphous oxide semiconductor.

[0392] From another point of view, the oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor other than the amorphous oxide semiconductor. Crystalline oxide semiconductors are classified into single crystal oxide semiconductors, CAAC-O S, polycrystalline oxide semiconductors, and microcrystalline oxide semiconductors.

[0393] <caac-os> First, let me explain about CAAC-OS. xis aligned nanocrystals) It is also possible.

[0394] CAAC-OS is an oxide semiconductor that has multiple crystal parts (also called pellets) aligned along the c-axis. It is a conductor.

[0395] Transmission Electron Microscope (TEM) A composite analysis image (high resolution) of the bright-field image and the diffraction pattern of CAAC-OS was obtained by using a scope. When observing the high-resolution TEM image, multiple pellets can be confirmed. In the high-resolution TEM image, the boundaries between the pellets, i.e., grain boundaries, are not clearly visible. Therefore, it is not possible to clearly confirm the presence of the CAAC-OS. Therefore, it can be said that the decrease in electron mobility caused by the above phenomenon is unlikely to occur.

[0396] The CAAC-OS observed by TEM will be described below. This shows a high-resolution TEM image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. For high-resolution TEM imaging, spherical aberration correction (SAC) is required. The spherical aberration corrector function was used. In particular, it is called a Cs-corrected high-resolution TEM image. This was carried out using an atomic resolution analytical electron microscope, such as the JEM-ARM200F manufactured by Nippon Denki Co., Ltd. This can be done.

[0397] FIG. 21(B) shows an enlarged Cs-corrected high-resolution TEM image of region (1) in FIG. 21(A). From FIG. 21(B), it can be seen that the metal atoms are arranged in layers in the pellet. The arrangement of each metal atom layer is the same as that of the surface on which the CAAC-OS film is formed (also called the surface on which the film is formed). The surface on which the CAAC-OS is formed or the top surface of the CAAC-OS reflects the unevenness of the surface on which the CAAC-OS is formed or the top surface of the CAAC-OS.

[0398] As shown in Figure 21(B), CAAC-OS has a characteristic atomic arrangement. The characteristic atomic arrangement is shown by auxiliary lines in Figure 21(B) and Figure 21(C). Therefore, the size of each pellet is about 1 nm to 3 nm, and the size of each pellet is about 1 nm to 3 nm. It can be seen that the size of the gap caused by the inclination of the The zeolites can also be referred to as nanocrystals (nc).

[0399] Here, based on the Cs-corrected high-resolution TEM image, the pellet of CAAC-OS on the substrate 5120 was The layout of the 5100 is shown diagrammatically as a stack of bricks or blocks. (See FIG. 21(D)). The inclination between the pellets observed in FIG. 21(C) The location where the crack occurs corresponds to an area 5161 shown in FIG.

[0400] FIG. 22(A) shows the Cs Corrected high-resolution TEM images are shown for regions (1), (2), and (3) in FIG. 22(A). The enlarged Cs-corrected high-resolution TEM images are shown in Fig. 22(B), Fig. 22(C), and Fig. 22(D), respectively. 22(D). From Fig. 22(B), Fig. 22(C) and Fig. 22(D), the pellet is It can be seen that the metal atoms are arranged in triangular, tetragonal or hexagonal shapes. However, no regularity is observed in the arrangement of metal atoms among different pellets.

[0401] Next, the CA analyzed by X-ray diffraction (XRD) We will explain AC-OS. For example, CAAC-OS with InGaZnO4 crystals When the structure is analyzed using the out-of-plane method, the result is as shown in Figure 23(A). A peak may appear at a diffraction angle (2θ) of about 31°. Since the crystal orientation of CAAC-OS is attributed to the (009) plane of nO4, the crystal orientation of CAAC-OS is considered to be c-axis oriented. It can be seen that the c-axis is oriented in a direction substantially perpendicular to the surface on which the film is formed or the upper surface.

[0402] In addition, in the out-of-plane structural analysis of CAAC-OS, 2θ is 31° In addition to the peaks around 2θ of 36°, a peak may also appear around 2θ of 36°. The peaks near the c-axis indicate that some of the CAAC-OS contains crystals that do not have the c-axis orientation. The more preferable CAAC-OS is the structure solution by the out-of-plane method. In the analysis, a peak is observed at 2θ of approximately 31°, but no peak is observed at 2θ of approximately 36°.

[0403] On the other hand, in-plan X-ray irradiation is performed on CAAC-OS in a direction perpendicular to the c-axis. When the structure is analyzed by the δ method, a peak appears at 2θ of about 56°. This peak is due to In It is assigned to the (110) plane of the GaZnO4 crystal. In the case of CAAC-OS, 2θ is set to 56 The sample was rotated around the normal vector of the sample surface as the axis (φ axis) while performing the analysis. Even if a φ scan is performed, no clear peak appears as shown in FIG. However, in the case of a single crystal oxide semiconductor such as InGaZnO4, 2θ is fixed at around 56° and φ shift is When scanning was performed, the peaks attributable to the crystal plane equivalent to the (110) plane were observed as shown in FIG. Therefore, from the structural analysis using XRD, CAAC-OS has the following structure: It can be seen that the orientation of the a-axis and b-axis is irregular.

[0404] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with nO4 crystals, a probe with a diameter of 300 nm was placed parallel to the sample surface. When an electron beam is incident, a diffraction pattern (selected area transmission electron diffraction) like that shown in Figure 40(A) is obtained. This diffraction pattern may show the InGaZnO4 This includes spots due to the (009) plane of the crystal. Therefore, even with electron diffraction, The pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is approximately aligned on the surface to be formed or the upper surface. On the other hand, the same sample was probed perpendicular to the sample surface. The diffraction pattern when an electron beam with a diameter of 300 nm is incident is shown in FIG. (B) shows a ring-shaped diffraction pattern. Therefore, by electron diffraction, It is seen that the a-axis and b-axis of the pellets contained in the CAAC-OS have no orientation. In addition, the first ring in FIG. 40(B) is the (010) plane of the InGaZnO4 crystal. This is thought to be due to the (100) plane and other factors. The second ring in Figure 40(B) This is thought to be due to the (110) plane, etc.

[0405] In addition, the CAAC-OS is an oxide semiconductor with a low density of defect states. Examples of defects include impurity-induced defects and oxygen vacancies. C-OS can also be considered an oxide semiconductor with a low impurity concentration. It can also be said that the oxide semiconductor has few oxygen vacancies.

[0406] Impurities contained in an oxide semiconductor can act as carrier traps or carrier generation sources. In addition, oxygen vacancies in an oxide semiconductor may become carrier traps or may cause hydrogen By capturing atoms, they can become a carrier generation source.

[0407] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, oxygen is more abundant than metal elements such as silicon that constitute oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor and rearrange the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, and nitrogen Carbon oxide and other elements have a large atomic radius (or molecular radius), so they can easily arrange the atoms of oxide semiconductors. This causes the crystallinity to decrease.

[0408] In addition, an oxide semiconductor with a low density of defect states (few oxygen vacancies) can reduce the carrier density. Such an oxide semiconductor can be obtained by using a high-purity intrinsic or substantially high-purity intrinsic oxide. CAAC-OS has a low impurity concentration and a low density of defect states. It is easy to obtain a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. A transistor using C-OS has electrical characteristics in which the threshold voltage is negative (normal In addition, the acid is highly pure or substantially pure. The oxide semiconductor has fewer carrier traps. The charge takes a long time to be discharged and behaves like a fixed charge. Therefore, transistors using oxide semiconductors with high impurity concentrations and high defect state densities are On the other hand, transistors using CAAC-OS may have unstable electrical characteristics. The resulting transistor has small fluctuations in electrical characteristics and is highly reliable.

[0409] In addition, because the density of defect states in CAAC-OS is low, the capacitive coupling generated by light irradiation can be suppressed. Therefore, the transistor using CAAC-OS is less likely to be captured by the defect level. The electrical characteristics of a transistor vary little when exposed to visible or ultraviolet light.

[0410] <Microcrystalline oxide semiconductor> Next, a microcrystalline oxide semiconductor will be described.

[0411] Microcrystalline oxide semiconductors are regions where crystals can be confirmed in high-resolution TEM images. A region in which no clear crystal part can be confirmed is also included. The crystal part contained in the crystal is 1 nm to 100 nm or 1 nm to 10 nm in size. In particular, microcrystals with a size of 1 nm to 10 nm or 1 nm to 3 nm are often found. The oxide semiconductor having nanocrystals is called nc-OS (nanocrystalline- The nc-OS is called the "High Resolution Oxide Semiconductor." In some cases, the grain boundaries cannot be clearly seen in the TEM images. Therefore, in the following, we will refer to the pellets in nc-OS as the pellets of the same origin. The crystalline part of S is sometimes called a pellet.

[0412] The nc-OS is a nano-sized area (e.g., an area of ​​1 nm to 10 nm, especially 1 nm to 3 nm). The nc-OS has periodic atomic arrangement in the sub-nm region. There is no regularity in the crystal orientation between the dots. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be indistinguishable from amorphous oxide semiconductors. For example, there is an XRD apparatus that uses X-rays with a diameter larger than that of the pellet for nc-OS. When structural analysis is performed using the out-of-plane method, No peaks were detected. Also, for nc-OS, the probe diameter (e.g. When electron diffraction (also called selected area electron diffraction) is performed using an electron beam of 50 nm or more, On the other hand, for nc-OS, a halo-like diffraction pattern is observed. Nanobeam electron diffraction using an electron beam with a probe diameter close to the pellet size or smaller than the pellet size. When the electron diffraction pattern is applied to the nc-OS, a spot is observed. In some cases, a bright area that appears circular (ring-shaped) may be observed. Multiple spots may be observed within a patchy region.

[0413] In this way, the crystal orientation between the pellets (nanocrystals) is not regular, so nc- OS with RANC (Random Aligned nanocrystals) oxide semiconductors, or NANCs (Non-Aligned Nanocrystals) ) can also be referred to as an oxide semiconductor.

[0414] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the amorphous oxide semiconductor. There is no regularity in the crystal orientation between different pellets. Therefore, nc-OS is The defect level density is higher than that of AC-OS.

[0415] <Amorphous oxide semiconductor> Next, the amorphous oxide semiconductor will be described.

[0416] Amorphous oxide semiconductors are oxides in which the atomic arrangement in the film is irregular and there are no crystalline parts. An example is an oxide semiconductor that has an amorphous state, such as quartz.

[0417] In the case of an amorphous oxide semiconductor, no crystalline parts can be confirmed in a high-resolution TEM image.

[0418] When the structure of amorphous oxide semiconductors is analyzed using an XRD device, out-of-plane In the analysis by the ane method, no peaks indicating crystal planes were detected. When electron diffraction is performed on the amorphous oxide semiconductor, a halo pattern is observed. However, when nanobeam electron diffraction was performed, no spots were observed, and only a halo pattern was observed. It is measured.

[0419] There are various views on amorphous structures. For example, A structure that does not have a completely amorphous structure is called a completely amorphous structure. In addition, the distance between the nearest neighbors or the second nearest neighbors is called the A structure that has order but does not have long-range order is sometimes called an amorphous structure. According to the strictest definition, an oxide semiconductor that has even a slight degree of order in its atomic arrangement is called an amorphous semiconductor. In addition, oxides with at least long-range order cannot be called solid oxide semiconductors. The semiconductor cannot be called an amorphous oxide semiconductor. For example, the CAAC-OS and nc-OS are It cannot be called a compound semiconductor.

[0420] <Amorphous-like oxide semiconductor> Note that an oxide semiconductor may have a structure between an nc-OS and an amorphous oxide semiconductor. An oxide semiconductor having such a structure is particularly called an amorphous-like oxide semiconductor (a-li ke OS:amorphous-like Oxide Semiconductor ) is called

[0421] In a-like OS, voids are observed in high-resolution TEM images. In addition, there are cases where crystals can be clearly seen in high-resolution TEM images. and regions where no crystalline portion can be identified.

[0422] Because of the porosity, the a-like OS is an unstable structure. To demonstrate that the OS has a less stable structure compared with CAAC-OS and nc-OS. , shows the change in structure due to electron irradiation.

[0423] The samples to be irradiated with electrons were a-like OS (referred to as sample A), nc-OS ( Sample B) and CAAC-OS (sample C) are prepared. The sample in is also an In-Ga-Zn oxide.

[0424] First, high-resolution cross-sectional TEM images of each sample are obtained. It can be seen that each of the samples has a crystalline portion.

[0425] The determination of which part is regarded as one crystal part can be made as follows. For example, The unit cell of the InGaZnO4 crystal has three In-O layers and one Ga-Zn-O layer. It is known that the structure has a total of nine layers, including six layers, stacked in layers in the c-axis direction. The spacing between adjacent layers is approximately the same as the lattice spacing (also called the d value) of the (009) plane. The value is calculated to be 0.29 nm from crystal structure analysis. The area where the spacing is 0.28 nm or more and 0.30 nm or less is considered to be the crystal part of InGaZnO4. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal.

[0426] Figure 41 shows an example of the average size of the crystal parts (22 to 45 places) of each sample. However, the length of the lattice fringes mentioned above is the size of the crystal part. It can be seen that the crystal part of eOS becomes larger according to the cumulative dose of electron irradiation. As shown by (1) in Figure 41, the initial TEM observation showed a size of about 1.2 nm. The crystal part (also called the initial nucleus) was 4.2×10 in size, but the cumulative irradiation dose was 4.2×10 8 e - / nm 2 On the other hand, in the nc-OS, the size of the nanoparticles grows to about 2.6 nm. For CAAC-OS, the cumulative electron dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals within the range of As shown in (2) and (3) in 41, the nc-OS and The sizes of the crystal parts of the CAAC-OS and CAAC-OS are about 1.4 nm and 2.1 nm, respectively. I realize something.

[0427] Thus, in a-like OS, the growth of crystals can be observed by electron irradiation. On the other hand, the growth of the crystals in the nc-OS and CAAC-OS was hardly observed by electron irradiation. In other words, a-like OS is not seen in nc-OS and CAAC-OS. It can be seen that compared with S, it has a less stable structure.

[0428] In addition, because of the porosity, a-like OS is more resistant to vascular endothelial cell proliferation than nc-OS and CAAC-OS. Specifically, the density of the a-like OS is lower than that of a single crystal of the same composition. The density of nc-OS is 78.6% or more and less than 92.3% of that of CAAC. The density of the -OS is 92.3% or more and less than 100% of the density of a single crystal of the same composition. It is difficult to form an oxide semiconductor film having a density of less than 78% of that of the oxide semiconductor film.

[0429] For example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn=1:1:1, The density of single crystal InGaZnO4 with a hexagonal crystal structure is 6.357 g / cm 3 It becomes. For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, , the density of a-like OS is 5.0g / cm 3 More than 5.9g / cm 3 It is less than. For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of nc-OS and that of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0430] In some cases, single crystals with the same composition do not exist. In such cases, the composition may differ in any ratio. By combining single crystals, we estimate the density equivalent to a single crystal of the desired composition. The density corresponding to a single crystal of a desired composition can be obtained by combining single crystals of different compositions. The weighted average of the proportion of It is preferable to estimate by combining different types of single crystals.

[0431] As described above, oxide semiconductors have various structures, each of which has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, or a microcrystalline oxide semiconductor. The layer may be a laminated film having two or more of a semiconductor and a CAAC-OS.

[0432] <Film formation model> An example of a film formation model for CAAC-OS and nc-OS will be described below.

[0433] FIG. 42A shows how a CAAC-OS film is formed by a sputtering method. FIG.

[0434] The target 5130 is attached to a backing plate. A plurality of magnets are disposed at positions facing the target 5130. The magnetic field is generated by the magnet. The magnetic field of the magnet is used to increase the deposition speed. The sputtering method is called magnetron sputtering.

[0435] The substrate 5120 is disposed so as to face the target 5130, and the distance therebetween is d ( The target-substrate distance (TS distance) is preferably 0.01 m or more and 1 m or less. The thickness of the deposition chamber is set to 0.02m or more and 0.5m or less. Most of the deposition gas (e.g., oxygen) is The chamber is filled with a gas mixture containing 5% or more by volume of nitrogen, argon, or oxygen. The pressure is controlled to be 0.1 Pa or more and 100 Pa or less, preferably 0.1 Pa or more and 10 Pa or less. By applying a certain voltage to the target 5130, discharge begins and plasma is generated. It is noted that a high-density plasma region is formed near the target 5130 by the magnetic field. In the high density plasma region, the deposition gas is ionized, and ions 5101 are generated. The ions 5101 are, for example, positive oxygen ions (O + ) and argon cations (A r + ) etc.

[0436] Here, the target 5130 has a polycrystalline structure having a plurality of crystal grains, and any of the grains The crystal grains include cleavage planes. FIG. 43(A) shows an example of a cleavage plane included in a target 5130. The crystal structure of InGaZnO4 is shown in Fig. 43(A). This is the structure of an InGaZnO4 crystal. In the Ga-Zn-O layer, the oxygen atoms in each layer are arranged close to each other. And because the oxygen atom has a negative charge, the two adjacent G Repulsion occurs between the a-Zn-O layers. As a result, the InGaZnO4 crystals are close to each other. The cleavage plane is between the two Ga-Zn-O layers.

[0437] Ions 5101 generated in the high-density plasma region are applied to the target 5130 side by the electric field. The cleavage plane is accelerated and eventually collides with the target 5130. At this time, flat or pellet-like particles are generated from the cleavage plane. Pellet 5100a and pellet 5100b, which are pellet-shaped sputtered particles, are peeled off and struck. The pellets 5100a and 5100b are the same as the pellets 5101. The impact of a collision can cause distortion of the structure.

[0438] The pellet 5100a is a flat or pellet-shaped pellet having a triangular, for example equilateral, plane. The pellet 5100b has a hexagonal, for example, regular hexagonal, planar surface. The sputtered particles are in the form of a plate or pellet. Pellet 5100b and other flat or pellet-shaped sputter particles are collectively referred to as pellet 5 The planar shape of the pellet 5100 is not limited to a triangle or a hexagon. For example, a triangle (e.g., an equilateral triangle) may have a shape that is made up of multiple triangles. In some cases, the shape may be two squares (for example, a diamond).

[0439] The thickness of the pellet 5100 is determined according to the type of deposition gas. The reason for this will be described later. It is preferable that the thickness of the pellet 5100 is uniform. Thin pellets are preferred over thick cubes. The thickness of the 5100 is 0.4 nm or more and 1 nm or less, preferably 0.6 nm or more and 0.8 nm or less. For example, the pellet 5100 has a width of 1 nm or more and 3 nm or less, preferably The diameter of the pellet 5100 is 1.2 nm or more and 2.5 nm or less. For example, the target 51 having In-Ga-Zn oxide corresponds to the initial nucleus described in . When ions 5101 are bombarded onto the surface of the semiconductor substrate 30, the Ga-Zn-O layer, A pellet 5100 having three layers, an In-O layer and a Ga-Zn-O layer, is exfoliated. (C) shows the structure of the exfoliated pellet 5100 observed from a direction parallel to the c-axis. The plate 5100 is a nanotube having two Ga-Zn-O layers (panels) and an In-O layer (tool). It can also be called a no-size sandwich structure.

[0440] The pellet 5100 may become negatively or positively charged on its sides as it passes through the plasma. The pellet 5100 may, for example, be negatively charged due to the oxygen atoms located on its sides. The sides of the particles have the same polarity, causing repulsion between the charges, forming a flat or pellet-like shape. It is possible to maintain the shape of the In-Ga-Zn In the case of oxides, the oxygen atoms bonded to the indium atoms may be negatively charged. Or, an oxygen atom bonded to an indium atom, a gallium atom, or a zinc atom is negatively charged. In addition, when the pellet 5100 passes through the plasma, it may be possible that the pellet 5100 may be oxidized by the impurities in the plasma. When it grows by combining with other atoms such as tungsten, gallium, zinc, and oxygen, The difference in size between (2) and (1) in Figure 41 above corresponds to the growth in the plasma. Here, when the substrate 5120 is at room temperature, the pellets on the substrate 5120 Since the growth of 5100 is difficult to occur, it becomes nc-OS (see Figure 42(B)). Since the film can be formed in a short time, it is possible to form a film of nc-OS even on a large-area substrate (5120). In order to grow the pellet 5100 in plasma, the sputtering method is used. It is effective to increase the film formation power in the pellet 51. The structure of 00 can be stabilized.

[0441] As shown in FIG. 42(A) and FIG. 42(B), for example, a pellet 5100 is It flies like a kite through the air and flutters up to the top of the substrate 5120. Pellet 51 Since the 00 is electrically charged, it approaches an area where other pellets 5100 are already deposited. Here, on the upper surface of the substrate 5120, a repulsive force is generated in a direction parallel to the upper surface of the substrate 5120. In addition, the substrate 5120 and the target 51 Since a potential difference is applied between the substrate 5120 and the target 5130, Therefore, the pellet 5100 is disposed on the upper surface of the substrate 5120 in a magnetic The force (Lorentz force) is exerted by the action of the electric field and the electric current. This is explained by Fleming's This can be understood using the left-hand rule.

[0442] The pellet 5100 has a large mass compared to a single atom. In order to move the object, it is important to apply some kind of force from the outside. It is possible that the force is generated by the action of a magnetic field and a current. In order to provide sufficient force to move the top surface of the substrate 5120, The magnetic field parallel to the upper surface of the plate 5120 is 10 G or more, preferably 20 G or more, and more preferably It is preferable to provide an area where the resistance is 30 G or more, and more preferably 50 G or more. On the upper surface of the substrate 5120, a magnetic field parallel to the upper surface of the substrate 5120 is applied to the upper surface of the substrate 5120. At least 1.5 times, preferably at least 2 times, more preferably at least 3 times the magnetic field perpendicular to the surface More preferably, a region in which the difference is 5 times or more is provided.

[0443] At this time, the magnet and the substrate 5120 move or rotate relatively to each other. Thus, the orientation of the horizontal magnetic field on the top surface of the substrate 5120 continues to change. On the upper surface of 5120, the pellet 5100 is subjected to forces from various directions and is moved in various directions. Can be moved.

[0444] Also, when the substrate 5120 is heated as shown in FIG. The resistance due to friction between the substrate 5120 and the substrate 5120 is small. The pellet 5100 glides over the upper surface of the substrate 5120. The movement occurs with the flat surface facing the substrate 5120. When the pellet 5100 reaches the side of the pellet, the sides of the pellet 5100 are joined together. The oxygen atom on the side of 0 is removed. The removed oxygen atom causes the acid in CAAC-OS to be Since the electron vacancies may be filled, the CAAC-OS has a low defect level density. The temperature of the upper surface of 5120 is, for example, 100°C or more and less than 500°C, 150°C or more and less than 450°C. 170° C. or more and less than 400° C. Therefore, Even in this case, it is possible to form a CAAC-OS film.

[0445] In addition, the pellet 5100 is heated on the substrate 5120, whereby the atoms are rearranged, The structural distortion caused by the collision of the ions 5101 is relieved. The pellet 51 with the distortion relieved is shown in FIG. 00 is almost a single crystal. Pellet 5100 is almost a single crystal, Even if the pellets 5100 are heated after being bonded to each other, the pellets 5100 themselves do not expand or contract. Therefore, the gaps between the pellets 5100 widen, causing the grains to It does not form defects such as boundaries or crevasse formation.

[0446] In addition, the CAAC-OS is not made of a single crystal oxide semiconductor. The aggregates of Pellet 5100 (nano crystals) are arranged like piles of bricks or blocks. In addition, there are no grain boundaries between the pellets 5100. The CAAC-OS was deformed, such as shrinking, due to heating during film formation, heating after film formation, or bending. Even in cases where the material is not fully deformed, it is possible to relieve local stress or release strain. This structure is suitable for use in flexible semiconductor devices. The resulting arrangement resembles randomly stacked nanocrystals.

[0447] When the target 5130 is sputtered by ions 5101, not only the pellet 5100 but also However, zinc oxide may peel off. Zinc oxide is lighter than pellet 5100, so Therefore, it will reach the upper surface of the substrate 5120 first. A zinc oxide layer 5102 having a thickness of 0.5 nm to 2 nm is formed. A schematic cross-sectional view is shown in Figure 44.

[0448] As shown in FIG. 44(A), a pellet 5105a and a pellet Here, the pellets 5105a and 5105b are piled up. The pellets 5105c are arranged so that their sides are in contact with each other. After being deposited on pellet 5105b, the pellet 5105b slides on the pellet 5105b. In another aspect of 5a, a plurality of particles 5103 detached from the target along with zinc oxide. However, due to heating from the substrate 5120, it is crystallized to form a region 5105a1. The particles 5103 may include oxygen, zinc, indium, and gallium, among others.

[0449] As shown in FIG. 44(B), the region 5105a1 is integrated with the pellet 5105a. The pellet 5105c is formed by cutting the pellet 5105a2. It is arranged so as to be in contact with another side surface of 105b.

[0450] Next, as shown in FIG. 44(C), a pellet 5105d is further formed on the pellet 5105a2. and pellet 5105b, and then pellet 5105a2 and pellet 51 It slides on the pellet 5105b. It also slides towards the other side of the pellet 5105c. The pellet 5105 e slides on the zinc oxide layer 5102 .

[0451] As shown in FIG. 44(D), the pellet 5105d has a side surface similar to that of the pellet 510. The pellet 5105e is arranged so that its side surface is in contact with the pellet 5105a. Also, the other side of the pellet 5105d is arranged so as to contact the other side of the pellet 5105c. In the process, a plurality of particles 5103 peeled off from the target 5130 together with zinc oxide are deposited on the substrate. Heat from 5120 causes crystallization, forming region 5105d1.

[0452] As described above, the piled up pellets are arranged so that they come into contact with each other, and the pellets are formed on the side surfaces. As a result of this growth, a CAAC-OS is formed on the substrate 5120. The pellets of C-OS are larger than those of nc-OS. The difference in size between (1) and (2) corresponds to the growth that occurred after deposition.

[0453] In addition, the gaps between the pellets become extremely small, so that one large pellet is formed. One large pellet may have a single crystal structure. For example, The thickness is 10 nm or more and 200 nm or less, or 15 nm or more and 100 nm or less, as viewed from the top surface; or In some cases, the thickness may be between 20 nm and 50 nm. In some cases, the channel formation region of a nitride semiconductor fits into a single large pellet. In other words, the region having a single crystal structure can be used as a channel forming region. As the size of the gate increases, the region having a single crystal structure becomes the channel formation region of the transistor, In some cases, they can be used as source and drain regions.

[0454] In this way, the channel formation region of the transistor and the like are formed in a region having a single crystal structure. By doing so, it may be possible to improve the frequency characteristics of the transistor.

[0455] Based on the above model, it is considered that the pellet 5100 accumulates on the substrate 5120. It is possible to form a CAAC-OS film even if the surface on which the film is to be formed does not have a crystalline structure. This indicates that the growth mechanism is different from epitaxial growth. C-OS does not require laser crystallization and can form a uniform film even on large glass substrates. For example, if the structure of the upper surface (formation surface) of the substrate 5120 is an amorphous structure (e.g., non-crystalline structure), It is possible to form a CAAC-OS film even on a substrate made of amorphous silicon oxide.

[0456] In addition, the CAAC-OS can be formed even if the upper surface of the substrate 5120 has unevenness. For example, the pellets 5100 are arranged along the shape of the upper surface of the substrate 5120. If the surface is atomically flat, the pellet 5100 will face down on a flat surface that is parallel to the ab plane. If the pellet 5100 has a uniform thickness, it is flat and has a uniform thickness. A layer with high crystallinity is formed. Then, the layer is stacked n levels (n is a natural number). By this, CAAC-OS can be obtained.

[0457] On the other hand, even if the upper surface of the substrate 5120 has unevenness, the CAAC-OS can be easily formed by the pellet 510. The structure is made up of n layers (n is a natural number) of layers with 0s arranged along the unevenness. Since the surface of the CAAC-OS is uneven, gaps may easily occur between the pellets. However, even in this case, intermolecular forces act between the pellets 5100, and unevenness may occur. The pellets are arranged so that the gaps between them are as small as possible. It is possible to obtain a CAAC-OS having high crystallinity.

[0458] Since the CAAC-OS film is formed by such a model, the sputtered particles have a thin film thickness. It is preferable that the sputtered particles are in the form of pellets. However, the surface facing the substrate 5120 may not be uniform, and the thickness and crystal orientation may not be uniform. be.

[0459] The film formation model shown above shows that a highly crystalline film can be formed even on a substrate surface with an amorphous structure. It is possible to obtain a CAAC-OS having the formula:

[0460] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0461] (Embodiment 8) In this embodiment, electronic devices to which one embodiment of the present invention is applied will be described with reference to FIGS. do.

[0462] By using the display device of one embodiment of the present invention, a highly reliable flexible electronic device can be manufactured. It can be manufactured.

[0463] Examples of electronic devices include television sets, computer monitors, digital Cameras, digital video cameras, digital photo frames, mobile phones, portable games Examples of such devices include portable information terminals, audio playback devices, and large game consoles.

[0464] In addition, since the display device of one embodiment of the present invention is flexible, it can be attached to the inner or outer wall of a house or a building. , or may be incorporated along curved surfaces in the interior or exterior of a vehicle.

[0465] FIG. 24A shows an example of a mobile phone. A mobile phone 7100 has a housing 71 In addition to the display unit 7102 incorporated in the 01, the operation buttons 7103 and the external connection port 7104 , a speaker 7105, a microphone 7106, a camera 7107, etc. The telephone 7100 is manufactured by using the light-emitting device of one embodiment of the present invention for the display portion 7102. According to one aspect of the present invention, a highly reliable mobile phone having a curved display is provided. can be provided.

[0466] In the mobile phone 7100 shown in FIG. 24A, when the display portion 7102 is touched with a finger or the like, You can also make calls, enter text, and perform any other functions. The operation can be performed by touching the display portion 7102 with a finger or the like. The application is started by touching an icon 7108 displayed in part 7102. It is possible.

[0467] In addition, by operating the operation button 7103, the power can be turned on and off, and the display unit 7102 can be displayed. For example, you can change the type of image displayed from the main menu to the email composition screen. You can switch to the screen.

[0468] FIG. 24B shows an example of a wristwatch-type portable information terminal. 0 denotes a housing 7201, a display unit 7202, a band 7203, a buckle 7204, and operation buttons. 7205, input / output terminal 7206, etc.

[0469] The portable information terminal 7200 is capable of carrying out mobile phone calls, e-mails, viewing and creating documents, playing music, and It can run various applications such as internet communication and computer games. can.

[0470] The display unit 7202 has a curved display surface, and displays images along the curved display surface. The display portion 7202 is provided with a touch sensor, and can be used to input a touch signal to the screen with a finger or a stylus. For example, the icon 72 displayed on the display unit 7202 can be operated by touching it. You can launch the application by touching 07.

[0471] The operation button 7205 is used to set the time, turn the power on and off, and turn wireless communication on and off. Various functions such as operation, silent mode activation and deactivation, power saving mode activation and deactivation For example, the portable information terminal 7200 can have an operation The functions of the operation buttons 7205 can be freely set by the operating system.

[0472] In addition, the portable information terminal 7200 is capable of performing short-distance wireless communication according to a communication standard. For example, by communicating with a wireless headset, a hands-free You can also make calls.

[0473] The portable information terminal 7200 also includes an input / output terminal 7206 and is connected to other information terminals via a connector. Data can be exchanged directly through the input / output terminal 7206. The charging operation can be performed by wireless power supply without going through the input / output terminal 7206. You may go.

[0474] The display device of one embodiment of the present invention is applied to the display portion 7202 of a portable information terminal 7200. can be done.

[0475] FIG. 24C shows an example of a portable display device. The display device 7300 has a housing 7 301, display unit 7302, operation button 7303, drawer member 7304, control unit 7305 Equipped with.

[0476] The display device 7300 is a flexible display unit wound in a roll in a cylindrical housing 7301. Equipped with 7102.

[0477] In addition, the display device 7300 can receive a video signal through the control unit 7305. The control unit 7305 is provided with a battery. In addition, a terminal unit for connecting a connector to the control unit 7305 is provided, and video signals and power can be transmitted by wire. Alternatively, the power may be supplied directly from the outside.

[0478] In addition, the operation button 7303 can be used to turn the power on and off and to switch the image to be displayed. etc. can be carried out.

[0479] FIG. 24D shows a state in which the display unit 7302 is pulled out by a pull-out member 7304. In this state, an image can be displayed on the display unit 7302. The operation button 7303 arranged on the surface of the housing 7301 allows easy operation with one hand. In addition, as shown in FIG. 24C, the operation button 7303 can be placed in the center of the housing 7301. By placing it close to one side, it can be easily operated with one hand.

[0480] Note that the display unit 7302 is fixed so that the display surface of the display unit 7302 becomes flat when the display unit 7302 is pulled out. In order to secure the display portion 7302 in place, a frame for reinforcing the display portion 7302 may be provided on the sides of the display portion 7302.

[0481] In addition to this configuration, a speaker is provided on the housing, and the device can be operated by receiving an audio signal together with the video signal. The configuration may be such that audio is output.

[0482] The light-emitting device according to one embodiment of the present invention is incorporated in the display portion 7302. A lighter and more reliable light emitting device can be provided.

[0483] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0484] (Embodiment 9) Here, modifications of the transistor described in the above embodiment will be described with reference to FIGS. The transistor shown in FIG. 37 is formed on an insulating film 824 on a substrate 821. The oxide semiconductor layer 828 is connected to an insulating film 837. and a conductive film 840 which is in contact with the insulating film 7 and overlaps with the oxide semiconductor layer 828. The conductive film 837 functions as a gate insulating film. The conductive film 840 functions as a gate electrode layer. It has the function of

[0485] In addition, the insulating film 846 in contact with the oxide semiconductor layer 828 and the insulating film The transistor is provided with an insulating film 847. At the end of the insulating layer 824, the conductive films 856 and 857 in contact with the oxide semiconductor layer 828 are Note that the conductive films 856 and 857 are formed as a source electrode layer and a drain electrode layer. In addition, the insulating film 847 and the insulating film 856 and the insulating film 857 are in contact with each other. 62 is provided.

[0486] Note that the structure of the transistor described in this embodiment and the conductive film and the insulating film in contact with the structure The present invention relates to a structure of a transistor shown in the above embodiment, a conductive film and an insulating film in contact with the structure. A membrane can be used as appropriate.

[0487] In the transistor illustrated in FIG. 37A, the oxide semiconductor layer 828 overlaps with the conductive film 840. and a region 828a formed in the region including the impurity element and sandwiching the region 828a. The conductive films 856 and 857 have regions 828b and 828c. The region 828a functions as a channel region. The regions 828b and 828c are The resistivity is lower than that of the region 828a, and the region 828b can be called a low resistance region. 28b, 828c function as source and drain regions.

[0488] Alternatively, as in the transistor illustrated in FIG. 37B, The regions 828d and 828e in contact with the conductive films 856 and 857 are not doped with impurity elements. In this case, the regions 828d and 828e in contact with the conductive films 856 and 857 and the region 82 Between the region 828 and the region 828a, there are regions 828b and 828c having an impurity element. d and 828e have conductivity when a voltage is applied to the conductive films 856 and 857. It functions as a source region and a drain region.

[0489] Note that in the transistor shown in FIG. 37B, after the conductive films 856 and 857 are formed, An impurity element is added to the oxide semiconductor layer by using 840 and the conductive films 856 and 857 as masks. By doing so, it can be formed.

[0490] The conductive film 840 may have a tapered end. The angle θ1 between the surface where the conductive film 840 and the conductive film 840 are in contact with each other is 90°. or 10° to 85° or 15° to 85° or 30° to 8 It may be 5° or less, or between 45° and 85°, or between 60° and 85°. The angle θ1 is set to less than 90°, or to 10° or more and 85° or less, or to 15° or more and 85° or less, Or 30° to 85°, or 45° to 85°, or 60° to 85° By setting the insulating film 837 and the conductive film 840 at the lower side, the insulating film 846 can be covered with the insulating film 846. It is possible to increase

[0491] Next, modified examples of the regions 828b and 828c will be described. 7(F) is an enlarged view of the oxide semiconductor layer 828 and its vicinity shown in FIG. The channel length L is the distance between the regions containing a pair of impurity elements.

[0492] As shown in FIG. 37C, in the cross section in the channel length direction, the region 828a and the region The boundary between the regions 828b and 828c is aligned with the end of the conductive film 840 via the insulating film 837. That is, in terms of the top surface shape, the area 828a and the area 828b are the same as the area 828a. The boundary of 8 c coincides or approximately coincides with the edge of the conductive film 840 .

[0493] Alternatively, as shown in FIG. 37D, in the cross section in the channel length direction, a region 828a However, there is a region that does not overlap with an end of the conductive film 840. This region functions as an offset region. The length of the offset region in the channel length direction is L off In addition, If there are multiple offset areas, the length of each offset area is L off That is said. of f is included in the channel length L. Also, L off is less than 20% of the channel length L, or Less than 10%, or less than 5%, or less than 2%.

[0494] Alternatively, as shown in FIG. 37E, in the cross section in the channel length direction, a region 828b 828c has a region overlapping with the conductive film 840 with the insulating film 837 interposed therebetween. The overlap region in the channel length direction functions as a Length L ov L ov is less than 20% of the channel length L, or less than 10%, or Less than 5% or less than 2%.

[0495] Alternatively, as shown in FIG. 37F, in the cross section in the channel length direction, a region 828a and region 828b, and region 828c. The regions 828f and 828g have a higher concentration of impurity elements than the regions 828b and 828c. Here, the regions 828f and 828g overlap the insulating film 837. However, the insulating film 837 and the conductive film 840 may overlap with each other.

[0496] 37C to 37F, the transistor shown in FIG. As described above, the transistor shown in FIG. 37B may also have the same characteristics as those shown in FIG. ) structure can be applied as appropriate.

[0497] In the transistor shown in FIG. 38A, an end of an insulating film 837 is located outside an end of a conductive film 840. That is, the insulating film 837 protrudes from the conductive film 840. Since the insulating film 846 can be separated from the insulating film 828a, the nitrogen contained in the insulating film 846 can be Therefore, it is possible to suppress the intrusion of hydrogen, hydrogen, etc. into the region 828a that functions as a channel region. can.

[0498] In the transistor shown in FIG. 38B, the insulating film 837 and the conductive film 840 have a tapered shape. The angles of the tapered portions are different. The angle θ1 between the contact surface and the side surface of the conductive film 840, the oxide semiconductor layer 828, and the insulating film The angle θ2 between the surface where the insulating film 837 is in contact and the side of the insulating film 837 is different. The angle θ2 is , or less than 90°, or between 30° and 85°, or between 45° and 70°. For example, when the angle θ2 is smaller than the angle θ1, the coverage of the insulating film 846 is improved. When the angle θ2 is greater than the angle θ1, the insulating film 846 can be spaced away from the region 828a. Therefore, nitrogen, hydrogen, and the like contained in the insulating film 846 form a region that functions as a channel region. It is possible to suppress the intrusion of 828a.

[0499] Next, regarding the modified examples of the regions 828b and 828c, FIG. 38(C) to FIG. 38(F) are used. 38C to 38F show the oxide semiconductor A close-up view of the vicinity of layer 828 is shown.

[0500] As shown in FIG. 38C, in the cross section in the channel length direction, a region 828a and a region The boundary between the regions 828b and 828c is aligned with the end of the conductive film 840 via the insulating film 837. That is, in terms of the top surface shape, the area 828a and the area 828b are the same as each other. The boundary of 28c coincides or approximately coincides with the edge of the conductive film 840.

[0501] Alternatively, as shown in FIG. 38D, in the cross section in the channel length direction, a region 828a However, there is a region that does not overlap with the conductive film 840. This region functions as an offset region. That is, in the top view, the ends of the regions 828b and 828c are aligned with the ends of the insulating film 837. , and does not overlap with the end of the conductive film 840.

[0502] Alternatively, as shown in FIG. 38E, in the cross section in the channel length direction, a region 828b 828c has a region overlapping with the conductive film 840 with the insulating film 837 interposed therebetween. In other words, in the top view, the ends of the regions 828b and 828c are It overlaps with the conductive film 840 .

[0503] Alternatively, as shown in FIG. 38(F), in the cross section in the channel length direction, a region 828a and region 828b, and region 828c. The regions 828f and 828g have a higher concentration of impurity elements than the regions 828b and 828c. Here, the regions 828f and 828g overlap the insulating film 837. However, the insulating film 837 and the conductive film 840 may overlap with each other.

[0504] 38C to 38F, the transistor shown in FIG. As described above, the transistor shown in FIG. 38B may also have the same characteristics as those shown in FIG. ) can be appropriately applied.

[0505] In the transistor shown in FIG. 39A, a conductive film 840 has a stacked structure and is in contact with an insulating film 837. The conductive film 840a is in contact with the conductive film 840a, and the conductive film 840b is in contact with the conductive film 840a. The end of the conductive film 840a is located outside the end of the conductive film 840b. The portion a protrudes from the conductive film 840b.

[0506] Next, modified examples of the regions 828b and 828c will be described. 39(E) is an enlarged view of the vicinity of the oxide semiconductor layer 828 shown in FIG.

[0507] As shown in FIG. 39B, in the cross section in the channel length direction, the region 828a and the region The boundary between the regions 828b and 828c is an end of the conductive film 840a included in the conductive film 840 and an insulating The film 837 is disposed between the region 828a and the region 828b. The boundaries of the regions 828b and 828c coincide or nearly coincide with the ends of the conductive film 840. There are.

[0508] Alternatively, as shown in FIG. 39C, in the cross section in the channel length direction, a region 828a However, there is a region that does not overlap with the conductive film 840. This region functions as an offset region. In addition, in the top view, the ends of the regions 828b and 828c are aligned with the ends of the insulating film 837. 840 and may not overlap with the end of the conductive film 840.

[0509] Alternatively, as shown in FIG. 39D, in the cross section in the channel length direction, a region 828b , 828c has a region overlapping with the conductive film 840, here the conductive film 840a. This is called the overlap region. In other words, in the top view, the ends of the regions 828b and 828c are , overlapping with the conductive film 840a.

[0510] Alternatively, as shown in FIG. 39E, in the cross section in the channel length direction, a region 828a and region 828b, and region 828c. The impurity element is added to the regions 828f and 828g through the conductive film 840a. Therefore, the regions 828f and 828g have a higher concentration of impurity elements than the regions 828b and 828c. Here, the regions 828f and 828g are the same as the conductive film 840a and have a low resistivity. However, it may overlap with the conductive film 840a and the conductive film 840b.

[0511] Note that the end of the insulating film 837 may be located outside the end of the conductive film 840a.

[0512] Alternatively, the side surface of the insulating film 837 may be curved.

[0513] Alternatively, the insulating film 837 may have a tapered shape. The angle between the surface of the insulating film 837 and the side of the insulating film 837 is less than 90°, preferably 3 It may be greater than or equal to 0° and less than 90°.

[0514] As shown in FIG. 39, the oxide semiconductor layer 828 has a higher impurity concentration than the regions 828b and 828c. The drain region has low concentration of silicon and high resistivity regions 828f and 828g. Therefore, the threshold voltage of the transistor caused by the electric field in the drain region can be reduced. It is possible to reduce deterioration such as fluctuations in the value voltage.

[0515] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is. [Explanation of symbols]

[0516] 101 Structure 101a Rotating body 101b Parts 102 Starting point 103 Processing materials 103a Parts 103b Parts 104 parts 105 Stages 107 Guide 108 Arrow 109 Rotational Axis 111 Components 151 Structure 152 Structure 153 Processing materials 153a Parts 153b Parts 155 Stages 156 Stages 157 Support 158 Transport roller 159 Rotational Axis 161 Components 162 Starting point 190 Transistors 194 Transistors 300 display device 300a display device 300b display device 301 Flexible substrate 302 Pixel section 304 Circuit section 305 Circuit section 307 Flexible substrate 308 FPC terminal section 310 Signal Line 311 Wiring section 312 Sealing material 316 FPC 318a adhesive layer 318b Adhesive layer 320a Organic resin layer 320b Organic resin layer 321a Insulating film 321b Insulating film 334 Insulating Film 336 Colored layer 338 Light blocking layer 350 Transistors 352 Transistor 360 Connection electrode 364 Insulating Film 366 Insulating Film 368 Insulating Film 370 Planarizing Insulating Film 372 Conductive Film 374 Conductive Film 375 Liquid crystal elements 376 Liquid crystal layer 378 Spacer 380 Anisotropic Conductive Film 410 Element Layer 411 Element Layer 430 Insulating film 432 Sealing layer 434 Insulating Film 444 Conductive Film 446 EL layer 448 Conductive Film 462 Substrate 463 Substrate 468 Ultraviolet light 480 Light emitting element 501 Pixel circuit 502 Pixel section 504 Drive circuit section 504a Gate Driver 504b source driver 506 Protection circuit 507 Terminal section 550 Transistor 552 Transistor 554 Transistor 560 Capacitive element 562 Capacitive element 570 Liquid crystal element 572 Light emitting element 600 Excimer Laser Device 610a Laser light 610b Laser light 610c Laser light 610d Linear Beam 630 Optical system 650 Mirror 670 Lens 700 Workpiece 710 Processing area 720 Substrate 801 Resist mask 802 Resist mask 803 Resist mask 810 Impurities 821 Substrate 824 Insulating film 828 Oxide semiconductor layer 828a area 828b area 828c area 828d area 828e area 828f area 828g area 837 Insulating film 840 Conductive Film 840a Conductive film 840b Conductive film 846 Insulating film 847 Insulating film 856 Conductive film 857 Conductive film 862 Insulating film 900 Substrate 910 Organic resin layer 915 Insulating film 920 Gate electrode layer 921 Conductive Film 930 Gate insulating film 931 Insulating film 932 Insulating film 933 Insulating film 935 Insulation Layer 940 Oxide semiconductor layer 940a Oxide semiconductor film 940b Oxide semiconductor film 940c Oxide semiconductor film 941a Oxide semiconductor layer 941b Oxide semiconductor layer 942a Oxide semiconductor layer 942b Oxide semiconductor layer 942c Oxide semiconductor layer 943a Oxide semiconductor layer 950 Source electrode layer 951 Source Region 960 Drain electrode layer 961 Drain Region 970 Insulating film 975 Insulating film 980 Insulating film 990 Insulating film 7100 Mobile Phone 7101 Case 7102 Display section 7103 Operation button 7104 External connection port 7105 Speaker 7106 Microphone 7107 Camera 7108 Icon 7200 Portable Information Terminal 7201 Case 7202 Display section 7203 Band 7204 Buckle 7205 Operation button 7206 Input / output terminal 7207 Icon 7300 display device 7301 Case 7302 Display section 7303 Operation button 7304 Materials 7305 Control Unit 5100 pellets 5100a Pellet 5100b Pellets 5101 AEON 5102 Zinc oxide layer 5103 particles 5105a Pellet 5105a1 area 5105a2 Pellet 5105b Pellet 5105c Pellet 5105d Pellet 5105d1 area 5105e Pellet 5120 PCB 5130 Target 5161 area 8000 Display Module 8001 Top cover 8002 Lower cover 8003 FPC 8004 Touch Panel 8005 FPC 8006 Display Panel 8007 Backlight 8008 light source 8009 Frame 8010 Printed Circuit Board 8011 Battery

Claims

[Claim 1] A method for manufacturing a display device including a first element layer and a second element layer, one of the first element layer and the second element layer including a pixel portion including a first transistor having an oxide semiconductor layer and a display element, and a circuit portion including a second transistor having an oxide semiconductor layer, and the other of the first element layer and the second element layer including a coloring layer and a light-shielding layer, forming a first organic resin layer on a first substrate; forming a first insulating film on the first organic resin layer; forming a first element layer on the first insulating film; forming a second organic resin layer on a second substrate; forming a second insulating film on the second organic resin layer; forming a second element layer on the second insulating film; bonding the first substrate and the second substrate together so that the first element layer and the second element layer are sealed; performing a first separation step of reducing adhesion between the first organic resin layer and the first substrate to separate the first substrate; The first organic resin layer and a first flexible substrate are bonded to each other via a first adhesive layer; performing a second separation step of reducing adhesion between the second organic resin layer and the second substrate to separate the second substrate; The second organic resin layer and the second flexible substrate are bonded to each other through a second adhesive layer.

Images