Nitride semiconductor module

Abstract

To improve thermal dispersion of a nitride semiconductor module.SOLUTION: A nitride semiconductor module 100 includes a chip 101 including a transistor 51. The chip 101 includes: a semiconductor substrate 12; an electron transit layer formed on the semiconductor substrate 12 and composed of GaN; and an electron supply layer formed on the electron transit layer and composed of GaN. The transistor is composed including a gate electrode, a source electrode, and a drain electrode formed on the electron supply layer. The semiconductor substrate 12 is a GaN substrate having a thickness of 100 μm or less.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a nitride semiconductor module. [Background technology]

[0002] Currently, high electron mobility transistors (HEMTs) using group III nitride semiconductors (hereinafter sometimes simply referred to as "nitride semiconductors") such as gallium nitride (GaN) are being commercialized. HEMTs use two-dimensional electron gas (2DEG) formed near the interface of semiconductor heterojunctions as a conductive path (channel). Power devices using HEMTs are recognized as devices that enable lower on-resistance and higher speed / frequency operation compared to typical silicon (Si) power devices.

[0003] For example, the nitride semiconductor device described in Patent Document 1 includes a silicon substrate, an electron transit layer formed of a gallium nitride (GaN) layer, and an electron supply layer formed of an aluminum gallium nitride (AlGaN) layer. A 2DEG is formed in the electron transit layer near the heterojunction interface between the electron transit layer and the electron supply layer. In addition, in the nitride semiconductor device of Patent Document 1, a gate layer (e.g., a p-type GaN layer) containing acceptor-type impurities is provided on the electron supply layer and directly below the gate electrode. In this configuration, in the region directly below the gate layer, the gate layer raises the band energy of the conduction band near the heterojunction interface between the electron transit layer and the electron supply layer, thereby eliminating the channel directly below the gate layer and realizing a normally-off state. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2017-73506 A Summary of the Invention [Problem to be solved by the invention]

[0005] In the case of a nitride semiconductor device including an element configured using a nitride semiconductor layer formed on a substrate, heat generated from the element is dissipated to the outside mainly via the substrate. Therefore, in order to suppress a temperature rise in the nitride semiconductor device, it is important to improve the heat dissipation from the substrate. [Means for solving the problem]

[0006] A nitride semiconductor module according to one embodiment of the present disclosure comprises a chip including a transistor, the chip comprising: a semiconductor substrate having a substrate upper surface and a substrate lower surface facing opposite to the substrate upper surface; an electron transit layer formed on the substrate upper surface of the semiconductor substrate and made of GaN; and an electron supply layer formed on the electron transit layer and made of GaN having a larger band gap than the electron transit layer, the transistor including a gate electrode, a source electrode, and a drain electrode formed on the electron supply layer, and the semiconductor substrate is a GaN substrate having a thickness of 100 μm or less. Effect of the Invention

[0007] According to the nitride semiconductor module of the present disclosure, heat dissipation properties can be improved. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a schematic plan view of an illustrative nitride semiconductor module according to the first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view taken along line 2-2 of FIG. [Diagram 3] FIG. 3 is an exemplary schematic plan view of a transistor. [Figure 4] FIG. 4 is a cross-sectional view taken along line 4-4 in FIG. [Diagram 5] FIG. 5 is a schematic plan view of an illustrative nitride semiconductor module according to the second embodiment. [Figure 6] FIG. 6 is a schematic circuit diagram of the nitride semiconductor module according to the third embodiment. [Figure 7]FIG. 7 is a schematic plan view of an illustrative nitride semiconductor module according to the third embodiment. [Figure 8] FIG. 8 is a schematic cross-sectional view of a first transistor and a second transistor included in the nitride semiconductor module according to the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, embodiments of a semiconductor module according to the present disclosure will be described with reference to the accompanying drawings. For simplicity and clarity of description, the components shown in the drawings are not necessarily drawn to scale. Also, hatching lines may be omitted in cross-sectional views to facilitate understanding. The accompanying drawings are merely illustrative of embodiments of the present disclosure and should not be considered as limiting the present disclosure.

[0010] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0011] First Embodiment [Schematic structure of semiconductor module] Fig. 1 is a schematic plan view of an illustrative nitride semiconductor module (hereinafter, referred to as a semiconductor module) 100 according to a first embodiment. Fig. 2 is a cross-sectional view taken along line 2-2 in Fig. 1.

[0012] 1 and 2, the semiconductor module 100 may be, for example, a surface-mount package. The semiconductor module 100 includes a module upper surface 100s and a module lower surface 100r facing the opposite side to the module upper surface 100s.

[0013] The semiconductor module 100 includes a chip 101 including a transistor 51 described below, a first conductive terminal 102A, a second conductive terminal 102B, and a third conductive terminal 102C electrically connected to the chip 101, a heat dissipation member 103, and a sealing member 104 that seals the chip 101. For ease of understanding, only the outline of the sealing member 104 is shown in Figures 1 and 2.

[0014] The chip 101 includes a chip top surface 101s and a chip bottom surface 101r facing the opposite side to the chip top surface 101s. The chip top surface 101s faces the same side as the module top surface 100s. The chip bottom surface 101r faces the same side as the module bottom surface 100r. The shape of the chip 101 in plan view, in other words, the shapes of the chip top surface 101s and the chip bottom surface 101r in plan view, are, for example, rectangular. The chip 101 includes a semiconductor substrate 12, a nitride semiconductor layer 50, a transistor 51, an insulator layer 60, an electrode pad 70, and a bottom electrode 80. In FIG. 2, the electrode pad 70 and the bottom electrode 80 are omitted from illustration.

[0015] The semiconductor substrate 12 is a substrate formed of GaN. The semiconductor substrate 12 is, for example, a n-type substrate in which N vacancies function as donors. - The substrate is made of GaN. The carrier density is, for example, 1×10 16 cm -3 It can be more than that.

[0016] The semiconductor substrate 12 includes a substrate upper surface 12s and a substrate lower surface 12r facing the opposite side to the substrate upper surface 12s. The substrate upper surface 12s faces the same side as the chip upper surface 101s. The substrate lower surface 12r faces the same side as the chip lower surface 101r.

[0017] 1 and 2, the Z-axis direction of the mutually orthogonal X, Y and Z axes is the thickness direction of the semiconductor substrate 12. Note that the term "planar view" used in this specification means that the semiconductor module 100 is viewed from above along the Z-axis direction, unless otherwise expressly stated. The thickness of the semiconductor substrate 12 will be described in detail later.

[0018] The nitride semiconductor layer 50 is formed on the substrate upper surface 12s of the semiconductor substrate 12. The transistor 51 is configured using the nitride semiconductor layer 50. The nitride semiconductor layer 50 and the transistor 51 will be described in detail later.

[0019] As shown in FIG. 4, the lower electrode 80 is formed on the substrate lower surface 12r of the semiconductor substrate 12. The lower electrode 80 is electrically connected to the source electrode 28 described later. The lower electrode 80 can be made of any conductive material including at least one of titanium (Ti), nickel (Ni), nickel vanadium alloy (NiV), silver (Ag), and gold (Au). The lower electrode 80 may be made of one or more metal layers. For example, one example of the lower electrode 80 is an electrode in which three layers of a Ti layer, a Ni layer, and an Au layer are laminated in this order from the substrate lower surface 12r side of the semiconductor substrate 12. The lower electrode 80 may also be an electrode in which four layers of a Ti layer, a Ni layer, an Au layer, and an Ag layer are laminated in this order from the substrate lower surface 12r side of the semiconductor substrate 12, or an electrode in which three layers of a Ti layer, a NiV layer, and an Ag layer are laminated in this order. The lower electrode 80 constitutes the chip lower surface 101r of the chip 101.

[0020] Also, the lower electrode 80 may be omitted. In this case, the semiconductor substrate 12 is electrically connected to the source electrode 28 described later. For example, a via that contacts the substrate upper surface 12s of the semiconductor substrate 12 and the source electrode 28 is formed in the nitride semiconductor layer 50 disposed between the semiconductor substrate 12 and the source electrode 28, thereby electrically connecting the semiconductor substrate 12 and the source electrode 28. When the lower electrode 80 is omitted, the chip lower surface 101r of the chip 101 may be constituted by, for example, the substrate lower surface 12r of the semiconductor substrate 12.

[0021] The insulator layer 60 is formed on the nitride semiconductor layer 50. The insulator layer 60 may be made of a material including any one of silicon nitride (SiN), silicon dioxide (SiO2), silicon oxynitride (SiON), alumina (Al2O3), AlN, and aluminum oxynitride (AlON), for example. In one example, the insulator layer 60 is made of a material including SiN.

[0022] The electrode pads 70 are formed on the upper surface of the insulator layer 60. The electrode pads 70 include one or more source pads 71, one or more drain pads 72, and one or more gate pads 73.

[0023] In FIG. 2, the electrode pads 70 are omitted. The source pad 71 is electrically connected to a source electrode 28, which will be described later. The drain pad 72 is electrically connected to a drain electrode 30, which will be described later. The gate pad 73 is electrically connected to a gate electrode 24, which will be described later. Each of the electrode pads can be made of any conductive material including at least one of Ti, titanium nitride (TiN), aluminum (Al), copper (Cu), an AlCu alloy, Ni, and Au. An example of the electrode pad 70 includes a metal layer and a plating layer covering the metal layer. The metal layer has a structure in which, for example, four layers, a Ti layer, a TiN layer, an AlCu layer, and a TiN layer, are laminated in this order from the upper surface side of the insulating layer 60. The plating layer has a structure in which, for example, a Cu layer, a Ni layer, and an Au layer are laminated in this order from the metal layer side.

[0024] 2, the chip 101 includes a plurality of source pads 71, a plurality of drain pads 72, and a plurality of gate pads 73. Each of the plurality of source pads 71 ​​and the plurality of drain pads 72 is formed in a rectangular shape extending in the Y-axis direction, and is arranged alternately in the X-axis direction at intervals. The gate pads 73 are arranged in the Y-axis direction at intervals from the pads (both drain pads 72 in FIG. 1) that are arranged on both sides in the X-axis direction among the plurality of source pads 71 ​​and the plurality of drain pads 72.

[0025] The first conductive terminal 102A, the second conductive terminal 102B, and the third conductive terminal 102C are electrically connected to the electrode pad 70 of the chip 101. More specifically, the first conductive terminal 102A is bonded to the upper surface of the source pad 71 via a conductive bonding material (not shown). The second conductive terminal 102B is bonded to the upper surface of the drain pad 72 via a conductive bonding material (not shown). The third conductive terminal 102C is bonded to the upper surface of the gate pad 73 via a wire 102D.

[0026] The first conductive terminal 102A, the second conductive terminal 102B, and the third conductive terminal 102C are formed of, for example, Cu or an alloy containing Cu. The conductive bonding material can be solder or conductive paste. The solder may be, for example, a lead (Pb)-free solder such as a tin (Sn)-silver (Ag)-copper (Cu) system, or a lead-containing solder such as a Sn-Pb-Ag system. An example of the conductive paste is Ag paste. The wire 102D is a bonding wire formed by a wire bonding device, and is formed of a conductor such as gold (Au), Al, or Cu.

[0027] Each of the first conductive terminal 102A and the second conductive terminal 102B has, for example, a bridge shape. Each of the first conductive terminal 102A, the second conductive terminal 102B, and the third conductive terminal 102C has an external connection surface (respective lower surface) that is partially exposed on the module lower surface 100r from the sealing member 104. Each of the external connection surfaces of the first conductive terminal 102A, the second conductive terminal 102B, and the third conductive terminal 102C is electrically connected to a mounting board (not shown) when the semiconductor module 100 is mounted on the mounting board.

[0028] The heat dissipation member 103 is attached to the chip underside 101r of the chip 101. The method of attaching the heat dissipation member 103 to the chip underside 101r is not particularly limited. In one example, the heat dissipation member 103 is attached using a bonding material (not shown). Examples of the bonding material include metal materials such as solder and Ag paste, and resin materials such as thermosetting resin and photocurable resin. In another example, the heat dissipation member 103 is bonded to the chip underside 101r of the chip 101 by diffusion bonding or solid-state diffusion bonding.

[0029] The heat dissipation member 103 includes an exposed surface that is partially exposed from the sealing member 104 to the module lower surface 100r. The shape of the heat dissipation member 103 is not particularly limited as long as it has an exposed surface. The heat dissipation member 103 is, for example, a plate-shaped heat dissipation plate. The heat dissipation member 103 is formed of a material with good thermal conductivity. The heat dissipation member 103 is made of, for example, ceramics and metal. The ceramics contains, for example, alumina (Al2O3) as a main component.

[0030] The sealing member 104 may define the package outer shape of the semiconductor module 100. The sealing member 104 seals the chip 101 as well as a part of the first conductive terminal 102A, a part of the second conductive terminal 102B, a part of the third conductive terminal 102C, and a part of the heat dissipation member 103. The sealing member 104 may be formed of an insulating resin material such as an epoxy resin, an acrylic resin, or a phenol resin. In one example, the sealing member 104 may be formed by molding an insulating resin material. The sealing member 104 is formed of a material having a lower thermal conductivity than the material (GaN) forming the semiconductor substrate 12. The chip upper surface 101s and the chip lower surface 101r of the chip 101 are formed by the sealing member 104.

[0031] [Details of nitride semiconductor layer and transistor] (Schematic structure of a transistor) In a plan view, the chip 101 includes an active region in which the transistor 51 is formed, and a non-active region in which the transistor 51 is not formed.

[0032] FIG. 3 is a schematic plan view of the transistor 51 formed in the active region. In FIG. 3, the insulating layer 60 and the electrode pad 70 are omitted. FIG. 4 is a schematic cross-sectional view of the transistor 51, taken along line 4-4 in FIG. 3. In one example, the transistor 51 may be a HEMT using GaN. In the following, the cross-sectional structure of the transistor 51 will be described with reference to FIG. 4, and then the planar structure of the transistor 51 will be described with reference to FIG. 3.

[0033] 4, the transistor 51 includes a semiconductor substrate 12 and a nitride semiconductor layer 50 formed on the semiconductor substrate 12. The nitride semiconductor layer 50 is epitaxially grown on the substrate upper surface 12s of the semiconductor substrate 12. The nitride semiconductor layer 50 includes an electron transit layer 16 formed on the semiconductor substrate 12, and an electron supply layer 18 formed on the electron transit layer 16.

[0034] The electron transit layer 16 is a GaN layer made of GaN. One example of the electron transit layer 16 is an undoped GaN layer. The thickness of the electron transit layer 16 will be described in detail later. In order to suppress leakage current in the electron transit layer 16, an impurity may be introduced into a part of the electron transit layer 16 to make the electron transit layer 16 semi-insulating except for the surface region. In this case, the impurity may be, for example, C, and the peak concentration of the impurity in the electron transit layer 16 may be, for example, 1×10 19 cm -3 That's all.

[0035] The electron supply layer 18 is made of a nitride semiconductor having a larger band gap than the electron transit layer 16. The electron supply layer 18 is, for example, an AlGaN layer. In this case, the band gap increases as the Al composition increases, so the electron supply layer 18, which is an AlGaN layer, has a larger band gap than the electron transit layer 16, which is a GaN layer. In one example, the electron supply layer 18 is made of Al x Ga 1-xIt is composed of N, where 0.1 < x < 0.4, and more preferably, 0.2 < x < 0.3. The thickness of the electron supply layer 18 is, for example, 5 nm or more and 20 nm or less.

[0036] The electron transport layer 16 and the electron supply layer 18 are composed of nitride semiconductors having different lattice constants from each other. Therefore, the GaN layer constituting the electron transport layer 16 and the GaN layer (for example, AlGaN layer) constituting the electron supply layer 18 form a hetero-junction of a lattice mismatch system. Due to the spontaneous polarization of the electron transport layer 16 and the electron supply layer 18 and the piezo-polarization caused by the stress received by the electron supply layer 18 near the hetero-junction interface, the energy level of the conduction band of the electron transport layer 16 near the hetero-junction interface becomes lower than the Fermi level. As a result, a two-dimensional electron gas (2DEG) 20 spreads in the electron transport layer 16 at a position close to the hetero-junction interface between the electron transport layer 16 and the electron supply layer 18 (for example, within a range of about several nm from the interface).

[0037] The nitride semiconductor layer 50 may have other layers other than the electron transport layer 16 and the electron supply layer 18. For example, the nitride semiconductor layer 50 may have an intermediate layer disposed between the semiconductor substrate 12 and the electron transport layer 16. An example of the intermediate layer is a buffer layer provided to facilitate the epitaxial growth of the electron transport layer 16, and it can be composed of any material that can facilitate the epitaxial growth of the electron transport layer 16. Another example of the intermediate layer is a high-resistance layer provided to suppress the leakage current in the vertical direction, that is, the leakage current between the semiconductor substrate 12 and the drain electrode 30 described later, and it can be composed of any material capable of epitaxial growth of the electron transport layer 16. The high-resistance layer is, for example, a layer having a higher resistance than the electron transport layer 16.

[0038] The transistor 51 includes a gate layer 22 formed on the electron supply layer 18, a gate electrode 24 formed on the gate layer 22, and a passivation layer 26. The passivation layer 26 is formed on the electron supply layer 18, the gate layer 22, and the gate electrode 24, and includes a first opening 26A and a second opening 26B. The transistor 51 also includes a source electrode 28 in contact with the upper surface 18A of the electron supply layer 18 through the first opening 26A, and a drain electrode 30 in contact with the upper surface 18A of the electron supply layer 18 through the second opening 26B.

[0039] The gate layer 22 is located between the first opening 26A and the second opening 26B of the passivation layer 26, and is spaced apart from each of the first opening 26A and the second opening 26B. The gate layer 22 is located closer to the first opening 26A than to the second opening 26B. The thickness of the gate layer 22 is, for example, not less than 50 nm and not more than 200 nm.

[0040] The gate layer 22 has a smaller band gap than the electron supply layer 18 and is composed of a nitride semiconductor containing acceptor-type impurities. The gate layer 22 may be composed of any material having a smaller band gap than the electron supply layer 18, which is, for example, an AlGaN layer. In one example, the gate layer 22 is a GaN layer doped with acceptor-type impurities (a p-type GaN layer).

[0041] The acceptor-type impurities may include at least one of magnesium (Mg), zinc (Zn), and C. An example of an acceptor-type impurity is Mg. The maximum concentration of the acceptor-type impurities in the gate layer 22 is, for example, 1×10 18 cm -3 or more, or 1×10 19 cm -3 The maximum concentration of the acceptor-type impurities in the gate layer 22 is, for example, 1×10 20 cm -3 The following is the result.

[0042] As described above, the gate layer 22 contains acceptor-type impurities, which raises the energy levels of the electron transit layer 16 and the electron supply layer 18. Therefore, in the region immediately below the gate layer 22, the energy level of the conduction band of the electron transit layer 16 near the heterojunction interface between the electron transit layer 16 and the electron supply layer 18 is approximately the same as or higher than the Fermi level. Therefore, at zero bias when no voltage is applied to the gate electrode 24, the 2DEG 20 is not formed in the electron transit layer 16 in the region immediately below the gate layer 22. On the other hand, the 2DEG 20 is formed in the electron transit layer 16 in regions other than the region immediately below the gate layer 22.

[0043] In this way, the presence of the gate layer 22 doped with acceptor-type impurities causes the 2DEG 20 to disappear in the region directly below the gate layer 22. As a result, the transistor operates normally off. When an appropriate on-voltage is applied to the gate electrode 24, a channel is formed by the 2DEG 20 in the electron transit layer 16 in the region directly below the gate electrode 24, providing electrical continuity between the source and drain.

[0044] The gate electrode 24 is composed of one or more metal layers. In one example, the gate electrode 24 is a titanium nitride (TiN) layer. Alternatively, the gate electrode 24 may be composed of a first metal layer formed of a material containing Ti and a second metal layer formed of a material containing TiN and stacked on the first metal layer. The gate electrode 24 can form a Schottky junction with the gate layer 22. The gate electrode 24 can be formed in an area smaller than the gate layer 22 in a plan view. The thickness of the gate electrode 24 is, for example, 50 nm or more and 200 nm or less.

[0045] The passivation layer 26 is formed on the electron supply layer 18. It can be said that the passivation layer 26 covers the upper surface 18A of the electron supply layer 18. The passivation layer 26 can be made of a material containing any one of silicon nitride (SiN), silicon dioxide (SiO2), silicon oxynitride (SiON), alumina (Al2O3), AlN, and aluminum oxynitride (AlON). In one example, the passivation layer 26 is formed of a material containing SiN. The portion of the passivation layer 26 covering the gate layer 22 and the gate electrode 24 is formed along the upper surfaces of the gate layer 22 and the gate electrode 24, and therefore has a non-flat upper surface. The passivation layer 26 has a thickness of, for example, 200 nm or less. Here, the thickness of the passivation layer 26 may be, for example, the thickness of the portion in contact with the electron supply layer 18, or may be the thickness of the portion in contact with the upper surface of the gate electrode 24.

[0046] The source electrode 28 and the drain electrode 30 are disposed on the upper surface 18A of the electron supply layer 18 so as to sandwich the gate layer 22. On the upper surface 18A of the electron supply layer 18, the gate layer 22, the source electrode 28, and the drain electrode 30 are aligned in the X-axis direction.

[0047] The source electrode 28 and the drain electrode 30 may be composed of one or more metal layers. For example, the source electrode 28 and the drain electrode 30 may be composed of a combination of two or more metal layers selected from a group including a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, and an AlCu layer. At least a part of the source electrode 28 is filled in the first opening 26A and is in ohmic contact with the 2DEG 20 directly below the electron supply layer 18 through the first opening 26A. Similarly, at least a part of the drain electrode 30 is filled in the second opening 26B and is in ohmic contact with the 2DEG 20 directly below the electron supply layer 18 through the second opening 26B.

[0048] As described above, the source electrode 28 is electrically connected to the source pad 71 via a wiring (not shown) formed in the insulator layer 60. The drain electrode 30 is electrically connected to the drain pad 72 via a wiring (not shown) formed in the insulator layer 60. The gate electrode 24 is electrically connected to the gate pad 73 via a wiring (not shown) formed in the insulator layer 60. The insulator layer 60 is formed on the passivation layer 26, the source electrode 28, and the drain electrode 30. It can be said that the insulator layer 60 covers the passivation layer 26, the source electrode 28, and the drain electrode 30.

[0049] (Planar structure of transistor) Next, the planar structure of the transistor 51 will be described with reference to Fig. 3. In Fig. 3, the passivation layer 26 and the source electrode 28 are omitted, and the first opening 26A and the second opening 26B of the passivation layer 26 are depicted by dashed lines.

[0050] The transistor 51 has a first active area that contributes to the transistor operation and a second active area (not shown) that does not contribute to the transistor operation within the active area. In one example, the first active area and the second active area are arranged alternately in the Y-axis direction.

[0051] In the first active region of the transistor 51, the source electrode 28 (see FIG. 4), the gate electrode 24, and the drain electrode 30 are arranged adjacent to each other in the X-axis direction on the electron supply layer 18 (see FIG. 4). A combination of the source electrode 28, the gate electrode 24, and the drain electrode 30 adjacent to each other in the X-axis direction constitutes one HEMT cell 51HC. In the example of FIG. 3, two HEMT cells 51HC are arranged in the X-direction in the active region. Note that, in practice, more HEMT cells 51HC may be arranged in each active region. The number of HEMT cells 51HC is not particularly limited, and may be one or more. The chip 101 may have a plurality of transistors 51 (HEMT cells 51HC) formed on the same substrate.

[0052] [Details of thickness of each part of semiconductor module] The thickness of each portion of the semiconductor module 100 will be described with reference to FIG. 2 and FIG.

[0053] 2, the thickness T1 of the semiconductor module 100 is, for example, 900 μm or more. The thickness T1 of the semiconductor module 100 is, for example, 1500 μm or less. The thickness T2 of the chip 101 is, for example, 80 μm or more, and the thickness T2 of the chip 101 is, for example, 140 μm or less.

[0054] The distance from the upper surface of the nitride semiconductor layer 50 (upper surface 18A of the electron supply layer 18) to the module upper surface 100s is defined as thickness T3. Thickness T3 is, for example, 400 μm or more. Thickness T3 is, for example, 550 μm or less.

[0055] 4, the thickness T4 of the semiconductor substrate 12 of the chip 101 is 100 μm or less. The thickness T4 of the semiconductor substrate 12 may be 80 μm or less. Moreover, the thickness T4 of the semiconductor substrate 12 is, for example, 60 μm or more.

[0056] An example of the thickness T4 of the semiconductor substrate 12 is thinner than the thickness T3 which is the distance from the upper surface of the nitride semiconductor layer 50 (the upper surface 18A of the electron supply layer 18) to the module upper surface 100s. The ratio (T4 / T3) of the thickness T4 of the semiconductor substrate 12 to the thickness T3 is, for example, 0.25 or less. In addition, the difference (T3-T4) between the thickness T3 and the thickness T4 of the semiconductor substrate 12 is, for example, 480 μm or more.

[0057] As shown in FIG. 4, the thickness T5 of the electron travel layer 16 constituting the nitride semiconductor layer 50 is, for example, 1.2 μm or more. The thickness T5 of the electron travel layer 16 is, for example, 6 μm or less. In one example of the nitride semiconductor layer 50, the electron travel layer 16 is formed on a semiconductor substrate 12 made of n-type GaN, and no intermediate layer such as a buffer layer is interposed between the semiconductor substrate 12 and the electron travel layer 16. In this case, the electron travel layer 16 is formed thick, for example, the thickness T5 is set to 1200 μm or more, thereby ensuring insulation between the 2DEG 20 generated in the electron travel layer 16 and the semiconductor substrate 12. This makes it possible to suppress leakage current flowing through the electron travel layer 16 to the semiconductor substrate 12.

[0058] The total thickness of the semiconductor substrate 12 and the nitride semiconductor layer 50, that is, the distance D1 from the lower surface 12r of the semiconductor substrate 12 to the upper surface 18A of the electron supply layer 18, is, for example, 106 μm or less. Moreover, the distance D1 is, for example, 61 μm or more.

[0059] 2, the thickness T6 of the heat dissipation member 103 is, for example, 150 μm or less. The thickness of the heat dissipation member 103 is, for example, 100 μm or more. By reducing the thickness T6 of the heat dissipation member 103, for example, to 150 μm or less, the heat dissipation performance of the heat dissipation member 103 is improved. The thickness T6 of the heat dissipation member 103 in one example is thicker than the thickness T4 of the semiconductor substrate 12. Moreover, the thickness T6 of the heat dissipation member 103 in another example is thinner than the thickness T4 of the semiconductor substrate 12.

[0060] In the thickness direction of the semiconductor module 100, the chip underside 101r of the chip 101 is disposed at a position closer to the module underside 100r than the module upper surface 100s of the semiconductor module 100. In other words, the distance D2 between the chip underside 101r and the module upper surface 100r is shorter than the distance D3 between the chip underside 101r and the module upper surface 100s.

[0061] [Effect] Next, the operation of the semiconductor module 100 according to the embodiment will be described. The semiconductor module 100 includes a chip 101 including a transistor 51. The chip 101 includes a semiconductor substrate 12 having a substrate upper surface 12s and a substrate lower surface 12r, and an electron transit layer 16 and an electron supply layer 18 formed on the substrate upper surface 12s and made of GaN. The transistor 51 includes the electron transit layer 16, the electron supply layer 18, and a gate electrode 24, a source electrode 28, and a drain electrode 30 formed on the electron supply layer 18.

[0062] In the case of the chip 101 having the above configuration, heat generated from the transistor 51 is dissipated to the outside via the semiconductor substrate 12. More specifically, the semiconductor module 100 is joined to the substrate lower surface 12r of the semiconductor substrate 12 and includes a heat dissipation member 103 exposed to the module lower surface 100r. Heat generated from the transistor 51 is dissipated to the outside from the module lower surface 100r of the semiconductor module 100 via the semiconductor substrate 12 and the heat dissipation member 103. Therefore, the semiconductor module 100 can be said to be a one-sided heat dissipation module.

[0063] Here, the chip 101 uses a GaN substrate as the semiconductor substrate 12, that is, a substrate made of the same material as the electron transit layer 16 and the electron supply layer 18 formed on the semiconductor substrate 12. This allows the thickness of the semiconductor substrate 12 to be thinner than in conventional structures using other substrates. Specifically, the thickness of the semiconductor substrate 12 can be made 100 μm or less.

[0064] More specifically, when the material constituting the semiconductor substrate 12 and the material constituting the electron transit layer 16 and the electron supply layer 18 formed thereon are different materials, stress that tends to warp the chip 101 occurs due to the difference in linear expansion coefficient between the two materials. Therefore, the semiconductor substrate needs to have a thickness that can ensure the strength against the above-mentioned stress. For example, when a Si substrate is used, the thickness of the Si substrate needs to be 200 μm or more.

[0065] On the other hand, when the material constituting the semiconductor substrate 12 and the material constituting the electron transit layer 16 formed thereon are both the same type of material (GaN-based material), the difference in the linear expansion coefficient between the two materials becomes small or disappears. Therefore, the stress that tends to warp the chip 101 due to the difference in linear expansion coefficient becomes small or does not occur. This makes it possible to reduce the strength required for the semiconductor substrate 12. As a result, it becomes possible to use a semiconductor substrate 12 with a relatively low strength, that is, a semiconductor substrate 12 with a thickness of 100 μm or less.

[0066] Furthermore, by using a thin semiconductor substrate 12 having a thickness of 100 μm or less, it is possible to reduce the thermal resistance when heat flows in the thickness direction of the semiconductor substrate 12. This reduces the thermal resistance when heat generated from the transistor 51 in the chip 101 is dissipated to the outside via the semiconductor substrate 12. As a result, the heat dissipation performance of the semiconductor module 100 is improved.

[0067] Furthermore, the thermal conductivity of Si used in conventional semiconductor substrates is 1.5 W / cm K. In contrast, the thermal conductivity of GaN is 2 W / cm K, which is higher than that of Si. Therefore, when a GaN substrate is used, the thermal conductivity of the material constituting the semiconductor substrate 12 is higher, and therefore, the effect of improving heat dissipation can be obtained compared to when a Si substrate is used.

[0068] For reference, the thermal resistance of a chip 101 using a GaN substrate as the semiconductor substrate 12 was compared with that of a chip 101 using a Si substrate by simulation. The thermal resistance was calculated as the thermal resistance between a specific first point on the upper surface 18A of the electron supply layer 18 and a specific second point on the substrate lower surface 12r of the semiconductor substrate 12. First, a Si substrate having a thickness of 200 μm and an area of ​​10 mm2 in a plan view was used. 2A first model of a semiconductor module including a chip 101 having a thickness of 80 μm was constructed, and its thermal resistance was calculated. Next, a second model having the same configuration as the first model except for the use of a GaN substrate having a thickness of 80 μm was constructed, and its thermal resistance was calculated. As a result, the thermal resistance of the first model using a Si substrate was 0.13° C. / W. In contrast, the thermal resistance of the second model using a GaN substrate was 0.04° C. / W, which was less than one-third of the thermal resistance of the first model.

[0069] [effect] According to the semiconductor module 100 of the first embodiment, the following effects can be obtained. (1-1) The semiconductor module 100 includes a chip 101 including a transistor 51. The chip 101 includes a semiconductor substrate 12, an electron transit layer 16 formed on the semiconductor substrate 12 and made of GaN, and an electron supply layer 18 formed on the electron transit layer 16 and made of GaN. The transistor 51 includes a gate electrode 24, a source electrode 28, and a drain electrode 30 formed on the electron supply layer 18. The semiconductor substrate 12 is a GaN substrate having a thickness of 100 μm or less.

[0070] According to the above configuration, by using a GaN substrate as the semiconductor substrate 12, the thickness of the semiconductor substrate 12 can be made 100 μm or less. This reduces the thermal resistance when heat generated from the transistor 51 is dissipated to the outside via the semiconductor substrate 12. As a result, the heat dissipation performance of the semiconductor module 100 is improved. The improved heat dissipation performance of the semiconductor module 100 reduces the amount of heat generated by the chip 101. This makes it possible to increase the upper limit (allowable current) of the drain current that can be passed through the transistor 51.

[0071] (1-2) Furthermore, when the semiconductor substrate 12 is a GaN substrate, the electron transit layer 16 and the electron supply layer 18, which are GaN layers, can be formed by epitaxial growth on the semiconductor substrate 12 without a buffer layer. For example, the electron supply layer 18 is formed in contact with the substrate upper surface 12s of the semiconductor substrate 12.

[0072] In this case, by omitting the buffer layer, the distance from the upper surface 18A of the electron supply layer 18 to the semiconductor substrate 12 can be shortened. This shortens the heat dissipation path through which heat generated from the transistor 51 is dissipated to the outside via the electron transit layer 16 and the semiconductor substrate 12. In this respect, too, the thermal resistance when the heat generated from the transistor 51 is dissipated to the outside through the heat dissipation path is reduced. As a result, the heat dissipation performance of the semiconductor module 100 is further improved.

[0073] When the electron transit layer 16 is disposed on the semiconductor substrate 12 made of n-type GaN without a buffer layer therebetween, the electron transit layer 16 made of undoped GaN may be formed thick in order to ensure insulation between the 2DEG 20 and the semiconductor substrate 12. Even in this case, the decrease in thickness due to the omission of the buffer layer is greater than the increase in thickness of the electron transit layer 16, so the distance from the upper surface 18A of the electron supply layer 18 to the semiconductor substrate 12 can be made shorter than in a configuration having a buffer layer.

[0074] (1-3) The chip 101 includes a plurality of transistors 51 (HEMT cells 51HC). Each of the transistors 51 is a horizontal transistor in which a gate electrode 24, a source electrode 28, and a drain electrode 30 are formed on an electron supply layer 18. The chip 101 can be made smaller by closely arranging a plurality of horizontal transistors 51, but the heat generated by the adjacent transistors 51 tends to interfere with each other, resulting in an increase in the amount of heat generated by the chip 101. For this reason, it is particularly effective to use a GaN substrate having a thickness of 100 μm or less for the chip 101 including the plurality of transistors 51.

[0075] (1-4) The semiconductor module 100 includes a sealing member 104 that covers the chip 101. The semiconductor module 100 has a module upper surface 100s facing the same side as the substrate upper surface 12s, and a module lower surface 100r facing the same side as the substrate lower surface 12r. The thickness T4 of the semiconductor substrate 12 is thinner than a thickness T3 that is a distance from the upper surface 18A of the electron supply layer 18 to the module upper surface 100s. In this case, the thin thickness T4 of the semiconductor substrate 12 further reduces the thermal resistance when heat generated from the transistor 51, particularly from the vicinity of the electron supply layer 18, is dissipated to the outside via the semiconductor substrate 12.

[0076] (1-5) In the thickness direction of the semiconductor substrate 12, the chip underside 101r of the chip 101 is disposed closer to the module underside 100r than the module upper side 100s of the semiconductor module 100. In this case, it is possible to shorten the path of one-sided heat dissipation in which the heat generated from the transistor 51 is dissipated from the module underside 100r via the semiconductor substrate 12. This further reduces the thermal resistance when the heat generated from the transistor 51 is dissipated to the outside via the semiconductor substrate 12.

[0077] (1-6) The transistor 51 includes a gate layer 22 formed on the electron supply layer 18 and made of GaN containing acceptor-type impurities. A gate electrode 24 is formed on the gate layer 22. That is, the transistor 51 is of a normally-off type. In this case, at zero bias when no voltage is applied to the gate electrode 24, the 2DEG 20 is not formed in the electron transit layer 16 in the region immediately below the gate layer 22. On the other hand, the 2DEG 20 is formed in the electron transit layer 16 in the region other than the region immediately below the gate layer 22. When an on-voltage is applied to the gate electrode 24, a channel is formed by the 2DEG 20 in the electron transit layer 16 in the region immediately below the gate electrode 24.

[0078] Here, when an on-voltage is applied to the gate electrode 24, the 2DEG 20 generated in the region immediately below the gate layer 22 in the electron transit layer 16 is smaller than the 2DEG 20 generated in the region other than the region immediately below the gate layer 22. Therefore, the region immediately below the gate layer 22 in the electron transit layer 16 has a higher resistance than the region other than the region immediately below the gate layer 22, resulting in a higher amount of heat generation. Therefore, when the transistor 51 included in the chip 101 is a normally-off type having the gate layer 22, the amount of heat generated by the chip 101 is likely to be larger than when the transistor 51 is a normally-on type not having the gate layer 22. Therefore, it is particularly effective to use a GaN substrate having a thickness of 100 μm or less for the chip 101 including the normally-off type transistor 51.

[0079] <Second embodiment> The semiconductor module 200 of the second embodiment differs from the first embodiment in that it includes a control circuit. The other configurations are the same as those of the first embodiment. In the following, the description of the components similar to those of the first embodiment will be omitted, and only the components different from those of the first embodiment will be described.

[0080] FIG. 5 is a schematic plan view of an illustrative semiconductor module 100 according to the second embodiment. [Schematic structure of semiconductor module] As shown in FIG. 5, the semiconductor module 200 includes a module upper surface 200s and a module lower surface (not shown) facing the opposite side to the module upper surface 200s.

[0081] The semiconductor module 200 includes a chip 101 including a transistor 51, a first conductive terminal 102A and a second conductive terminal 102B electrically connected to the chip 101, and a heat dissipation member 103. Each of these configurations is similar to that of the first embodiment.

[0082] The semiconductor module 200 further includes a control chip 201 including a control circuit, a plurality of fourth conductive terminals 102E electrically connected to the control chip 201, a control heat dissipation member 202, and a sealing member 203 that seals the chip 101 and the control chip 201.

[0083] The fourth conductive terminals 102E have external connection surfaces (respective lower surfaces) that are partially exposed on the lower surface of the module from the sealing member 203. Examples of materials for forming the fourth conductive terminals 102E include the same materials as those for forming the first conductive terminals 102A.

[0084] The control chip 201 includes a chip top surface 201s facing the same side as the module top surface 200s. The control chip 201 includes a first electrode pad 81 and a plurality of second electrode pads 82 formed on the chip top surface 201s. The first electrode pad 81 is bonded to the top surface of the gate pad 73 of the chip 101 via a wire 81A. Each of the plurality of second electrode pads 82 is bonded to a different fourth conductive terminal 102E via a wire 82A. The first electrode pad 81 and the second electrode pad 82 may be formed from a material similar to the material forming the electrode pad 70. The wires 81A and 82A may be formed from a material similar to the material forming the wire 102D.

[0085] The control heat dissipation member 202 is attached to the chip underside of the control chip 201. The method of attaching the control heat dissipation member 202 to the chip underside is not particularly limited. The method of attaching the control heat dissipation member 202 may be the same as that described for the heat dissipation member 103. The control heat dissipation member 202 includes an exposed surface (not shown) that is partially exposed from the sealing member 203 to the module underside. The material for forming the control heat dissipation member 202 may be the same as that for forming the heat dissipation member 103.

[0086] The sealing member 203 may define the package outer shape of the semiconductor module 200. The sealing member 203 seals the chip 101 and the control chip 201 as well as a part of the first conductive terminal 102A, a part of the second conductive terminal 102B, a part of the fourth conductive terminal 102E, a part of the heat dissipation member 103, and a part of the control heat dissipation member 202. Examples of materials for forming the sealing member 203 include materials similar to those for forming the sealing member 104.

[0087] A control circuit in the control chip 201 generates a drive signal for driving the transistor 51. The drive signal is applied to the gate electrode 24 of the transistor 51. The control circuit controls the on / off state of the transistor 51.

[0088] [effect] The semiconductor module 200 of the second embodiment provides the same effects as the semiconductor module 100 of the first embodiment.

[0089] <Third embodiment> The semiconductor module 300 of the third embodiment differs from the second embodiment in that it is embodied as a bridge module having a bridge circuit. In this embodiment, as an example, a semiconductor module 300 embodied as a half-bridge module having a half-bridge circuit will be described.

[0090] [Circuit configuration of semiconductor module] 6 is a schematic circuit diagram of a semiconductor module 300. The semiconductor module 300 includes a half-bridge circuit 301 and a control circuit C. The half-bridge circuit 301 includes a first transistor 302 and a second transistor 303. The control circuit C controls the driving of the first transistor 302 and the second transistor 303.

[0091] The first transistor 302 and the second transistor 303 are connected in series to each other. The first transistor 302 functions as a high-side transistor (control transistor) of the half-bridge circuit 301, and the second transistor 303 functions as a low-side transistor (synchronous rectification transistor) of the half-bridge circuit 301.

[0092] The first transistor 302, which is provided as a high-side transistor, includes a source terminal 302S, a drain terminal 302D, and a gate terminal 302G, the drain terminal 302D being connected to the input terminal T10, and the source terminal 302S being connected to the output terminal T20. IN is applied.

[0093] The second transistor 303 provided as a low-side transistor includes a source terminal 303S, a drain terminal 303D, and a gate terminal 303G, with the drain terminal 303D connected to the output terminal T20 and the source terminal 303S connected to the ground GND. Thus, the first transistor 302 and the second transistor 303 are connected in series between the input terminal T10 and the ground GND, and the connection node between the first transistor 302 and the second transistor 303 is connected to the output terminal T20.

[0094] The control circuit C includes a high-side driver 310 and a low-side driver 320. The high-side driver 310 outputs a high-side control signal V GH Generates the high-side control signal V GH is applied to the gate terminal 302G of the first transistor 302. The low-side driver 320 supplies a low-side control signal V GL Generates the low-side control signal V GL is applied to the gate terminal 303G of the second transistor 303.

[0095] The control circuit C controls the high-side control signal V GH and the low-side control signal VGL Based on this, the first transistor 302 and the second transistor 303 are complementarily controlled on and off to provide a switching voltage V SW It should be noted that a load circuit (not shown) including, for example, a coil and an inductor is connected to the output terminal T20.

[0096] When the first transistor 302 is in an on state and the second transistor 303 is in an off state, a switch current I flows from the input terminal T10 to the load circuit (output terminal T20) via the first transistor 302. SW flows, and the input voltage V IN Switch voltage based on V SW is output to the output terminal T20. When the first transistor 302 is in an off state and the second transistor 303 is in an on state, a switch current I SW flows, and the switch voltage V SW is pulled to 0V.

[0097] [Schematic structure of semiconductor module] As shown in FIG. 7, the semiconductor module 300 includes a module upper surface 300s and a module lower surface (not shown) facing the opposite side to the module upper surface 300s.

[0098] The semiconductor module 300 includes a chip 331 including a first transistor 302 and a second transistor 303, a fifth conductive terminal 332A, a sixth conductive terminal 332B, and a seventh conductive terminal 332C electrically connected to the chip 331, and a heat dissipation member 335 joined to the chip 331. The semiconductor module 300 further includes a control chip 333 including a control circuit C, a plurality of eighth conductive terminals 332D electrically connected to the control chip 333, a control heat dissipation member 202, and a sealing member 337 that seals the chip 331 and the control chip 333. For ease of understanding, in FIG. 7, only the outline of the sealing member 337 is shown.

[0099] The chip 331 includes a chip upper surface 331s facing the same side as the module upper surface 300s. The shape of the chip 331 in a plan view, in other words, the shape of the chip upper surface 331s in a plan view, is, for example, rectangular. The chip 331 includes a semiconductor substrate 12, a nitride semiconductor layer 50 (see FIG. 8), a first transistor 302 (see FIG. 8) and a second transistor 303 (see FIG. 8), an insulator layer 60 (not shown), an electrode pad 370, and a lower surface electrode 80. The semiconductor substrate 12, the lower surface electrode 80 (see FIG. 8), and the insulator layer 60 are the same as those in the first embodiment. Details of the nitride semiconductor layer 50 will be described later.

[0100] The electrode pad 370 is formed on the chip upper surface 331s. The electrode pad 370 includes one or more source pads 371H, one or more drain pads 372H, and one or more gate pads 373H. The source pad 371H is electrically connected to a source electrode 28H of the first transistor 302, which will be described later. The drain pad 372H is electrically connected to a drain electrode 30H of the first transistor 302, which will be described later. The gate pad 373H is electrically connected to a gate electrode 24H of the first transistor 302, which will be described later.

[0101] The electrode pad 370 includes one or more source pads 371L, one or more drain pads 372L, and one or more gate pads 373L. The source pad 371L is electrically connected to a source electrode 28L of the second transistor 303, which will be described later. The drain pad 372L is electrically connected to a drain electrode 30L of the second transistor 303, which will be described later. The gate pad 373L is electrically connected to a gate electrode 24L of the second transistor 303, which will be described later. The material forming the electrode pad 370 is the same as the material forming the electrode pad 70 of the first embodiment.

[0102] In the example shown in FIG. 7, the chip 331 includes a plurality of source pads 371H, a plurality of drain pads 372H, a gate pad 373H, a plurality of source pads 371L, a plurality of drain pads 372L, and a gate pad 373L.

[0103] Each of the source pads 371H and the drain pads 372H is formed in a rectangular shape extending in the Y-axis direction, and is arranged alternately in the X-axis direction in the region on the +Y-axis direction side of the chip upper surface 331s. The gate pad 373H is arranged at a position closer to the outer periphery of the chip upper surface 331s than the source pads 371H and the drain pads 372H. More specifically, the gate pads 373H are arranged at intervals in the +Y-axis direction from the pad (the source pad 371H in FIG. 7) arranged at the end in the -X-axis direction.

[0104] Each of the multiple source pads 371L and the multiple drain pads 372L is formed in a rectangular shape extending in the Y-axis direction, and is arranged alternately in the X-axis direction at intervals in the region on the -Y-axis direction side of the chip upper surface 331s. Also, each of the source pads 371L is arranged at intervals on the -Y-axis direction side of the drain pad 372H. Each of the drain pads 372L is arranged at intervals on the -Y-axis direction side of the source pad 371H. The gate pad 373L is arranged at a position closer to the outer periphery of the chip upper surface 331s than the multiple source pads 371L and the multiple drain pads 372L. More specifically, the gate pads 373L are arranged at intervals in the -Y-axis direction of the pad (the drain pad 372L in FIG. 7) arranged at the end in the -X-axis direction.

[0105] The fifth conductive terminal 332A, the sixth conductive terminal 332B, and the seventh conductive terminal 332C are electrically connected to the electrode pad 370 of the chip 331. In detail, the fifth conductive terminal 332A is bonded to the upper surface of the drain pad 372H via a conductive bonding material (not shown). The sixth conductive terminal 332B is bonded to the upper surface of the source pad 371L via a conductive bonding material (not shown). The seventh conductive terminal 332C is bonded to both the upper surface of the source pad 371H and the upper surface of the drain pad 372L via a conductive bonding material (not shown).

[0106] Each of the fifth conductive terminal 332A, the sixth conductive terminal 332B, and the seventh conductive terminal 332C has, for example, a bridge shape. Each of the fifth conductive terminal 332A, the sixth conductive terminal 332B, and the seventh conductive terminal 332C has an external connection surface (respective lower surface) that is partially exposed from the sealing member 337 to the lower surface of the module. The external connection surface of the fifth conductive terminal 332A corresponds to the input terminal T10 in FIG. 6. The external connection surface of the sixth conductive terminal 332B corresponds to the ground GND in FIG. 6. The external connection surface of the seventh conductive terminal 332C corresponds to the output terminal T20 in FIG. 6.

[0107] The control chip 333 includes a chip top surface 333s that faces the same side as the module top surface 300s. The shape of the control chip 333 in a plan view, in other words, the shape of the chip top surface 333s in a plan view, is, for example, rectangular.

[0108] The control chip 333 includes a third electrode pad 335A, a fourth electrode pad 335B, and a plurality of fifth electrode pads 335C formed on the chip upper surface 333s. The third electrode pad 335A is bonded to the upper surface of the gate pad 373H of the chip 331 via a wire 336A. The fourth electrode pad 335B is bonded to the upper surface of the gate pad 373L of the chip 331 via a wire 336B. Each of the plurality of fifth electrode pads 335C is bonded to a plurality of different eighth conductive terminals 332D via a wire 336C. ​​Each of the plurality of eighth conductive terminals 332D has an external connection surface (respective lower surface) that is partially exposed from the sealing member 337 to the module lower surface.

[0109] (Schematic Structure of First Transistor and Second Transistor) FIG. 8 is a schematic cross-sectional view of the first transistor 302 and the second transistor 303. The first transistor 302 and the second transistor 303 include a common semiconductor substrate 12 and a common nitride semiconductor layer 50 formed on the semiconductor substrate 12. The nitride semiconductor layer 50 is epitaxially grown on the substrate upper surface 12s of the semiconductor substrate 12. The nitride semiconductor layer 50 includes an electron transit layer 16 formed on the semiconductor substrate 12, and an electron supply layer 18 formed on the electron transit layer 16. The semiconductor substrate 12 and the nitride semiconductor layer 50 are similar to those in the first embodiment.

[0110] The first transistor 302 includes a gate layer 22H formed on the electron supply layer 18 and a gate electrode 24H formed on the gate layer 22H. The second transistor 303 includes a gate layer 22L formed on the electron supply layer 18 and a gate electrode 24L formed on the gate layer 22L.

[0111] The first transistor 302 and the second transistor 303 include a passivation layer 26. The passivation layer 26 is formed on the electron supply layer 18, the gate layers 22H, 22L, and the gate electrodes 24H, 24L, and includes first openings 26AH, 26AL and second openings 26BH, 26BL.

[0112] The first openings 26AH, 26AL and the second openings 26BH, 26BL are arranged at intervals in the +X direction in the order of the first opening 26AL, the second opening 26BL, the first opening 26AH, and the second opening 26BH. In one example, in the X direction, the distance between the first opening 26AL and the second opening 26BL is equal to the distance between the first opening 26AH and the second opening 26BH. The distance between the second opening 26BL and the first opening 26AH is shorter than the distance between the first opening 26AL and the second opening 26BL and the distance between the first opening 26AH and the second opening 26BH.

[0113] The first transistor 302 includes a source electrode 28H in contact with the upper surface 18A of the electron supply layer 18 through the first opening 26AH, and a drain electrode 30H in contact with the upper surface 18A of the electron supply layer 18 through the second opening 26BH. The gate layer 22H of the first transistor 302 is located between the first opening 26AH and the second opening 26BH of the passivation layer 26, and is spaced apart from each of the first opening 26AH and the second opening 26BH. The source electrode 28H and the drain electrode 30H are disposed on the upper surface 18A of the electron supply layer 18 so as to sandwich the gate layer 22H. On the upper surface 18A of the electron supply layer 18, the gate layer 22H, the source electrode 28H, and the drain electrode 30H are aligned in the X-axis direction. The details of the configuration of the first transistor 302 are similar to those of the transistor 51 of the first embodiment. The source electrode 28H is electrically connected to a source pad 371H. The drain electrode 30H is electrically connected to a drain pad 372H. The gate electrode 24H is electrically connected to a gate pad 373H.

[0114] The second transistor 303 includes a source electrode 28L in contact with the upper surface 18A of the electron supply layer 18 through the first opening 26AL, and a drain electrode 30L in contact with the upper surface 18A of the electron supply layer 18 through the second opening 26BL. The gate layer 22L of the second transistor 303 is located between the first opening 26AL and the second opening 26BL of the passivation layer 26, and is spaced apart from each of the first opening 26AL and the second opening 26BL. The source electrode 28L and the drain electrode 30L are disposed on the upper surface 18A of the electron supply layer 18 so as to sandwich the gate layer 22L. On the upper surface 18A of the electron supply layer 18, the gate layer 22L, the source electrode 28L, and the drain electrode 30L are aligned in the X-axis direction. The source electrode 28L is electrically connected to the source pad 371L. The drain electrode 30L is electrically connected to the drain pad 372L. The gate electrode 24L is electrically connected to a gate pad 373L.

[0115] [effect] The semiconductor module 300 of the third embodiment provides the same effects as the semiconductor module 100 of the first embodiment. Furthermore, according to the semiconductor module 300 of the third embodiment, the following effects can be obtained.

[0116] (3-1) The chip 331 includes a bridge circuit configured using a plurality of transistors (a first transistor 302 and a second transistor 303). An example of a bridge circuit is a half-bridge circuit 301 including a first transistor 302 (a high-side transistor) and a second transistor 303 (a low-side transistor) connected in series with each other. The semiconductor module 300 includes a control circuit C that controls the on / off of the plurality of transistors (the first transistor 302 and the second transistor 303).

[0117] In the case of a bridge circuit, multiple transistors are arranged close to each other in order to operate at high frequency and to reduce the size of chip 331. Therefore, the heat generated by each of the multiple adjacent transistors interferes with each other, and the amount of heat generated by chip 331 tends to increase. For this reason, it is particularly effective to use a GaN substrate having a thickness of 100 μm or less for chip 101 having a bridge circuit.

[0118] <Example of change> The above-described embodiments can be modified, for example, as follows. The above-described embodiments and the following modified examples can be combined with each other as long as no technical contradiction occurs. In the following modified examples, the same reference numerals as those in the above-described embodiments are used for the parts common to the above-described embodiments, and the description thereof will be omitted.

[0119] The transistor 51 may be a normally-on type that does not have the gate layer 22. The same applies to the first transistor 302 and the second transistor 303. The term "on" as used in this disclosure includes both the meanings of "on" and "above" unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer may be disposed directly on the second layer in contact with the second layer, while in other embodiments, the first layer may be disposed above the second layer without contacting the second layer. That is, the term "on" does not exclude a structure in which another layer is formed between the first layer and the second layer.

[0120] The Z direction used in this disclosure does not necessarily have to be a vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" of the Z direction described in this specification being "up" and "down" of the vertical direction. For example, the X-axis direction may be a vertical direction, or the Y-axis direction may be a vertical direction.

[0121] The terms "first", "second", "third", etc. in this disclosure are used merely to distinguish objects and do not rank the objects. <Additional Notes> The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding, not for the purpose of limitation, the components described in the appendices are given the reference symbols of the corresponding components in the embodiments. The reference symbols are shown as examples for the purpose of aiding understanding, and the components described in each appendix should not be limited to the components indicated by the reference symbols.

[0122] [Appendix 1] A chip (101, 331) including a transistor (51, 302, 303), The chip (101, 331) A semiconductor substrate (12) having a substrate upper surface (12s) and a substrate lower surface (12r) facing the opposite side to the substrate upper surface (12s); an electron transit layer (16) formed on the substrate upper surface (12s) of the semiconductor substrate (12) and made of GaN; an electron supply layer (18) formed on the electron transit layer (16) and made of GaN having a larger band gap than the electron transit layer (16); The transistor (51, 302, 303) includes a gate electrode (24), a source electrode (28), and a drain electrode (30) formed on the electron supply layer (18); The nitride semiconductor module (100, 200, 300), wherein the semiconductor substrate (12) is a GaN substrate having a thickness of 100 μm or less.

[0123] [Appendix 2] The nitride semiconductor module according to claim 1, wherein the chip (101, 331) includes a plurality of the transistors (51, 302, 303).

[0124] [Appendix 3] A sealing member (26, 203) that covers the chip (101, 331), a module upper surface (100s, 200s, 300s) formed by the sealing member (26, 203) and facing the same side as the substrate upper surface (12s), and a module lower surface (100r, 200r, 300r) facing the same side as the substrate lower surface (12r), A nitride semiconductor module (100, 200, 300) according to Appendix 1 or Appendix 2, wherein a thickness (T4) of the semiconductor substrate (12) is thinner than a distance (T3) from an upper surface (18A) of the electron supply layer (18) to the module upper surface (100s, 200s, 300s).

[0125] [Appendix 4] A sealing member (26, 203) that covers the chip (101, 331), a module upper surface (100s, 200s, 300s) formed by the sealing member (26, 203) and facing the same side as the substrate upper surface (12s), and a module lower surface (100r, 200r, 300r) facing the same side as the substrate lower surface (12r), A nitride semiconductor module (100, 200, 300) according to any one of Appendices 1 to 3, wherein in the thickness direction of the semiconductor substrate (12), a chip underside (101r, 331r) of the chip (101, 331) is positioned closer to the module underside (100r, 200r, 300r) than to the module top side (100s, 200s, 300s).

[0126] [Appendix 5] A sealing member (26, 203) that covers the chip (101, 331), a module upper surface (100s, 200s, 300s) formed by the sealing member (26, 203) and facing the same side as the substrate upper surface (12s), and a module lower surface (100r, 200r, 300r) facing the same side as the substrate lower surface (12r), The nitride semiconductor module (100, 200, 300) according to any one of claims 1 to 4, comprising a heat dissipation member (103) attached to the substrate lower surface (12r) and exposed to the module lower surface (100r, 200r, 300r).

[0127] [Appendix 6] The nitride semiconductor module (100, 200, 300) according to claim 5, wherein the heat dissipation member (26, 203) has a thickness of 150 μm or less.

[0128] [Appendix 7] the electron transport layer (16) is a GaN layer, 7. The nitride semiconductor module according to any one of claims 1 to 6, wherein the electron supply layer (18) is an AlGaN layer.

[0129] [Appendix 8] The transistor (51, 302, 303) includes a gate layer (22) formed on the electron supply layer (18) and made of GaN containing acceptor-type impurities; The nitride semiconductor module (100, 200, 300) according to any one of appendix 1 to 7, wherein the gate electrode (24) is formed on the gate layer (22).

[0130] [Appendix 9] the electron transport layer (16) is a GaN layer, the electron supply layer (18) is an AlGaN layer; The nitride semiconductor module (100, 200, 300) according to appendix 8, wherein the gate layer (22) is a GaN layer containing the acceptor-type impurity.

[0131] [Appendix 10] The nitride semiconductor module (200, 300) according to any one of appendix 1 to 9, further comprising a control circuit (C1, C2) that controls on / off of the transistor (51, 302, 303).

[0132] [Appendix 11] The chip (101, 331) includes a plurality of the transistors (51, 302, 303), The nitride semiconductor module (300) according to any one of claims 1 to 9, comprising a bridge circuit (301) configured using a plurality of the transistors (302, 303).

[0133] [Appendix 12] The plurality of transistors (302, 303) constitute a half-bridge circuit (301) including a high-side transistor (302) and a low-side transistor (303) connected in series with each other; 12. The nitride semiconductor module (300) according to claim 11, further comprising a control circuit (C2) for controlling the on / off of the high-side transistor (302) and the low-side transistor (303).

[0134] [Appendix 13] a nitride semiconductor layer (50) formed on the semiconductor substrate (12); A chip comprising a plurality of transistors (302, 303) including the nitride semiconductor layer (50), The plurality of transistors (302, 303) constitute a half-bridge circuit (301) including a high-side transistor (302) and a low-side transistor (303) connected in series with each other; one or more source pads (371H) electrically connected to a source electrode (28H) of the high-side transistor (302), one or more drain pads (372H) electrically connected to a drain electrode (30H) of the high-side transistor (302), and one or more gate pads (373H) electrically connected to a gate electrode (24H) of the high-side transistor (302), which are formed on a chip upper surface (101s) perpendicular to a thickness direction of the semiconductor substrate (12); a plurality of source pads (371L) formed on the upper surface (101s) of the chip, electrically connected to the source electrodes (28L) of the low-side transistors (303), a plurality of drain pads (372L) electrically connected to the drain electrodes (30L) of the low-side transistors (303), and a gate pad (373L) electrically connected to the gate electrodes (24L) of the low-side transistors (303); Each of the plurality of source pads (371H) and the plurality of drain pads (372H) is arranged alternately in a second direction (X-axis direction) perpendicular to the first direction on the chip upper surface (101s) in a region on one side (+Y-axis direction) of a first direction on the chip upper surface (101s), The plurality of source pads (371H) and the plurality of drain pads (372H) are arranged alternately in the second direction (X-axis direction) on the chip top surface (101s) in a region on the other side (-Y-axis direction) of the first direction on the chip top surface (101s), A chip in which each of the multiple source pads (371H) is arranged to be aligned at intervals on the other side in the first direction (-Y axis direction side) of the drain pad (372H), and each of the multiple drain pads (372L) is arranged to be aligned at intervals on the other side in the first direction (-Y axis direction side) of the source pad (371H).

[0135] [Appendix 14] the gate pad (373H) is disposed at a position closer to the outer periphery than the plurality of source pads (371H) and the plurality of drain pads (372H); 14. The chip of claim 13, wherein the gate pad (373L) is disposed at a position closer to an outer periphery than the plurality of source pads (371L) and the plurality of drain pads (372L).

[0136] The thickness of the semiconductor substrate (12) included in the chip described in Supplementary Note 13 and Supplementary Note 14 and the material forming the semiconductor substrate (12) are not particularly limited. [Explanation of symbols]

[0137] C…Control circuit D1, D2, D3...Distance T1~T6…Thickness T10: Input terminal T20: Output terminal 12...Semiconductor substrate 12r…Bottom surface of board 12s…Top surface of board 16...Electron transport layer 18...electron supply layer 18A…Top surface 20...Two-dimensional electron gas 22, 22H, 22L...Gate layer 24, 24H, 24L...gate electrode 26…Passivation layer 26A, 26AH, 26AL…1st opening 26B, 26BH, 26BL…Second opening 28, 28H, 28L...Source electrode 30, 30H, 30L...Drain electrode 50...Nitride semiconductor layer 51...Transistor 51HC…HEMT cell 60…Insulator layer 70...Electrode pad 71...Sauce Pad 72…Drain pad 73…Gate pad 80…Bottom electrode 81…First electrode pad 81A, 82A…Wire 82…Second electrode pad 100...Semiconductor module 100r…Module bottom 100s…Module top 101...Chip 101r…Chip bottom 101s: Chip top 102A…1st conductive terminal 102B…Second conductive terminal 102C…Third conductive terminal 102D…Wire 102E...Fourth conductive terminal 103...Heat dissipation member 104...Sealing member 200...Semiconductor module 200s…Module top 201...Control chip 201s…Chip top 202...Control heat dissipation member 203...Sealing member 300...Semiconductor module 300s…Module top 301...Half-bridge circuit 302...first transistor 302D, 303D...Drain terminal 302G, 303G: Gate terminal 302S, 303S: Source terminal 310…High side driver 320…Low side driver 331…Chip 331s…Chip top 332A…5th conductive terminal 332B…6th conductive terminal 332C…7th conductive terminal 332D…8th conductive terminal 333...Control chip 333s…Chip top 335...Heat dissipation material 335A…Third electrode pad 335B…4th electrode pad 335C…5th electrode pad 336A, 336B, 336C...Wire 337...Sealing member 370…Electrode pad 371H, 371L…Sauce pad 372H, 372L...Drain pad 373H, 373L...Gate pad

Claims

1. A chip including a transistor, The chip comprises: a semiconductor substrate having a substrate upper surface and a substrate lower surface facing away from the substrate upper surface; an electron transit layer formed on the upper surface of the semiconductor substrate and made of GaN; an electron supply layer formed on the electron transit layer and made of GaN having a band gap larger than that of the electron transit layer; the transistor includes a gate electrode, a source electrode, and a drain electrode formed on the electron supply layer; The nitride semiconductor module, wherein the semiconductor substrate is a GaN substrate having a thickness of 100 μm or less.

2. The nitride semiconductor module according to claim 1 , wherein the chip includes a plurality of the transistors.

3. a sealing member covering the chip; a module upper surface formed by the sealing member and facing the same side as the substrate upper surface, and a module lower surface facing the same side as the substrate lower surface; The nitride semiconductor module according to claim 1 , wherein a thickness of said semiconductor substrate is smaller than a distance from an upper surface of said electron supply layer to an upper surface of said module.

4. a sealing member covering the chip; a module upper surface formed by the sealing member and facing the same side as the substrate upper surface, and a module lower surface facing the same side as the substrate lower surface; 2. The nitride semiconductor module according to claim 1, wherein in a thickness direction of said semiconductor substrate, a chip lower surface of said chip is located closer to said module lower surface than said module upper surface.

5. a sealing member covering the chip; a module upper surface formed by the sealing member and facing the same side as the substrate upper surface, and a module lower surface facing the same side as the substrate lower surface; The nitride semiconductor module according to claim 1 , further comprising a heat dissipation member attached to a lower surface of said substrate and exposed to a lower surface of said module.

6. The nitride semiconductor module according to claim 5 , wherein the heat dissipation member has a thickness of 150 μm or less.

7. the electron transport layer is a GaN layer, The nitride semiconductor module according to claim 1 , wherein the electron supply layer is an AlGaN layer.

8. the transistor includes a gate layer formed on the electron supply layer and made of GaN containing an acceptor-type impurity; The nitride semiconductor module according to claim 1 , wherein the gate electrode is formed on the gate layer.

9. the electron transport layer is a GaN layer, the electron supply layer is an AlGaN layer; 9. The nitride semiconductor module according to claim 8, wherein the gate layer is a GaN layer containing the acceptor-type impurity.

10. The nitride semiconductor module according to claim 1 , further comprising a control circuit that controls the on / off of said transistor.

11. The nitride semiconductor module according to claim 2 , further comprising a bridge circuit configured using a plurality of said transistors.

12. the plurality of transistors form a half-bridge circuit including a high-side transistor and a low-side transistor connected in series with each other; The nitride semiconductor module according to claim 11 , further comprising a control circuit that controls on / off of the high-side transistor and the low-side transistor.

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