Integrated circuit and manufacturing method thereof

Abstract

To provide an integrated circuit suitable for being used in a signal frequency band of 1 THz or more.SOLUTION: An integrated circuit having a short gate long transistor formation area, an antenna element formation area and a gallium nitride device formation area integrally comprises: a short gate long transistor 100 including a substrate 2 having an uppermost face 22 which is a single crystal of silicon nitride, a vertical face 21 crossing with the uppermost face and extending below the uppermost face and a lower stage face 23 almost parallel to the uppermost face and crossing with the vertical face, and a single crystal graphene layer 3 provided in contact with the uppermost face of the substrate; and an antenna element. The short gate long transistor comprises: an insulator film 6 serving as a gate electrode at an end where the graphene layer crosses with the vertical face, and covering at least the vertical face and the end of the graphene layer; and a two-dimensional semiconductor layer 7 formed to cover the uppermost face, the vertical face and the lower stage face, and overlaid to cover the graphene layer and / or the insulator film at a portion where the graphene layer and / or the insulator film exist.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to an integrated circuit that uses graphene formed on a silicon carbide substrate as wiring or electrodes, and a method for manufacturing the same. [Background technology]

[0002] In order to realize the next generation mobile communication system (so-called 6G, Beyond 5G), high performance antennas suitable for transmission and reception at high frequencies of 100 GHz or more are required. As a candidate for such an antenna, an antenna using graphene as an antenna element, which has superior properties (high electrical conductivity, high carrier mobility, high thermal conductivity) compared to copper, ITO (Indium Tin Oxide), etc., which have been used as conductors in conventional antenna elements, has been proposed (see, for example, Patent Document 1).

[0003] The microwave band antenna described in Patent Document 1 has an antenna element formed by transferring a graphene film formed on copper foil by a CVD method to a substrate, providing an Au film appropriately on the transferred graphene film, and patterning the graphene film by photolithography, etching, UV-ozone treatment, etc. This makes it possible to produce an antenna element of a desired shape on the substrate. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2019-75626 A Summary of the Invention [Problem to be solved by the invention]

[0005] Incidentally, antennas used in mobile communication systems are used together with amplifiers that amplify signals transmitted and received by antenna elements. In the signal frequency band from several tens of GHz to 100 GHz or more, the transmission distance between the amplifier and the antenna element needs to be extremely short (for example, less than 100 μm). In addition, in anticipation of the next generation of mobile communication systems with a frequency band exceeding 1 THz, active devices that are different from gallium nitride (GaN) active devices and are suitable for use in the signal frequency band of 1 THz or more are required. When transitioning from the signal frequency band of several tens of GHz to 100 GHz or more to the signal frequency band of 1 THz or more, devices that cover both bands (for example, using multiple types of active devices in combination) are required.

[0006] The present invention has been made in view of the above, and has an object to provide an integrated circuit suitable for use in a signal frequency band of 1 THz or more, and a method for manufacturing the same. [Means for solving the problem]

[0007] The integrated circuit according to the embodiment of the present invention includes a substrate having at least a top surface made of single crystal silicon carbide (SiC), a vertical surface intersecting with the top surface and extending downward from the top surface, and a lower surface that is substantially parallel to the top surface and intersects with the vertical surface, and a single crystal graphene layer provided in contact with the top surface of the substrate, and is integrally formed with a short gate length transistor and an antenna element. The short gate length transistor includes an end of the graphene layer intersecting with the vertical surface as a gate electrode, an insulating film formed to cover at least the vertical surface and the end of the graphene layer, a two-dimensional semiconductor layer formed to cover the top surface, the vertical surface, and the lower surface, and is formed to cover the graphene layer and / or the insulating film at a location where the graphene layer and / or the insulating film are present, a source electrode provided at a location covering the top surface of the two-dimensional semiconductor layer, and a drain electrode provided at a location covering the lower surface of the two-dimensional semiconductor layer. The antenna element is formed by patterning the graphene layer.

[0008] In the present invention, in the graphene layer, the portion forming the gate electrode of the short gate length transistor and the portion forming the antenna element may be formed as a continuous graphene film.

[0009] In the present invention, the integrated circuit may further include a gallium nitride layer in an area on the substrate where the short gate length transistor and the antenna element are not provided, and active elements may be formed in the gallium nitride layer.

[0010] Another example of an integrated circuit according to an embodiment of the present invention is an integrated circuit including a substrate having at least a top surface made of single crystal silicon carbide, a vertical surface intersecting with the top surface and extending downward from the top surface, and a lower surface that is substantially parallel to the top surface and intersects with the vertical surface, a single crystal graphene layer provided in contact with the top surface of the substrate, and a gallium nitride layer provided on the substrate, and an active element portion formed on the gallium nitride layer and a short gate length transistor using the graphene layer as a gate are integrally formed. In the integrated circuit, the short gate length transistor includes an end portion where the graphene layer intersects with the vertical surface as a gate electrode, an insulating film formed to cover at least the vertical surface and the end portion of the graphene layer, a two-dimensional semiconductor layer formed to cover the top surface, the vertical surface, and the lower surface, and is formed to cover the graphene layer and / or the insulating film at the portion where the graphene layer and / or the insulating film are present, a source electrode provided at a portion covering the top surface of the two-dimensional semiconductor layer, and a drain electrode provided at a portion covering the lower surface of the two-dimensional semiconductor layer.

[0011] In the present invention, the short gate length transistor may further include a conductive shielding layer on the graphene layer forming the gate, and insulating layers may be provided on both sides of the shielding layer. Also, at least an end portion of the graphene layer may be a monolayer of graphene.

[0012] In the present invention, the substrate may have a slope that is non-parallel to the top surface at a position away from an edge where the top surface and the vertical surface meet, and the graphene layer may be formed from the top surface to the slope. The graphene layer on the slope may be a multi-layer graphene.

[0013] In the present invention, the substrate may be a hybrid substrate in which a single crystal layer of silicon carbide is formed on an insulating base substrate.

[0014] In the structure including the gallium nitride layer of the present invention, the gallium nitride layer may be provided so as to cover a part of the graphene layer. In this case, the gallium nitride layer may be a layer epitaxially grown using the graphene layer as a buffer layer. Also, the active element formed on the gallium nitride layer may include an amplifier using a HEMT (High Electron Mobility Transistor).

[0015] A method for manufacturing an integrated circuit according to an embodiment of the present invention is a method for manufacturing an integrated circuit in which a short gate length transistor and an antenna element are integrally formed. The method includes the steps of preparing a substrate having at least a top surface made of single crystal silicon carbide, forming a graphene layer on the top surface of the substrate, removing the graphene layer and the top of the substrate from other portions by microfabrication in a first region of the substrate in which the short gate length transistor is to be formed, while leaving the graphene layer in a portion, to form in the substrate a vertical surface that intersects with the top surface and extends downward from the top surface, and a lower surface that is approximately parallel to the top surface and intersects with the vertical surface, and depositing an insulating film so as to cover at least the vertical surface and an end portion of the graphene layer. depositing a two-dimensional semiconductor layer over the top surface, the vertical surface, and the lower surface, and also over the graphene layer and / or the insulating film where the graphene layer and / or the insulating film are present; forming a source electrode over the portion of the two-dimensional semiconductor layer covering the graphene layer, and forming a drain electrode over the portion of the two-dimensional semiconductor layer covering the lower surface; and patterning the graphene layer to form an antenna element in a second region of the substrate where the antenna element is to be formed.

[0016] The present invention may further include the steps of epitaxially growing a gallium nitride layer using the graphene layer as a buffer layer, removing the gallium nitride layer in the first region and the second region to expose the graphene layer, and forming an active element portion including an amplifier in the remaining gallium nitride layer.

[0017] Alternatively, the present invention may further include the steps of removing a portion of the graphene layer, epitaxially growing a gallium nitride layer in the area from which the graphene layer has been removed, and forming an active element portion including an amplifier in the gallium nitride layer, in which case the first region and the second region may be provided in the area where the graphene layer remains.

[0018] Another example of a method for manufacturing an integrated circuit according to an embodiment of the present invention includes the steps of: preparing a substrate having at least a top surface made of single crystal silicon carbide; forming a graphene layer on the top surface of the substrate; epitaxially growing a gallium nitride layer using the graphene layer as a buffer layer; removing the gallium nitride layer to expose the graphene layer in a first region of the substrate where a short gate length transistor is to be formed; and removing the graphene layer and an upper portion of the substrate by microfabrication while leaving the graphene layer in a portion, to form a substrate having a vertical plane intersecting with the top surface and extending downward from the top surface, and a vertical plane approximately parallel to the top surface and intersecting with the vertical plane. The method includes the steps of forming a lower surface, a vertical surface, and a lower surface; depositing an insulating film so as to cover at least the vertical surfaces and ends of the graphene layer; depositing a two-dimensional semiconductor layer so as to cover the top surface, the vertical surface, and the lower surface and also to cover the graphene layer and / or the insulating film in places where the graphene layer and / or the insulating film are present; forming a source electrode so as to overlap the place covering the graphene layer in the two-dimensional semiconductor layer and forming a drain electrode so as to overlap the place covering the lower surface in the two-dimensional semiconductor layer; and forming an active element portion including an amplifier in the remaining gallium nitride layer.

[0019] Yet another example of a method for manufacturing an integrated circuit according to an embodiment of the present invention includes the steps of: preparing a substrate having at least a top surface made of single crystal silicon carbide; forming a graphene layer on the top surface of the substrate; removing a portion of the graphene layer; epitaxially growing a gallium nitride layer in the region from which the graphene layer has been removed; forming an active element portion including an amplifier on the gallium nitride layer; and removing the graphene layer and an upper portion of the substrate from other portions by microfabrication in the region where the graphene layer remains, thereby forming a layer on the substrate that intersects with the top surface and is below the top surface. the steps of forming a vertical surface extending in a direction perpendicular to the top surface and a lower surface that is approximately parallel to the vertical surface and intersects with the vertical surface; depositing an insulating film so as to cover at least the vertical surface and an end portion of the graphene layer; depositing a two-dimensional semiconductor layer so as to cover the top surface, the vertical surface, and the lower surface and also to cover the graphene layer and / or the insulating film in places where the graphene layer and / or the insulating film are present; and forming a source electrode so as to overlap the place covering the graphene layer in the two-dimensional semiconductor layer, and forming a drain electrode so as to overlap the place covering the lower surface in the two-dimensional semiconductor layer.

[0020] The manufacturing method according to any of the above examples may include a step of providing a gallium nitride layer by bonding a gallium nitride device, in which an active element portion including an amplifier is formed, to a graphene layer on a substrate.

[0021] In the present invention, in the step of forming the antenna element, an electrode pad and a connection portion connecting the antenna element and the electrode pad may be formed together with the antenna element, and in the step of providing the gallium nitride layer, the gallium nitride device may be bonded to the graphene layer on the substrate so that the electrode provided on the gallium nitride device is electrically connected to the electrode pad.

[0022] In the present invention, in the step of forming the graphene layer, the graphene layer may be epitaxially grown by sublimating silicon atoms in the single crystal of silicon carbide on the uppermost surface of the substrate.

[0023] In the present invention, the substrate may be a hybrid substrate in which a single crystal layer of silicon carbide is formed on an insulating base substrate. Effect of the Invention

[0024] According to the integrated circuit and the manufacturing method thereof of the present invention, it is possible to realize an integrated circuit suitable for use in a signal frequency band of 1 THz or more. [Brief description of the drawings]

[0025] [Figure 1] 1 is a schematic diagram showing the structure of an integrated circuit 1. FIG. [Diagram 2] 4 is a cross-sectional view showing a basic structure of a short-gate length transistor formed in a first region R1. FIG. [Diagram 3] 11 is a cross-sectional view showing the structure of a modified example of a short gate length transistor. [Figure 4] 13 is a schematic diagram showing a structure in which a GaN layer is formed in a third region R3. FIG. [Diagram 5] 1A to 1C are diagrams illustrating a first example of a procedure for fabricating an integrated circuit 1. [Figure 6] 1A to 1C are diagrams illustrating a procedure for producing a short gate length transistor. [Figure 7] 11 is a diagram showing a second example of a procedure for fabricating the integrated circuit 1. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] Hereinafter, an embodiment of the present invention will be described. The same reference numerals are used to denote common components in the drawings, including those used to describe the background art.

[0027] FIG. 1 is a schematic diagram showing the structure of an integrated circuit 1 according to an embodiment of the present invention. As shown in FIG. 1, the integrated circuit 1 has a structure in which a first region R1, a second region R2, and a third region R3 are provided on a substrate 2. The first region R1 is a region in which a short gate length transistor 100 is formed. The second region R2 is a region in which an antenna element 200 is formed. The third region R3 is a region in which a gallium nitride device 310 is formed. Thus, the integrated circuit 1 has the short gate length transistor 100, the antenna element 200, and the GaN device 310 formed on one substrate. The short gate length transistor 100, the antenna element 200, and the GaN device 310 on the substrate 2 are connected to each other as necessary to achieve the required functions.

[0028] At least the top surface 21 of the substrate 2 is made of single-crystal silicon carbide. The top surface 21 is the uppermost flat surface of the substrate 2. The portion of the substrate 2 other than the top surface may be an insulator other than silicon carbide. In other words, the substrate 2 may be a single-crystal substrate of silicon carbide, or may be a hybrid substrate in which a single-crystal layer of silicon carbide is fabricated on an insulator. The surface of the single-crystal layer of silicon carbide in the substrate 2 may be the (0001) plane. The substrate 2 serves as a base for epitaxially growing graphene constituting the graphene layer 3. The graphene layer 3 is a thin film of graphene of a single atomic layer or several atomic layers formed in contact with the top surface 21 of the substrate 2. The graphene constituting the graphene layer 3 can be formed into a single-layer thin film on the (0001) plane of silicon carbide, which is suitable as the substrate 2.

[0029] Hereinafter, configuration examples and modifications of the first region R1, the second region R2, and the third region R3 on the substrate 2 will be described.

[0030] FIG. 2 is a cross-sectional view showing a basic structure of a short gate length transistor 100 formed in the first region R1. As shown in FIG. 2, the short gate length transistor 100 includes a graphene layer 3, a shielding layer 4, an insulating layer 5, an insulating film 6, a two-dimensional semiconductor layer 7, an electrode 8, and an electrode 9 on a substrate 2. In the basic structure of the short gate length transistor 100, a vertical surface 22 and a lower surface 23 are formed on the substrate 2 by digging down from a top surface 21. The vertical surface 22 is a plane that intersects with the top surface 21 and extends downward from the top surface 21. In the example of FIG. 2, the vertical surface 22 and the top surface 21 are perpendicular to each other. The lower surface 23 is formed as a plane that is approximately parallel to the top surface 21 and intersects with the vertical surface 22. In the example of FIG. 2, the lower surface 23 and the vertical surface 22 are perpendicular to each other, and the top surface 21 and the lower surface 23 are parallel to each other. The vertical surface 22 is formed as a plane intersecting the top surface 21 and the lower surface 23 .

[0031] In the short gate length transistor 100 formed in the first region R1, the thickness of the graphene layer 3 is set to about several nm or less. The width from one end to the other end of the graphene layer 3 (horizontal direction in FIG. 2) may be about 100 nm to 1 μm. The graphene layer 3 is provided so as to cover the top surface 21 up to the vicinity of the ridge line where the top surface 21 and the vertical surface 22 of the substrate 2 intersect. An end (edge) 31 of the graphene layer 3 overlapping the vicinity of the ridge line where the top surface 21 and the vertical surface 22 intersect functions as a gate in the short gate length transistor 100. The portion of the graphene layer 3 other than the edge 31 functions as wiring to the gate described later.

[0032] In the short gate length transistor 100 formed in the first region R1, the shielding layer 4 is a layer of a conductor such as a metal provided on the graphene layer 3, and shields between the electrode 8 and the graphene layer 3. The shielding layer 4 is electrically connected to a predetermined ground potential (for example, 0 V). At least the front and back surfaces of the shielding layer 4 are provided with an insulating layer 5 to prevent the shielding layer 4 from shorting with the graphene layer 3 or the electrode 8. The shielding layer 4 is preferably made of aluminum (Al) or nickel (Ni). When Al is used as the shielding layer 4, a natural oxide film formed on the surface of Al can be used as the insulating layer 5 as it is, and the manufacturing process can be simplified. When Ni is used as the shielding layer 4, it is necessary to form a separate insulating layer 5 to prevent a short circuit with the graphene layer 3 or the electrode 8. Note that when it is not necessary to shield between the electrode 8 and the graphene layer 3 (for example, when signal interference between the electrode 8 and the graphene layer 3 is not a problem), the shielding layer 4 and the insulating layer 5 may not be provided. The end face 51 of the insulating layer 5 should be a flat surface that is substantially aligned with the vertical face 22 .

[0033] The insulating film 6 is a thin film of an insulator that functions as a gate insulating film of the short gate length transistor 100. As the insulating film 6, a high dielectric constant insulating film such as hafnium oxide, silicon carbide, zirconium oxide, erbium oxide, aluminum oxide, etc., a thin film of silicon carbide, etc. can be used. For high frequency applications exceeding 1 THz, a thin film of silicon carbide is suitable. In the example shown in FIG. 2, the insulating film 6 is formed so as to cover from the upper surface of the insulating layer 5 through the end surface 51, the edge 31, the vertical surface 22, and the lower surface 23. Note that, as long as the insulating film 6 covers at least the vertical surface 22, the edge 31, and the end surface 51 of the substrate 2, there are cases where it is not necessary to form the insulating film 6 on other parts. For example, in a configuration including the insulating layer 5 and the shielding layer 4, the insulating film 6 does not need to be provided on the insulating layer 5. On the other hand, in a configuration not including the insulating layer 5 and the shielding layer 4, it is necessary to provide the insulating film 6 also between the graphene layer 3 and the electrode 8 to prevent a short circuit between the graphene layer 3 and the electrode 8. Furthermore, if the substrate 2 has sufficient insulating properties, the insulating film 6 does not need to be provided on the lower surface .

[0034] The two-dimensional semiconductor layer 7 is a semiconductor layer that functions as a carrier transport layer of the short gate length transistor 100. The two-dimensional semiconductor layer 7 is formed so as to cover the top surface 21, the vertical surface 22, and the lower surface 23. In the places where the graphene layer 3, the shielding layer 4, the insulating layer 5, and / or the insulating film 6 are present, the two-dimensional semiconductor layer 7 is formed so as to cover them as well. For the two-dimensional semiconductor layer 7, graphene, transition metal dichalcogenides (e.g., molybdenum disulfide (MoS2), tungsten disulfide (WS2), tungsten diselenide (WSe2), etc.), indium oxide (In2O3), boron phosphide, boron arsenide, etc., each having a monoatomic layer or a few atomic layers can be used. For high frequency applications exceeding 1 THz, graphene is suitable as the two-dimensional semiconductor layer 7. For high frequency applications of about 300 GHz to 1 THz, transition metal dichalcogenides such as MoS2 and WS2 are suitable for the two-dimensional semiconductor layer 7. For relatively low frequency applications such as logic circuits, In2O3 and transition metal dichalcogenides are suitable for the two-dimensional semiconductor layer 7.

[0035] The electrode 8 and the electrode 9 are electrodes made of metals such as Au, Al, In, Bi, Ni, Pd, Ti, and Pt, or transparent conductive oxides such as ITO and FTO. The electrode 8 is provided overlapping a portion of the two-dimensional semiconductor layer 7 that covers the graphene layer 3, and functions as a source electrode of the short gate length transistor 100. The electrode 9 is provided overlapping a portion of the two-dimensional semiconductor layer 7 that covers the lower surface 23, and functions as a drain electrode of the short gate length transistor 100.

[0036] In the short gate length transistor 100 having the basic structure described above, the formation surface of the graphene layer 3 and the formation surface of the two-dimensional semiconductor layer 7 covering the vertical surface 22 are perpendicular to each other, and an edge 31 of the graphene layer 3 faces the two-dimensional semiconductor layer 7 via the insulating film 6, so that the thickness of the graphene layer 3 defines the gate length of the transistor 1. If the graphene layer 3 is a monoatomic layer of graphene, the gate length of the short gate length transistor 100 can be shortened to 0.3 nm. Even if the graphene layer 3 is a multilayer film of graphene, a gate length of several nm or less corresponding to the thickness of the graphene layer 3 can be realized.

[0037] The short gate length transistor formed in the first region R1 may have a structure shown in FIG. 3 in order to suppress the gate resistance while realizing a gate length of a monoatomic layer. FIG. 3 is a cross-sectional view showing the structure of a short gate length transistor 100a according to a modified example. The short gate length transistor 100a includes a graphene layer 3, a shielding layer 4, an insulating layer 5, an insulating film 6, a two-dimensional semiconductor layer 7, an electrode 8, and an electrode 9 in the first region R1 of the substrate 2, similar to the above-mentioned short gate length transistor 100. The first region R1 of the substrate 2 has a slope 24 in addition to a top surface 21, a vertical surface 22, and a lower surface 23. In the substrate 2, at least the top surface 21 and the slope 24 are made of single crystal silicon carbide. The slope 24 is a surface that is non-parallel (inclined) to the top surface 21 and is provided adjacent to the top surface 21 at an end opposite to the edge of the top surface 21 that contacts the vertical surface 22. The inclination angle of the inclined surface 24 is arbitrary, and may be, for example, 45°, 22°, etc. The inclination angle of the inclined surface 24 does not need to be constant, and may be, for example, a curved surface. Such inclined surface 24 is provided prior to the formation of the graphene layer 3. In the short gate length transistor 100a, the graphene layer 3 is simultaneously formed from the top surface 21 to the inclined surface 24. Since the growth rate of graphene on the inclined surface 24 is faster than the growth rate of graphene on the top surface 21, which is the (0001) plane of silicon carbide, multiple layers of graphene (preferably about 10 to 20 layers) grow on the inclined surface 24 while a single layer of graphene is grown on the top surface 21. Therefore, the graphene layer 3 in the short gate length transistor 100a is formed from the top surface 21 to the slope 24, and has a structure in which the vicinity of the edge 31 is a single-layer graphene 32 and the inner slope 24 is switched to a multi-layer graphene 33. The distance from the ridge where the top surface 21 and the vertical surface 22 of the substrate 2 intersect to the slope 24 (i.e., the length of the top surface 21) is preferably a distance sufficient to prevent the formation of the multi-layer graphene from extending to the vicinity of the edge 31 (for example, about several hundreds of nm).

[0038] The short gate length transistor 100a is configured by providing the above-described graphene layer 3 with a shielding layer 4, an insulating layer 5, an insulating film 6, a two-dimensional semiconductor layer 7, an electrode 8, and an electrode 9, which are similar to those of the short gate length transistor 100. Note that, due to the inclination of the slope 24 serving as the base, a depression is formed in the graphene layer 3 at the portion of the slope 24, but it is preferable to fill this depression with an insulating material or the like to form a flat surface before stacking the shielding layer 4, the insulating film 6, the two-dimensional semiconductor layer 7, and the like.

[0039] In the short gate length transistor 100a configured as described above, in addition to the same effects as those of the transistor 1 of the first embodiment, the multi-layering of the graphene layer 3 increases the carrier density, thereby reducing the resistance of the graphene layer 3 as a whole. Meanwhile, at the edge 31 of the graphene layer 3, the single layer of graphene faces the two-dimensional semiconductor layer 7 via the insulating film 6 and functions as a gate electrode, so that the gate length of the transistor 1 can be set to one atom (approximately 0.3 nm).

[0040] In the second region R2, the graphene layer 3 is patterned into a desired shape as shown in FIG. 1 to form the antenna element 200 and the connection portion 210. The antenna element 200 has a structure in which the graphene layer 3 is patterned into a shape for realizing desired antenna characteristics. A metal film such as Au or a protective film such as an insulator may be provided to be superimposed on a part or all of the patterned graphene. Compared with metals such as copper (Cu) and ITO, graphene has various properties such as electrical conductivity, carrier mobility, and thermal conductivity, so that it is possible to realize antenna characteristics superior to those of Cu, and characteristic deterioration can be suppressed even if the size of the antenna is reduced. The graphene layer 3 forming the antenna element 200 in the second region R2 and the graphene layer 3 forming the gate of the short gate length transistor 100 in the first region R1 are preferably formed as a continuous graphene film. That is, the gate of the short gate length transistor 100 and the antenna element 200 are preferably electrically connected to each other using the graphene layer 3 as wiring. In this way, the length of the wiring connecting the gate of the short gate length transistor 100 and the antenna element 200 can be made extremely short.

[0041] The connection part 210 is a wiring that connects the electrode 312 of the amplifier of the GaN device 310 described later and the antenna element 200. The connection part 210 may not be provided with the GaN layer 300 described later, or the GaN layer 300 may be provided over a part or the whole of the connection part 210. The connection part 210 may be formed by patterning the graphene layer 3, or may be formed of a metal film such as Au. In addition, the connection part 210 may be partially formed of a metal film and the other part may be formed of graphene, or may have a part in which a metal film is provided overlaid on graphene. If the antenna element 200 and the connection part 210 are formed only of graphene, a transparent wiring can be realized. It is preferable that the connection part 210 is formed as short as possible (for example, so that the transmission distance is preferably less than 100 μm, more preferably less than 30 μm, and even more preferably less than 10 μm) so that the signal transmitted between the GaN device 310 and the antenna element 200 is not deteriorated.

[0042] In the third region R3, a gallium nitride layer 300 is laminated on the substrate 2. As an example, the gallium nitride layer 300 is provided overlapping the graphene layer 3 as shown in FIG. 4(a). In this structure, the graphene layer 3 functions as a buffer layer for relieving stress between the substrate 2 and the GaN layer 300. As another example, as shown in FIG. 4(b), the gallium nitride layer 300 may be provided directly on the substrate 2 without the graphene layer 3. In the gallium nitride layer 300, a gallium nitride device 310, which is an active element such as an amplifier, is formed using an element capable of high-speed operation such as a HEMT (High Electron Mobility Transistor). Although not shown in FIG. 4, a metal film (e.g., an Au film) for forming an electrode or wiring pattern, a protective film, etc. may be provided overlapping the graphene layer 3 or the gallium nitride layer 300 as necessary.

[0043] The gallium nitride device 310 may include other active elements in addition to the above-mentioned amplifier. The gallium nitride device 310 may include an electrode 312 to which wiring from the outside (e.g., the antenna element 200 or the connection part 210) is connected. The electrode 312 may be provided on the surface of the gallium nitride layer 300 facing the substrate 2, or on the surface opposite to the surface facing the substrate 2.

[0044] When the electrode 312 is provided on the surface of the gallium nitride layer 300 facing the substrate 2, the electrode 312 and an electrode pad 314 provided at one end of the connection portion 210 may be connected directly or indirectly via a conductor, as shown in Fig. 4(c). When the electrode 312 is provided on the surface of the gallium nitride layer 300 opposite to the surface facing the substrate 2, the electrode 312 and the connection portion 210 may be connected by wire bonding 316, as shown in Fig. 4(a) or 4(b). Alternatively, as shown in Fig. 4(d), a conductor layer 318 such as metal or graphene may be added to connect the electrode 312 and the connection portion 210.

[0045] As a modification of the third region, instead of epitaxially growing the gallium nitride layer 300 on the substrate 2, a gallium nitride device 310 may be separately prepared, and the gallium nitride layer 300 may be provided by bonding the gallium nitride device 310 to the third region R3 of the substrate 2 on which the graphene layer 3 is provided. The structure shown in Fig. 5(c) corresponds to the configuration of this modification.

[0046] The integrated circuit 1 realizes a desired function by arranging on the substrate 2 the above-mentioned first region R1, second region R2, and third region R3, as well as other necessary circuit elements, in any combination.

[0047] Next, a description will be given of a method for manufacturing the integrated circuit 1. Fig. 5 is a diagram showing a first example of a procedure for manufacturing the integrated circuit 1.

[0048] As shown in Fig. 5, first, a substrate 2 is prepared (Fig. 5(a)). As described above, at least the uppermost surface of the substrate 2 is made of single crystal silicon carbide. The crystal structure of the silicon carbide on the uppermost surface is preferably any one of 4H-SiC, 6H-SiC, and 3C-SiC.

[0049] When using a hybrid substrate in which a single crystal layer of silicon carbide is fabricated on an insulator, rather than a single crystal substrate of silicon carbide, as the substrate 2, one of single crystal silicon, sapphire, polycrystalline silicon, alumina, silicon nitride, aluminum nitride, diamond, and polycrystalline silicon carbide is used as a base substrate, on which a film of silicon oxide, single crystal silicon, polycrystalline silicon, amorphous silicon, alumina, silicon nitride, silicon carbide, aluminum nitride, or diamond is provided as necessary, and the bonding surfaces of the base substrate and the silicon carbide substrate are subjected to a surface treatment and bonded together. Then, a hybrid substrate in which the single crystal layer of silicon carbide is thinned may be fabricated by an ion implantation peeling method in which hydrogen ions, helium ions, or the like are implanted into the silicon carbide substrate before thinning by grinding and polishing or peeling, and peeling is performed at the ion implantation interface by heat treatment after bonding. In addition, after fabricating the hybrid substrate, the surface may be CVD-treated with polycrystalline silicon carbide, and then the base substrate may be removed to obtain a hybrid substrate in which a single crystal layer of silicon carbide is fabricated on an insulator.

[0050] Although not shown, when the short gate length transistor 100a is formed in the first region R1, the slope 24 is formed in the location where the short gate length transistor 100a is to be formed.

[0051] Next, the substrate 2 is heated to preferably 1,100° C. or higher to sublimate silicon atoms (Si) near the top surface 21 (and the inclined surface 24) of the substrate 2, thereby forming a graphene film of a desired thickness (for example, about 50 to 1,500 nm) as the graphene layer 3 (FIG. 5(b)). An example of typical graphene growth conditions is 1000 nm under an argon (Ar) atmosphere. 5It is recommended to heat the silicon substrate at 1500 to 1600°C and 1 bar for 5 to 30 minutes. When the silicon is sublimated, a nanocarbon film of either fullerene, graphene, or carbon nanotube is formed, and the preparation conditions are appropriately adjusted so that graphene is obtained. The graphene layer 3 thus formed grows epitaxially so that the crystals are oriented in a predetermined direction with respect to the crystal plane of the silicon carbide single crystal on the top surface of the substrate 2, which serves as the base.

[0052] Next, gallium nitride is epitaxially grown using the graphene layer 3 as a buffer layer (i.e., a nucleation layer (template layer) of gallium nitride epicrystal) to form a gallium nitride layer 300 (FIG. 5(c)). Gallium nitride may be epitaxially grown, for example, by metalorganic chemical vapor deposition (MOCVD). Specifically, trimethylgallium (TMGa), trimethylaluminum (TMAl), and ammonia (NH3) may be used as precursors of Ga, Al, and N, respectively, and H2 and N2 may be used as carrier gases. Prior to film formation, the substrate 2 on which the graphene layer 3 is provided may be thermally cleaned in an H2 atmosphere at 1100°C for about 5 minutes. An AlN buffer layer may be grown to a thickness of about several tens to several hundreds of nm on the surface of the substrate after cleaning, and then an undoped gallium nitride layer 300 may be grown to a thickness of about 2 μm at 1050°C. The AlN buffer layer may be grown such that a high-temperature AlN buffer layer grown at about 1080° C. is stacked on top of a low-temperature AlN buffer layer grown at about 780° C. In the above example, the graphene layer 3 is used as a nucleation layer (template layer) for the gallium nitride epitaxial crystal, but before the growth of the gallium nitride epitaxial crystal, the graphene layer 3 may be removed from the portion where the gallium nitride is to be grown (i.e., the portion where the active element portion is to be provided), and gallium nitride may be grown directly on the silicon carbide single crystal on the uppermost surface 21 of the substrate 2.

[0053] Then, active elements such as HEMT, passive elements such as resistors, capacitors, and inductors, wiring, electrodes, etc. are formed on the formed gallium nitride layer 300 to form a gallium nitride device 310 including an amplifier, etc. (FIG. 5(d)).

[0054] Next, the gallium nitride layer 300 is removed by etching from the portions other than the gallium nitride device 310, and the graphene layer 3 in the regions that will become the first region R1 and the second region R2 is exposed (FIG. 5(e)). Furthermore, the antenna element 200 and the connection portion 210 are patterned on the graphene layer 3 (FIG. 5(f)). Note that when patterning the graphene layer 3, the graphene layer 3 is left in the region that will become the first region R1. This patterning may be performed, for example, by vapor-depositing an Au film on the graphene layer 3, patterning the Au film by photolithography and etching, removing the exposed graphene that is not covered with the Au film by UV-ozone treatment or the like, and further removing unnecessary portions of the Au film.

[0055] Next, the short gate length transistor 100 or 100a is formed in the region that will become the first region R1 (FIG. 5(g)). Detailed procedures for forming the short gate length transistor 100 are shown in FIG. 6. That is, the shielding layer 4 of Al is formed in the region that will become the first region R1 where the graphene layer 3 is exposed. In the process of forming the shielding layer 4, an insulating layer 5 of a natural oxide film is formed on the shielding layer 4 so as to cover its surface (FIG. 6(a)). When a material other than Al that does not form a natural oxide film is used as the shielding layer 4, it is preferable to form insulating layers above and below the shielding layer 4 to ensure insulation between the shielding layer 4 and the graphene 3 or the electrode 8. Next, by performing microfabrication by reactive ion etching or neutral particle beam etching using a chlorine-based gas or a fluorine-based gas, a part of the first region R1 of the substrate 2 is dug down to form a vertical surface 22 and a lower surface 23 on the substrate 2, and the shielding layer 4 is processed to match the vertical surface 22 (FIG. 6(b)). In the process of microfabrication, the side surface of the shielding layer 4 is exposed, and the insulating layer 5 of a natural oxide film is formed again to cover the exposed surface. The graphene layer 3 is not present on the vertical surface 22 or the lower surface 23 formed by microfabrication, but a single layer of the graphene layer 3 remains on the remaining top surface 21. Next, the insulating film 6 is deposited (FIG. 6(c)). In FIG. 6(c), the insulating film 6 is formed so as to cover the upper surface of the insulating layer 5, the end surface 51, the edge 31, the vertical surface 22, and the lower surface 23. Note that, as long as the insulating film 6 covers at least the vertical surface 22, the edge 31, and the end surface 51 of the substrate 2, it may not be necessary to form the insulating film 6 on other parts. Next, the two-dimensional semiconductor layer 7 is deposited so as to cover the top surface 21, the vertical surface 22, and the lower surface 23 (FIG. 6(d)). At this time, the two-dimensional semiconductor layer 7 is formed so as to cover the graphene layer 3, the shielding layer 4, the insulating layer 5, and / or the insulating film 6 at locations where they are present. Then, an electrode 8 is formed so as to cover the portion of the two-dimensional semiconductor layer 7 that covers the graphene layer 3, and an electrode 9 is formed so as to cover the portion of the two-dimensional semiconductor layer 7 that covers the lower surface 23 (FIG. 6(e)). With the above steps, the structure of the short gate length transistor 100 is completed.

[0056] Returning to Figure 5, finally, the integrated circuit 1 is obtained by forming mutual connections between the first region R1, the second region R2, and the third region R3 (for example, a connection between the electrode 312 of the gallium nitride device 310 and the connection portion 210) and electrode pads for connection to the outside (for example, pads for connecting to the source electrode, drain electrode, and gate electrode of the short gate length transistor 100) (Figure 5 (h)).

[0057] By the above-mentioned procedure, it is possible to manufacture a monolithic integrated circuit 1 in which a short gate length transistor, an antenna element, and a gallium nitride device are provided on a substrate 2. The order of the formation of the short gate length transistor, the antenna element, and the gallium nitride device may be reversed, or some or all of the steps may be performed simultaneously.

[0058] In the integrated circuit 1 fabricated as described above, the antenna element 200 and the short gate length transistor 100 are provided in close proximity to each other and connected by a continuous graphene layer 3, so that signal degradation can be suppressed even in a signal frequency band of 1 THz or more.

[0059] Furthermore, in the integrated circuit 1 manufactured by the above procedure, in addition to the short gate length transistor 100, the gallium nitride device 310 can also be formed on the same substrate, making it possible to cover a wide range of signal frequency bands from several tens of GHz to over 100 GHz, up to over 1 THz.

[0060] 7 is a diagram showing a second example of a procedure for fabricating an integrated circuit 1. This procedure differs from the first example in that the gallium nitride layer 300 is not epitaxially grown, but a gallium nitride device 310 is separately prepared, and the gallium nitride layer is provided by bonding the gallium nitride device 310 to a substrate 2 provided with a graphene layer 3.

[0061] In a second example of a procedure for fabricating an integrated circuit, first, a substrate 2 is prepared (FIG. 7(a)), and if necessary, an inclined surface 24 is formed, and a graphene layer 3 is formed (FIG. 7(b)) by a method similar to that described with reference to FIGS. 5(a) and 5(b).

[0062] Next, the antenna element 200 and the connection portion 210 are patterned on the graphene layer 3 (FIG. 7(c)). In addition, when the gallium nitride device 310 is attached in a later stage, the electrode pad 314 connected to the electrode 312 of the integrated circuit is also patterned in a form extending from the connection portion 210. When the graphene layer 3 is patterned, the graphene layer 3 is left in the region that becomes the first region R1. In addition, a pattern of the graphene layer 3 (or the Au film provided thereon) required for bonding with the gallium nitride device 310 may be formed. In other words, the graphene layer 3 may function as an adhesive layer for attaching the gallium nitride device 310 to the substrate 2. For example, these patternings may be performed in the following procedure: an Au film is vapor-deposited on the graphene layer 3, and then the Au film is patterned by photolithography and etching techniques, the exposed graphene not covered with the Au film is removed by UV-ozone treatment or the like, and the unnecessary portion of the Au film is further removed. In this manner, the antenna element 200 can be monolithically formed on the substrate 2. The pattern used for bonding to the gallium nitride device 310 may be formed only of a metal thin film such as Au after removing the graphene layer 3. The pattern used for bonding to the gallium nitride device 310 may be made of graphene, a metal thin film, or a laminate of these. The pattern used for bonding to the gallium nitride device 310 may also function to ensure electrical connection between the elements in the gallium nitride device 310 and the outside, similar to the electrode pad 314 connected to the electrode 312.

[0063] Next, the short gate length transistor 100 or 100a is formed in the first region R1 by the same method as that described with reference to FIG. 7 (FIG. 7(d)).

[0064] Next, a gallium nitride device 310 prepared separately is bonded to an appropriate position in the third region R3 of the substrate 2 (FIG. 7(e)). The gallium nitride device 310 is formed by forming active elements such as an amplifier on a gallium nitride substrate and cutting it into a predetermined size. An electrode 312 for transmitting and receiving signals is provided on the surface of the gallium nitride device 310 (the surface bonded to the substrate 2). When the gallium nitride device 310 and the substrate 2 are bonded to each other, the electrode 312 of the gallium nitride device 310 and the electrode pad 314 on the substrate 2 are electrically connected. The bonding of the gallium nitride device 310 and the substrate 2 may be performed after performing an activation process or a surface treatment on the surfaces of both. The gallium nitride device 310 can also be bonded to the substrate 2 by flip-chip bonding. The gallium nitride device 310 bonded to the substrate 2 becomes the gallium nitride layer 300 in the integrated circuit 1.

[0065] By the above-mentioned procedure, a monolithic integrated circuit 1 having a short gate length transistor, an antenna element, and a gallium nitride device provided on a substrate 2 can be fabricated.

[0066] In the integrated circuit 1 fabricated as described above, the antenna element 200 and the short gate length transistor 100 are provided in close proximity to each other and connected by a continuous graphene layer 3, so that signal degradation can be suppressed even in a signal frequency band of 1 THz or more.

[0067] Furthermore, in the integrated circuit 1 manufactured by the above procedure, in addition to the short gate length transistor 100, the gallium nitride device 310 can also be formed on the same substrate, making it possible to cover a wide range of signal frequency bands from several tens of GHz to over 100 GHz, up to over 1 THz.

[0068] Furthermore, in the integrated circuit 1 fabricated by the above procedure, the gallium nitride device 310 can be prepared separately and then bonded to the substrate 2, allowing for high design freedom. Furthermore, by preparing multiple types of gallium nitride devices 310 with different functions and performance to be bonded, integrated circuits 1 with a wide variety of third regions R3 can be fabricated while sharing the first region R1 and second region R2.

[0069] The present invention is not limited to the above-mentioned embodiments and examples. Anything that has substantially the same configuration as the technical idea described in the claims of the present invention and exhibits similar effects is included in the technical scope of the present invention, regardless of any modifications. [Explanation of symbols]

[0070] 1 Integrated Circuits 2. Board 21 Top surface 22 Vertical plane 23 Lower Level 24 Slope 3 Graphene layers 31 Edge 4 Shielding layer 5. Insulation layer 51 End face 6. Insulating film 7 Two-dimensional semiconductor layer 8,9 electrode 100,100a short gate length transistor 200 Antenna Element 300 Gallium nitride layer 310 Gallium nitride devices 318 Conductor Layer R1 1st area R2 2nd area R3 3rd area

Claims

1. A substrate having at least a top surface that is a single crystal of silicon carbide, the substrate having a vertical surface that intersects with the top surface and extends downward from the top surface, and a lower surface that is substantially parallel to the top surface and intersects with the vertical surface; a single-crystal graphene layer provided in contact with a top surface of the substrate; Equipped with An integrated circuit having a short gate length transistor and an antenna element integrally formed therein, The short gate length transistor is an end portion of the graphene layer intersecting with the vertical surface serves as a gate electrode; an insulating film formed to cover at least the vertical surface and the end portion of the graphene layer; a two-dimensional semiconductor layer formed so as to cover the top surface, the vertical surface, and the lower surface, the two-dimensional semiconductor layer being formed so as to overlap the graphene layer and / or the insulating film in a portion where the graphene layer and / or the insulating film are present, so as to cover the graphene layer and / or the insulating film; A source electrode provided at a portion covering the top surface of the two-dimensional semiconductor layer; a drain electrode provided at a portion covering the lower surface of the two-dimensional semiconductor layer; The antenna element is formed by patterning the graphene layer. Integrated circuits.

2. 2. The integrated circuit according to claim 1, wherein in the graphene layer, a portion forming a gate electrode of the short gate length transistor and a portion forming the antenna element are formed as a continuous graphene film.

3. a gallium nitride layer is further provided on the substrate in a region where the short gate length transistor and the antenna element are not provided; 2. The integrated circuit of claim 1, wherein active elements are formed in the gallium nitride layer.

4. A substrate having at least a top surface that is a single crystal of silicon carbide, the substrate having a vertical surface that intersects with the top surface and extends downward from the top surface, and a lower surface that is substantially parallel to the top surface and intersects with the vertical surface; a single-crystal graphene layer provided in contact with a top surface of the substrate; a gallium nitride layer provided on the substrate; Equipped with An integrated circuit in which an active element portion formed on the gallium nitride layer and a short gate length transistor using the graphene layer as a gate are integrally formed, The short gate length transistor is an end portion of the graphene layer intersecting with the vertical surface serves as a gate electrode; an insulating film formed to cover at least the vertical surface and the end portion of the graphene layer; a two-dimensional semiconductor layer formed so as to cover the top surface, the vertical surface, and the lower surface, the two-dimensional semiconductor layer being formed so as to overlap the graphene layer and / or the insulating film in a portion where the graphene layer and / or the insulating film are present, so as to cover the graphene layer and / or the insulating film; A source electrode provided at a portion covering the top surface of the two-dimensional semiconductor layer; and a drain electrode provided at a portion covering the lower surface of the two-dimensional semiconductor layer.

5. The short gate length transistor is Further comprising a conductive shielding layer on the graphene layer forming the gate; An insulating layer is provided on both the front and back surfaces of the shielding layer.

5. An integrated circuit according to any one of claims 1 to 4.

6. 5. The integrated circuit according to claim 1, wherein at least the end portion of the graphene layer is made of monolayer graphene.

7. the substrate includes a slope that is non-parallel to the top surface and located away from an edge where the top surface and the vertical surface meet; the graphene layer is formed from the top surface to the slope; The graphene layer on the slope is a multi-layer graphene.

7. The integrated circuit of claim 6.

8. 5. The integrated circuit according to claim 1, wherein the substrate is a hybrid substrate in which a single crystal layer of silicon carbide is fabricated on an insulating base substrate.

9. The integrated circuit according to claim 3 or 4, wherein the gallium nitride layer is provided so as to cover a portion of the graphene layer.

10. The integrated circuit of claim 9 , wherein the gallium nitride layer is a layer epitaxially grown using the graphene layer as a buffer layer.

11. 5. The integrated circuit according to claim 3, wherein the active element formed on the gallium nitride layer includes an amplifier using a HEMT (High Electron Mobility Transistor).

12. 1. A method for manufacturing an integrated circuit having a short gate length transistor and an antenna element integrally formed therein, comprising the steps of: providing a substrate having at least a top surface that is single crystal silicon carbide; forming a graphene layer on a top surface of the substrate; In a first region of the substrate in which the short gate length transistor is to be formed, removing the graphene layer and an upper portion of the substrate from other portions while leaving the graphene layer in a portion by microfabrication to form, on the substrate, a vertical surface that intersects with the top surface and extends downward from the top surface, and a lower surface that is substantially parallel to the top surface and intersects with the vertical surface; depositing an insulating film to cover at least the vertical surfaces and edges of the graphene layer; depositing a two-dimensional semiconductor layer so as to cover the top surface, the vertical surface, and the lower surface, and also to cover the graphene layer and / or the insulating film where the graphene layer and / or the insulating film are present; forming a source electrode overlapping a portion of the two-dimensional semiconductor layer covering the graphene layer, and forming a drain electrode overlapping a portion of the two-dimensional semiconductor layer covering the lower surface; patterning the graphene layer to form an antenna element in a second region of the substrate where the antenna element is to be formed; A method for manufacturing an integrated circuit comprising:

13. epitaxially growing a gallium nitride layer using the graphene layer as a buffer layer; removing the gallium nitride layer to expose the graphene layer in the first region and the second region; forming an active element portion including an amplifier in the remaining gallium nitride layer; The method of claim 12 further comprising:

14. removing a portion of the graphene layer; epitaxially growing a gallium nitride layer in the area from which the graphene layer has been removed; forming an active element portion including an amplifier in the gallium nitride layer; Further equipped with The method of claim 12 , wherein the first region and the second region are provided in an area where the graphene layer remains.

15. 1. A method for manufacturing an integrated circuit having a short gate length transistor and an active element formed in a gallium nitride layer, comprising: providing a substrate having at least a top surface that is single crystal silicon carbide; forming a graphene layer on a top surface of the substrate; epitaxially growing a gallium nitride layer using the graphene layer as a buffer layer; In a first region of the substrate in which the short gate length transistor is to be formed, removing the gallium nitride layer to expose the graphene layer; removing the graphene layer and an upper portion of the substrate from other portions while leaving the graphene layer in a portion by microfabrication to form, on the substrate, a vertical surface that intersects with the top surface and extends downward from the top surface, and a lower surface that is substantially parallel to the top surface and intersects with the vertical surface; depositing an insulating film to cover at least the vertical surfaces and edges of the graphene layer; depositing a two-dimensional semiconductor layer so as to cover the top surface, the vertical surface, and the lower surface, and also to cover the graphene layer and / or the insulating film where the graphene layer and / or the insulating film are present; forming a source electrode overlapping a portion of the two-dimensional semiconductor layer covering the graphene layer, and forming a drain electrode overlapping a portion of the two-dimensional semiconductor layer covering the lower surface; forming an active element portion including an amplifier in the remaining gallium nitride layer; and, A method for manufacturing an integrated circuit comprising:

16. 1. A method for manufacturing an integrated circuit having a short gate length transistor and an active element formed in a gallium nitride layer, comprising: providing a substrate having at least a top surface that is single crystal silicon carbide; forming a graphene layer on a top surface of the substrate; removing a portion of the graphene layer; epitaxially growing a gallium nitride layer in the area from which the graphene layer has been removed; forming an active element portion including an amplifier in the gallium nitride layer; In the region where the graphene layer remains, removing the graphene layer and an upper portion of the substrate from other portions while leaving the graphene layer in a portion by microfabrication to form, on the substrate, a vertical surface that intersects with the top surface and extends downward from the top surface, and a lower surface that is substantially parallel to the top surface and intersects with the vertical surface; depositing an insulating film to cover at least the vertical surfaces and edges of the graphene layer; depositing a two-dimensional semiconductor layer so as to cover the top surface, the vertical surface, and the lower surface, and also to cover the graphene layer and / or the insulating film where the graphene layer and / or the insulating film are present; forming a source electrode overlapping a portion of the two-dimensional semiconductor layer covering the graphene layer, and forming a drain electrode overlapping a portion of the two-dimensional semiconductor layer covering the lower surface; A method for manufacturing an integrated circuit comprising:

17. A step of bonding a gallium nitride device having an active element portion including an amplifier to the graphene layer on the substrate to provide a gallium nitride layer; The method of claim 12 , further comprising:

18. In the step of forming the antenna element, an electrode pad and a connection portion that connects the antenna element and the electrode pad are formed together with the antenna element; 18. The method for manufacturing an integrated circuit according to claim 17, wherein in the step of providing a gallium nitride layer, the gallium nitride device is bonded to the graphene layer on the substrate so that an electrode provided on the gallium nitride device is electrically connected to the electrode pad.

19. 19. The method for manufacturing an integrated circuit according to claim 12, wherein in the step of forming the graphene layer, the graphene layer is epitaxially grown by sublimating silicon atoms in a single crystal of silicon carbide on the top surface of the substrate.

20. 19. The method for manufacturing an integrated circuit according to claim 12, wherein the substrate is a hybrid substrate in which a single crystal layer of silicon carbide is fabricated on an insulating base substrate.

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