Semiconductor device

Abstract

To propose a storage device capable of enhancing storage capacity per unit area while ensuring a data retention period.SOLUTION: A storage device includes: a storage element; a transistor including an oxide semiconductor in an active layer for controlling accumulation, retention, and release of charges in the storage element; and a capacitive element connected to the storage element. At least one of a pair of electrodes of the capacitive element has light-blocking properties. In addition, the storage device has a conduction film or an insulation film having light-blocking properties. The active layer is located between the electrode having light-blocking properties and the conduction film or the insulation film having light-blocking properties.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a memory device and a semiconductor device using the memory device. [Background technology]

[0002] In recent years, the high mobility achieved by polysilicon and microcrystalline silicon and the high mobility achieved by amorphous silicon have been Oxide semiconductors are being developed as new semiconductor materials that combine uniform device characteristics obtained by the use of Metal oxides, which are called conductors and exhibit semiconducting properties, are attracting attention. For example, indium oxide, a well-known metal oxide, is used in liquid It is used as a transparent electrode material in liquid crystal display devices. Examples of the oxides include tungsten oxide, tin oxide, indium oxide, and zinc oxide. Insulated-gate field-effect transistors using metal oxides with such semiconducting properties in the channel formation region Transistors (hereinafter simply referred to as transistors) are already known.

[0003] The above-described transistor including an oxide semiconductor emits light having a wavelength shorter than that of light, particularly visible light such as ultraviolet light. Light in the side region can cause degradation of characteristics such as a shift in threshold voltage and an increase in off-current. It is known that the transistors used in semiconductor devices have a characteristic that the change in the characteristics is small. It is desirable that the variation caused by the change in characteristics is small. As disclosed in Patent Document 1 or Patent Document 2, the deterioration of the transistor characteristics due to light can be prevented. Research and development is being conducted on technologies aimed at preventing this. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2010-021520 A [Patent Document 2] JP 2009-277701 A Summary of the Invention [Problem to be solved by the invention]

[0005] A transistor including the above oxide semiconductor in a channel formation region is used as a switching element. In the case of a semiconductor memory device (hereinafter simply referred to as a memory device) having the above-mentioned transistor threshold voltage The charge to be held in the memory element is shifted or the off-current is increased. This makes it easier for the memory device to release the charge and shortens the period during which data can be retained. In order to ensure that accurate data is retained for a longer period of time, It is important to prevent the degradation of the transistor characteristics.

[0006] In addition, the smaller the area occupied by each memory cell, the greater the memory capacity per unit area. However, as the area occupied by the memory cell becomes smaller, the capacity of the memory element The area required for the capacitance element provided in each memory cell to hold the charge must also be reduced. Therefore, the capacitance element is large enough to hold data for a long period of time in the storage device. It becomes difficult to secure a capacitance value of sufficient magnitude.

[0007] In view of the above-mentioned problems, the present invention provides a method for increasing the recording capacity per unit area while ensuring a data retention period. Another object of the present invention is to propose a storage device capable of increasing the storage capacity. One object of the present invention is to propose a semiconductor device using the above memory device. [Means for solving the problem]

[0008] A memory device according to one embodiment of the present invention includes a transistor functioning as a memory element, A transistor including an oxide semiconductor in the active layer for controlling the accumulation, retention, and release of electric charges in a semiconductor. The semiconductor memory device according to one embodiment of the present invention includes a transistor and a capacitor connected to the memory element. The memory device includes a capacitor that functions as a memory element, and a memory element that stores and holds electric charge. and a transistor including an oxide semiconductor in a channel formation region for retaining the charge and controlling emission. do.

[0009] At least one of the pair of electrodes of the capacitor element has a light-shielding property. In the memory device according to one embodiment of the present invention, a light-shielding layer such as a conductive film or an insulating film having a light-shielding property is formed. The active layer is located between an electrode having a light-shielding property and a light-shielding layer. It is a sign.

[0010] An active layer of a transistor functioning as a memory element may also contain an oxide semiconductor. .

[0011] Oxide semiconductors have a band gap three times larger than that of silicon, and therefore have a higher The intrinsic carrier density is low. The semiconductor material having the above-mentioned characteristics is used for the channel formation region. By including the above-described structure, a transistor having an extremely low off-state current can be realized. The transistor is used as a switching element to hold the charge stored in the memory element. By using this, leakage of electric charge from the memory element can be prevented.

[0012] Note that the oxide semiconductor can be obtained with the same degree of conductivity as that obtained with microcrystalline silicon or polycrystalline silicon. The semiconductor material combines high mobility with the uniform device characteristics obtained by amorphous silicon. It is a metal oxide that exhibits conductive properties. And water or hydrogen acts as an electron donor. The oxide semiconductor (purified oxide semiconductor) is highly purified by reducing impurities such as those mentioned above and has reduced oxygen vacancies. The i-type (intrinsic semiconductor) is an i-type semiconductor or is very close to the i-type. A transistor using a semiconductor material has a characteristic that the off-state current is extremely low. The oxide semiconductor with high purification and reduced oxygen vacancies was analyzed by secondary ion mass spectrometry (SIM Hydrogen concentration by Secondary Ion Mass Spectrometry The degree measurement is 5 x 10 19 / cm 3 Less than or equal to 5×10 18 / cm 3 More details below. Preferably 5 x 10 17 / cm 3 Less than 1×10, more preferably 16 / cm 3 The following The carrier density of the oxide semiconductor film, which can be measured by Hall effect measurement, is 1×10 14 / cm 3 Less than 1 x 10 12 / cm 3 less than 1×10 1 1 / cm 3 The band gap of the oxide semiconductor is preferably 2 eV or more. is 2.5 eV or more, more preferably 3 eV or more. By using an oxide semiconductor film in which oxygen vacancies are reduced, the oxide semiconductor film is highly purified by sufficiently reducing the amount of oxygen. As a result, the off-state current and leakage current of the transistor can be reduced.

[0013] Here, the analysis of the hydrogen concentration in the oxide semiconductor film will be described. The hydrogen concentration in the conductive film is measured by SIMS. However, it is known that it is difficult to obtain accurate data near the interface between layers of different materials. Therefore, when analyzing the distribution of hydrogen concentration in the thickness direction of a film by SIMS, The area where the target film exists, where there are no extreme fluctuations in the value and where an almost constant value is obtained. The average value in the region is adopted as the hydrogen concentration. When the hydrogen concentration in the film is not increased, a region where a nearly constant value is obtained due to the influence of the hydrogen concentration in the adjacent film was found. In this case, the maximum hydrogen concentration or The minimum value is adopted as the hydrogen concentration in the film. , if there is no mountain-shaped peak having a maximum value or a valley-shaped peak having a minimum value, the inflection point The value is adopted as the hydrogen concentration.

[0014] Specifically, a transistor using an oxide semiconductor film that is highly purified and has reduced oxygen vacancies as an active layer is The low off-state current of transistors can be demonstrated by various experiments. The width is 1×10 6 Even if the device has a channel length of 10 μm, the source and drain electrodes When the voltage between the electrodes (drain voltage) was in the range of 1 V to 10 V, the off-current (gate The drain current when the voltage between the gate and source electrodes is set to 0 V or less is calculated using a semiconductor parameter analyzer. Below the riser measurement limit, i.e. 1×10 -13 It is possible to obtain a characteristic of A or less. In this case, the off-current density, which is the value obtained by dividing the off-current by the channel width of the transistor, is In addition, the capacitance element and the transistor (gate insulator) are The insulating film is 100 nm thick, and the current flowing into and out of the capacitance element is measured. In an experiment using a circuit that controls a load with the transistor, When a purified oxide semiconductor film in which oxygen vacancies are reduced is used for a channel formation region, The off-current density of the transistor was measured from the change in the charge amount per unit time of the capacitance element. However, when the voltage between the source and drain electrodes of the transistor is 3V, the current is 10zA / It has been found that even lower off-current densities of up to 100 zA / μm can be obtained. Therefore, in the semiconductor device according to one embodiment of the present invention, the semiconductor device is highly purified and has reduced oxygen vacancies. The off-state current density of a transistor using an oxide semiconductor film as an active layer was measured by Depending on the voltage between the rain electrodes, the current may be 10 zA / μm or less, preferably 1 zA / μm or less, and more preferably 1 zA / μm or less. Therefore, the purity is high and the oxygen deficiency is small. A transistor using an oxide semiconductor film having a reduced thickness as an active layer has a low off-state current and a high crystallinity. This is significantly lower than that of a silicon-based transistor having a high pass filter.

[0015] The oxide semiconductor is an In-Sn-Ga-Zn-O oxide semiconductor, which is a quaternary metal oxide. Conductors, ternary metal oxides such as In-Ga-Zn-O oxide semiconductors, In-Sn-Z nO-based oxide semiconductor, In-Al-Zn-O-based oxide semiconductor, Sn-Ga-Zn-O-based Oxide semiconductors, Al-Ga-Zn-O oxide semiconductors, Sn-Al-Zn-O oxide semiconductors Conductors, binary metal oxides such as In-Zn-O oxide semiconductors and Sn-Zn-O oxides Semiconductors, Al-Zn-O oxide semiconductors, Zn-Mg-O oxide semiconductors, Sn-Mg -O-based oxide semiconductors, In-Mg-O-based oxide semiconductors, In-Ga-O-based oxide semiconductors, , In-O-based oxide semiconductors, Sn-O-based oxide semiconductors, Zn-O-based oxide semiconductors, etc. In the present specification, for example, an In-Sn-Ga-Zn-O system Oxide semiconductors are made of indium (In), tin (Sn), gallium (Ga), and zinc (Zn). The stoichiometric composition ratio is not particularly limited. The oxide semiconductor may contain silicon.

[0016] Alternatively, the oxide semiconductor may have the chemical formula InMO3(ZnO) m (m>0, m is a natural number. (but not limited to) where M is Zn, Ga, Al, Mn, or C. o represents one or more metal elements selected from the group consisting of Ga, Ga and Al, Examples include Ga and Mn, or Ga and Co. Effect of the Invention

[0017] In one embodiment of the present invention, a transistor including an oxide semiconductor in an active layer is used as an electric field in a memory element. By using it as a switching element to control the retention of charge, In addition, the active layer can be prevented from leaking by using light-shielding electrodes, conductive films, and insulating films. By sandwiching the transistor, it is possible to prevent the characteristics of the transistor from being deteriorated by light. Specifically, it is possible to suppress the shift of the threshold voltage and prevent the off-current from increasing. In one embodiment of the present invention, the light-blocking electrode is used as an electrode of a capacitor. In addition, since the capacitance element and the transistor are arranged in the memory cell so as to overlap each other, It is possible to reduce the area occupied by the memory cell while maintaining the area or capacitance of the memory cell. can.

[0018] Therefore, the storage device according to one aspect of the present invention can secure a period for storing data while Alternatively, the present invention provides a semiconductor memory device having a high memory capacity per unit area. By using the same in a semiconductor device, the reliability of the semiconductor device can be improved and the functionality of the device can be enhanced. [Brief description of the drawings]

[0019] [Figure 1] 1A and 1B are a circuit diagram and a cross-sectional view of a memory cell. [Diagram 2] FIG. 1 is a circuit diagram of a memory cell. [Diagram 3] FIG. [Figure 4] FIG. [Diagram 5] FIG. [Figure 6] FIG. [Figure 7] FIG. [Figure 8] 4 is a timing chart of the memory unit. [Figure 9] FIG. 1 is a block diagram of a storage device. [Figure 10] FIG. 1 is a block diagram of a storage device. [Figure 11] FIG. [Figure 12] Circuit diagram of the characteristic evaluation circuit. [Figure 13] 4 is a timing chart of a characteristic evaluation circuit. [Figure 14] 4 is a diagram showing the relationship between the elapsed time Time and the potential Vout of the output signal in the characteristic evaluation circuit. [Figure 15] FIG. 13 is a graph showing the relationship between the elapsed time Time in the characteristic evaluation circuit and the leakage current calculated by the measurement. [Figure 16] FIG. 13 is a graph showing the relationship between the potential of node A and the leakage current in the characteristic evaluation circuit. [Figure 17] Block diagram of an RF tag. [Figure 18] FIG. 2 is a diagram showing the configuration of a storage medium. [Figure 19] Electronic devices illustration. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and the embodiments and aspects of the present invention may be modified without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the details. However, the present invention should not be construed as being limited to the description of the following embodiment.

[0021] In addition, microprocessors, integrated circuits such as image processing circuits, RF tags, storage media, semiconductor Any and all semiconductor devices that can use memory devices, such as display devices, can be used in the present invention. In addition, the semiconductor display device includes liquid crystal display devices and organic light emitting diodes (OLEDs). Light-emitting devices with light-emitting elements such as l Micromirror Device), PDP (Plasma Display) Panel), FED (Field Emission Display), etc. The category includes semiconductor display devices that have circuit elements using a thin film in the pixel section or driver circuit. is included.

[0022] (Embodiment 1) FIG. 1A is a circuit diagram illustrating an example of a memory cell configuration of a memory device according to one embodiment of the present invention. In the circuit diagram shown in FIG. 1A, a memory cell 101 functions as a memory element. A transistor 102, a transistor 103 functioning as a switching element, and a capacitor The transistor 102 functioning as a memory element has a gate electrode and an active layer 104. Data is stored by accumulating charges in the gate capacitance formed between the gate electrodes.

[0023] The memory cell 101 may include a transistor, a diode, a resistor, a capacitor, or the like as required. It may further include other circuit elements such as inductances.

[0024] The source electrode and the drain electrode of the transistor are determined by the polarity and the potential of the transistor. The name is changed depending on the difference in potential between the electrodes. Generally, n-channel In a transistor with a low potential, the electrode to which a high potential is applied is called the source electrode. The electrode that is connected to the drain electrode is called the drain electrode. The electrode to which a low potential is applied is called the drain electrode, and the electrode to which a high potential is applied is called the source electrode. In the following, either the source electrode or the drain electrode is referred to as the first terminal, and the other is referred to as the second terminal. The memory cell 101 includes a transistor 102, a transistor 103, and a capacitor 10. The connection relationship of 4 is explained.

[0025] In the memory cell 101 shown in FIG. 1A, A potential of a signal including data is applied to a node corresponding to the first transistor 103. The second terminal is connected to the gate electrode of the transistor 102. One of the pair of electrodes is connected to the gate electrode of the transistor 102, and the other is connected to a predetermined potential. is connected to the given node.

[0026] FIG. 1B is a circuit diagram showing an example of a memory cell configuration different from that shown in FIG. In the circuit diagram shown in FIG. 1B, the memory cell 101 is a capacitor that functions as a memory element. The memory element includes a transistor 105 functioning as a switching element and a transistor 103 functioning as a switching element. Data is stored by accumulating charges in the capacitor 105 which functions as a charge storage element.

[0027] In the memory cell 101 shown in FIG. 1B, A potential of a signal including data is applied to the node. One of the pair of electrodes is connected to the second terminal of the transistor 103, and the other is applied with a predetermined potential. It is connected to a node that is being

[0028] In this specification, the term "connection" means electrical connection, and the term "connection" means a state in which a current, a voltage, or a potential is Therefore, the connected state corresponds to a direct connection. It does not necessarily refer to the state in which a current, voltage or potential is available or is transmitted through circuit elements such as wires, resistors, diodes, and transistors. This also includes situations where the connection is indirectly made via another means.

[0029] In addition, even if components that are independent on the circuit diagram are connected, For example, when a part of a wiring functions as an electrode, one conductive film is a In this specification, the term "connection" refers to such a single conductive film. However, cases where the functions of multiple components are combined are also included in this category.

[0030] In one embodiment of the present invention, the switching element shown in FIG. The channel forming region of the functioning transistor 103 is made of a material having a larger band gap than silicon semiconductor. The semiconductor has a wide band and is characterized by including an oxide semiconductor having a lower intrinsic carrier density than silicon. By including an oxide semiconductor having the above-described characteristics in a channel formation region, the off-current It is possible to realize a transistor 103 having an extremely low resistance. The data 103 is stored in a transistor 102 functioning as a memory element or a capacitor 105. By using it as a switching element to hold the accumulated charge, leakage of the charge can be prevented. It is possible to do so.

[0031] Unless otherwise specified, in this specification, the off-state current is In this case, the drain electrode is set at a higher potential than the source and gate electrodes. When the potential of the gate electrode is 0 or less with respect to the potential of the source electrode, The off-state current in this specification refers to the current that flows between the drain electrode and the p In a channel type transistor, the drain electrode is lower than the source electrode and the gate electrode. When the potential of the gate electrode is set to zero or less, the potential of the gate electrode is set to zero or less. This refers to the current that flows between the source and drain electrodes when the potential is above the threshold.

[0032] A semiconductor with a wider band gap than silicon semiconductors and a lower intrinsic carrier density than silicon. Examples of conductive materials include oxide semiconductors, silicon carbide (SiC), gallium nitride ( Compound semiconductors such as silicon carbide and gallium nitride are also included. Compound semiconductors must be single crystals, and to obtain single crystal materials, Crystal growth at temperatures significantly higher than the process temperature, or epitaxy on special substrates The manufacturing conditions are strict, and both require silicon wafers that are easily available. However, oxide semiconductors can be formed on a thin film of a thin film of a glass substrate, which has a low heat resistance. It can be produced by coating or wet methods (printing, etc.), and has the advantage of being suitable for mass production. In addition, since oxide semiconductors can be formed at room temperature, they can be formed on glass substrates or semiconductor substrates. It is possible to form films on integrated circuits using conductive elements, and it is also possible to accommodate larger substrates. Therefore, among the wide-gap semiconductors mentioned above, oxide semiconductors are particularly suitable for mass production. In addition, it has the advantage of improving the performance (e.g., field effect mobility) of the transistor. Even when trying to obtain a crystalline oxide semiconductor for the purpose of In this way, a crystalline oxide semiconductor can be obtained.

[0033] In FIG. 1A, the transistor 102 functioning as a memory element has an active layer Alternatively, an oxide semiconductor film may be used for the active layer of the transistor 102. Amorphous, microcrystalline, polycrystalline, or single-crystalline silicon or gel other than an oxide semiconductor All the transistors in the memory cell 101 may be made of a semiconductor such as tungsten. By using an oxide semiconductor film for the active layer of the capacitor, the process can be simplified. In addition, for example, polycrystalline or single crystal is used for the active layer of the transistor 102 functioning as a memory element. The use of semiconductor materials such as crystalline silicon that offer higher mobility than oxide semiconductors. This allows data to be read from the memory cell 101 at high speed.

[0034] In FIG. 1A or 1B, the transistor 103 has a gate electrode on one side of the active layer. The figure shows a case where the active layer is sandwiched between the transistor 103 and the active layer. In the case where the transistor has a pair of gate electrodes, one of the gate electrodes is connected to a gate electrode for controlling switching. A signal is applied to the gate electrode, and the other gate electrode is in an electrically insulated floating state. It may be in a non-uniform state, or a state in which a potential is applied from another source. The pair of electrodes may be given the same potential, or only the other gate electrode may be given a potential of 100V. A fixed potential such as a fixed potential may be applied to the other gate electrode. By controlling the voltage Vcc, the threshold voltage of the transistor 103 can be controlled.

[0035] In FIG. 1B, the memory cell 101 is a transistor that functions as a switching element. Although the present invention is not limited to a single configuration, the present invention is not limited to this configuration. In one embodiment of the present invention, at least one transistor that functions as a switching element is provided in each memory cell. It is sufficient to provide one transistor, and the number of the transistors may be more than one. When the first transistor has a plurality of transistors functioning as switching elements, The transistors may be connected in parallel, in series, or in both series and Parallel connections may also be combined.

[0036] In this specification, the state in which transistors are connected in series refers to, for example, a first Only one of the first terminal and the second terminal of the first transistor is connected to the first terminal of the second transistor. This means that the transistor is connected to only one of the terminals. A state in which transistors are connected in parallel is when the first terminal of a first transistor is connected to the a second terminal of the first transistor connected to a first terminal of the second transistor; It means that it is connected to a child.

[0037] Next, in FIG. 1C, a cross-sectional view of the transistor 103 and the capacitor 104 shown in FIG. 1C shows an example of a cross-sectional view of the memory cell 101 shown in FIG. 1B, the transistor 103 and the capacitor 105 shown in FIG. A configuration similar to that of C) can be adopted.

[0038] In the cross-sectional view shown in FIG. 1C, a capacitor 104 and a transistor are formed on a substrate 110 having an insulating surface. The capacitor element 104 and the transistor 103 are formed on the insulating film 11. They are stacked with 1 in between.

[0039] Specifically, the capacitor 104 includes an electrode 112 formed on a substrate 110 having an insulating surface. 1, an insulating film 113 on the electrode 112, and an electrode 112 overlapping the electrode 112 with the insulating film 113 sandwiched therebetween. The portion where the electrode 112, the insulating film 113, and the electrode 114 overlap each other forms a capacitance. It functions as element 104.

[0040] In addition, the transistor 103 has a gate electrode 1 on the insulating film 111 covering the electrode 114. 15, an insulating film 116 on the gate electrode 115, and a gate electrode 115 with the insulating film 116 sandwiched therebetween. 15 and an active layer 117 including an oxide semiconductor, and a source electrode 11 on the active layer 117. 8 and a drain electrode 119. The transistor 103 further includes an active layer 117, The insulating film 120 covering the source electrode 118 and the drain electrode 119 is included as a component. The transistor 103 is a bottom gate type and has a source electrode 11. Between the active layer 117 and the drain electrode 119, a channel is formed by etching a part of the active layer 117. It is an etched structure.

[0041] Note that FIG. 1C illustrates the case where the transistor 103 has a single-gate structure. However, the transistor 103 has a plurality of gate electrodes electrically connected to each other. A multi-gate structure having a plurality of channel forming regions may also be used.

[0042] In one embodiment of the present invention, as shown in FIG. 1(C), a light-shielding insulating film 1 21 is formed so as to cover the transistor 103. An insulating film 121 that functions as a light-shielding layer is formed so as to overlap the active layer 117 of 03.

[0043] In addition, a light-shielding layer such as an insulating film, wiring, or an electrode having a light-shielding property is used in the active layer. The transmittance of light in the wavelength range near or shorter than the absorption edge wavelength of the oxide semiconductor is low. Specifically, if the absorption edge wavelength is λ0, the light-shielding layer is a layer having a wavelength of 100 nm or more. The transmittance of light of λ0+100 nm or less is 50% or less, and more preferably 30% or less. For example, the absorption edge of the active layer 117 formed using an In-Ga-Zn-O oxide semiconductor When the wavelength is 393 nm, the light-shielding layer has a transmittance of light having a wavelength of 100 nm or more and 493 nm or less. The ratio is set to 50% or less, and more preferably 30% or less. All light included in the above wavelength range However, it is not necessary to satisfy the above transmittance, and at least one wavelength included in the above wavelength range is It is sufficient that the light having a longer wavelength than the above wavelength range satisfies the above transmittance range. The light transmittance of the oxide semiconductor must also satisfy the above range to prevent the oxide semiconductor from being deteriorated by light. This is desirable in some respects.

[0044] For example, the insulating film 121 is made of a low-order oxidizing agent having a smaller oxidation number than carbon black or titanium dioxide. Resins containing dispersed black pigments such as titanium dioxide and ultraviolet absorbing agents such as zinc oxide. The resin may be, for example, acrylic resin, polyimide, or benzene. Organic resins such as cyclobutene resin, polyamide, epoxy resin, siloxane resin, etc. Siloxane resins are made of silicon (Si) and oxygen (O) that bond to bone. It is a material that has a lattice structure. Substituents include hydrogen, fluorine, fluoro groups, and organic groups. (for example, an alkyl group, an aromatic hydrocarbon) may be included.

[0045] When a resin is used for the insulating film 121, impurities such as hydrogen and water contained in the resin may cause the active layer to be damaged. The active layer 117, the insulating film 116, or the interface between the active layer 117 and another insulating film and its vicinity In order to prevent the ingress of the metal, a material with high barrier properties is used between the insulating film 121 and the active layer 117. It is preferable to form the insulating film 122 using a material having high barrier properties, such as nitrogen. Silicon nitride film, silicon oxynitride film, aluminum nitride film, aluminum oxide nitride film, etc. In addition, the active layer 117 and the insulating film 122 having a high nitrogen content are in direct contact with each other. As a result, the characteristics of the transistor 103 may deteriorate. Between the conductive layer 117 and the insulating film 122, a silicon oxide film or a silicon oxynitride film having a low nitrogen content is formed. It is desirable to form the insulating film 120 in this manner.

[0046] In addition, by using an inorganic material containing oxygen for the insulating film 120 in contact with the active layer 117, water Oxygen vacancies have been generated in the active layer 117 by heat treatment for reducing oxygen or hydrogen. Even if this is the case, oxygen is supplied to the active layer 117 from the insulating film 120, and oxygen vacancies that become donors are reduced. Therefore, it is possible to reduce the active layer 117 to satisfy the stoichiometric composition ratio. The variation in the electrical characteristics of the transistor 103 due to oxygen vacancies can be reduced. This can reduce the electrical resistance and improve the electrical characteristics.

[0047] In addition, oxygen is added to the oxide semiconductor by subjecting the active layer 117 to a heat treatment in an oxygen atmosphere. In addition, oxygen vacancies that act as donors in the active layer 117 may be reduced. The reaction is carried out, for example, at a temperature of 100° C. or higher and lower than 350° C., preferably 150° C. or higher and lower than 250° C. The oxygen gas used in the heat treatment in the oxygen atmosphere does not contain water, hydrogen, etc. Alternatively, the purity of the oxygen gas introduced into the heat treatment device is preferably 6N (99.9999%) or less. ) or more, preferably 7N (99.99999%) or more (i.e., impurity concentration in oxygen is 1p pm or less, preferably 0.1 ppm or less).

[0048] Alternatively, oxygen may be added to the active layer 117 by using an ion implantation method or an ion doping method. For example, the 2.45 GHz master clock can be used to reduce the oxygen vacancies that act as donors. Oxygen plasma generated by microwaves may be added to the active layer 117 .

[0049] In this specification, an oxynitride is a material having a composition in which oxygen is more abundant than nitrogen. Nitrogen oxide is a substance that contains more nitrogen than oxygen. For example, silicon oxynitride is a material that is made up of 50 atomic % to 70 atomic % oxygen and 10 atomic % nitrogen. 0.5 atomic % to 15 atomic % of silicon, 25 atomic % to 35 atomic % of silicon, 0 atomic % of hydrogen The content of the nitriding agent in the material may be in the range of 1 atomic % to 10 atomic %. Silicon dioxide is a material that contains 5 atomic % to 30 atomic % of oxygen and 20 atomic % to 55 atomic % of nitrogen. Silicon is 25 atomic % or more and 35 atomic % or less, and hydrogen is 10 atomic % or more and 30 atomic % or less. However, the above composition range is based on the Rutherford backscattering method ( RBS: Rutherford Backscattering Spectromet ry) and Hydrogen Forward Scattering (HFS) The content ratio of the constituent elements is the sum of the takes a value not exceeding 100 atomic %.

[0050] In one embodiment of the present invention, as shown in FIG. At least one of the electrodes 112 and 114 has a light-shielding property. The electrode 112 or electrode 114 is formed at a position where it overlaps with the active layer 117 of the transistor 103. It has been made.

[0051] With the above-mentioned configuration, the electrode 112 or 114 having a light-shielding property and the insulating film having a light-shielding property Since the active layer 117 is sandwiched between the oxide semiconductor 121 and the active layer 117, light having a wavelength near the absorption edge of the oxide semiconductor, if It is possible to prevent light having a wavelength in a range shorter than this from entering the active layer 117 .

[0052] Next, in FIG. 1D, a cross-sectional view of the transistor 103 and the capacitor 104 shown in FIG. 1D shows an example of a cross-sectional view of the memory cell 101 shown in FIG. 1B, the transistor 103 and the capacitor 105 shown in FIG. A configuration similar to that of D) can be adopted.

[0053] In the cross-sectional view shown in FIG. 1D, similarly to FIG. 1C, A capacitor 104 and a transistor 103 are formed. 103 overlaps with an insulating film 111 sandwiched therebetween.

[0054] The specific configurations of the capacitor 104 and the transistor 103 are the same as those in FIG. In FIG. 1D, a wiring 123 is formed using a conductive film having a light-shielding property. It covers the transistor 103. Specifically, it overlaps the active layer 117 of the transistor 103. In order to achieve this, the wiring 123 having light blocking properties is formed.

[0055] As described above, the characteristics required for the light-shielding wiring 123 are the same as those of the active layer. The transmittance of light in the wavelength range near or shorter than the absorption edge wavelength of the oxide semiconductor is low. Therefore, the wiring 123 is made of a metal that is both conductive and light-shielding. For example, the wiring 123 may be made of molybdenum, titanium, chromium, tantalum, tungsten, aluminum, etc. Metallic materials such as tungsten, copper, neodymium, and scandium, and alloy materials that contain these metallic materials as the main components A conductive film using a material or a nitride of these metals can be used in a single layer or a laminated layer. .

[0056] In addition, in FIG. 1D, the electrode 112 or At least one of the electrodes 112 and 114 has a light-shielding property. Alternatively, an electrode 114 is formed at a position overlapping an active layer 117 of the transistor 103 .

[0057] With the above-described structure, in FIG. 1D, the light-shielding electrode 112 or the light-shielding electrode 114 Since the active layer 117 is sandwiched between the wiring 123 having the characteristic, the absorption edge wavelength of the oxide semiconductor It is possible to prevent light in the vicinity or in a shorter wavelength region from entering the active layer 117. This can be done.

[0058] Note that in FIG. 1C and FIG. 1D, the transistor 103 is In addition, a back gate electrode may be provided at a position overlapping with the channel formation region of the active layer 117. When the back gate electrode is formed, an insulating film is formed so as to cover the back gate electrode. The back gate electrode may be in an electrically insulated floating state, or may be in an electrically insulated floating state. In the latter case, the back gate electrode may be provided with a gate electrode 1. The same potential as 15 may be applied, or a fixed potential such as ground may be applied. By controlling the level of the potential applied to the back gate electrode, the transistor 1 The threshold voltage of .03 can be controlled.

[0059] Note that in FIGS. 1C and 1D, the transistor 103 is a bottom-gate transistor. In addition, the case of having a channel etch structure is shown, but the present invention can be used in one embodiment. The structure of the transistor is not limited to this configuration.

[0060] In one embodiment of the present invention, the transistor 103 including an oxide semiconductor in the active layer 117 is used as a memory element. The charge retention in the transistor 102 or the capacitor 105 used as a transistor is controlled. By using it as a switching element for this purpose, the leakage of the charge can be prevented. In addition, by sandwiching the active layer 117 between layers such as light-shielding electrodes, conductive films, and insulating films, It is possible to prevent the characteristics of the transistor 103 from being deteriorated by light. In this way, the shift in threshold voltage can be suppressed and the increase in off-current can be prevented. In one embodiment, the light-shielding electrode is a light-shielding electrode of the capacitor 104 or the capacitor 105. The electrode 112 or the electrode 114 is used as the capacitor element 104 or the capacitor element 105. Since the transistor 103 is arranged in the memory cell 101 so as to overlap with the capacitance element 104 or the capacitance value of the capacitance element 105 while ensuring the area occupied by the memory cell 10 The area occupied by 1 can be reduced.

[0061] Therefore, the storage device according to one aspect of the present invention can secure a period for storing data while Alternatively, the present invention provides a semiconductor memory device having a high memory capacity per unit area. By using the same in a semiconductor device, the reliability of the semiconductor device can be improved and the functionality of the device can be enhanced.

[0062] Next, FIG. 2 shows a more specific example of the connection configuration of various wirings in the memory cell 101. vinegar.

[0063] The memory cell 101 shown in FIG. 2A includes a transistor 1 functioning as a switching element. The gate of the transistor 103 is connected to the gate of the capacitor 105. The first terminal of the transistor 103 is connected to a word line WL. The second terminal is connected to one electrode of the capacitance element 105. The other electrode of the capacitance element 105 is connected to a node to which a fixed potential such as ground is applied. This is being continued.

[0064] In the memory cell 101 shown in FIG. 2A, the transistor 103 is turned on when data is written. The potential of the signal including data is transferred from the data line DL to the transistor 103. The potential of the signal is applied to one electrode of the capacitance element 105. The amount of charge stored in the capacitor 105 is controlled, so that data can be written to the capacitor 105. will be carried out.

[0065] Next, when data is held, the transistor 103 is turned off and the capacitor 105 As described above, the off-state current of the transistor 103 is extremely low. Therefore, the charge stored in the capacitor 105 is unlikely to leak, and the charge is shielded. When light is not used, or when a semiconductor material such as silicon is used for the transistor 103, This allows data to be retained for a longer period of time than in the case of a hard disk.

[0066] When reading data, the transistor 103 is turned on, and the capacitance is transferred via the data line DL. The charge stored in the element 105 is extracted. Then, the difference in the amount of charge is read. The data can be read out by

[0067] The memory cell 101 shown in FIG. 2B includes a transistor 1 functioning as a switching element. The semiconductor memory device includes a semiconductor memory device having a semiconductor memory element, a transistor 102 functioning as a memory element, and a capacitor 104. The gate electrode of the transistor 103 is connected to the first word line WLa. The first terminal of the transistor 103 is connected to the first data line DLa, and the second terminal of the transistor The first terminal of the transistor 102 is connected to the gate electrode of the second data line The second terminal is connected to DLb, and the second terminal is a node to which a fixed potential such as ground is applied. The capacitor 104 has a pair of electrodes, one of which is connected to the One end is connected to the gate electrode, and the other end is connected to a second word line WLb.

[0068] In the memory cell 101 shown in FIG. 2B, the transistor 103 is turned on when data is written. The potential of the signal including data is supplied from the first data line DLa to the transistor 103. Then, according to the potential of the signal, The gate capacitance of the transistor 102 and the amount of charge stored in the capacitor 104 are controlled. Thus, data is written to the transistor 102 and the capacitor 104.

[0069] Next, when data is held, the transistor 103 is turned off and the transistor 102 is turned off. The charge stored in the gate capacitance and the capacitance element 104 is held. The transistor 103 has a characteristic that the off-current is extremely low. The charge is unlikely to leak, and if light is not blocked or if the transistor 103 is made of silicon, Compared to semiconductor materials such as silicon, data can be retained for a longer period of time. Cut.

[0070] When reading data, the potential of the second word line WLb is changed. Since the potential difference between the pair of electrodes connected to the second word line WL The change in potential of b is applied to the gate electrode of transistor 102. The threshold voltage of a transistor varies depending on the amount of charge stored in its gate capacitance. The potential of the gate electrode of the transistor 102 is changed. The difference in the amount of accumulated charge can be read from the magnitude of the drain current, and data can be obtained. can be read out.

[0071] In the memory cell 101 shown in FIG. 2C, one data line DL is connected to the first data line DLa and the second data line DLb. The memory cell 10 shown in FIG. 2B has the functions of the data line DLb and the data line DLc. Specifically, the memory cell 101 shown in FIG. a transistor 103 functioning as a memory element; and a transistor 102 functioning as a memory element. The gate electrode of the transistor 103 is connected to the first word line WLa. The first terminal of the transistor 103 is connected to the data line DL. The second terminal is connected to the gate electrode of the transistor 102. The first terminal is connected to the data line DL, and the second terminal is given a fixed potential such as ground. The capacitor 104 has a pair of electrodes, one of which is a transistor. One end of the transistor 102 is connected to the gate electrode of the transistor 102, and the other end is connected to the second word line WLb.

[0072] The memory cell 101 shown in FIG. 2C performs operations such as writing, holding, and reading data. This can be performed in the same manner as in the memory cell 101 shown in FIG.

[0073] The memory cell 101 shown in FIG. 2D includes a transistor 1 functioning as a switching element. 03, a transistor 102 functioning as a memory element, a capacitor 104, and a data read and a transistor 106 which functions as a switching element for controlling the leakage. The gate electrode of the transistor 103 is connected to the first word line WLa. The first terminal of the transistor 103 is connected to the first data line DLa, and the second terminal of the transistor The first terminal of the transistor 102 is connected to the gate electrode of the transistor The second terminal is connected to the second terminal of the 106, and the second terminal is given a fixed potential such as ground. A first terminal of the transistor 106 is connected to a node where the second data line D The gate electrode of transistor 106 is connected to the second word line WLb. The capacitor 104 has a pair of electrodes, one of which is connected to the gate of the transistor 102. One end is connected to an electrode, and the other end is connected to a node to which a fixed potential is applied.

[0074] In the memory cell 101 shown in FIG. 2D, the transistor 103 is turned on when data is written. The potential of the signal including data is supplied from the first data line DLa to the transistor 103. Then, according to the potential of the signal, The gate capacitance of the transistor 102 and the amount of charge stored in the capacitor 104 are controlled. Then, data is written to the transistor 102 and the capacitor 104 .

[0075] Next, when data is held, the transistor 103 is turned off and the transistor 102 is turned off. The gate capacitance holds the charge stored in the capacitance element 104. The off-state current of the photodiode 103 is extremely low. The charge is unlikely to leak, and if light is not blocked or if semiconductor materials such as silicon are used, This allows data to be retained for a longer period of time than if data was stored in a separate database.

[0076] When reading data, the potential of the second word line WLb changes, so that the transistor 10 When transistor 106 is turned on, transistor 102 has its gate A drain current flows that is proportional to the amount of charge stored in the gate capacitance. The difference in the amount of stored charge can be read from the magnitude of the drain current of the transistor 102. This allows the data to be read out.

[0077] (Embodiment 2) In this embodiment, a specific configuration of a memory cell included in a memory device according to one embodiment of the present invention will be described. In this embodiment, an example of the circuit configuration shown in FIG. The structure will be described by taking a memory cell as an example.

[0078] FIG. 3 shows an example of a top view of a memory cell. Note that in FIG. 3, the configuration of the memory cell is not clearly shown. In order to avoid this, all insulating films other than the insulating film having the light-shielding property are omitted. A cross-sectional view taken along dashed line A1-A2 of FIG. 3 is shown in FIG.

[0079] The memory cell shown in FIG. 3 and FIG. 4 includes a transistor 102 on a substrate 110 having an insulating surface. The semiconductor device includes a semiconductor device having a transistor 103 and a capacitor 104. The capacitor element 104 is covered with an insulating film 111, and a transistor 1 is provided on the insulating film 111. A capacitor 104 and a transistor 103 are formed. The stator 102 and the transistor 103 overlap with each other with an insulating film 111 interposed therebetween.

[0080] Specifically, the capacitor 104 includes an electrode 112 formed on a substrate 110 having an insulating surface. 1, an insulating film 113 on the electrode 112, and an electrode 112 overlapping the electrode 112 with the insulating film 113 sandwiched therebetween. The portion where the electrode 112, the insulating film 113, and the electrode 114 overlap each other forms a capacitance. It functions as element 104.

[0081] In addition, the transistor 103 has a source electrode or a drain electrode over the insulating film 111. The conductive film 130 and the conductive film 131 functioning, and the acid in contact with the conductive film 130 and the conductive film 131 The active layer 132 includes a nitride semiconductor, and a conductive film 130, a conductive film 131, and a film covering the active layer 132. The insulating film 133 is sandwiched between the active layer 132 and the gate electrode 13 4 and

[0082] The transistor 103 shown in FIGS. 3 and 4 is a top-gate type transistor, and the source electrode Alternatively, the conductive film 130 and the conductive film 131 functioning as drain electrodes are disposed under the active layer 132. It is a bottom contact structure in which the sides are in contact.

[0083] In addition, the transistor 102 has a source electrode or a drain electrode over the insulating film 111. The conductive film 131 and the conductive film 135 functioning, and the acid in contact with the conductive film 131 and the conductive film 135 The active layer 136 includes a nitride semiconductor, and a conductive film 131, a conductive film 135, and a film covering the active layer 136. The insulating film 133 is sandwiched between the active layer 136 and the gate electrode 13 7 and

[0084] The transistor 102 shown in FIGS. 3 and 4 is a top-gate type transistor like the transistor 103. The conductive film 131 and the conductive film 132 function as a source electrode and a drain electrode, respectively. Reference numeral 135 denotes a bottom contact structure that contacts the lower side of the active layer 136 .

[0085] In addition, in FIG. 3 and FIG. 4, the transistor 102 and the transistor 103 have a single gate structure. However, the transistor 102 and the transistor 103 are not electrically connected. By having a plurality of gate electrodes connected to each other, a multi-gate semiconductor device having a plurality of channel forming regions is formed. It may have a structure.

[0086] The conductive film 130 is connected to the insulating film 111 through a contact hole 138. It is in contact with the electrode 114 .

[0087] In addition, an insulating film 139 is formed so as to cover the transistor 102 and the transistor 103. On the insulating film 139, a contact hole 1 formed in the insulating film 139 is formed. 40, a light-shielding conductive material connected to the gate electrode 137 of the transistor 102. The conductive film 141 is formed on the insulating film 139 and the insulating film 133. The insulating film 130 is connected to the conductive film 130 through a contact hole 142 formed therein. A transistor is provided on the film 139 through a contact hole 143 formed in the insulating film 139. A conductive film 144 having a light-shielding property is formed on the gate electrode 134 of the transistor 103. do.

[0088] The conductive film 141 having a light-shielding property is formed on at least a part of the active layer 136 of the transistor 102. In order to more effectively prevent light from being incident on the active layer 136, It is preferable to completely cover the entirety of 36 with the conductive film 141 .

[0089] The conductive film 144 having a light-shielding property is formed on at least the active layer 132 of the transistor 103. In order to more effectively prevent light from being incident on the active layer 132, It is preferable to completely cover the entire conductive layer 132 with the conductive film 144 .

[0090] Furthermore, in one embodiment of the present invention, at least one of the electrodes 112 and 114 of the capacitor 104 At least one of the electrodes 112 and 114 has a light-shielding property. , the position where the active layer 132 of the transistor 103 and the active layer 136 of the transistor 102 overlap. At least a part of the active layer 132 and the active layer 136 is formed on the electrode 11. 2 or electrode 114. However, the active layer 132 or the active layer 136 may overlap the In order to better block the incident light, the entire active layer 132 or the entire active layer 136 is preferably completely It is desirable for it to overlap with electrode 112 or electrode 114 .

[0091] Characteristics required for the light-shielding electrode 112, the electrode 114, the conductive film 141, and the conductive film 144 As described above, is near the absorption edge wavelength of the oxide semiconductor used in the active layer, or The transmittance of light in a shorter wavelength range than this is low. 4. The conductive film 141 and the conductive film 144 are made of a metal having both electrical conductivity and light blocking properties. For example, the electrodes 112 and 114 may be made of molybdenum, titanium, chromium, tantalum, tungsten, etc. The materials used are metals such as niobium, neodymium, and scandium, as well as alloys that contain these metals as their main components. The conductive film or nitride of these metals can be used as a single layer or a laminated layer. In addition to the above-mentioned materials, aluminum or copper may be used for the conductive film 141 and the conductive film 144. When aluminum or copper is used for the conductive film 141 and the conductive film 144, To avoid problems with heat resistance and corrosion, it is recommended to use it in combination with a high melting point metal material. High melting point metal materials include molybdenum, titanium, chromium, tantalum, tungsten, and neodymium. Dymium, scandium, etc. can be used.

[0092] For example, the electrode 112, the electrode 114, the conductive film 141, and the conductive film 144 are formed into a two-layer laminate structure. In the case of a two-layer structure, a molybdenum film is laminated on an aluminum film, and a molybdenum film is laminated on a copper film. Two-layer structure with a titanium nitride film laminated on a copper film, and two-layer structure with a titanium nitride film or a tantalum nitride film laminated on a copper film Alternatively, it is preferable to use a two-layer structure in which a titanium nitride film and a molybdenum film are laminated. In the case where the electrode 112, the electrode 114, the conductive film 141, and the conductive film 144 are stacked in three layers, , aluminum film, aluminum-silicon alloy film, aluminum-titanium alloy film, Or an alloy film of aluminum and neodymium is used as an intermediate layer, and a tungsten film, tungsten nitride film, It is preferable that the insulating film has a structure in which a titanium nitride film or a titanium film is laminated as upper and lower layers.

[0093] The thickness of the electrode 112, the electrode 114, the conductive film 141, and the conductive film 144 is, for example, 10 The thickness is set to 100 nm to 400 nm, and preferably 100 nm to 200 nm.

[0094] In one embodiment of the present invention, the above-described structure provides the light-blocking electrode 112 or the light-blocking electrode 114, Since the active layer 136 is sandwiched between the conductive films 141 having a light-shielding property, the absorption edge of the oxide semiconductor The light having a wavelength close to or shorter than this is prevented from entering the active layer 136. In addition, the electrode 112 or the electrode 114 having a light-shielding property and the Since the active layer 132 is sandwiched between the conductive films 144, light having a wavelength near the absorption edge of the oxide semiconductor, Alternatively, light in a shorter wavelength region than this can be prevented from entering the active layer 132. .

[0095] 3 and 4, the conductive film 141 and the conductive film 144 functioning as wirings are used to form an active layer. The structure shown in FIG. 1(C) is an example of a structure in which the layer 132 or the active layer 136 is shielded from light. In the same manner as in the above, the active layer 132 or the active layer 136 is shielded from light by an insulating film having a light shielding property. That's fine too.

[0096] 3 and 4, the transistor 102 functioning as a memory element has an active layer 13 However, the transistor 102 does not necessarily include an oxide semiconductor. The active layer does not have to contain a semiconductor such as silicon or germanium. When a conductive material is used to form the active layer of the transistor 102, the active layer is formed on one insulating surface. The conductive layer and the capacitive element 104 can be formed together. The electrode 112 is also made of a semiconductor material such as silicon or germanium, like the active layer. It can be formed by:

[0097] The electrode 112 also functions as a second word line WLb. The conductive film 131 also functions as a first word line WLa. The conductive film 135 functions as a wiring to which a fixed potential such as a ground potential is applied.

[0098] There is no particular limitation on the material that can be used for the substrate 110. However, at least It is necessary for the material to have heat resistance sufficient to withstand the heat treatment in the manufacturing process. For example, the substrate 110 may be a glass substrate manufactured by the fusion method or the float method, a quartz substrate, A ceramic substrate or the like can be used. A glass substrate is suitable for use in the subsequent heat treatment at a high temperature. In cases where the temperature is too high, it is advisable to use a material with a strain point of 730°C or higher. Generally, the heat resistance of the synthetic resin substrate tends to be lower than that of the above substrates. However, any material can be used as long as it can withstand the processing temperatures in the manufacturing process.

[0099] The insulating film 133 is a silicon oxide film formed by using a plasma CVD method, a sputtering method, or the like. , silicon nitride film, silicon oxynitride film, silicon nitride oxide film, aluminum oxide film, aluminum nitride aluminum oxide film, aluminum oxynitride film, aluminum nitride oxide film, hafnium oxide film or oxide The tantalum film can be formed as a single layer or a multilayer. It functions as a gate insulating film. It is desirable that the insulating film 133 contains as little impurities as possible, such as moisture, hydrogen, and oxygen. When forming a silicon oxide film by the ion beam deposition method, a silicon target is used as the target. The sputtering gas is oxygen or a mixture of oxygen and argon. Use the s.

[0100] By removing impurities, an oxide semiconductor that has been made i-type or substantially i-type (highly purified) Since the oxide semiconductor (a highly purified oxide semiconductor) is extremely sensitive to the interface state and the interface charge, The interface between the oxide semiconductor and the gate insulating film is important. The gate insulating film (GI) that contacts the conductor is required to have high quality.

[0101] For example, high-density plasma CVD using μ-waves (frequency 2.45 GHz) produces dense, high-insulation Since a high-quality insulating film with high pressure can be formed, this method is suitable for forming the insulating film 133. The highly purified oxide semiconductor and the high-quality gate insulating film are in close contact with each other, This is because the level can be reduced and the interface characteristics can be improved.

[0102] Of course, if a good insulating film 133 can be formed as a gate insulating film, sputtering is possible. Other film formation methods such as the ring method and plasma CVD method can be applied. The insulating film may be one whose film quality or interface characteristics with an oxide semiconductor are improved by heat treatment. In any case, the quality of the gate insulating film must be good. Any material that can reduce the interface state density between the film and the oxide semiconductor and form a good interface is acceptable. .

[0103] In addition, by using an inorganic material containing oxygen for the insulating film 133, moisture or hydrogen can be reduced. Even if oxygen vacancies occur in the active layers 132 and 136 due to the heat treatment for , oxygen is supplied to the active layer 132 and the active layer 136 from the insulating film 133, and oxygen vacancies serving as donors are formed. Therefore, it is possible to reduce the amount of the active layer 13 so as to satisfy the stoichiometric composition ratio. 2. The active layer 136 can be made closer to an i-type, and the electrical characteristics of the transistor due to oxygen deficiency can be improved. This reduces the variation in the electrical characteristics and improves the electrical properties.

[0104] The oxide semiconductor film used as the active layer 132 or the active layer 136 has a thickness of 2 nm or more. 200 nm or less, preferably 3 nm to 50 nm, more preferably 3 nm The oxide semiconductor film is formed by using an oxide semiconductor as a target. The oxide semiconductor film is formed by sputtering under a rare gas (for example, argon) atmosphere. , in an oxygen atmosphere, or in a mixture of rare gas (e.g., argon) and oxygen. The method can be carried out.

[0105] As described above, the oxide semiconductor film is made of a quaternary metal oxide, In-Sn-Ga-Zn -O-based oxide semiconductors, and In-Ga-Zn-O-based oxide semiconductors, which are ternary metal oxides. In-Sn-Zn-O oxide semiconductor, In-Al-Zn-O oxide semiconductor, Sn-G a-Zn-O oxide semiconductor, Al-Ga-Zn-O oxide semiconductor, Sn-Al-Zn -O-based oxide semiconductors, binary metal oxide In-Zn-O-based oxide semiconductors, Sn- Zn-O oxide semiconductor, Al-Zn-O oxide semiconductor, Zn-Mg-O oxide semiconductor body, Sn-Mg-O oxide semiconductor, In-Mg-O oxide semiconductor, In-Ga-O Oxide semiconductors, In-O oxide semiconductors, Sn-O oxide semiconductors, Zn-O oxide semiconductors A semiconductor or the like can be used.

[0106] For example, a thin film of an In-Ga-Zn-O oxide semiconductor obtained by a sputtering method is oxidized. When used as a semiconductor film, the target is, for example, In2O3:Ga2O3:Z A target with a composition ratio of In2O = 1:1:1 [molar ratio] is used. A target having a composition ratio of 3:Ga2O3:ZnO=1:1:2 [molar ratio], The target used was In2O3:Ga2O3:ZnO=1:1:4 [molar ratio]. In addition, the filling rate of the target containing In, Ga, and Zn is 90% or more. The filling rate is 100% or less, preferably 95% or more and less than 100%. As a result, the formed oxide semiconductor film becomes a dense film.

[0107] When using an In-Zn-O-based material as the oxide semiconductor, the composition of the target to be used is The composition ratio is In:Zn=50:1-1:2 in atomic ratio (In2O3 In:ZnO=25:1 to 1:4, preferably In:Zn=20:1 to 1:1 (molar ratio) In terms of In2O3:ZnO=10:1 to 2:1), more preferably In:Zn=1 .5:1 to 15:1 (converted to a molar ratio of In2O3:ZnO = 3:4 to 15:2) For example, the target used for forming an In-Zn-O oxide semiconductor has an atomic ratio of When In:Zn:O=X:Y:Z, Z>1.5X+Y. The ratio of Zn is within the above range. By enclosing the electrons in the electron-doped region, it is possible to improve the mobility.

[0108] Note that moisture or hydrogen as an impurity is contained in the oxide semiconductor film formed by sputtering or the like. Moisture or hydrogen can easily form donor levels, so oxidation In one embodiment of the present invention, water in an oxide semiconductor film is an impurity. In order to reduce impurities such as hydrogen or nitrogen, the oxide semiconductor film is Heat treatment is performed in an atmosphere of dry air or rare gas (argon, helium, etc.). The gas has a water content of 20 ppm or less, preferably 1 ppm or less, preferably 1 It is desirable for the level to be below 0 ppb.

[0109] By performing heat treatment on the oxide semiconductor film, moisture or hydrogen is released from the oxide semiconductor film. Specifically, the temperature is 300° C. or higher and 700° C. or lower, preferably 300° C. or higher and 50° C. or lower. Heat treatment can be performed at 0°C or below. For example, it can be performed at 500°C for 3 to 6 minutes. If the RTA method is used for the heat treatment, dehydration or dehydrogenation can be performed in a short time. Processing can be carried out at temperatures above the strain point of the glass substrate.

[0110] Heat treatment equipment includes electric furnaces, as well as resistance heating elements and other heating elements that use heat conduction or heat radiation. For example, a GRTA (Gas Rapid Transient Atomic Heater) thermal annealing) equipment, LRTA (Lamp Rapid Thermal RTA (Rapid Thermal Anneal) equipment such as The LRTA device can be used with halogen lamps, metal halide lamps, xenon lamps, etc. Arc lamps, carbon arc lamps, high pressure sodium lamps, high pressure mercury lamps, etc. This is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp. The equipment uses high-temperature gas for heat treatment. The gas contains rare gas such as argon. Inert gases such as nitrogen or argon that do not react with the material to be treated by heat treatment are used. do.

[0111] By the above-described heat treatment, the hydrogen concentration in the oxide semiconductor film can be reduced and the oxide semiconductor film can be highly purified. This makes it possible to stabilize the characteristics of the oxide semiconductor film. Heat treatment below the transition temperature reduces the carrier density caused by hydrogen and widens the band gap. Therefore, a large-area substrate can be used to form a thin oxide semiconductor film. 102 and the transistor 103 can be manufactured, and mass productivity can be improved.

[0112] In the case where the oxide semiconductor film is heated, depending on the material of the oxide semiconductor film and heating conditions, Plate-like crystals may be formed on the surface of the oxide semiconductor film. It is preferable that the single crystal has a c-axis oriented substantially vertically. It is preferable that the crystals are polycrystalline with the c-axis oriented substantially perpendicular to the surface of the oxide semiconductor film. In addition to the c-axis orientation, the polycrystalline body has ab planes that coincide with each other. It is preferable that the a-axis or the b-axis of the oxide semiconductor film be the same as that of the oxide semiconductor film. If the surface is uneven, the plate crystals will become polycrystalline. Therefore, the surface of the substrate should be as smooth as possible. It is desirable that it be flat.

[0113] In one embodiment of the present invention, the transistor 103 including an oxide semiconductor in the active layer 132 is used as a memory element. Controlling charge retention in the transistor 102 or the capacitor 104 used as a By using it as a switching element for this purpose, the leakage of the charge can be prevented. In addition, the active layer 132 is sandwiched between light-shielding layers such as electrodes, conductive films, and insulating films having light-shielding properties. Therefore, it is possible to prevent the characteristics of the transistor 103 from being deteriorated by light. In addition, it is possible to suppress the shift of the threshold voltage and prevent the off-current from increasing. In one embodiment of the present invention, the light-blocking electrode is used as the electrode 112 of the capacitor 104 or The capacitor 104 and the transistor 103 are used as the electrode 114. Since the capacitor element 104 is disposed in the memory cell 101, the area occupied by the capacitor element 104 or the capacitance value is secured. At the same time, the area occupied by the memory cell 101 can be reduced.

[0114] Therefore, the storage device according to one aspect of the present invention can secure a period for storing data while Alternatively, the present invention provides a semiconductor memory device having a high memory capacity per unit area. By using the same in a semiconductor device, the reliability of the semiconductor device can be improved and the functionality of the device can be enhanced.

[0115] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0116] (Embodiment 3) In this embodiment, the transistor 103 functioning as a switching element is An example of a different configuration will be described.

[0117] FIG. 5A illustrates an example of a cross-sectional view of the transistor 103 and the capacitor 104. 5(A) shows a cross-sectional structure of the memory cell 101 shown in FIG. 1(A), The transistor 103 and the capacitor 105 included in the semiconductor device 100 also have the same configuration as those in FIG. It is possible.

[0118] In the cross-sectional view shown in FIG. 5A, similarly to FIG. 1D, A capacitor 104 and a transistor 103 are formed. 103 overlaps with an insulating film 111 sandwiched therebetween.

[0119] The specific configuration of the capacitor 104 is the same as that shown in FIG. 1D in that the sta 103 has a channel protection structure.

[0120] The transistor 103 shown in FIG. 5A includes a gate electrode 150 and a gate An insulating film 151 on the electrode 150 and a gate electrode 150 overlapping the insulating film 151 The active layer 152 includes an oxide semiconductor, and the active layer 152 includes an active layer 152 that includes an oxide semiconductor and is located at a position where the active layer 152 overlaps with the gate electrode 150. A channel protection film 153 formed on the active layer 152 and a source electrode 154 formed on the active layer 152 The transistor 103 further has a source electrode 154 and a drain electrode 155. The electrode 154, the drain electrode 155, the channel protection film 153, and the insulating film formed on the active layer 152 A velum 156 may be included as a component.

[0121] By providing the channel protection film 153, the portion of the active layer 152 that will become the channel formation region is The film is not thinned by plasma or etching agent during the subsequent etching process. This can prevent damage to the transistor, thereby improving the reliability of the transistor. do.

[0122] By using an inorganic material containing oxygen for the channel protection film 153, moisture or hydrogen is reduced. Even if oxygen vacancies occur in the active layer 152 due to the heat treatment for the purpose of 2, oxygen is supplied from the channel protective film 153 to reduce the oxygen vacancies that act as donors, and the stoichiometry is achieved. Therefore, it is possible to make the active layer 152 closer to the i-type. This reduces the variation in the electrical characteristics of transistors caused by oxygen vacancies and provides high voltage resistance. In addition, it is possible to realize improvements in electrical characteristics such as a low off-state current.

[0123] Note that the transistor 103 further includes a backgate electrode over the insulating film 156. The back gate electrode is formed so as to overlap the channel forming region of the active layer 152. The back gate electrode may be in an electrically insulating floating state, In the latter case, the back gate electrode may be in a state where a potential is applied. The potential may be the same as 150, or a fixed potential such as ground may be applied. By controlling the level of the potential applied to the back gate electrode, The threshold voltage of 103 can be controlled.

[0124] In FIG. 5A, the wiring 123 is formed using a conductive film having a light-shielding property. 1D in that the transistor 103 is covered by the A light-shielding wiring 123 is formed so as to overlap with an active layer 152 of the transistor 103. do.

[0125] In addition, in FIG. 5A, the electrode 112 or At least one of the electrodes 112 and 114 has a light-shielding property. Alternatively, an electrode 114 is formed at a position overlapping an active layer 152 of the transistor 103 .

[0126] With the above-mentioned structure, in FIG. 5A, the electrode 112 or the electrode 114 having a light-shielding property and the light-shielding Since the active layer 152 is sandwiched between the wiring 123 having the characteristic, the absorption edge wavelength of the oxide semiconductor It is possible to prevent light in the vicinity or in a shorter wavelength region from entering the active layer 152. This can be done.

[0127] In addition, the transistor 103 functioning as a switching element may have a different structure from that shown in FIG. Another example of the above will be described.

[0128] FIG. 5B illustrates an example of a cross-sectional view of the transistor 103 and the capacitor 104. 5(B) shows a cross-sectional structure of the memory cell 101 shown in FIG. 1(A), The transistor 103 and the capacitor 105 included in the semiconductor device 100 also have the same configuration as those in FIG. It is possible.

[0129] In the cross-sectional view shown in FIG. 5B, similarly to FIG. 1D, A capacitor 104 and a transistor 103 are formed. 103 overlaps with an insulating film 111 sandwiched therebetween.

[0130] The specific configuration of the capacitor 104 is the same as that shown in FIG. The transistor 103 is a bottom gate type, and the source electrode or the drain electrode is an active layer. 1(D) in that it has a bottom contact structure in which the bottom side of the semiconductor substrate is in contact with the bottom side of the semiconductor substrate.

[0131] The transistor 103 shown in FIG. 5B includes a gate electrode 160 and a gate An insulating film 161 on the electrode 160, a source electrode 164 formed on the insulating film 161, and a drain electrode 165 formed on the insulating film 161. The gate electrode 165 is formed on the insulating film 161 at a position where the gate electrode 160 overlaps the insulating film 161. Also, the active layer including the oxide semiconductor is in contact with the source electrode 164 and the drain electrode 165. The transistor 103 further includes a source electrode 164, a drain electrode 165, and a gate insulating layer 166. The components may include an electrode 165 and an insulating film 166 formed on the active layer 162 .

[0132] In addition, by using an inorganic material containing oxygen for the insulating film 166 in contact with the active layer 162, water Oxygen vacancies have been generated in the active layer 162 by heat treatment for reducing oxygen or hydrogen. Even if this is the case, oxygen is supplied to the active layer 162 from the insulating film 166, and oxygen vacancies that become donors are reduced. Therefore, the active layer 162 can be reduced to satisfy the stoichiometric composition ratio. The variation in the electrical characteristics of the transistor 103 due to oxygen vacancies can be reduced. This can reduce the electrical resistance and improve the electrical characteristics.

[0133] Note that the transistor 103 further includes a backgate electrode over the insulating film 166. The back gate electrode is formed so as to overlap the channel forming region of the active layer 162. The back gate electrode may be in an electrically insulating floating state, In the latter case, the back gate electrode may be in a state where a potential is applied. The potential may be the same as that of 160, or a fixed potential such as ground may be applied. By controlling the level of the potential applied to the back gate electrode, The threshold voltage of 103 can be controlled.

[0134] In FIG. 5B, a wiring 123 is formed using a conductive film having a light-shielding property. 1D in that the transistor 103 is covered by the A light-shielding wiring 123 is formed so as to overlap with an active layer 162 of the transistor 103. do.

[0135] In addition, in FIG. 5B, the electrode 112 or At least one of the electrodes 112 and 114 has a light-shielding property. Alternatively, an electrode 114 is formed at a position overlapping an active layer 162 of the transistor 103 .

[0136] With the above-described structure, in FIG. 5B, the light-shielding electrode 112 or the light-shielding electrode 114 Since the active layer 162 is sandwiched between the wiring 123 having the characteristic, the absorption edge wavelength of the oxide semiconductor It is possible to prevent light in the vicinity or in a shorter wavelength region from entering the active layer 162. This can be done.

[0137] In addition, in FIG. 5(A) and FIG. 5(B), the active layer 152 or the active layer 1 62 is taken as an example, but it is possible to use a structure having a light-shielding property similar to the structure shown in FIG. The active layer 152 or the active layer 162 may be shielded from light by the insulating film.

[0138] In addition, in FIGS. 5A and 5B, the transistor 103 has a single-gate structure. In the illustrated example, the transistor 103 has a plurality of gate electrodes electrically connected to each other. By having such a structure, a multi-gate structure having a plurality of channel formation regions may be obtained.

[0139] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0140] (Embodiment 4) In this embodiment, a specific configuration of the storage unit and its operation will be described.

[0141] FIG. 6 is a circuit diagram of a memory unit 200 having a plurality of memory cells 101 shown in FIG. The configuration of the memory cell 101 is shown in FIG. I can pour drinks.

[0142] In the memory unit 200 shown in FIG. 6, various wirings such as a plurality of word lines WL and a plurality of data lines DL are A signal or a fixed potential from the driving circuit is supplied to each memory through these wirings. The number of the wirings is determined by the number and arrangement of the memory cells 101. It is possible.

[0143] Specifically, in the case of the memory unit 200 shown in FIG. 6, memory cells of 3 rows and 4 columns are connected in a matrix. The word lines WL1 to WL3 and the data lines DL1 to DL4 are connected to the memory section 200. 13 illustrates an example in which the

[0144] Next, the operation of the storage unit 200 shown in FIG. 6 will be described.

[0145] First, the operation of the storage unit 200 when writing data will be described. In this case, when a signal having a pulse is input to the word line WL1, the potential of the pulse, specifically Specifically, a high-level potential is applied to the gate of the transistor 103 connected to the word line WL1. Therefore, the transistor whose gate electrode is connected to the word line WL1 All of the switches 103 are turned on.

[0146] Next, signals including data as information are input to the data lines DL1 to DL4. The potential levels of the signals input to the lines DL1 to DL4 naturally differ depending on the contents of the data. The potentials input to the data lines DL1 to DL4 are applied via the on-transistor 103. The potential is applied to one electrode of the capacitor 105. The amount of charge stored in the capacitor 105 is controlled, so that data can be written to the capacitor 105. The inclusion takes place.

[0147] When the input of the signal having a pulse to the word line WL1 is finished, a gate is applied to the word line WL1. All of the transistors 103 to which the electrodes are connected are turned off. Then, the word line WL2 A signal having a pulse is input to the word line WL3 in sequence, and a memory having the word line WL2 The above-described operation is similarly performed in the memory cell 101 having the word line WL3. is repeated.

[0148] Next, the operation of the storage unit 200 when storing data will be described. All the word lines WL1 to WL3 are supplied with a potential at a level at which the transistor 103 is turned off. Specifically, a low-level potential is applied. As described above, the transistor 103 is turned off. Since the current is extremely low, the charge stored in the capacitance element 105 is unlikely to leak, and light blocking is not performed. In comparison with a case where no semiconductor material is used or a case where a semiconductor material such as silicon is used for the transistor 103, , data can be retained for a long period of time.

[0149] Next, the operation of the storage unit 200 when reading data will be described. When reading, as in the case of writing, a signal having a pulse is sequentially applied to the word lines WL1 to WL3. The potential of the pulse, specifically, the high-level potential, is input to the word line WL1. When the voltage is applied to the gate electrode of the transistor 103 connected to the will all be turned on.

[0150] When the transistor 103 is turned on, the stored charge in the capacitor 105 is transferred through the data line DL. The charge is then extracted. By reading the difference in the amount of charge, data can be read out. It is possible.

[0151] A read circuit is connected to the end of each data line DL, and the output signal of the read circuit contains the data actually read from the store.

[0152] In this embodiment, each operation of writing, holding, and reading is performed on a plurality of memory cells 101. In the above, a driving method in which the driving is performed in sequence has been described, but the present invention is not limited to this configuration. Alternatively, the above operation may be performed only in the memory cell 101 at the specified address.

[0153] In the case of the storage unit 200 shown in FIG. 6, each memory cell 101 is provided with a data line DL and a word line The three wirings are a wiring for supplying a fixed potential to the electrode of the capacitance element 105 and a wiring for supplying a fixed potential to the electrode of the capacitance element 105. However, in one embodiment of the present invention, the wiring of each memory cell is connected. The number of the transistors is not limited to the above. A signal for controlling the charge amount of the capacitance element 105 and a fixed potential are supplied to the memory cell 101. Moreover, the amount of charge stored in the capacitor 105 can be included as information. The number of wirings and the connection structure can be appropriately determined so that the potential to be transmitted to the driving circuit can be sent. That's good.

[0154] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0155] (Embodiment 5) In this embodiment, a specific configuration of the storage unit and its operation will be described.

[0156] FIG. 7 is a circuit diagram of a memory unit 201 having a plurality of memory cells 101 shown in FIG. The configuration of the memory cell 101 is shown in FIG. I can pour drinks.

[0157] In the memory section 201 shown in FIG. 7, a plurality of first word lines WLa, a plurality of second word lines WLb, Various wiring such as multiple data lines DL is provided, and signals or fixed voltages from the drive circuit are transmitted. The number of the above-mentioned wirings is determined by the number of the memory cells. This can be determined by the number and arrangement of the modules 101.

[0158] Specifically, in the case of the storage unit 201 shown in FIG. 7, memory cells of 3 rows and 3 columns are connected in a matrix. The first word lines WLa1 to WLa3, the second word lines WLb1 to WLb3, and the 2 shows an example in which the data lines DL1 to DL3 are arranged in the storage unit 201.

[0159] Next, the operation of the memory unit 201 shown in Fig. 7 will be described. WLa1 to WLa3, a plurality of second word lines WLb1 to WLb3, a plurality of data lines DL1 to 8 is a timing chart showing the time change of the potential of the signal input to DL3. In the timing chart, the transistors 102 and 103 are both n-channel types. This shows an example of a case where binary data is handled.

[0160] In addition, the potential of the signal in the timing chart rises or falls vertically. However, the actual signal potential is affected by the wiring load, noise, etc. It will be easily understood by those skilled in the art that the waveform becomes dull due to the increase in the frequency.

[0161] First, the operation of the storage unit 201 when writing data will be described. In this case, when a signal having a pulse is input to the first word line WLa1, the potential of the pulse Specifically, a high-level potential is applied to the transistor connected to the first word line WLa1. The gate electrode of the first word line WLa1 is connected to the gate electrode of the second word line WLa2. On the other hand, the transistors 103 connected to the second word lines WLb1 to WLb 3 is given a low level potential.

[0162] Next, signals including data as information are input to the data lines DL1 to DL3. The potential levels of the signals input to the lines DL1 to DL3 naturally differ depending on the contents of the data. The potentials input to the data lines DL1 to DL3 are applied via the on-transistor 103. The potential is applied to a gate electrode of the transistor 102 and one electrode of the capacitor 104 . Then, the gate capacitance of the transistor 102 and the capacitance element 104 are changed according to the potential of the signal. The amount of charge stored in the memory cell 101 is controlled to write data to the memory cell 101. can be.

[0163] When the input of the signal having a pulse to the first word line WLa1 is completed, the first word line WL All the transistors 103 whose gate electrodes are connected to a1 are turned off. A signal having a pulse is input to the first word line WLa2 and the first word line WLa3 in this order. A memory cell 101 having a first word line WLa2, a memory cell 102 having a first word line WLa3 In the loop 101, the above-mentioned operations are repeated in the same manner.

[0164] Next, the operation of the storage unit 201 when storing data will be described. In all the first word lines WLa1 to WLa3, a level at which the transistor 103 is turned off is applied. The transistor 103 is supplied with a potential of a low level, specifically, a potential of a low level. Since the off-state current is extremely low, the gate capacitance of the transistor 102 and the capacitance of the capacitor 104 The accumulated charge is unlikely to leak, and if light is not blocked or if the semiconductor is silicon or other The data can be retained for a longer period of time compared to when the material is used for the transistor 103. This can be done.

[0165] On the other hand, the second word lines WLb1 to WLb3 continue to be supplied with a low-level potential. .

[0166] Next, the operation of the storage unit 201 when reading data will be described. During read, a low-level potential is input to all of the first word lines WLa1 to WLa3. As a result, a low-level potential is applied to the gate electrode of the transistor 103. The transistors 103 each having a gate electrode connected to one of the word lines WLa1 to WLa3 are and remains off.

[0167] On the other hand, a signal having a pulse is input to the second word line WLb1, and the potential of the pulse is Specifically, a high-level potential is applied to the other electrode of the capacitor 104. The potential difference between the pair of electrodes of 04 is maintained according to the law of conservation of charge, so the second The change in potential of the gate line WLb1 is applied to the gate electrode of the transistor 102. The threshold voltage of the transistor 102 changes depending on the amount of charge stored in its gate capacitance. Therefore, the transistor 102 has a gate capacitance corresponding to the amount of charge stored in the gate capacitance. Therefore, the magnitude of the drain current of the transistor 102 is By reading the difference in the amount of charge stored in the data line DL, data can be read from the data line DL. It can be seen.

[0168] When the input of the pulsed signal to the second word line WLb1 is completed, the second word line WL All the transistors 102 of the memory cells 101 having b1 are turned off. A pulse signal is input to the first word line WLb2 and the second word line WLb3 in this order. A memory cell 101 having a first word line WLb2, a memory cell 102 having a second word line WLb3 At 01, the above operations are repeated in the same manner.

[0169] A read circuit is connected to the data lines DL1 to DL3. The output signal contains the data actually read from the storage unit 201 .

[0170] In this embodiment, each operation of writing, holding, and reading is performed on a plurality of memory cells 101. In the above, a driving method in which the driving is performed in sequence has been described, but the present invention is not limited to this configuration. Alternatively, the above operation may be performed only in the memory cell 101 at the specified address.

[0171] In the case of the memory unit 201 shown in FIG. 7, each memory cell 101 is provided with a first word line WLa and In order to supply a fixed potential to the second word line WLb, the data line DL, and the transistor 102, In the illustrated example, four wirings are connected to the wiring for the first wiring. The number of wirings in each memory cell is not limited to this. A signal for controlling the gate capacitance of the transistor 102 and a signal for controlling the amount of charge stored in the gate capacitance of the transistor 102 are A signal for reading and a fixed potential can be supplied to the memory cell 101, and The potential, which includes information on the amount of charge stored in the gate capacitance, can be sent to the drive circuit. The number of wirings and the connection structure should be appropriately determined so that the required number of wirings can be achieved.

[0172] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0173] (Embodiment 6) FIG. 9 is a block diagram illustrating an example of a configuration of a memory device according to one embodiment of the present invention. The memory device 300 shown in FIG. 1 includes a memory section 301 having a plurality of memory cells, and and a drive circuit 302 for controlling the operation of the

[0174] The driving circuit 302 writes data to the storage unit 301 and reads data from the storage unit 301. The various operations such as reading data from the memory unit 301 and storing data in the memory unit 301 are performed according to signals from the control circuit. This can be controlled.

[0175] In FIG. 9, the control circuitry that supplies signals to the driving circuitry 302 is not included in the memory device 300. It is assumed that the control circuit is provided outside the storage device 300. may be included in the components of

[0176] Next, a specific example of a configuration of a driver circuit in a memory device according to one embodiment of the present invention will be described. do.

[0177] FIG. 10 is a block diagram illustrating a specific configuration example of a memory device according to one embodiment of the present invention. In the block diagram shown in Figure 10, the circuits in the memory device are classified by function and are mutually Although they are shown as independent blocks, the actual circuit can be completely separated by function. It is difficult, and one circuit may be involved in multiple functions.

[0178] The storage device 300 shown in FIG. 10 includes a storage unit 301 and a driving circuit 302. The circuit 302 is a read circuit that generates a signal including data read from the memory unit 301 as information. A read circuit 303 and a word line driver for selecting the memory cells of the memory unit 301 on a row-by-row basis. A control circuit 304 and a write circuit for writing data to a selected memory cell in the memory unit 301 The drive circuit 302 includes a data line drive circuit 305 for controlling the read circuit. A control circuit for controlling the operation of the word line driving circuit 303, the word line driving circuit 304, and the data line driving circuit 305. It has 306.

[0179] In the memory device 300 shown in FIG. 10, the word line driver circuit 304 is connected to a decoder 307. , a level shifter 308, and a buffer 309. The data line driving circuit 305 includes It includes a decoder 310 , a level shifter 311 , and a selector 312 .

[0180] The storage device 300 according to an embodiment of the present invention includes at least a storage unit 301. Furthermore, the storage device 300 according to one embodiment of the present invention may include a drive circuit for the storage unit 301. The category includes memory modules with some or all of the circuitry 302 connected. The memory module is provided with connection terminals that can be mounted on a printed wiring board, etc. The semiconductor device may be in a so-called packaged state, protected by resin or the like.

[0181] In addition, a storage unit 301, a read circuit 303, a word line driving circuit 304, a data line driving circuit The control circuit 305 and the control circuit 306 may all be formed using a single substrate. One or all of the electrodes may be formed using different substrates.

[0182] If different substrates are used, FPC (Flexible Printed Circuit) In this case, the electrical connection of the driving circuit 302 can be ensured through a A part of it may be connected to the FPC using a COF (Chip On Film) method. Alternatively, the COG (Chip On Glass) method can be used to ensure electrical connection. This can be done.

[0183] A signal AD including the address (Ax, Ay) of the storage unit 301 as information is input to the storage device 300. When the address Ax is input, the control circuit 306 sends the address Ax in the column direction to the data line driving circuit 305. The control circuit 306 also transmits a row address Ay to the word line driver circuit 304. A signal DATA including the data input to the storage device 300 as information is transmitted to a data line driving circuit Send to 305.

[0184] The selection of the data write operation or read operation in the memory unit 301 is performed by the control circuit 306. The supplied signals RE (Read enable) and WE (Write enable In addition, when there are multiple storage units 301, the control circuit 306 A signal CE (Chip enable) for selecting the storage unit 301 is input to the In this case, the operation selected by the signals RE and WE may be selected by the signal CE. The program is executed in the storage unit 301 .

[0185] In the memory unit 301, when a write operation is selected by the signal WE, the control circuit 306 In response to the instruction, the decoder 307 in the word line driving circuit 304 reads the address A A signal is generated to select the memory cell corresponding to y. The signal is generated by a level shifter After the amplitude is adjusted by 308, the waveform is processed in buffer 309 and stored in memory 3 On the other hand, in the data line driving circuit 305, according to an instruction from the control circuit 306, Thus, among the memory cells selected by the decoder 310, the memory cell corresponding to the address Ax A signal for selecting a memory cell is generated. The signal is shifted by a level shifter 311. After the amplitude is adjusted, the signal is input to the selector 312. The signal DATA is sampled according to the signal, and the memory cell corresponding to the address (Ax, Ay) is The sampled signal is input to the

[0186] In addition, in the memory unit 301, when a read operation is selected by the signal RE, the control circuit 30 In accordance with the instruction from 6, the decoder 307 of the word line driving circuit 304 A signal is generated to select the memory cell corresponding to address Ay. The signal has a level After the amplitude is adjusted by the shifter 308, the waveform is processed and stored in the buffer 309. On the other hand, in the read circuit 303, the control circuit 306 Therefore, among the memory cells selected by the decoder 307, the memory cell corresponding to the address Ax Then, the data stored in the memory cell corresponding to the address (Ax, Ay) is selected. The data stored in the memory is read out and a signal containing the data as information is generated.

[0187] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0188] (Embodiment 7) In this embodiment, an example of a specific configuration of the readout circuit will be described.

[0189] The potential read from the memory section is determined according to the data written in the memory cell. Therefore, ideally, the same digital value of data is stored in multiple memory cells. If this is the case, the potentials read from multiple memory cells should all be at the same level. However, in reality, the transistors that function as memory elements or the transistors that are used for reading data The characteristics of the transistors that function as switching elements in the memory cells vary. In this case, even if all the data to be read out is the same digital value, However, the potential actually read out varies, and the distribution has a certain range. Even if there is some variation in the potential read from the memory, accurate data is stored as information. and a readout circuit that produces a signal whose amplitude and waveform have been processed to meet desired specifications. It is desirable to provide a path in the drive circuit.

[0190] FIG. 11 is a circuit diagram showing an example of a readout circuit. The readout circuit shown in FIG. A switching circuit for controlling the input of the potential Vdata read from the A transistor 260 functioning as an element and a transistor 261 functioning as a resistor are 11 also includes an operational amplifier 262.

[0191] Specifically, the transistor 261 has a gate electrode and a drain electrode (or drain region) is connected, and a high level is applied to the gate electrode and the drain electrode. The transistor 261 has a source electrode connected to the op amp. The transistor 261 is connected to the non-inverting input terminal (+) of the amplifier 262. , a node to which the power supply potential Vdd is applied, and the non-inverting input terminal (+) of the operational amplifier 262 In FIG. 11, the gate electrode and the drain electrode are connected to each other, and function as a resistor. In the above embodiment, a transistor having a connected pole is used as a resistor, but the present invention is not limited to this. Any element that functions as such can be substituted.

[0192] In addition, the transistor 260 that functions as a switching element has a gate electrode connected to the bit line B L1 to BL3 are connected to the bit lines BL1 to BL3, respectively. Thus, the supply of the potential Vdata to the source electrode of the transistor 260 is controlled.

[0193] For example, when the transistor 260 connected to the bit line BL1 is turned on, the potential Vdat a and the power supply potential Vdd are resistively divided by transistors 260 and 261. The potential obtained by this is given to the non-inverting input terminal (+) of the operational amplifier 262. Since the level of the power supply potential Vdd is fixed, the level of the potential obtained by resistive division is The level of the potential Vdata, that is, the digital value of the read data, is reflected in is.

[0194] On the other hand, the inverting input terminal (-) of the operational amplifier 262 is supplied with a reference potential Vref. And the potential applied to the non-inverting input terminal (+) is higher than the reference potential Vref. Depending on whether the output terminal potential Vout is low or high, the level of the output terminal potential Vout can be made different. It is possible to indirectly obtain a signal containing data as information.

[0195] Note that even if the same data value is stored in memory cells, there may be variations in the characteristics between the memory cells. Due to the variation, the level of the read potential Vdata also varies, and the distribution becomes wider. Therefore, the level of the reference potential Vref is important for reading the data value accurately. In order to achieve this, the variation in the node potential Vdata is taken into consideration.

[0196] Also, since FIG. 11 shows an example of a read circuit that handles binary digital values, The operational amplifiers used to read the data are connected to the nodes to which the potential Vdata is applied. However, the number of operational amplifiers is not limited to this. When dealing with data, the number of operational amplifiers for the node to which the potential Vdata is applied is n- Let's say it's 1.

[0197] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0198] (Embodiment 8) In this embodiment, an example of calculating the off-state current of a transistor will be described.

[0199] First, the configuration of the characteristic evaluation circuit used to calculate the off-state current will be described with reference to FIG. In this embodiment, the characteristic evaluation circuit includes a plurality of measurement systems 801 connected in parallel to each other. Specifically, in FIG. 12, eight measurement systems 801 are connected in parallel to form a characteristic evaluation circuit. It illustrates the path.

[0200] The measurement system 801 includes a transistor 811, a transistor 812, a capacitance element 813, and a It includes a transistor 814 and a transistor 815 .

[0201] The transistor 811 is a charge injection transistor. , its first terminal is connected to a node to which potential V1 is applied, and its second terminal is , is connected to the first terminal of the transistor 812. The gate electrode of the transistor 811 is , is connected to a node to which a potential Vext_a is applied.

[0202] The transistor 812 is a transistor for evaluating leakage current. The leakage current includes the off-state current of the transistor. 2 has a first terminal connected to the second terminal of the transistor 811, and a second terminal The gate voltage of the transistor 812 is connected to a node to which a potential V2 is applied. The pole is connected to a node to which a potential Vext_b is applied.

[0203] The first electrode of the capacitor 813 is connected to the second terminal of the transistor 811 and the second terminal of the transistor 812. A second electrode of the capacitor 813 is connected to a first terminal of the capacitor 813. A potential V2 is applied to the second electrode of the capacitor 813. It is connected to a node that is

[0204] The transistor 814 has a first terminal connected to a node to which a potential V3 is applied. The second terminal of the transistor 815 is connected to the first terminal of the transistor 815. The gate electrode of 814 is connected to the second terminal of the transistor 811 and the first terminal of the transistor 812. The gate of the transistor 814 is connected to the first electrode of the capacitor element 813. The point where the output electrode is connected is referred to as node A.

[0205] The first terminal of the transistor 815 is connected to the second terminal of the transistor 814. The second terminal of the transistor is connected to a node to which a potential V4 is applied. The gate electrode of 815 is connected to a node to which a potential Vext_c is applied.

[0206] The measurement system 801 includes a second terminal of the transistor 814 and a first terminal of the transistor 815. The potential of the node to which the terminal is connected is output as the potential Vout of the output signal.

[0207] In this embodiment, the transistor 811 includes an oxide semiconductor in an active layer. Furthermore, the size of the channel formation region included in the active layer is the channel length L = 10 μm, A transistor with a panel width W=10 μm is used.

[0208] The channel formation region is a region in the semiconductor film between the source electrode and the drain electrode. , which corresponds to a region overlapping with the gate electrode with the gate insulating film sandwiched therebetween.

[0209] The transistors 814 and 815 each include an oxide semiconductor in an active layer. Furthermore, the size of the channel formation region included in the active layer is the channel length L = 3 μm, A transistor with a panel width W=100 μm is used.

[0210] The transistor 812 includes an oxide semiconductor in an active layer and has a source The source electrode and the drain electrode are in contact with each other, and the gate electrode and the source electrode and the drain electrode are overlapped with each other. A bottom-gate transistor with a 1 μm-wide offset region without a burlap region. By providing an offset region, the parasitic capacitance can be reduced. Further, as the transistor 812, a channel formation region included in an active layer is Transistors having different sizes are used, as shown in Conditions 1 to 6 of Table 1.

[0211] [Table 1]

[0212] In addition, when the charge injection transistor 811 is not provided in the measurement system 801, the capacitance element 81 When injecting charge into the transistor 812, the transistor 812 for evaluating leakage current must be turned on once. In this case, the leakage current evaluation transistor 812 is in a steady state of being turned on and off. If the device requires time to measure, it will take time. The transistor 811 for use and the transistor 812 for leak current evaluation are separately connected to a measurement system 80. 1, the leakage current evaluation transistor 812 is always turned on during charge injection. Therefore, the time required for measurement can be shortened.

[0213] In addition, the charge injection transistor 811 and the leakage current evaluation transistor 812 are measured. By providing each transistor separately in the system 801, the size of each transistor can be appropriately adjusted. In addition, the channel width W of the leakage current evaluation transistor 812 can be set to the width W of the charge injection transistor 812. By making the channel width W of the transistor 811 larger, the transistor for evaluating leakage current The leakage current components in the characteristic evaluation circuit other than the leakage current of the resistor 812 are relatively small. As a result, the leakage current of the leakage current evaluation transistor 812 can be measured with high accuracy. At the same time, the leakage current evaluation transistor 8 Since there is no need to turn on 12 once, some of the charge in the channel formation region flows to node A. There is no effect of the potential fluctuation of node A due to the inclusion of

[0214] On the other hand, the channel width W of the charge injection transistor 811 is set to By making the channel width W of the charge injection transistor 811 smaller than that of the charge injection transistor 812, In addition, the peak current in the channel formation region can be relatively small during charge injection. The effect of the potential fluctuation at node A caused by a part of the charge flowing into node A is also small.

[0215] In addition, as shown in FIG. 12, by connecting multiple measurement systems 801 in parallel, This allows for more accurate calculation of the leakage current of the characteristic evaluation circuit.

[0216] Next, a specific method for calculating the off-state current of a transistor using the characteristic evaluation circuit shown in FIG. This article explains:

[0217] First, the method for measuring the leakage current of the characteristic evaluation circuit shown in FIG. 12 will be described with reference to FIG. 13. FIG. 13 is a diagram for explaining a leakage current measuring method using the characteristic evaluation circuit shown in FIG. 2 is a timing chart.

[0218] The leakage current measurement method using the characteristic evaluation circuit shown in FIG. The operation during each period is explained below. During both the pulse width and the hold period, the potentials V2 and V4 are set to 0 V, the potential V3 is set to 5 V, and the potential Set Vext_c to 0.5V.

[0219] First, in the writing period, the potential Vext_b is set to 0 so that the transistor 812 is turned off. The potential V1 is set to a write potential Vw. After that, the potential Vext_a is set to a potential level such that the transistor 811 is turned on for a certain period of time. VH (5V). With the above configuration, charge is accumulated at node A, and the potential of node A The potential Vext_a is then set to a value equal to the write potential Vw. The potential VL is set to a level such that the potential 11 is turned off. Then, the potential V1 is set to the potential VSS (0 V).

[0220] Next, during the hold period, the charge stored in node A changes. The amount of change in potential is measured. From the amount of change in potential, the first terminal and the second terminal of the transistor 812 are determined. The current flowing between the nodes can be calculated. It is possible to measure the amount of change in the potential of node A.

[0221] Accumulating charge at node A and measuring the change in potential at node A (also called the accumulation and measurement operation) First, the first accumulation and measurement operation is repeated 15 times. In the measurement operation, a potential of 5 V is input as the write potential Vw during the write period, and The second accumulation and measurement are then repeated twice. In the measurement operation, the write potential Vw is set to 3.5 V during the write period and 50 h during the hold period. Then, the third accumulation and measurement operation is performed once. In the write period, the write potential Vw is set to 4.5 V, and the hold period is set to 10 hours. By repeating the accumulation and measurement operations, the measured current value becomes the value in the steady state. In other words, the current I flowing through node A A Of which, It is possible to eliminate transient currents (current components that decrease over time after the start of measurement) As a result, leakage current can be measured with higher accuracy.

[0222] In general, the potential of node A, V A is expressed as a function of the output signal potential Vout as follows: It is possible.

[0223]

number

[0224] Also, the charge Q at node A A is the potential V of node A. A , capacitance C connected to node A A , fixed Using a constant, the capacitance C connected to node A is expressed as follows: A teeth, This is the sum of the capacitance of the capacitor 813 and the capacitance of the capacitors other than the capacitor 813 .

[0225]

number

[0226] Current I at node A A is the charge flowing into (or out of) node A. Since it is a time derivative, the current I A is expressed as follows:

[0227]

number

[0228] For example, Δt is set to about 54000 sec. The capacitance C connected to node A A and the output signal The current I ASince it is possible to obtain The peak current can be calculated.

[0229] Next, the measurement results of the potential Vout of the output signal by the measurement method using the above-mentioned characteristic evaluation circuit and The leakage current value of the characteristic evaluation circuit calculated from the measurement results is shown.

[0230] FIG. 14 shows, as an example, the above measurements under conditions 1, 2, and 3 (first accumulation and measurement). FIG. 15 shows the relationship between the elapsed time Time and the potential Vout of the output signal. The relationship between the elapsed time Time in the above measurement and the leakage current calculated by the measurement is The output signal potential Vout fluctuates after the measurement starts, and it takes time for the output signal to reach a steady state. It turns out it takes more than 10 hours.

[0231] FIG. 16 shows the potential of node A under conditions 1 to 6 estimated by the above measurements. The relationship between leakage current and the potential at node A is shown in Figure 16. At 0V, the leakage current is 28yA / μm. The leakage current is Since the off-current is also included, the off-current of the transistor 812 is also considered to be 28 yA / μm or less. It is possible.

[0232] As described above, the present invention can be implemented by using a semiconductor device that includes a highly purified oxide semiconductor layer having a function as a channel formation layer. In the characteristic evaluation circuit using a transistor including It can be seen that the off-state current of the transistor is sufficiently small.

[0233] (Embodiment 9) In this embodiment mode, an example of the configuration of an RF tag, which is one of the semiconductor devices of the present invention, will be described. Reveal.

[0234] FIG. 17 is a block diagram showing one embodiment of the RF tag of the present invention. The antenna circuit 551 and the integrated circuit 552 are power supply circuit 553, demodulation circuit 554, modulation circuit 555, regulator 556, and arithmetic circuit 557 , a memory device 558, and a boost circuit 559.

[0235] Next, an example of the operation of the RF tag 550 will be described. The radio waves are converted into AC voltage in the antenna circuit 551. The AC voltage from the antenna circuit 551 is rectified to generate a power supply voltage. The power supply voltage generated in is provided to an arithmetic circuit 557 and a regulator 556. The regulator 556 stabilizes the voltage for the power supply from the power supply circuit 553, or After adjusting the height, the demodulation circuit 554, the modulation circuit 555, the arithmetic circuit 557, a memory device 558, or a boost circuit 559.

[0236] The demodulation circuit 554 demodulates the AC signal received by the antenna circuit 551 and outputs it to the downstream arithmetic circuit The arithmetic circuit 557 performs arithmetic processing according to the signal input from the demodulation circuit 554. When performing the above-mentioned calculation processing, the storage device 558 stores the primary cache. The arithmetic circuit 557 can be used as a flash memory or a secondary cache memory. analyzes the signal input from the demodulation circuit 554 and determines the contents of the command sent from the interrogator. Thus, the output of information in the memory device 558 or the contents of instructions in the memory device 558 The signal output from the arithmetic circuit 557 is encoded and sent to the modulation circuit 555. The modulation circuit 555 modulates the radio wave received by the antenna circuit 551 according to the signal. The radio waves modulated by antenna circuit 551 are received by the interrogator.

[0237] In this way, the communication between the RF tag 550 and the interrogator uses radio waves as a carrier. This is done by modulating the carrier. The carriers are 125kHz, 13.56MHz, and 950MHz. The modulation method also varies depending on the standard, and can be amplitude modulation, frequency modulation, phase modulation, etc. There are various modulation methods, such as 100-MHz modulation, but any modulation method that complies with the standard can be used. .

[0238] The signal transmission method is electromagnetic coupling method, electromagnetic induction method, microwave method, etc. depending on the carrier wavelength. They can be classified into various types, such as:

[0239] The boost circuit 559 boosts the voltage output from the regulator 556 and outputs it to the storage device 558. We are supplying it.

[0240] In one embodiment of the present invention, the memory device 558 has the structure described in the above embodiment. The fact that it is possible to increase the memory capacity per unit area while ensuring the data retention period is achieved Therefore, the RF tag 550 according to one aspect of the present invention has the above-mentioned memory device 558. By using the storage device 558, the reliability of the data can be improved. By doing so, the RF tag 550 can be made smaller and have higher functionality.

[0241] In this embodiment, the configuration of an RF tag 550 having an antenna circuit 551 will be described. However, the RF tag according to one embodiment of the present invention does not necessarily include an antenna circuit as a component. It is not necessary to provide an oscillator circuit or a secondary battery in the RF tag shown in FIG. .

[0242] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0243] (Embodiment 10) In this embodiment, a semiconductor device using a memory device according to one embodiment of the present invention, An example of a strip-type storage medium will be described.

[0244] FIG. 18A shows an example of the configuration of a storage medium according to one embodiment of the present invention. The storage medium shown in A) is a storage device 701 according to one embodiment of the present invention, a drive device, and a storage medium. A connector 702 for electrical connection and a connector 703 for various signals input and output via the connector 702 , an interface 703 that processes signals according to the specifications, and an interface 704 that processes signals according to the operating state of the storage medium, etc. Therefore, the light emitting diode 704 is turned on, and the memory device 701, the interface 703, the light emitting diode 704 ... A controller that controls the operation of various circuits and semiconductor elements in the storage medium, such as a photodiode 704. A roller 705 is mounted on a printed wiring board 706. In addition, a controller A quartz crystal used to generate a clock signal to control the operation of the 705, memory A regulator for controlling the level of the power supply potential in the medium may be provided. stomach.

[0245] The printed wiring board 706 shown in FIG. 18(A) is provided with a connector 7 as shown in FIG. The cover 707 is made of resin or the like so that the 02 and the light emitting diode 704 are partially exposed. It is also possible to provide protection by doing so.

[0246] The storage device 701 according to one aspect of the present invention secures a period for storing data while The storage capacity per unit area can be increased. By using the storage device 701, the reliability of data in such a storage medium can be improved. In addition, by using the storage device 701, the storage medium can be made smaller. .

[0247] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes. EXAMPLES

[0248] By using the semiconductor device according to one embodiment of the present invention, highly reliable electronic devices and highly functional electronic devices can be provided. It is possible to provide an electronic device that

[0249] The semiconductor device according to one embodiment of the present invention is applicable to a display device, a notebook personal computer, a recording medium, Image playback device equipped with a medium (typically DVD: Digital Versatile (Devices with a display that can play back recording media such as discs and display the images) In addition, a semiconductor device according to one embodiment of the present invention can be used in a power As child devices, mobile phones, portable game consoles, personal digital assistants, electronic books, video cameras, Digital still camera, goggle-type display (head-mounted display), navigation systems, audio playback devices (car audio, digital audio players, etc.) , copiers, facsimiles, printers, printer-combination machines, automated teller machines (A TM), vending machines, etc. Specific examples of these electronic devices are shown in Figure 19.

[0250] FIG. 19A shows a portable game machine. The portable game machine includes a housing 7031, a housing 7032, a display portion 7033, A display unit 7034, a microphone 7035, a speaker 7036, an operation key 7037, a star The semiconductor device according to one embodiment of the present invention is a driving circuit for a portable game machine. The present invention can be used in an integrated circuit for controlling a portable game machine. By using a semiconductor device according to one embodiment of the present invention for an integrated circuit of a portable game device, a highly reliable portable game device can be realized. It is possible to provide a portable game machine with high functionality. The portable game machine has two display units 7033 and 7034. The number of display units that the game machine has is not limited to this.

[0251] FIG. 19B shows a mobile phone. The mobile phone includes a housing 7041, a display unit 7042, an audio input unit 7043, The device has a voice output unit 7044, an operation key 7045, a light receiving unit 7046, etc. By converting the light received in the sensor into an electrical signal, an external image can be captured. The semiconductor device according to one embodiment of the present invention can be used in an integrated circuit for controlling the operation of a mobile phone. The semiconductor device according to one aspect of the present invention can be used in an integrated circuit for controlling the operation of a mobile phone. By using this device, it is possible to provide highly reliable mobile phones and mobile phones with advanced functions. Cut.

[0252] FIG. 19C shows a portable information terminal, which includes a housing 7051, a display unit 7052, and operation keys 7053. The portable information terminal shown in FIG. 19C has a modem built in a housing 7051. The semiconductor device according to one embodiment of the present invention may be a semiconductor device for controlling the driving of a portable information terminal. The present invention can be used in an integrated circuit for controlling the operation of a portable information terminal. By using the semiconductor device according to one embodiment, a highly reliable portable information terminal, a highly functional portable information terminal, It is possible to provide a portable information terminal.

[0253] This embodiment can be implemented in appropriate combination with any of the above embodiment modes. [Explanation of symbols]

[0254] 101 Memory Cell 102 Transistor 103 Transistor 104 Capacitive element 105 Capacitive element 106 Transistor 110 Substrate 111 Insulating film 112 Electrode 113 Insulating film 114 Electrode 115 Gate electrode 116 Insulating film 117 Active layer 118 Source Electrode 119 Drain electrode 120 Insulating film 121 Insulating film 122 Insulating film 123 Wiring 130 Conductive Film 131 Conductive Film 132 Active layer 133 Insulating Film 134 Gate electrode 135 Conductive Film 136 Active layer 137 Gate electrode 138 Contact Hole 139 Insulating Film 140 Contact Hole 141 Conductive Film 142 Contact Hole 143 Contact Hole 144 Conductive Film 150 Gate electrode 151 Insulating film 152 Active layer 153 Channel protection film 154 Source Electrode 155 Drain electrode 156 Insulating Film 160 Gate electrode 161 Insulating film 162 Active layer 164 Source Electrode 165 Drain electrode 166 Insulating Film 200 Storage section 201 Storage section 260 Transistors 261 Transistor 262 Operational Amplifier 300 storage device 301 Storage section 302 Drive circuit 303 Readout circuit 304 Word line driver circuit 305 Data line driver circuit 306 Control Circuit 307 Decoder 308 Level Shifter 309 Buffer 310 Decoder 311 Level Shifter 312 Selector 550 RF Tag 551 Antenna Circuit 552 Integrated Circuits 553 Power supply circuit 554 Demodulation Circuit 555 Modulation Circuit 556 Regulator 557 Arithmetic circuit 558 Storage device 559 Boost Circuit 701 Storage device 702 Connector 703 Interface 704 Light Emitting Diode 705 Controller 706 Printed Wiring Board 707 Cover material 801 Measurement System 811 Transistor 812 Transistor 813 Capacitive element 814 Transistor 815 Transistor 7031 Case 7032 Case 7033 Display section 7034 Display section 7035 Microphone 7036 Speaker 7037 Operation Key 7038 Stylus 7041 Case 7042 Display section 7043 Audio input section 7044 Audio output section 7045 Operation key 7046 Light receiving section 7051 Case 7052 Display section 7053 Operation key

Claims

1. a capacitance element, a first transistor, and a second transistor; one of a source electrode and a drain electrode of the first transistor is always electrically connected to a gate electrode of the second transistor; the capacitance element includes a first electrode, an insulating film having a region on the first electrode, and a second electrode having a region on the insulating film; a second electrode of the capacitor element has a region in contact with a first conductive film functioning as one of a source electrode and a drain electrode of the first transistor, a channel formation region of the first transistor is above the capacitance element and has a region overlapping the capacitance element, an oxide semiconductor layer; the oxide semiconductor layer includes a channel formation region of the first transistor, The semiconductor device, in a cross-sectional view taken in a channel length direction of the first transistor, includes a bending point in the oxide semiconductor layer.

2. a capacitance element, a first transistor, and a second transistor; one of a source electrode and a drain electrode of the first transistor is always electrically connected to a gate electrode of the second transistor; the capacitance element includes a first electrode, an insulating film having a region on the first electrode, and a second electrode having a region on the insulating film; a second electrode of the capacitor element has a region in contact with a first conductive film functioning as one of a source electrode and a drain electrode of the first transistor, a channel formation region of the first transistor is above the capacitance element and has a region overlapping the capacitance element, an oxide semiconductor layer and a first insulating layer; the oxide semiconductor layer includes a channel formation region of the first transistor, the first insulating layer has a region in contact with the oxide semiconductor layer, the first insulating layer comprises silicon and oxygen; The semiconductor device, in a cross-sectional view taken in a channel length direction of the first transistor, includes a bending point in the oxide semiconductor layer.

3. a capacitance element, a first transistor, and a second transistor; one of a source electrode and a drain electrode of the first transistor is always electrically connected to a gate electrode of the second transistor; the capacitance element includes a first electrode, an insulating film having a region on the first electrode, and a second electrode having a region on the insulating film; a second electrode of the capacitor element has a region in contact with a first conductive film functioning as one of a source electrode and a drain electrode of the first transistor, a channel formation region of the first transistor is above the capacitance element and has a region overlapping the capacitance element, an oxide semiconductor layer, a first insulating layer, and a second insulating layer; the oxide semiconductor layer includes a channel formation region of the first transistor, the first insulating layer has a region between the oxide semiconductor layer and the second insulating layer, the first insulating layer comprises silicon and oxygen; the second insulating layer comprises silicon and nitrogen; The semiconductor device, in a cross-sectional view taken in a channel length direction of the first transistor, includes a bending point in the oxide semiconductor layer.

4. In any one of claims 1 to 3, The oxide semiconductor layer includes In, Ga, and Zn.

5. In any one of claims 1 to 3, The oxide semiconductor layer is In-Zn-O.

6. a capacitance element, a first transistor, and a second transistor; one of a source electrode and a drain electrode of the first transistor is always electrically connected to a gate electrode of the second transistor; the capacitance element includes a first electrode, an insulating film having a region on the first electrode, and a second electrode having a region on the insulating film; a second electrode of the capacitor element has a region in contact with a first conductive film functioning as one of a source electrode and a drain electrode of the first transistor, a channel formation region of the first transistor is above the capacitance element and has a region overlapping the capacitance element, an oxide semiconductor layer; the oxide semiconductor layer includes a channel formation region of the first transistor, the oxide semiconductor layer is In—O; The semiconductor device, in a cross-sectional view taken in a channel length direction of the first transistor, includes a bending point in the oxide semiconductor layer.

7. a capacitance element, a first transistor, and a second transistor; one of a source electrode and a drain electrode of the first transistor is always electrically connected to a gate electrode of the second transistor; the capacitance element includes a first electrode, an insulating film having a region on the first electrode, and a second electrode having a region on the insulating film; a second electrode of the capacitor element has a region in contact with a first conductive film functioning as one of a source electrode and a drain electrode of the first transistor, a channel formation region of the first transistor is above the capacitance element and has a region overlapping the capacitance element, an oxide semiconductor layer and a first insulating layer; the oxide semiconductor layer includes a channel formation region of the first transistor, the first insulating layer has a region in contact with the oxide semiconductor layer, the oxide semiconductor layer is In—O; the first insulating layer comprises silicon and oxygen; The semiconductor device, in a cross-sectional view taken in a channel length direction of the first transistor, includes a bending point in the oxide semiconductor layer.

8. a capacitance element, a first transistor, and a second transistor; one of a source electrode and a drain electrode of the first transistor is always electrically connected to a gate electrode of the second transistor; the capacitance element includes a first electrode, an insulating film having a region on the first electrode, and a second electrode having a region on the insulating film; a second electrode of the capacitor element has a region in contact with a first conductive film functioning as one of a source electrode and a drain electrode of the first transistor, a channel formation region of the first transistor is above the capacitance element and has a region overlapping the capacitance element, an oxide semiconductor layer, a first insulating layer, and a second insulating layer; the oxide semiconductor layer includes a channel formation region of the first transistor, the first insulating layer has a region between the oxide semiconductor layer and the second insulating layer, the oxide semiconductor layer is In—O; the first insulating layer comprises silicon and oxygen; the second insulating layer comprises silicon and nitrogen; The semiconductor device, in a cross-sectional view taken in a channel length direction of the first transistor, includes a bending point in the oxide semiconductor layer.

9. In any one of claims 1 to 8, The off-state current density of the first transistor is 100 zA / μm or less.

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