Semiconductor device

Abstract

To provide a memory device having gain cell type memory cells and capable of storing a large amount of data per unit area.SOLUTION: A peripheral circuit of a memory device is formed using a transistor formed on a semiconductor substrate, and a memory cell of the memory device is formed using a thin film transistor. By stacking a plurality of layers including thin film transistors forming memory cells above the semiconductor substrate, the amount of data that can be stored per unit area can be increased. In addition, by using an OS transistor with a very small off-current as a thin film transistor, the capacitance of a capacitive element that accumulates electric charge can be reduced. In other words, the area of the memory cell can be reduced.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a memory device. In particular, a memory device that can function by utilizing semiconductor characteristics. Related to storage devices.

[0002] Another embodiment of the present invention relates to a semiconductor device. This refers to any device that can function by utilizing the properties of semiconductors. For example, integrated circuits, Chips equipped with such devices, electronic components that house chips in packages, and electronic devices equipped with integrated circuits , which is an example of a semiconductor device.

[0003] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field relates to products, methods, or manufacturing methods. is a process, machine, manufacture, or composition of matter. This concerns the issue of the [Background technology]

[0004] DRAM (Dynamic Random Access Memory) is a It is widely used as a storage device (also called memory) built into devices. A memory cell consists of one transistor and one capacitance element, and DRAM is a It is a memory that stores data by accumulating charges.

[0005] A DRAM memory cell may be composed of two transistors and one capacitance element. By amplifying the charge stored in the capacitor by a nearby transistor, the The gain cell type memory cell can operate as a gain cell.

[0006] In addition, in a region where a channel of a transistor is formed (hereinafter also referred to as a channel formation region), Transistors containing metal oxide (also called oxide semiconductor transistors or OS transistors) In recent years, OS transistors have attracted attention because It is used in DRAM memory cells because its drain current (also called off current) is very small. This allows the charge stored in the capacitance element to be held for a long period of time.

[0007] Since the OS transistor is a thin film transistor, it can be provided in a stacked structure. For example, A first circuit is formed using a Si transistor formed on a single crystal silicon substrate, A second circuit can be constructed above using OS transistors. By using this for DRAM, for example, the first circuit can be a peripheral circuit such as a driver circuit or a control circuit. The memory cell can be configured as a second circuit, which reduces the chip area of ​​the DRAM. It is possible.

[0008] In Patent Document 1, a plurality of OS transistors are formed on a semiconductor substrate on which peripheral circuits are formed. An example of a semiconductor device having a memory cell is disclosed in Patent Document 2. The gain cell is a transistor other than the OS transistor (e.g., a Si transistor). An example of using the same in a memory cell (wherein the capacitive element may be omitted) is disclosed.

[0009] In this specification and the like, a memory cell having a gain cell type memory cell using an OS transistor is The memory device or semiconductor device is referred to as NOSRAM (registered trademark, Nonvolatile Oxi It is called the 10Gb / s Semiconductor Random Access Memory (10Gb / s). Oink. [Prior art documents] [Patent documents]

[0010] [Patent Document 1] JP 2012-256820 A [Patent Document 2] JP 2012-256400 A Summary of the Invention [Problem to be solved by the invention]

[0011] In DRAM, a gain cell type memory cell transfers the accumulated charge to a nearby transistor. Since the capacitance of the capacitor can be reduced, the capacitance of the transistor can be reduced. By using the gate capacitance and the parasitic capacitance of the wiring, it is not necessary to create a capacitance element (capacitance (quantum elements may be omitted).

[0012] However, the gain cell type memory cell has at least two transistors per memory cell. This makes it difficult to increase the number of memory cells that can be placed per unit area (placement density). In other words, by increasing the density of memory cells, There was a problem that it was difficult to increase memory density (the amount of data that can be stored per unit area). Ta.

[0013] According to one embodiment of the present invention, in a memory device having gain cell type memory cells, One of the objectives of the present invention is to provide a storage device that can store a large amount of data. One aspect of the invention is a memory cell having a gain cell type memory cell, and a data storage capacity per unit area. It is an object of the present invention to provide an electronic device having a large amount of storage device.

[0014] Note that one embodiment of the present invention does not necessarily have to solve all of the above problems, but at least It is enough if it can solve one problem. Also, the description of the problem above may be subject to the existence of other problems. Problems other than these are not limited to the description of the specification, claims, drawings, etc. This becomes self-evident from the description, claims, drawings, etc. It is possible to extract issues other than these. [Means for solving the problem]

[0015] One aspect of the present invention is a semiconductor device having a semiconductor substrate and first to lth layers (l is an integer of 1 or more). The semiconductor substrate is a peripheral circuit using transistors formed on the semiconductor substrate. A thin film transistor formed on the kth layer is formed on the kth layer (k is an integer of 1 to l). The transistors are used to form a memory cell array. The first layer is located above the semiconductor substrate. The jth layer (j is an integer between 2 and 1) is stacked on top of the j-1th layer. It will be established as follows.

[0016] Further, one embodiment of the present invention is a semiconductor device having a semiconductor substrate and first to lth layers (l is an integer of 1 or more). The semiconductor substrate is a memory device using transistors formed on the semiconductor substrate. A peripheral circuit is formed, and the kth layer (k is an integer of 1 to l) has a A memory cell array is constructed using thin film transistors. Each of the memory cells includes a first thin film transistor and a second thin film transistor. The first layer is stacked above the semiconductor substrate, and has a jth (j is 2 The j-1th layer (an integer equal to or larger than 1) is stacked above the j-1th layer.

[0017] Further, one embodiment of the present invention is a semiconductor device having a semiconductor substrate and first to lth layers (l is an integer of 1 or more). The semiconductor substrate is a memory device using transistors formed on the semiconductor substrate. A peripheral circuit is formed, and the kth layer (k is an integer of 1 to l) has a A memory cell array is formed using thin film transistors. The peripheral circuits are the first to the second A word line driver circuit and a bit line driver circuit are provided in the kth layer. The recell array is electrically connected to the kth word line driver circuit, and the memory cell array , which are electrically connected to the bit line driver circuit. The jth layer (j is an integer between 2 and 1) is stacked on top of the j-1th layer. The layers are provided.

[0018] Further, one embodiment of the present invention is a semiconductor device having a semiconductor substrate and first to lth layers (l is an integer of 1 or more). The semiconductor substrate is a memory device using transistors formed on the semiconductor substrate. A peripheral circuit is formed, and the kth layer (k is an integer of 1 to l) has a A memory cell array is formed using thin film transistors. The peripheral circuits are the first to the second A word line driver circuit and a bit line driver circuit are provided in the kth layer. The recell array is electrically connected to the kth word line driver circuit, and the memory cell array , each electrically connected to a bit line driver circuit. The memory cell includes a first thin film transistor and a second thin film transistor. The first layer is stacked above the semiconductor substrate, and includes a jth (j is 2 or more) The j-1th layer (an integer equal to or smaller than l) is stacked above the j-1th layer.

[0019] In the above embodiment, the thin film transistor has a metal oxide in a channel formation region. .

[0020] In the above embodiment, the thin film transistors each have a front gate and a back gate. It has.

[0021] In the above embodiment, the thin film transistor has a metal oxide in a channel formation region, Each of the thin film transistors has a front gate and a back gate. Effect of the Invention

[0022] According to one embodiment of the present invention, in a memory device having a gain cell type memory cell, It is possible to provide a storage device capable of storing a large amount of data per unit time. In one embodiment, the memory cell has a gain cell type memory cell, and the amount of data that can be stored per unit area is It is possible to provide an electronic device having a memory device with a large capacity.

[0023] The description of these effects does not preclude the existence of other effects. A form does not necessarily have to have all of these effects. Effects other than these may be included in the description. The above will be obvious from the description, claims, drawings, etc. Other effects can be extracted from the claims, drawings, etc. [Brief description of the drawings]

[0024] [Figure 1] FIG. 1 is a perspective view showing a configuration example of a storage device. [Diagram 2]FIG. 2 is a schematic perspective view showing a configuration example of the storage device. [Diagram 3] FIG. 3 is a block diagram illustrating an example of the configuration of a storage device. [Figure 4] FIG. 4 is a block diagram showing an example of the configuration of a memory cell array. [Diagram 5] 5A and 5B are circuit diagrams showing configuration examples of a memory cell. [Figure 6] FIG. 6 is a circuit diagram showing a configuration example of a circuit that constitutes a bit line driver circuit. [Figure 7] FIG. 7 is a timing chart illustrating an example of the operation of the memory cell. [Figure 8] 8A and 8B are a top view and a cross-sectional view of a memory device according to one embodiment of the present invention. [Figure 9] 9A and 9B are a top view and a cross-sectional view of a memory device according to one embodiment of the present invention. [Figure 10] FIG. 10 is a top view of a storage device according to one embodiment of the present invention. [Figure 11] FIG. 11 is a cross-sectional view of a memory device according to one embodiment of the present invention. [Figure 12] FIG. 12 is a cross-sectional view of a memory device according to one embodiment of the present invention. [Figure 13] FIG. 13 is a cross-sectional view of a memory device according to one embodiment of the present invention. [Figure 14] Fig. 14A is a diagram for explaining the classification of IGZO crystal structures, Fig. 14B is a diagram for explaining the XRD spectrum of silica glass, and Fig. 14C is a diagram for explaining the XRD spectrum of crystalline IGZO. [Figure 15] 15A and 15B are diagrams illustrating an example of an electronic component. [Figure 16] 16A, 16B, 16C, 16D, 16E, and 16F are diagrams illustrating an example of an electronic device. [Figure 17] 17A and 17B are diagrams illustrating an example of an electronic device. [Figure 18] 18A, 18B, and 18C are diagrams illustrating an example of an electronic device. [Figure 19] FIG. 19 is a diagram showing various storage devices by hierarchy. [Figure 20] 20A and 20B are diagrams illustrating an example of an electronic device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] Hereinafter, an embodiment will be described with reference to the drawings. However, the embodiment may be different from the embodiment. The present invention may be implemented in any form without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the details of the present invention. The present invention should not be construed as being limited to the description of the following embodiment.

[0026] In addition, the following embodiments can be combined as appropriate. When multiple configuration examples are shown in one embodiment, the configuration examples may be combined with each other as appropriate. It is possible.

[0027] In the drawings attached to this specification, the components are classified by function and are shown as independent blocks. Although the block diagram is shown as a block diagram, the actual components are completely separated by function. It is difficult to determine the function of each component, and one component may be involved in multiple functions.

[0028] In addition, in the drawings, etc., the size, layer thickness, area, etc. may be exaggerated for clarity. Therefore, the scale is not necessarily limited. The drawings are schematic representations of ideal examples. The present invention is not limited to the shapes or values ​​shown in the drawings.

[0029] In addition, in the drawings, etc., the same elements, elements having similar functions, elements made of the same material, Alternatively, elements formed at the same time may be given the same reference numerals, and the description thereof may be repeated. may be omitted.

[0030] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" may be changed to "insulating layer." In some cases, it may be possible to change the term to

[0031] In addition, in this specification and the like, terms indicating an arrangement such as "upper" and "lower" refer to the positional relationship of components. The relationship is not limited to being "directly above" or "directly below". For example, If the expression "gate electrode on the edge layer" is used, it means that there is another component between the gate insulating layer and the gate electrode. Does not exclude those that include.

[0032] In addition, in this specification, ordinal numbers such as "first," "second," and "third" refer to elements of the This is added to avoid confusion and is not intended to limit the number.

[0033] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." " includes cases where the device is connected via "anything that has some electrical effect." " is not subject to any particular restriction as long as it enables the transmission and reception of electrical signals between the connection objects. For example, "things that have some kind of electrical function" include electrodes, wiring, and transistors. These include switching elements, resistor elements, inductors, capacitor elements, and various other functions. In addition, even if it is expressed as "electrically connected", it is not necessarily the actual circuit. In some cases, there may be no physical connection and only wiring extending therethrough.

[0034] In addition, in this specification and the like, the terms "electrode" and "wiring" are used to refer to these components functionally. This is not intended to be limiting. For example, an "electrode" may be used as a part of a "wire." , and vice versa.

[0035] In addition, in this specification, a "terminal" in an electric circuit means a terminal through which a current or potential is input (or It refers to the part where the signal is received (or transmitted) and the signal is output (or received). Alternatively, a part of the electrode may function as a terminal.

[0036] Generally, a "capacitance" has a structure in which two electrodes face each other through an insulator (dielectric). In this specification and the like, the term "capacitive element" includes the above-mentioned "capacitance." In other words, in this specification, a "capacitive element" refers to a capacitor having two electrodes facing each other with an insulator interposed therebetween. a configuration in which two wires face each other through an insulator; This includes cases where two wires are arranged with an insulator between them.

[0037] In this specification, the term "voltage" refers to a potential between a certain potential and a reference potential (for example, a ground potential). Therefore, voltage and potential difference can be expressed in other words. can.

[0038] In this specification, a transistor includes a gate, a drain, and a source. , an element having at least three terminals. And the drain (drain terminal, drain (source terminal, source region, or source electrode) and the source (source terminal, source region, or source electrode) A channel forming region is formed between the source and drain. In this specification and the like, a channel formation region is a region in which a current can flow. The region refers to the region through which current mainly flows.

[0039] In addition, the source and drain functions may differ depending on whether transistors with different polarities are used or the circuit operation. In some cases, such as when the direction of the current changes during operation, the positions may be reversed. In the text, the terms source and drain may be used interchangeably.

[0040] Unless otherwise specified in this specification, the off-state current refers to the current that flows when a transistor is in an off-state. The drain current when the device is in the off state (also called the non-conducting state or cut-off state). Unless otherwise specified, for n-channel transistors, the gate to source voltage V When gs is lower than the threshold voltage Vth, in a p-channel transistor, This refers to a state in which the gate voltage Vgs is higher than the threshold voltage Vth. The off-state current of a transistor is the voltage Vgs between the gate and the source, which is the threshold voltage. This may be referred to as the drain current when the gate voltage is lower than Vth.

[0041] In the above description of the off-state current, the drain may be read as the source. The off-state current may refer to the source current when the transistor is in the off state. In this specification, the off-state current is refers to the current that flows between the source and drain when the transistor is in the off state. There is a match.

[0042] In this specification, the on-state current is the current that flows when a transistor is in an on-state (also called a conductive state). It can also refer to the current that flows between the source and drain when the device is in a non-uniform state.

[0043] In the present specification and the like, the term "metal oxide" means a metal oxide in a broad sense. Metal oxides are oxide insulators and oxide conductors (transparent oxide conductors). Semiconductors are classified into three categories:

[0044] For example, when a metal oxide is used for a channel formation region of a transistor, the metal oxide is In other words, metal oxides have amplifying, rectifying, and When the metal oxide has at least one switching function, the metal oxide is called a metal oxide semiconductor. (metal oxide semiconductor). A transistor having a metal oxide in a channel formation region is called an "oxide semiconductor transistor." These transistors can be called "OS transistors."

[0045] In the present specification and the like, metal oxides having nitrogen are also referred to as metal oxides. Metal oxides containing nitrogen are sometimes called metal oxynitrides (met de). Metal oxides may also be called alkoxynitrides. Details of metal oxides will be described later. .

[0046] (Embodiment 1) In this embodiment, a configuration example of a storage device according to one embodiment of the present invention will be described. The storage device according to one embodiment of the present invention is a storage device that can function by utilizing semiconductor characteristics, The memory device according to one embodiment of the present invention is formed on a semiconductor substrate. A layer having an OS transistor is stacked above a layer having a semiconductor transistor. It has a structure in which

[0047] FIG. 1 is a perspective view showing a configuration example of a storage device 10 according to an embodiment of the present invention. 0 includes a layer 100 and layers 200_1 to 200_l (where l is an integer equal to or greater than 1). In this specification, in order to distinguish between multiple elements having similar functions, " or [_2] is used. That is, layers 200_1 to 200_l When referring to any of the layers, the reference number for layer 200 is used and it is not necessary to specify one. At certain times, the description will use reference numbers such as layer 200_1, layer 200_2, etc.

[0048] As shown in FIG. 1, the memory device 10 has a layer 200_1 stacked on top of a layer 100. A layer 200_2 is laminated on the layer 200_1, and a layer 200_3 (illustrated The layers 200_1 and 200_2 are also stacked in order. For ease of understanding, in the following description of the present embodiment, the case where l is 2 will be taken as an example. explain.

[0049] <Schematic perspective view of storage device> FIG. 2 is a schematic perspective view showing a configuration example of a storage device 10 according to an embodiment of the present invention.

[0050] The storage device 10 shown in FIG. 2 includes a layer 100, a layer 200_1, and a layer 200_2. A layer 200_1 is provided above the layer 100, and a layer 200_2 is provided above the layer 200_1. The electrodes are provided in a layered structure.

[0051] The layer 100, the layer 200_1, and the layer 200_2 each utilize semiconductor properties. Specifically, the layer 100 includes peripheral circuitry 101, A memory cell array 111 is provided in the layer 200_1 and the layer 200_2. In the drawings described in this specification, the flow of main signals is indicated by arrows or lines. Power lines, etc. may be omitted.

[0052] The peripheral circuit 101 includes a row decoder 121, a word line driver circuit 122, a word line driver a page buffer circuit 123, a column decoder 131, a bit line driver circuit 132, 38, an output circuit 141, and a control logic circuit 151. 01 functions as a drive circuit and a control circuit for the memory cell array 111.

[0053] The peripheral circuit 101 is configured using transistors formed on a semiconductor substrate SUB. The conductive substrate SUB may be formed with any suitable thickness, as long as it is capable of forming a channel region of a transistor. For example, a single crystal silicon substrate, a single crystal germanium substrate, a compound semiconductor substrate, (SiC substrate, GaN substrate, etc.), SOI (Silicon on Insulator ) substrates, etc. can be used.

[0054] In addition, SOI substrates are made by implanting oxygen ions into mirror-polished wafers and then heating them at high temperatures. This allows an oxide layer to form at a certain depth from the surface, and also removes defects that have occurred in the surface layer. Separation by Implantation (SIMOX) Growth of microvoids formed by hydrogen ion implantation and by heat treatment The Smart Cut method and the ELTRAN method (registered trademark: Epi The SOI substrate was formed using a method such as taxial layer transfer. A transistor formed using a single crystal substrate may have a single crystal It has a semiconductor.

[0055] In this embodiment, a single crystal silicon substrate is used as the semiconductor substrate SUB. The transistor formed on a single crystal silicon substrate is called a Si transistor. The peripheral circuit 101, which is made up of Si transistors, is capable of high-speed operation. do.

[0056] The memory cell array 111 has a plurality of memory cells 112. The memory cells 112 are Since OS transistors are thin-film transistors, The recell array 111 can be provided by stacking on a semiconductor substrate SUB.

[0057] Here, the band gap of the oxide semiconductor is 2.5 eV or more, preferably 3.0 eV or more. Therefore, OS transistors have low leakage current due to thermal excitation and extremely low off-state current. stomach.

[0058] The metal oxide used in the channel formation region of OS transistors is indium (In) and It is preferable that the oxide semiconductor contains at least one of zinc (Zn). Examples of suitable oxide semiconductors include In-M-Zn oxide (wherein the element M is, for example, Al, Ga, Y, or The most typical example is Sn. It reduces impurities such as water and hydrogen, which act as electron donors. By reducing oxygen vacancies, the oxide semiconductor can be made i-type (intrinsic) or substantially i-type. Such an oxide semiconductor is called a highly purified oxide semiconductor. Note that the OS transistor will be described in detail in Embodiment 3.

[0059] The memory cell 112 has a function of storing data by accumulating and holding electric charges. The memory cell 112 has a function of storing binary data (high level or low level). It may have a function of storing data of four or more values. The device may have a function of storing the log data.

[0060] Since the off-state current of the OS transistor is very small, the transistor used in the memory cell 112 The OS transistor is suitable as a transistor having an off-state current per 1 μm of channel width, for example. current is 100zA / μm or less, or 10zA / μm or less, or 1zA / μm or less, The OS transistor is used in the memory cell 112. This allows the data stored in the memory cell 112 to be retained for a long period of time. do.

[0061] The OS transistor has a feature that the off-state current is not easily increased even at high temperatures. 0 can operate even when the temperature of the environment in which it is installed is high. Even at high temperatures caused by the heat generated by the memory cell 101, data stored in the memory cell 112 is not lost. By using an OS transistor, the reliability of the memory device 10 can be improved. .

[0062] Alternatively, if the transistor used in the memory cell 112 has a low off-state current, it may be an OS transistor. For example, a transistor having a band gap in a channel forming region may be used. A transistor having a wide band gap semiconductor may be used. This can refer to semiconductors with a band gap of 2.2 eV or more, such as silicon carbide. , gallium nitride, diamond, etc.

[0063] As shown in FIG. 2, in a memory cell array 111, memory cells 112 are arranged in a matrix. Each memory cell 112 is electrically connected to the wiring WL and the wiring BL. The memory cell 112 is selected by a potential applied to the wiring WL. Data is written to the selected memory cell 112 via the line BL. The cell 112 is selected by a potential applied to the line WL, and the selected cell is selected via the line BL. That is, the wiring WL is connected to the memory cell 11 2, and the wiring BL functions as a bit line of the memory cell 112. has.

[0064] In addition, the wiring WL and the wiring BL shown in FIG. 2 are each composed of multiple wirings. For example, the wiring WL includes a plate line PL, a write word line WWL, and a read word line RWL. , wiring BG1, and wiring BG2, and wiring BL is a read bit line RBL , and a write bit line WBL (see FIG. 3 and FIG. 4).

[0065] The memory cell array 111 provided in the layer 200_1 is connected to the word line WL via the wiring WL. A memory cell array electrically connected to the line driver circuit 122 and disposed in layer 200_2 111 is electrically connected to the word line driver circuit 123 via the wiring WL. A memory cell array 111 provided in a layer 200_1 and a memory The cell array 111 is electrically connected to a bit line driver circuit 132 via wiring BL. can be.

[0066] A memory cell array 111, a word line driver circuit 122, and a word line driver circuit 123 4. The electrical connection with the bit line driver circuit 132 will be described later with reference to FIG. The peripheral circuit 101 will be described with reference to FIG.

[0067] <Block diagram of storage device> FIG. 3 is a block diagram showing an example of the configuration of the storage device 10. In the block diagram shown in FIG. The memory cell array 111 and the word line driver circuit 123 provided in 200_2 are omitted. However, only one memory cell 112 included in the memory cell array 111 is shown as a representative example. do.

[0068] As shown in FIG. 3, the memory device 10 includes a peripheral circuit 101 and a memory cell array 111. The peripheral circuit 101 includes a row decoder 121, a word line driver circuit 122, a color A memory decoder 131, a bit line driver circuit 132, a page buffer 138, and an output circuit 14 1 and a control logic circuit 151.

[0069] The memory cell array 111 has a plurality of memory cells 112 (only one is shown in FIG. 3 ), The memory cell 112 is connected to a plate line PL, a write word line WWL, and a read word line RW L, wiring BG1, and wiring BG2 are electrically connected to the word line driver circuit 122. The bit line driver is connected to the read bit line RBL and the write bit line WBL. The driver circuit 132 is electrically connected to the input terminals 132.

[0070] The memory device 10 has a potential Vss, a potential Vdd, a potential Vdh, a precharge potential Vpre, A reference potential Vref is input to the write word line WW L high power supply potential.

[0071] The memory device 10 includes a clock signal CLK, a chip enable signal CE, a global write signal CLK, write enable signal GW, byte write enable signal BW, address signal ADDR, and The data signal WDATA is input, and the storage device 10 outputs the data signal RDATA. These signals can be either high or low (High or Low, H or L, 1 or 0, etc.) is a digital signal represented as

[0072] In this embodiment, the high level of a digital signal is represented by a potential Vdd, and the low level is represented by a potential Vdd. The level is expressed by the potential Vss. Also, the high level of the write word line WWL is A potential Vdh is used for the low level, and a potential Vss is used for the low level. A write enable signal BW, an address signal ADDR, a data signal WDATA, and a data The signal RDATA is a signal having multiple bits.

[0073] In this specification, for a signal having multiple bits, for example, a byte write enable If the signal BW has 4 bits, it is written as byte write enable signal BW[3:0]. This means that the byte write enable signals have the names BW[0] through BW[3]. If you need to specify one bit, e.g., byte write enable The signal is written as BW[0]. Also, when written as the byte write enable signal BW, It points to any bit.

[0074] For example, the byte write enable signal BW is 4 bits, the data signal WDATA and The data signal RDATA can be 32 bits, i.e., byte write enable. The signal BW, the data signal WDATA, and the data signal RDATA are Write enable signal BW[3:0], data signal WDATA[31:0], The data signal is represented as RDATA[31:0].

[0075] In the storage device 10, the above-mentioned circuits, signals, and potentials may be changed as necessary. Alternatively, other circuits, other signals, or other potentials may be added. This is also fine.

[0076] The control logic circuit 151 outputs a chip enable signal CE, a global write enable signal CE, and a The enable signal GW is processed to generate control signals for the row decoder 121 and the column decoder 131. For example, when the chip enable signal CE is high and the global write enable When the read signal GW is at a low level, the row decoder 121 and the column decoder 131 The chip enable signal CE is set to high level, and the global write enable signal When the enable signal GW is at a high level, the row decoder 121 and the column decoder 131 If the chip enable signal CE is low, the global write Regardless of the high level or low level of the enable signal GW, the row decoder 121 and The column decoder 131 can be in a standby mode. The signals processed by 151 are not limited to these, and other signals can be input as necessary. You may do so.

[0077] In addition, the control logic circuit 151 outputs the byte write enable signal BW[3:0 ] to control the write operation. Specifically, the byte write enable signal B When W[0] is at a high level, the row decoder 121 and the column decoder 131 Similarly, the byte write enable When the signal BW[1] is at a high level, the data signal WDATA[15:8] is written. When the byte write enable signal BW[2] is high, the data signal WDATA Write operation on [23:16], byte write enable signal BW[3] is high level In this case, a write operation of the data signal WDATA[31:24] is performed.

[0078] The row decoder 121 and the column decoder 131 include the control logic In addition to the control signal generated by the circuit 151, an address signal ADDR is input.

[0079] The row decoder 121 decodes the address signal ADDR and outputs the address to the word line driver circuit 12. The word line driver circuit 122 generates a control signal for the plate line PL, the write line A function for driving the read word line WWL, the read word line RWL, the wiring BG1, and the wiring BG2. The word line driver circuit 122 has a function of applying a predetermined potential to the word line. Based on the control signal from the decoder 121, the write word line WWL of the row to be accessed, or The word line driver circuit 122 selects the line BG1 or the read word line RWL. Alternatively, it may have a function of selecting the wiring BG2.

[0080] In addition, when the memory cell array 111 is divided into a plurality of blocks, A pre-decoder 124 may be provided. The pre-decoder 124 decodes the address signal ADDR and It has the function of determining the block to be accessed.

[0081] The column decoder 131, the bit line driver circuit 132, and the page buffer 138 The data input by the data signal WDATA is written to the memory cell array 111. a function for reading data from the memory cell array 111; a function for amplifying the read data and outputting it; The output circuit 141 has a function of outputting the signal.

[0082] The output circuit 141 is configured to output a signal from the column decoder 131 and the bit line driver circuit 132. The data read from the memory cell array 111 and stored in the page buffer 138 is It is output as the data signal RDATA.

[0083] In the example of FIG. 3, the bit line driver circuit 132 includes a precharge circuit 133, a sense An amplifier circuit 134, an output MUX (multiplexer) circuit 135, and a write driver The precharge circuit 133, the sense amplifier circuit 134, and the output buffer circuit 136 are also included. The MUX circuit 135 and the write driver circuit 136 will be described later.

[0084] <Memory cell array> FIG. 4 is a block diagram showing a configuration example of the memory cell array 111. In FIG. A memory cell array 111, a word line driver circuit 122, a word line driver circuit 123, 4 illustrates a bit line driver circuit 132. A write word line PL, a write word line WWL, a read word line RWL, a wiring BG1, and The state in which the word line driver circuit 122 is electrically connected via the wiring BG2, the memory cell The array 111 is electrically connected to the word line driver circuit 123 via the wiring WL. , and the memory cell array 111 is connected to the read bit line RBL and the write bit It also shows the electrical connection to the bit line driver circuit 132 via the line WBL.

[0085] Here, the memory cells electrically connected to the word line driver circuit 122 via the wiring WL The array 111 is a memory cell array 111 provided in the layer 200_1, and has wiring WL. The memory cell array 111 is electrically connected to the word line driver circuit 123 via a layer 200_2 is a memory cell array 111 provided in the memory cell array 111.

[0086] A single memory cell array 111 has m (m is an integer of 1 or more) memory cells in a column and n (n is 1 The memory cells 112 are arranged in a matrix. In FIG. 4, the same memory cell array is arranged in the layer 200_1 and the layer 200_2. The memory cell array 111 provided in the layer 200_1 is 1, and in the memory cell array 111 provided in the layer 200_2, The number of 12's etc. may be different.

[0087] In FIG. 4, the addresses of the memory cells 112 are also shown, and are represented as [1,1], [i,1], and [m ,1], [1,j], [i,j], [m,j], [1,n], [i,n], [m,n]( i is an integer between 1 and m, and j is an integer between 1 and n) is an address of the memory cell 112. For example, a memory cell 112 denoted as [i,j] is a memory arranged in the i-th row and the j-th column. Resell 112.

[0088] As with the address, the plate line PL, the write word line WWL, and the read word line RWL , the wiring BG1, the wiring BG2, the read bit line RBL, and the write bit line WBL are attached to the rear of the wiring BG1, the wiring BG2, the read bit line RBL, and the write bit line WBL. The numbers [1], [i], [m], [j], and [n] used above are also numbers representing rows or columns.

[0089] The memory cell 112 arranged in the i-th row and j-th column is connected to a plate line PL[i] and a write word line W WL[i], read word line RWL[i], wiring BG1[i], wiring BG2[i], read The read bit line RBL[j] and the write bit line WBL[j] are electrically connected to each other. The memory cell 112 arranged in the i-th row and j-th column is connected to the plate line PL[i] and the write the write word line WWL[i], the read word line RWL[i], the wiring BG1[i], and A word line driver circuit 122 or a word line driver circuit 123, and a read bit line RBL[j] and a write bit line Electrical connection is made to the bit line driver circuit 132 via WBL[j].

[0090] That is, the memory device 10 has 2×m plate lines PL and 2×m write word lines W WL, 2×m read word lines RWL, 2×m wires BG1, 2×m wires BG 2. It has n read bit lines RBL and n write bit lines WBL.

[0091] <Memory cell> FIG. 5A is a circuit diagram showing an example of the configuration of the memory cell 112. As shown in FIG.

[0092] The memory cell 112 includes a transistor 11, a transistor 12, and a capacitance element C11. Here, transistor 11 is a write transistor and transistor 12 is a read transistor. In addition, the transistors 11 and 12 are Each has a front gate (sometimes simply called a gate) and a back gate. do.

[0093] Either the source or the drain of the transistor 11 is electrically connected to the write bit line WBL. The other of the source and drain of the transistor 11 is connected to the front end of the transistor 12. The gate of the transistor 1 is electrically connected to one terminal of the capacitance element C11 and the The front gate of transistor 11 is electrically connected to the write word line WWL. The back gate of the transistor BG1 is electrically connected to the wiring BG1.

[0094] Either the source or the drain of the transistor 12 is electrically connected to the read bit line RBL. The other of the source and drain of the transistor 12 is connected to a read word line RWL and the back gate of the transistor 12 is electrically connected to the wiring BG2. The other terminal of the capacitive element C11 is electrically connected to the plate line PL.

[0095] Here, the wiring BG1 is used to apply a predetermined potential to the back gate of the transistor 11. The wiring BG2 functions as a wiring for supplying a predetermined potential to the back gate of the transistor 12. The plate line PL functions as a wiring for applying a voltage to the other terminal of the capacitance element C11. It functions as a wiring for applying a predetermined potential.

[0096] The other of the source or drain of the transistor 11 and the front The gate and one terminal of the capacitance element C11 are electrically connected to a node N The transistor 11 couples the node N11 and the write bit line WBL. The memory cell 112 has a function as a switch that turns on or off. The capacitance element C11 may be omitted.

[0097] To write data, a high-level potential is applied to the write word line WWL to turn on the transistor. By making the transistor N11 conductive, the node N11 and the write bit line WBL are electrically connected to each other. Specifically, when the transistor 11 is in a conducting state, the write bit A potential corresponding to the data to be written is applied to the line WBL, and the potential is written to the node N11. Thereafter, a low-level potential is applied to the write word line WWL to turn off the transistor 11. By making it conductive, the potential of node N11 is maintained.

[0098] To read data, a predetermined potential is applied to the read bit line RBL. The bit line RBL is electrically floating, and the read word line R This is done by applying a low level potential to the read bit line RB WL. A predetermined potential is applied to L, and then the read bit line RBL is set to a floating state. This is expressed as precharging the read bit line RBL.

[0099] For example, by precharging the read bit line RBL with a potential Vdd, the transistor The transistor 12 has a potential difference between its source and drain. The current flowing between the read and write pins is determined by the potential held at node N11. The potential change of the read bit line RBL when the read bit line RBL is in a floating state. By reading out the voltage stored in the node N11, the voltage stored in the node N11 can be read out. .

[0100] Moreover, a high-level potential is applied to the row in which the memory cell 112 to which data is to be written is arranged. The memory cell 112 from which data is read is selected by the write word line WWL to be applied. The row to which the data is allocated is selected by a read word line RWL to which a low-level potential is applied. Conversely, the rows in which the memory cells 112 to which data is not written are arranged are written. A low-level potential is applied to the word line WWL, and the memory cell 112 from which data is not to be read is The rows in which the data is arranged are precharged to the read word lines RWL and the read bit lines RBL. By applying the same potential as that for selecting a pixel, the pixel can be made unselected.

[0101] The memory cell 112 stores data by accumulating and holding charge at the node N11. In this embodiment, it is assumed that the node N11 can store binary data. .

[0102] The memory cell 112 is composed of two transistors and one capacitance element (or two transistors). The gain cell type memory cell is a type that stores electric charge. Even if the capacitance of the memory cell is small, the accumulated charge can be amplified by the nearest transistor. The memory cells 112 are the NOSRAM described above.

[0103] <Transistor> The transistor 11 and the transistor 12 are transistors having a metal oxide in a channel formation region. For example, transistor 11 and transistor In the channel formation region of 12, indium, element M (element M is aluminum, gallium, Yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium Cr, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum one or more selected from the group consisting of zinc, tungsten, and magnesium, Metal oxides having any one of these elements can be used. In particular, indium, gallium, A metal oxide made of zinc is preferred.

[0104] Since the off-state current of an OS transistor is very small, the OS transistor is used as the transistor 11. By using this, the potential written to the node N11 can be held for a long time. That is, data written in the memory cell 112 can be retained for a long period of time.

[0105] Alternatively, by using an OS transistor for the transistor 11, the capacitance of the capacitor C11 can be For example, the capacitance of the capacitance element C11 can be a gate capacitance of a transistor. In this case, the parasitic capacitance of the wiring can be utilized. There is no need to create a capacitance element separately from the transistor and the wiring. The memory cell 112 may have a configuration in which the capacitor element C11 is not included. By configuring the memory cell 112 in this manner, the area of ​​the memory cell 112 can be reduced.

[0106] In addition, since the OS transistor is a thin film transistor, the transistor 11 and the transistor By using OS transistors for the registers 12, the memory cell array 111 can be 01.

[0107] Regarding the back gates of the transistors 11 and 12, 11 and the back gate of the transistor 12 are connected to a wiring BG1 or wiring BG2. By applying a constant potential, the threshold voltages of the transistors 11 and 12 are It can be increased or decreased.

[0108] Specifically, the potentials applied to the back gates of the transistors 11 and 12 are By increasing the threshold voltage, the threshold voltage is shifted negatively, and the transistors 11 and By lowering the potential applied to the back gate of the transistor 12, the threshold voltage is shifted to the positive side. By shifting the threshold voltage negatively, the on-current of the transistor is increased. This allows the memory cell 112 to operate at high speed. By shifting the transistor to the off-state, the off-state current of the memory cell 11 can be reduced. 2. Data can be retained for a long time.

[0109] In the memory cell 112 shown in FIG. 5A, the back gate of the transistor 11 is connected to the wiring BG1. and the back gate of the transistor 12 is electrically connected to the wiring BG2. Therefore, the potential applied to the wiring BG1 is lowered to reduce the off-state current of the transistor 11. By increasing the potential applied to the wiring BG2, the on-state current of the transistor 12 is increased. The transistors 11 and 12 can be arranged in a manner suitable for their respective purposes. Alternatively, the wiring BG1 and the wiring BG2 may be combined into one wiring. The back gate of the transistor 11 and the back gate of the transistor 12 are connected to the same A potential may be applied.

[0110] Alternatively, the wiring BG2 may be connected to the word line driver circuit 122 or the word line driver circuit 123. The word line driver circuit 122 or the word line driver circuit 1 23, the potential applied to the wiring BG2 of the row to be read is increased during the read operation. On the other hand, the on-current of the transistor 12 can be increased in the row other than the row to be read. By applying a low potential to the line BG2, the transistor 12 not performing the read operation is turned on. The off-current can be reduced.

[0111] The transistor 12 of the memory cell 112 in which the data read operation is being performed is turned on. By increasing the current, the read operation of the memory cell 112 can be performed at a high speed, while the other memories can be read at a high speed. By reducing the off-current of the transistor 12 in the cell 112, the read bit line R The current leaking to the read bit line RBL can be reduced. By reducing the current, the accuracy of the read operation can be increased.

[0112] <Memory cell 2> Alternatively, the back gate of the transistor 11 and the front gate of the transistor 11 may be The back gate of the transistor 12 is electrically connected to the 5B shows the structure of the memory cell 113. FIG.

[0113] The memory cell 113 includes a transistor 11, a transistor 12, and a capacitance element C11. Yes.

[0114] Either the source or the drain of the transistor 11 is electrically connected to the write bit line WBL. The other of the source and drain of the transistor 11 is connected to the front end of the transistor 12. the front gate of the transistor 12, the back gate of the transistor 13, and one terminal of the capacitance element C11. The front gate of the transistor 11 is electrically connected to the write word line WWL and In addition, it is electrically connected to the back gate of the transistor 11 .

[0115] Either the source or the drain of the transistor 12 is electrically connected to the read bit line RBL. The other of the source and drain of the transistor 12 is connected to a read word line RWL The other terminal of the capacitance element C11 is electrically connected to the plate line PL. is connected to.

[0116] The back gate of the transistor 11 and the front gate of the transistor 11 are By electrically connecting the transistor 11, the on-state current of the transistor 11 can be increased. The back gate of the transistor 12 and the front gate of the transistor 12 are By electrically connecting the transistor 12, the on-state current of the transistor 12 can be increased. That is, the memory cell 113 can perform high-speed operation.

[0117] Alternatively, the transistor 11 and the transistor 12 each have no back gate. The transistors 11 and 12 may be, The transistor manufacturing process is simplified by using a transistor with only a front gate. It is possible.

[0118] <Example of bit line driver circuit configuration> The bit line driver circuit 132 is provided with a circuit 50 shown in FIG. 6 is a circuit diagram showing a configuration example of the circuit 50. In this embodiment, the memory cell array 11 1 has 128 memory cells 112 in one row (n=128).

[0119] The circuit 50 includes transistors 61 to 66, a sense amplifier circuit 51, an AND circuit The input / output circuit 52 has an analog switch 53 and an analog switch 54 .

[0120] The circuit 50 receives signals SEN, SEP, BPR, RSEL[3:0], and WS It operates according to EL, signals GRSEL[3:0], and GWSEL[15:0]. In each circuit 50, any one bit of the 4-bit signal RSEL[3:0] is input. For other signals with multiple bits (such as GRSEL[3:0]), Same here.

[0121] The bit line driver circuit 132 supplies data DIN[31:0] to the memory cell array 1 11, and data DOUT[31:0] is read from the memory cell array 111. Each circuit 50 outputs one bit of the 32-bit data DIN[31:0]. The data is written to the memory cell array 111, and the 32-bit data DOUT[31: 0] from the memory cell array 111. do.

[0122] Note that data DIN[31:0] and data DOUT[31:0] are internal signals. Data DIN[31:0] is sent from the page buffer 138 to the bit line driver circuit 132. The data DOUT[31:0] is supplied from the bit line driver circuit 132. The page buffer 138 also includes a recording signal. A data signal WDATA is input from outside the memory device 10, and the page buffer 138 outputs The data signal RDATA is outputted to the outside of the storage device 10 via the circuit 141 .

[0123] The page buffer 138 can store at least one row of the memory cell array 111. It is preferable that the amount of data (n bits) that can be stored in the memory can be 128 bits. It is preferable to be able to store the above data.

[0124] <<Precharge circuit>> The transistor 61 constitutes a precharge circuit 133. The read bit line RBL is precharged to a precharge potential Vpre. In the embodiment, the potential Vdd (high level) is used as the precharge potential Vpre. The case will be described below (in Figs. 6 and 7, it is written as Vdd (Vpre)). The signal BPR is a charge signal, and controls the conductive state of the transistor 61 .

[0125] <<Sense amplifier circuit>> The sense amplifier circuit 51 constitutes the sense amplifier circuit 134. The sense amplifier circuit 51 During a read operation, the data input to the read bit line RBL is at high level or During a write operation, the sense amplifier circuit 51 determines the write It functions as a latch circuit that temporarily holds the data DIN input from the driver circuit 136. It works.

[0126] The sense amplifier circuit 51 shown in FIG. 6 is a latch-type sense amplifier. FIG. 1 shows a circuit configuration of a multi-stage inverter circuit having two inverter circuits, one of which is connected to the input node of the other inverter circuit. The input node of one inverter circuit is connected to node NS. If the output node is node NSB, then complementary data is stored at nodes NS and NSB. is retained.

[0127] The signals SEN and SEP are used to activate the sense amplifier circuit 51. The reference potential Vref is a read determination potential. The amplifier circuit 51 is activated by detecting the potential of the node NS It is determined whether the potential of B is at a high level or a low level.

[0128] The AND circuit 52 controls the conduction state between the node NS and the write bit line WBL. In addition, the analog switch 53 controls the conduction state between the node NSB and the read bit line RBL. The analog switch 54 supplies a node NS and a reference potential Vref. Controls the electrical continuity with wiring.

[0129] That is, the potential of the read bit line RBL is set to the node NSB When the potential of the read bit line RBL becomes lower than the reference potential Vref, The sense amplifier circuit 51 determines that the read bit line RBL is at a low level. In addition, if the potential of the read bit line RBL does not become lower than the reference potential Vref, The sense amplifier circuit 51 determines that the read bit line RBL is at a high level.

[0130] The signal WSEL is a write selection signal and controls the AND circuit 52. 3:0] is a read selection signal, and analog switch 53 and analog switch 5 Control 4.

[0131] <<Output MUX circuit>> The transistors 62 and 63 constitute the output MUX circuit 135. RSEL[3:0] is the global read select signal that controls the output MUX circuit 135. The output MUX circuit 135 reads data from 128 read bit lines RBL. The output MUX circuit 135 has a function of selecting one of the 32 read bit lines RBL from which the data is read. functions as a 128-input, 32-output multiplexer.

[0132] The output MUX circuit 135 receives the data DOUT[31:0] from the sense amplifier circuit 134. The data is read and output to the page buffer 138.

[0133] <<Write driver circuit>> The transistors 64 to 66 constitute a write driver circuit 136. The signal GWSEL[15:0] is the global write select signal and is connected to the write driver circuit. The write driver circuit 136 controls the data DIN[31:0]. The amplifier circuit 134 has a function of writing data thereto.

[0134] The write driver circuit 136 functions to select the column to which the data DIN[31:0] is written. The write driver circuit 136 outputs the byte Data is written in units, half-words, or words.

[0135] The circuit 50 electrically connects data DIN[h] (h is an integer between 0 and 31) to every four columns. The circuit 50 is electrically connected to the data DOUT[h] for every four columns. do.

[0136] <Memory cell operation example> FIG. 7 is a timing chart illustrating an example of the operation of the memory cell 112. The write word line WWL in the write and read operations of the memory cell 112. The read word line RWL, the read bit line RBL, and the write bit line WBL The potential relationship will be described. Also, the wiring BG2 is connected to the word line driver circuit 122 or The case where the signal is driven using the code line driver circuit 123 will also be described later.

[0137] In FIG. 7, the period Twrite is a period during which a write operation is performed, and the period Tread is In this period, a read operation is performed. The high level of the write bit line WBL is the potential Vdd, and the low level of the write bit line WBL is the potential Vdd. The high level of the write word line WWL is the potential Vdh. The low level of the word line WWL is the potential Vss.

[0138] <<Write operation>> During the period Twrite, a voltage corresponding to the data to be written is applied to the write bit line WBL. A potential Vdata corresponding to the data to be written to the write bit line WBL is applied. With data applied, the row in which the memory cell 112 to which data is to be written is arranged When a potential Vdh is applied to the write word line WWL, the transistor 11 becomes conductive. As a result, a potential Vdata corresponding to the data to be written is written to the node N11.

[0139] During the period Twrite, the read word line RWL and the read bit line RB A potential Vdd is applied to L.

[0140] <<Read operation>> During the period Tread, the read bit line RBL is precharged with the potential Vdd. The read bit line RBL is floating and the memory cell from which data is read When a potential Vss is applied to the read word line RWL of the row in which the transistor 112 is arranged, When the data written to node N11 is high, transistor N12 is in a conductive state. As a result, the potential of the read bit line RBL starts to drop.

[0141] The potential of the read bit line RBL drops by ΔV1 and becomes lower than the reference potential Vref. Then, the sense amplifier circuit 51 determines that the read bit line RBL is at a low level.

[0142] In addition, when the read bit line RBL is in a floating state, the memory cell from which data is read Even if the potential Vss is applied to the read word line RWL of the row in which 112 is arranged, When the data written to node N11 is low, transistor M12 is turned on. In this case, the potential of the read bit line RBL does not change. 51 determines that the read bit line RBL is at a high level.

[0143] In the period Tread, the write bit line WBL and the write word line WWL are The potential Vss is applied.

[0144] The wiring BG2 is connected to the word line driver circuit 122 or the word line driver circuit 123. When driving, for example, the high level of the wiring BG2 is set to the potential Vdh, and the low level of the wiring BG2 is set to the potential Vdh. can be set to potential Vss.

[0145] In the period Twrite, the potential Vss is applied to the wiring BG2. The wiring BG2 in the row in which the memory cell 112 from which data is to be read is connected to a potential Vd h is applied.

[0146] When a potential Vdh is applied to the wiring BG2, the memory cell 112 from which data is read is enabled. In addition, the on-state current of the transistor 12 can be increased by applying a potential V By applying ss, the off-state current of the transistor 12 can be reduced.

[0147] As described above, the memory device 10 is a gain cell type memory device made up of n-channel transistors. The memory cell has a write word line WWL, a read word line RWL, a write bit line The read bit line WBL and the read bit line RBL are set to three potentials (potential Vss, potential Vd d, and potential Vdh) represent a high level or a low level. The storage device 10 can be operated with a small number of power supplies, and the electronic device in which the storage device 10 is mounted can be The cost of the device can be reduced.

[0148] Gain cell type memory cells require at least two transistors per memory cell. It was difficult to increase the number of memory cells that could be placed per unit area. By using an OS transistor as the transistor constituting the rechargeable battery 112, A plurality of the arrays 111 are stacked on the semiconductor substrate SUB on which the peripheral circuit 101 is formed. That is, the amount of data that can be stored per unit area can be increased.

[0149] In addition, even if the capacity of the gain cell type memory cell to store electric charge is small, the stored electric charge By amplifying the charge with the nearest transistor, it can function as a memory. In addition, an OS transistor with a very small off-state current is used as a transistor constituting the memory cell 112. By using it as a resistor, the capacitance of the capacitance element C11 can be reduced. The gate capacitance of a transistor and the parasitic capacitance of a wiring can be used as a capacitance element. C11 can be omitted, which means that the area of ​​the memory cell 112 can be reduced.

[0150] This embodiment may be implemented in appropriate combination with other embodiments described in this specification. It is possible.

[0151] (Embodiment 2) In the following, an example of the storage device according to the above embodiment will be described with reference to FIGS. 8A, 8B, 9A, and 9B. 9B and 10 to 13. First, the memory cells constituting the memory device A configuration example will be described.

[0152] <Memory cell configuration example> 8A and 8B show the structure of a memory cell 860 constituting a memory device according to one embodiment of the present invention. FIG. 8A is a top view of the memory cell 860 and its surroundings. FIG. 8B is a top view of the memory cell 860 and its surroundings. 8B is a cross-sectional view of the filter 860, and FIG. 8B corresponds to the area indicated by the dashed line A1-A2 in FIG. 8A. 8B, a cross section of the transistor 600 in the channel length direction and a cross section of the transistor 70 8A shows a cross section in the channel width direction of 0. Note that in the top view of FIG. 8A, some parts are omitted for clarity. In addition, the X direction, the Y direction, and the Z direction shown in FIG. 8A are respectively are directions perpendicular or intersecting each other. Here, the X and Y directions are It is preferable that the Z direction is perpendicular or approximately perpendicular to the substrate surface. I wish.

[0153] The memory cell 860 shown in this embodiment includes a transistor 600, a transistor 700, and a capacitor 655. The memory cell 860 is the same as the memory cell shown in the previous embodiment. 112, and includes a transistor 600, a transistor 700, and a capacitance element 65 5 are the transistors 11, 12, and the capacitors shown in the above embodiments, respectively. Therefore, one of the source and drain of the transistor 600 and the transistor C11 The gate of the transistor 700 and one of the electrodes of the capacitor 655 are electrically connected to each other.

[0154] As shown in FIGS. 8A and 8B, in memory cell 860, transistor 614 is disposed on insulator 614. 00 and transistor 700 are arranged, and transistor 600 and An insulator 680 is disposed on a portion of the transistor 700, and the transistors 600 and 70 0 and insulator 680, an insulator 682 is disposed on the insulator 682, and an insulator 685 is disposed on the insulator 682. A capacitor element 655 is disposed on the insulator 685, and an insulator is disposed on the capacitor element 655. The insulator 614, the insulator 680, the insulator 682, the insulator 685, and the insulator 688 are disposed. and insulator 688 functions as an interlayer film.

[0155] Here, the transistor 600 is configured with an insulator 616 on an insulator 614 and a buried insulator 616. A conductor 605 (conductor 605a and conductor 605b) arranged so as to be embedded in the An insulator 622 on the insulator 616 and on the conductor 605, and an insulator 62 on the insulator 622 4, an oxide 630a on the insulator 624, an oxide 630b on the oxide 630a, and The oxide 643a and the oxide 643b on the substrate 630b, and the conductor 64 on the oxide 643a 2a, the conductor 642b on the oxide 643b, a part of the insulator 624, and the oxide 630a. Side, side of oxide 630b, side of oxide 643a, side of conductor 642a, conductor 6 The top surface of 42a, the side of oxide 643b, the side of conductor 642b, and the An insulator 672 in contact with the upper surface, an insulator 673 on the insulator 672, and an oxide 630 b, an oxide 630c on the oxide 630c, an insulator 650 on the insulator 650, , a conductor 660 (conductor 660a and conductor 660b) overlapping the oxide 630c; The oxide 630c has a side surface of the oxide 643a, a side surface of the oxide 643b, and a conductive layer. The side of the conductive body 642a and the side of the conductive body 642b are in contact with each other. As shown, the top surface of conductor 660 is connected to the top surface of insulator 650, the top surface of oxide 630c, and The insulator 682 is disposed so as to be substantially flush with the upper surface of the conductor 660. It contacts the top surfaces of edge 650, oxide 630c, and insulator 680, respectively.

[0156] In the following, oxide 630a, oxide 630b, and oxide 630c are collectively referred to as oxide 630a, oxide 630b, and oxide 630c. In addition, oxide 643a and oxide 643b are collectively referred to as oxide 630. The conductor 642a and the conductor 642b are collectively called the conductor It is sometimes called 642.

[0157] In transistor 600, conductor 660 serves as a gate, and conductors 642a and and the conductor 642b function as a source and a drain, respectively. The transistor 600 has a conductor that functions as a gate. The conductive material 660 is self-aligned to fill the openings formed by the insulating material 680, etc. In this manner, in the storage device according to the present embodiment, the conductor 660 can be securely positioned in the area between conductor 642a and conductor 642b.

[0158] The transistor 700 also includes an insulator 616 on the insulator 614 and a transistor embedded in the insulator 616. A conductor 705 (conductor 705a and conductor 705b) is arranged so as to be enclosed in the insulating layer 705. An insulator 622 on the edge 616 and on the conductor 705, and an insulator 624 on the insulator 622 , an oxide 730a on the insulator 624, an oxide 730b on the oxide 730a, and an oxide Oxide 743a and oxide 743b on 730b, and conductor 742 on oxide 743a a, the conductor 742b on the oxide 743b, a part of the insulator 624, the side of the oxide 730a surface, a side surface of the oxide 730b, a side surface of the oxide 743a, a side surface of the conductor 742a, and the conductor 74 2a, the side of oxide 743b, the side of conductor 742b, and the top of conductor 742b. Insulator 672 in contact with the surface, insulator 673 on insulator 672, and oxide 730b an oxide 730c on the oxide 730c, an insulator 750 on the oxide 730c, and a A conductor 760 (conductor 760a and conductor 760b) overlapping the oxide 730c. In addition, the oxide 730c has a side surface of the oxide 743a, a side surface of the oxide 743b, and a conductive The conductors 742a and 742b are in contact with each other as shown in FIG. Thus, the top surface of the conductor 760 is in contact with the top surface of the insulator 750, the top surface of the oxide 730c, and the top surface of the insulator 750. The insulator 682 is disposed so as to be substantially flush with the upper surface of the conductor 760. 7. The insulating body 750 contacts the top surface of the oxide 730c and the insulator 680.

[0159] In the following, oxide 730a, oxide 730b, and oxide 730c are collectively referred to as oxides 730a, 730b, and 730c. The oxide 743a and the oxide 743b are collectively called oxide 730. The conductor 742a and the conductor 742b are collectively referred to as a conductor It is sometimes called 742.

[0160] In the transistor 700, the conductor 760 serves as a gate, and the conductors 742a and and the conductor 742b function as a source and a drain, respectively. The transistor 700 has a conductor that functions as a gate. The dielectric 760 is formed in a self-aligning manner to fill the opening formed by the insulator 680 etc. In this manner, in the storage device according to the present embodiment, the conductor 760 can be securely positioned in the area between conductors 742a and 742b.

[0161] Here, transistor 700 is formed in the same layer as transistor 600 and has a similar configuration. Therefore, a cross section of the transistor 700 in the channel length direction is not illustrated, but 8B. That is, the cross section in the channel length direction of the transistor 600 is similar to that of the transistor 600 shown in FIG. The oxide 743 and conductor 742, which are not shown in the cross-sectional view, are also shown in FIG. The object 643 and the conductor 642 have the same structure. Although a cross section in the channel width direction is not shown, the cross section in the channel width direction of the transistor 700 shown in FIG. It has a similar structure to the cross section.

[0162] Therefore, the oxide 730 has the same structure as the oxide 630, and the description of the oxide 630 should be referred to. The conductor 705 has a similar structure to the conductor 605. The oxide 743 has the same structure as the oxide 643. The description of the conductor 643 can be referred to. The conductor 742 has a similar structure to the conductor 642. The description of the conductor 642 can be referred to. The insulator 750 has the same structure as the insulator 650. The conductor 760 has a similar structure to the insulator 650, and the description of the insulator 650 can be referred to. The conductor 660 has a similar structure to that of the conductor 660, and the description of the conductor 660 can be referred to. Unless otherwise noted, the configuration of transistor 700 as described above is the same as that of transistor 60 The description of the configuration of 0 can be taken into consideration.

[0163] Here, the transistor 600 and the transistor 700 are formed by oxidizing a region including a channel formation region. The oxide 630 and the oxide 730 are formed of a metal oxide functioning as an oxide semiconductor (hereinafter, an oxide It is preferable to use a semiconductor.

[0164] For example, metal oxides that function as oxide semiconductors have an energy gap of 2 eV or more. It is preferable to use one having an energy gap of 2.5 eV or more. By using a metal oxide, the leakage current of the transistor 600 in the non-conducting state (off The current) can be made extremely small.

[0165] As an oxide semiconductor, for example, In-M-Zn oxide (wherein the element M is aluminum, gallium, Aluminum, Yttrium, Tin, Copper, Vanadium, Beryllium, Boron, Titanium, Iron, Nickel, Germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium , tantalum, tungsten, magnesium, etc.) In particular, the element M may be an oxide of a metal such as aluminum, gallium, yttrium, or the like. In-M oxide, In-Zn oxide, or In-Zn Alternatively, M-Zn oxide or M-Zn oxide may be used.

[0166] Transistor 600 and transistor 700 each having an oxide semiconductor in a channel formation region Since the leakage current (off-state current) is extremely small when the transistor is off, it is a low-power memory. In addition, the transistor 600 and the transistor 700 can be used in a high-temperature environment. Even if the temperature is above room temperature and below 200°C, the off-state current hardly increases. The off-state current hardly increases. Therefore, the operation is stable even in high temperature environments, and the reliability is high. A good storage device can be realized.

[0167] Since the off-state current of the transistor 600 is extremely small, the capacitance value of the capacitor 655 is set small. This reduces the area occupied by the memory cell 860, and Integration can be achieved.

[0168] As shown in FIG. 8A, conductor 742a, conductor 660, conductor 605, and conductor 70 It is preferable that the conductor 74 extends in the Y direction. 2a functions as the read word line RWL shown in the previous embodiment. 60 functions as the write word line WWL shown in the previous embodiment. The conductor 705 functions as the wiring BG1 in the above embodiment. This functions as the wiring BG2 shown in the embodiment.

[0169] The capacitance element 655 is a conductor 646 a on an insulator 685 and an insulator 686 that covers the conductor 646 a. 86, and a conductor disposed on the insulator 686 overlapping at least a portion of the conductor 646a. Here, the conductor 646a functions as one electrode of the capacitor 655. The conductor 656 serves as the other electrode of the capacitor 655. 6 functions as a dielectric of the capacitive element 655 .

[0170] The conductor 656 extends in the Y direction and serves as the plate line PL shown in the previous embodiment. It is preferable to make it function as such.

[0171] Also, the insulators 672, 673, 680, 682, and 685 An opening is formed in the conductor 640 (conductor 640a, conductor 640b, conductor 640c, and conductor 640d) are set to be embedded in the openings. Moreover, the conductor 640 is provided exposed on the upper surface of the insulator 685.

[0172] The lower surface of the conductor 640a contacts the conductor 642a, and the upper surface of the conductor 640a contacts the conductor 646a. The lower surface of the body 640c contacts the conductor 760, and the upper surface of the body 640c contacts the conductor 646a. The source and drain of the transistor 600 and the gate of the transistor 700 are connected to each other. The gate and one electrode of the capacitor 655 are electrically connected to each other.

[0173] The conductor 640b is provided so that its lower surface is in contact with the conductor 642b. A conductor 646b is provided in contact with the upper surface. The conductor 646b is in the same layer as the conductor 646a. As shown in FIG. 8A, the conductor 646b extends in the X direction. With this structure, the conductor 646b is preferably The line functions as the write bit line WBL shown in FIG.

[0174] Although not shown in the cross-sectional view, the lower surface of the conductor 640d is set in contact with the conductor 742b. In addition, a conductor 746 is provided in contact with the upper surface of the conductor 640d. 6 is formed in the same layer as conductor 646a and has a similar configuration. The conductive body 746 preferably extends in the X direction. The body 746 functions as the read bit line RBL shown in the previous embodiment.

[0175] As shown in FIG. 8B, transistors 600 and 700 are formed in the same layer. Therefore, the transistors 600 and 700 can be formed in the same process. The process for manufacturing the storage device can be shortened, and productivity can be improved.

[0176] In the memory cell 860, the channel length direction of the transistor 600 and the The transistors 600 and 700 are arranged so that their channel width directions are parallel to each other. However, the memory device shown in this embodiment is not limited to this. The memory cell 860 shown in FIG. 8 is an example of the configuration of a memory device, and the circuit configuration By appropriately arranging transistors or capacitance elements of appropriate structures according to the driving method, good.

[0177] [Detailed memory cell configuration] The detailed configuration of the memory cell 860 according to one embodiment of the present invention will be described below. In the figure, the components of the transistor 700 are the same as those of the transistor 600. It is possible to serve alcohol.

[0178] As shown in FIG. 8, the oxide 630 is formed of an oxide 630a on the insulator 624 and an oxide 630b on the insulator 624. a) on the oxide 630a; and b) on the oxide 630b, at least a portion of which is formed on the oxide 630a. and an oxide 630c in contact with the upper surface of b. The side of the oxide 643a, the oxide 643b, the conductor 642a, the conductor 642b, the insulator It is preferable that the insulator 672 is provided in contact with the insulator 673 and the insulator 680 .

[0179] By having the oxide 630a under the oxide 630b, the oxide 630a is formed below the oxide 630a. The diffusion of impurities from the structure to the oxide 630b can be suppressed. By having an oxide 630c on the oxide 630b, the oxide 630c is formed above the oxide 630c. This can suppress the diffusion of impurities from the structure into oxide 630b.

[0180] In the transistor 600, the oxide 630 is formed in the channel formation region and in the vicinity thereof. The figure shows a structure in which three layers of oxide 630a, oxide 630b, and oxide 630c are laminated. However, the present invention is not limited thereto. For example, a single layer of oxide 630b, oxide 630 a two-layer structure of oxide 630b and oxide 630a, a two-layer structure of oxide 630b and oxide 630c, or For example, the oxide 630c may have a two-layer structure. Alternatively, a four-layer laminate structure may be provided.

[0181] In addition, the oxide 630 has a laminated structure of multiple oxide layers having different atomic ratios of metal atoms. Specifically, in the metal oxide used for the oxide 630a, the constituent elements The atomic ratio of element M in the oxide 630b is the atomic ratio of element M in the metal oxide in the constituent elements. It is preferable that the atomic ratio of the metal oxide used for the oxide 630a is larger than that of the element M. In the metal oxide used for the oxide 630b, the atomic ratio of element M to In is It is preferable that the atomic ratio of element M to In is larger than that of element In. In the metal oxide used, the atomic ratio of In to the element M is It is preferable that the atomic ratio of In is larger than that of the element M in the metal oxide. The oxide 630c is a metal oxide that can be used for the oxide 630a or the oxide 630b. In addition, in the metal oxide used for the oxide 630c, the element M The atomic ratio of In to element M in the metal oxide used for the oxide 630b is The atomic ratio of In may be larger than that of In.

[0182] Specifically, for example, when gallium is used as the element M, the oxide 630a is In:Ga Zn=1:3:4 [atomic ratio] or a composition close to that, or 1:1:0.5 [atomic ratio] It is sufficient to use a metal oxide having a composition of [0.15 to 0.25% by weight] or a composition close to that ratio.

[0183] The oxide 630b is In:Ga:Zn=4:2:3 [atomic ratio] or or a metal oxide with a composition of 1:1:1 or a composition of 1:1:1 or a similar ratio. In addition, the oxide 630b may have an atomic ratio of In:Ga:Zn=5:1:3. or a composition close to that, or In:Ga:Zn=10:1:3 [atomic ratio] or Alternatively, a metal oxide having a composition close to the above may be used as the oxide 630b. In:Zn=2:1 [atomic ratio] or a composition close to that, 5:1 [atomic ratio] or a composition close to that, or In:Zn=10:1 [atomic ratio] Alternatively, the oxide 630b may be In oxide. You may use it.

[0184] In addition, the oxide 630c is In:Ga:Zn=1:3:4 [atomic ratio or close thereto]. Ga:Zn=2:1 [atomic ratio] or a composition close to that, or Ga:Z Metal oxides having a composition of n=2:5 [atomic ratio] or close to that may be used. A material that can be used for the oxide 630b is applied to the oxide 630c, and the material is formed in a single layer or a laminate. For example, a specific example of the oxide 630c having a layered structure is In: The composition is Ga:Zn=4:2:3 [atomic ratio] or close to that, and In:Ga:Zn=1 :3:4 [atomic ratio] or a layered structure with a composition close to that, Ga:Zn=2:1 [atomic ratio] In:Ga:Zn=4:2:3 [atomic ratio] or a composition close to that. Layer structure with a composition close to that, Ga:Zn=2:5 [atomic ratio] or a composition close to that and a laminated structure of In:Ga:Zn=4:2:3 [atomic ratio] or a composition close thereto, Gallium oxide and In:Ga:Zn=4:2:3 [atomic ratio] or a composition close thereto and a laminated structure.

[0185] In addition, by increasing the ratio of indium in the oxides 630b and 630c, the transistor This is advantageous because it can increase the on-current or field effect mobility of the transistor. The aforementioned "nearby composition" includes a range of ±30% of the desired atomic ratio.

[0186] The oxide 630b may have crystallinity. For example, the oxide 630b may have crystallinity. (c-axis aligned crystalline oxide semico It is preferable to use a crystalline oxide such as CAAC-OS. has few impurities and defects (such as oxygen vacancies), and has a highly crystalline and dense structure. Therefore, the extraction of oxygen from the oxide 630b by the source electrode or the drain electrode In addition, even if a heat treatment is performed, oxygen is not extracted from the oxide 630b. Since the transistor 600 can be manufactured at high temperatures (so-called Thermal budget.

[0187] The oxide 630c may be provided in an opening in an interlayer film including the insulator 680. Therefore, the insulator 650 and the conductor 660 are preferably connected to each other through the oxide 630c. The layer structure includes a region overlapping with the layer structure of the oxide 630a and the layer structure of the oxide 630b. This makes it possible to form the oxide 630c and the insulator 650 by successive film formation. Therefore, the interface between the oxide 630 and the insulator 650 can be kept clean. The effect of scattering on carrier conduction is reduced, and the transistor 600 has a high on-state current and and high frequency characteristics can be obtained.

[0188] The oxide 630 (for example, the oxide 630b) is an oxide semiconductor having a low carrier concentration. In the case where the carrier concentration of the oxide semiconductor is reduced, it is preferable to It is sufficient to lower the impurity concentration in the body and to lower the defect level density. A material having a low concentration of impurities and a low density of defect states is called high purity intrinsic or substantially high purity intrinsic. Examples of impurities in an oxide semiconductor include hydrogen, nitrogen, an alkali metal, an alkali metal, and an alkali metal. These include earth metals, iron, nickel, silicon, etc.

[0189] In particular, hydrogen contained in oxide semiconductors reacts with oxygen that bonds with metal atoms to form water. , oxygen vacancies (V O :Oxygen vacancy (also called In addition, there are defects in which hydrogen is inserted into oxygen vacancies (hereafter referred to as V O Sometimes referred to as H. can act as a donor and generate electrons as carriers. may combine with oxygen, which combines with a metal atom, to generate electrons, which act as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen has a normally-on characteristic. In addition, hydrogen in the oxide semiconductor is easily moved by stress such as heat or an electric field. Therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of a transistor may decrease. There is also.

[0190] V O H can function as a donor in oxide semiconductors. Therefore, in oxide semiconductors, the donor concentration is not important, but the chirality is important. Therefore, in this specification and the like, the parameters of the oxide semiconductor are evaluated as follows. As the data, the carrier concentration assuming the absence of an applied electric field is used instead of the donor concentration. In other words, the "carrier concentration" described in this specification is sometimes called the "donor concentration." It may be possible to replace it.

[0191] From the above, when an oxide semiconductor is used for the oxide 630, V in the oxide 630 O H It is preferable to reduce the amount of the fluorine-containing compound as much as possible to obtain a high-purity pure compound or a substantially high-purity pure compound. V O In order to obtain an oxide semiconductor with a sufficiently reduced amount of H, impurities such as moisture and hydrogen in the oxide semiconductor must be eliminated. Removal of impurities (sometimes referred to as dehydration or dehydrogenation) and It is preferable to supply oxygen to the substrate to compensate for the oxygen deficiency (sometimes referred to as oxygen addition treatment). It's strange. O The oxide semiconductor with sufficiently reduced impurities such as H is used as the channel By using it in the composition region, stable electrical characteristics can be imparted.

[0192] For example, secondary ion mass spectrometry (SIMS) of oxide 630b The hydrogen concentration obtained by mass spectrometry was calculated as 1×10 20 a toms / cm 3 Less than 1 x 10 19 atoms / cm 3 Less than, more preferably is 5 x 10 18 atoms / cm 3 less than 1×10 18 atoms / c m 3 The oxide 630 in which impurities such as hydrogen are sufficiently reduced can be obtained by trasforming. By using it in the channel formation region of Transistor 600, it is possible to achieve normally-off characteristics. As a result, it is possible to provide stable electrical characteristics and improve reliability.

[0193] In addition, when an oxide semiconductor is used for the oxide 630, a region functioning as a channel formation region The carrier concentration of the oxide semiconductor is 1×10 18 cm -3 Preferably, it is equal to or less than 1. ×10 17 cm -3 More preferably, it is less than 1×10 16 cm -3 Less than More preferably, 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 It is more preferable that the thickness of the first insulating film which functions as a channel forming region is less than 100 nm. The lower limit of the carrier concentration of the oxide semiconductor in the region is not particularly limited. For example, ×10 -9 cm -3 It can be said that:

[0194] Therefore, the insulators 614, 622, 672, 673, and 68 2) A material that suppresses the diffusion of impurities (hereinafter, also referred to as a barrier material against impurities) It is preferable to use a SiO 2 layer to reduce the diffusion of impurities such as hydrogen into the oxide 630. In this specification, the term "barrier property" refers to a function of suppressing the diffusion of a corresponding substance (permeability). Or, the corresponding substance is captured and fixed (gettering). In addition, in this specification and the like, an insulating film having a barrier property is referred to as a barrier insulating film. It is sometimes called the velum.

[0195] For example, aluminum oxide is a material that has the function of suppressing the diffusion of hydrogen and oxygen. nium, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride In particular, silicon nitride or silicon nitride oxide is Since it has a high barrier property against hydrogen, it is preferable to use it as a sealing material.

[0196] Furthermore, for example, aluminum oxide is used as a material having the function of capturing and fixing hydrogen. Metal oxides such as hafnium oxide, gallium oxide, and indium gallium zinc oxide are also used. be.

[0197] For example, aluminum oxide or hafnium oxide may be used as the insulator 614. This is preferable because impurities such as water or hydrogen can be prevented from entering the transistor 600 from the substrate side. Alternatively, oxygen contained in the insulator 624 can be prevented from diffusing to the other side. Diffusion to the substrate side can be suppressed.

[0198] The conductor 605 is disposed so as to overlap the oxide 630 and the conductor 660. The conductor 605 is preferably embedded in the insulator 616 .

[0199] When the conductor 605 functions as a gate electrode, the potential applied to the conductor 605 is By changing the potential applied to the transistor 600 independently of the potential applied to the transistor 660, In particular, when a negative potential is applied to the conductor 605, By adding a second gate, the Vth of the transistor 600 can be increased and the off-current can be reduced. Therefore, applying a negative potential to the conductor 605 is preferable. In this case, the drain current when the potential applied to the conductor 660 is 0 V can be made smaller than that when the potential applied to the conductor 660 is 0 V. can.

[0200] As shown in FIG. 8A, the conductor 605 is a conductor 642a of the oxide 630 and a conductor It is preferable that the area is larger than the area that does not overlap with the body 642b. Thus, the conductor 605 is formed in a region outside the end of the oxide 630 that intersects with the channel width direction. In other words, it is preferable that the oxide 630 extends in the channel width direction. On the outside of the side surface, the conductor 605 and the conductor 660 overlap with each other via an insulator. Alternatively, it is preferable to provide the conductor 605 in a large size. In the plasma processing in the manufacturing process after formation, local charging (charge However, one aspect of the present invention is not limited to this. The conductor 605 is formed by at least the oxide located between the conductor 642a and the conductor 642b. It is sufficient to overlap with compound 630.

[0201] In addition, with the bottom surface of the insulator 624 as a reference, the oxide 630a and the oxide 630b and the conductive The height of the bottom surface of the conductor 660 in the region where the conductor 660 does not overlap with the oxide 630b is It is preferable that the contact hole is disposed at a position lower than the height of the bottom surface.

[0202] As shown in the figure, a conductor 660 acting as a gate is formed on the oxide 63 of the channel forming region. The side and top surfaces of the insulating layer 630b are covered with an oxide 630c and an insulator 650. As a result, the electric field generated by the conductor 660 is transmitted to the entire channel forming region generated in the oxide 630b. Therefore, the on-current of the transistor 600 is increased, and the frequency characteristic In this specification, the voltage of the first gate and the voltage of the second gate can be improved. The structure of a transistor in which the channel formation region is electrically surrounded by a field is called a surrou This is called the ned channel (S-channel) structure.

[0203] The conductor 605a is a conductor that suppresses the permeation of impurities such as water or hydrogen and oxygen. For example, titanium, titanium nitride, tantalum, or tantalum nitride is preferably used. The conductor 605b is made of tungsten, copper, or aluminum. It is preferable to use a conductive material having a high conductivity. Although the conductor 605 is illustrated as having two layers, it may be formed as having three layers. The above multi-layer structure may be used.

[0204] In addition, the insulators 616, 680, 685, and 688 are the same as the insulators 61 It is preferable that the dielectric constant of the interlayer film is lower than that of the interlayer film 4. For example, the insulator 616, the insulator 680, the insulator The substrate 685 and the insulator 688 may be silicon oxide, silicon oxynitride, or silicon nitride oxide. Silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, carbon Silicon oxide doped with hydrogen and nitrogen, or silicon oxide having vacancies, etc., are appropriately used. That's good.

[0205] In addition, the insulators 616, 680, 685, and 688 are insulators that absorb hydrogen atoms. CVD or ALD using compound gases that do not contain hydrogen atoms or that contain only a small amount of hydrogen atoms The film may be formed by a method.

[0206] In the deposition of the insulating film, a gas having molecules containing silicon atoms is mainly used as the deposition gas. In order to reduce the hydrogen contained in the insulating film, the hydrogen contained in the molecule containing the silicon atom is It is preferable that the number of hydrogen atoms contained in the silicon atom is small, and the molecule containing the silicon atom does not contain hydrogen atoms. Of course, it is preferable that the deposition gas is not a gas having molecules containing silicon atoms. The hydrogen atom content of the fluorine-containing compound is preferably as small as possible, and more preferably it is free of hydrogen atoms. It is nice.

[0207] The above silicon-containing molecules are called Si x -R y For example, the functional group R is , isocyanate group (-N=C=O), cyanate group (-OC≡N), cyano group (-C ≡N), diazo group (=N 2 ), azide group (-N 3 ), nitroso group (-NO), and nitro -NO 2 For example, 1≦x≦3, 1≦y ≦8. Examples of molecules that contain silicon atoms include tetraisopropyl ether. Cyanate silane, tetracyanate silane, tetracyanosilane, hexaisocyanate The silicon source can be used in the present invention. Although a molecule having the same type of functional group bonded to each of the molecules is illustrated, the present embodiment is not limited to this. However, it is also possible to have a structure in which different types of functional groups are bonded to the silicon atom.

[0208] Also, for example, halogen (chlorine, bromine, iodine, or fluorine) is used as the functional group R. For example, 1≦x≦2 and 1≦y≦6. An example of a molecule containing a silane atom is tetrachlorosilane (SiCl 4 ), hexachloro Disilane (Si 2 Cl 6 ) can be used. An example of using chlorine as a functional group is shown, but Other than chlorine, halogens such as bromine, iodine, and fluorine may also be used as functional groups. A structure in which different types of halogens are bonded to the recombinant atoms may also be used.

[0209] The insulator 622 and the insulator 624 function as gate insulators.

[0210] Here, it is preferable that the insulator 624 in contact with the oxide 630 is heated to release oxygen. In this specification, the oxygen released by heating may be called excess oxygen. The body 624 may be made of silicon oxide or silicon oxynitride as appropriate. By providing an insulator in contact with the oxide 630, oxygen vacancies in the oxide 630 are reduced, The reliability of the transistor 600 can be improved.

[0211] Specifically, the insulator 624 is made of an oxide material from which some oxygen is released when heated. It is preferable that the oxides which desorb oxygen by heating are those which are determined by thermal desorption spectrometry (TDS (T Thermal Desorption Spectroscopy (DS) analysis revealed that the oxygen content The amount of child detachment is 1.0×10 18 molecules / cm 3 More than 1.0x1, preferably 0 19molecules / cm 3 More preferably, 2.0×10 19 Molec ules / cm 3 or more than 3.0×10 20 molecules / cm 3 That's all. The surface temperature of the film during the TDS analysis was 100°C or higher for 7 00°C or lower, or in the range of 100°C to 400°C is preferred.

[0212] The insulator 622 prevents impurities such as water or hydrogen from entering the transistor 600 from the substrate side. For example, the insulator 622 preferably functions as a barrier insulating film that suppresses the It is preferable that the hydrogen permeability is lower than that of the insulator 624. The insulators 622 and 672, etc. By surrounding the insulator 624 and the oxide 630, water or water This can prevent impurities such as silicon from entering the transistor 600.

[0213] Further, the insulator 622 is made of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). It is preferable that the material has a function of suppressing diffusion (i.e., the oxygen is less likely to permeate). For example, Preferably, the insulator 622 has a lower oxygen permeability than the insulator 624. The oxide 630 has a function of suppressing the diffusion of impurities and oxygen contained in the insulator 6 22, it is preferable because it can reduce diffusion below the insulating film 22. This can suppress reaction with the oxygen contained in the oxide 630 or the body 624 .

[0214] The insulator 622 is made of an oxide of one or both of aluminum and hafnium, which are insulating materials. It is recommended to use an insulator containing an oxide of aluminum and / or hafnium. Examples of insulators containing oxides include aluminum oxide, hafnium oxide, aluminum and hafnium oxide. It is preferable to use an oxide containing hafnium (e.g., hafnium aluminate). When the insulator 622 is formed using such a material, the insulator 622 is oxidized by the oxide 630. The release of hydrogen and other impurities from the periphery of the transistor 600 into the oxide 630 is suppressed. It functions as a controlling layer.

[0215] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, etc. may be added to these insulators. Aluminum, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, Alternatively, zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride or silicon nitride may be laminated on the insulator. .

[0216] The insulator 622 may be, for example, aluminum oxide, hafnium oxide, tantalum oxide, or oxide. Zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTi O 3 ) or (Ba,Sr)TiO 3 (BST) and other so-called high-k materials. The insulator may be a single layer or a multilayer. For example, when the insulator 622 is a multilayer, the oxide A three-layer laminate in which zirconium, aluminum oxide, and zirconium oxide are formed in this order. Zirconium oxide, aluminum oxide, zirconium oxide, aluminum oxide The insulator 622 may be a four-layer laminate in which the layers are formed in this order. A compound containing tungsten and zirconium may also be used. As integration density increases, the gate insulator becomes thinner, causing problems such as leakage current. By using a high-k material as the insulator that functions as the gate insulator, It is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0217] Note that the insulator 622 and the insulator 624 may have a layered structure of two or more layers. In this case, the laminate structure is not limited to a laminate structure made of the same material, but may be a laminate structure made of different materials. stomach.

[0218] In addition, the oxide 630b and the conductor 642 ( Conductor 642a and conductor 642b) and oxide 643 (oxide 643a and The conductor 642 and the oxide 630 may be arranged in such a manner that they are not in contact with each other. Therefore, the conductor 642 can be prevented from absorbing oxygen from the oxide 630. By preventing the oxidation of the conductor 642, the decrease in the conductivity of the conductor 642 can be suppressed. Therefore, it is preferable that the oxide 643 has a function of suppressing the oxidation of the conductor 642. It is nice.

[0219] Therefore, it is preferable that the oxide 643 has a function of suppressing the permeation of oxygen. The oxide 630b is formed between the conductor 642, which functions as a cathode or drain electrode, and the oxide 630b. By disposing the oxide 643 having a function of suppressing the electric field, the conductor 642 and the oxide 630b are This is preferable because it reduces the electrical resistance between the transistors. The electrical characteristics of the transistor 600 and the reliability of the transistor 600 can be improved.

[0220] The oxide 643 may be a metal oxide having an element M. In particular, the element M is Al. For example, aluminum, gallium, yttrium, or tin may be used. It is preferable that the concentration of element M is higher than that of oxide 630b. Alternatively, the oxide 643 may be a metal oxide such as In-M-Zn oxide. Specifically, in the metal oxide used for the oxide 643, The atomic ratio of element M to element In in the metal oxide used for oxide 630b is It is preferable that the atomic ratio of M is larger than that of M. Also, the thickness of the oxide 643 is 0.5 nm or more. The thickness is preferably 5 nm or less, and more preferably 1 nm or more and 3 nm or less. It is preferable that the oxide 643 has crystallinity. When the oxide 643 has crystallinity, the oxide 630 For example, the oxide 643 can be a hexagonal Such a crystal structure may be capable of suppressing the release of oxygen from the oxide 630.

[0221] The oxide 643 is not necessarily provided. In that case, the conductor 642 (the conductor 64 2a and the conductor 642b) come into contact with the oxide 630, the oxygen in the oxide 630 may diffuse into the conductor 642, causing the conductor 642 to oxidize. As a result, the conductivity of the conductor 642 is likely to decrease. The diffusion into the conductor 642 is referred to as the conductor 642 absorbing the oxygen in the oxide 630. It can be replaced.

[0222] In addition, oxygen in the oxide 630 is converted into conductors 642 (conductors 642a and 642b). Diffusion into the oxide 630b and between the conductor 642a and the oxide 630b causes A foreign layer may be formed between the oxide 630b and the conductor 642. Since the layer contains a large amount of oxygen, it is presumed that the layer has insulating properties. The three-layer structure of the oxide 630b and the hetero layer is a three-layer structure consisting of a metal, an insulator, and a semiconductor. It can be considered as MIS (Metal-Insulator-Semiconductor) structure. In some cases, it is called a diode junction structure, or a MIS structure. do.

[0223] In addition, the above-mentioned different layer is not limited to being formed between the conductor 642 and the oxide 630b. For example, a different layer may be formed between the conductor 642 and the oxide 630c, or between the conductor 64 2 and oxide 630b, and between conductor 642 and oxide 630c. There is a match.

[0224] On the oxide 643, a conductor 642 (conductor) functioning as a source electrode and a drain electrode is formed. The thickness of the conductor 642 is, for example, The thickness may be 1 nm or more and 50 nm or less, and preferably 2 nm or more and 25 nm or less.

[0225] The conductor 642 may be aluminum, chromium, copper, silver, gold, platinum, tantalum, or nickel. , titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, Magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium A metal element selected from the group consisting of indium, lanthanum, and lanthanum, or an alloy containing the above-mentioned metal elements. It is preferable to use an alloy or the like that combines the above-mentioned metal elements. For example, tantalum nitride titanium nitride, tungsten, nitrides containing titanium and aluminum, tantalum and aluminum Ruthenium nitrides, ruthenium oxide, ruthenium nitride, strontium and ruthenium It is preferable to use an oxide containing lanthanum and nickel. Tantalum, titanium nitride, nitrides containing titanium and aluminum, tantalum and aluminum Ruthenium nitride, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium Oxides containing lanthanum and nickel are conductive materials that are difficult to oxidize or absorb oxygen. This is preferable because it is a material that maintains its conductivity even after being heated.

[0226] The insulator 672 is provided in contact with the upper surface of the conductor 642 and functions as a barrier insulating film. It is preferable that an insulator 673 serving as a barrier insulating film is formed over the insulator 672. With such a configuration, the conductor 642 is preferably provided as an insulator 6 Absorption of excess oxygen from the conductive material 80 can be suppressed. In addition, oxidation of the conductive material 642 can be suppressed. This makes it possible to suppress an increase in contact resistance between the transistor 600 and the wiring. Therefore, the transistor 600 can have good electrical characteristics and reliability.

[0227] Therefore, the insulators 672 and 673 have a function of suppressing the diffusion of oxygen. For example, the insulator 672 has a function of suppressing oxygen diffusion more than the insulator 680. The insulator 672 is preferably made of, for example, aluminum and hafnium. An insulator containing one or both oxides may be formed. For example, the insulator 673 may be Silicon nitride, silicon oxynitride, or the like may be used.

[0228] In addition, impurities such as water or hydrogen are arranged through the insulators 672 and 673. This can prevent diffusion from the insulator 680 or the like to the transistor 600 side. In this way, the transistor 600 is protected against impurities such as water or hydrogen, and against the diffusion of oxygen. It is preferable to surround the insulator 672 and the insulator 673 having a function of suppressing the heat generation. I wish.

[0229] The insulator 650 functions as a gate insulator. The insulator 650 is formed on the top surface of the oxide 630c. The insulator 650 is preferably made of silicon oxide, silicon oxynitride, Silicon oxynitride, silicon nitride, silicon oxide with fluorine, silicon oxide with carbon Uses silicon, silicon oxide doped with carbon and nitrogen, and silicon oxide with vacancies In particular, silicon oxide and silicon oxynitride are stable against heat. preferable.

[0230] Similar to insulator 624, insulator 650 is formed using an insulator that releases oxygen upon heating. It is preferable to use an insulator that releases oxygen when heated as the insulator 650. By providing the oxide 630b in contact with the upper surface of the oxide 630c, the channel forming region of the oxide 630b is effectively As in the insulator 624, the water in the insulator 650 can be effectively supplied with oxygen. Alternatively, it is preferable that the concentration of impurities such as hydrogen be reduced. It is preferable to set the thickness to 1 nm or more and 20 nm or less.

[0231] A metal oxide may be provided between the insulator 650 and the conductor 660. It is preferable to suppress the diffusion of oxygen from the insulator 650 to the conductor 660. By providing a metal oxide that suppresses the diffusion of oxygen from the insulator 650 to the conductor 660, In other words, the decrease in the amount of oxygen supplied to the oxide 630 can be suppressed. In addition, oxidation of the conductor 660 due to oxygen in the insulator 650 can be suppressed.

[0232] The metal oxide may also function as a part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 650, the metal oxide It is preferable to use metal oxide, which is a high-k material with a high relative dielectric constant, for the gate electrode. By forming the insulating material into a laminated structure of the insulating material 650 and the metal oxide, the insulating material is stable against heat. Therefore, the physical film of the gate insulator can be formed into a laminated structure having a high dielectric constant. This makes it possible to reduce the gate potential applied during transistor operation while maintaining the thickness. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator. .

[0233] Specifically, hafnium, aluminum, gallium, yttrium, zirconium, tungsten made of tin, titanium, tantalum, nickel, germanium, or magnesium. A metal oxide containing one or more selected metals can be used. Aluminum oxide, an insulator containing oxides of either or both of aluminum and hafnium Hafnium, hafnium oxide, aluminum and oxides containing hafnium (hafnium aluminium) It is preferable to use a laminate.

[0234] Alternatively, the metal oxide may function as a part of the gate. In this case, In this case, it is preferable to provide a conductive material containing oxygen on the channel formation region side. By providing the conductive material on the channel formation region side, oxygen released from the conductive material is This will make it easier for the supply to be provided to the region.

[0235] In particular, the metal oxide in which the channel is formed is used as a conductor that functions as a gate. It is preferable to use a conductive material containing a metal element and oxygen. Conductive materials containing indium tin oxide and tungsten oxide may also be used. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide Indium tin oxide containing nitrogen may also be used. Mugallium zinc oxide may be used. By using such a material, the channel is formed In some cases, hydrogen can be captured from the metal oxide that is insulated from the outer In some cases, it may be possible to capture hydrogen that is mixed in from the surroundings, etc.

[0236] The conductor 660 is disposed so that its bottom surface and side surface are in contact with the insulator 650. The conductor 660 is Although FIG. 8 shows a two-layer structure, it may be a single-layer structure or a laminated structure of three or more layers. This is also fine.

[0237] The conductor 660a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule ( N 2 O, NO, NO 2 ), conductive material that suppresses the diffusion of impurities such as copper atoms It is preferable to use a material that is low in oxygen (e.g., oxygen atoms, oxygen molecules, etc.). It is preferable to use a conductive material having a function of suppressing the diffusion of the metal oxide (metal oxide layer) or the like.

[0238] In addition, the conductor 660a has a function of suppressing the diffusion of oxygen, and thus the conductor 660a is included in the insulator 650. The oxygen contained in the conductive material 660b can prevent the conductive material 660b from being oxidized and the conductivity from decreasing. Examples of conductive materials that have the function of suppressing oxygen diffusion include tantalum and nitride. It is preferable to use tantalum, ruthenium, ruthenium oxide, or the like.

[0239] The conductor 660b is a conductive material mainly composed of tungsten, copper, or aluminum. In addition, since the conductor 660 also functions as a wiring, It is preferable to use a highly conductive material for the body 660b. For example, tungsten, copper, Alternatively, a conductive material mainly composed of aluminum can be used. 0b may be a laminated structure, for example a laminate of titanium or titanium nitride and the above conductive material. The structure may also be used.

[0240] The insulator 680 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or fluorine. silicon oxide doped with , silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen It is preferable to use silicon or silicon oxide having vacancies. Silicon and silicon oxynitride are preferred because they are thermally stable. In particular, silicon oxide Materials such as silicon oxynitride, silicon oxide with vacancies, etc., have oxygen that is released by heating. In addition, the insulator 680 is preferably a material having the above-mentioned structure. The material may be laminated, for example, a silicon oxide film formed by a sputtering method, A layered structure of silicon oxynitride formed by CVD can be formed on top of the silicon oxide. Furthermore, silicon nitride may be laminated on top of it.

[0241] Here, it is preferable that the insulator 680 has excess oxygen. For example, the insulator 680 is Silicon oxide or silicon oxynitride may be used as appropriate. By providing the oxide 630 in contact with the oxide 630, oxygen vacancies in the oxide 630 are reduced, and the The reliability of the transistor 600 can be improved by adding excess oxygen to the insulator 680. For example, the insulator 682 is deposited by sputtering in an atmosphere containing oxygen. The insulator 682 is formed in an atmosphere containing oxygen by sputtering. This allows oxygen to be added to the insulator 680 while it is being formed.

[0242] It is preferable that the concentration of impurities such as water or hydrogen in the insulator 680 is reduced. , the top surface of the insulator 680 may be planarized.

[0243] The insulator 682 prevents impurities such as water or hydrogen from entering the insulator 680 from above. In addition, the insulator 682 preferably functions as a barrier insulating film that prevents oxygen from permeating. The insulator 682 preferably functions as a barrier insulating film that suppresses the Alternatively, an insulator such as aluminum oxide, silicon nitride, or silicon nitride oxide may be used. For example, aluminum oxide, which has a high barrier property against oxygen, is used as the insulator 682. That's good.

[0244] As shown in FIG. 8B, insulator 682 is configured to directly contact oxide 630c. This structure suppresses the diffusion of oxygen contained in the insulator 680 into the conductor 660. Therefore, the oxygen contained in the insulator 680 can be oxidized through the oxide 630c. Since the oxide 630a and the oxide 630b can be efficiently supplied with the oxygen, the oxide 630a and oxide 630b, thereby improving the electrical and signal characteristics of transistor 600. The reliability can be improved.

[0245] In addition, it is preferable to provide an insulator 685 functioning as an interlayer film over the insulator 682. The insulator 685, like the insulator 624, has a low impurity concentration, such as water or hydrogen, in the film. It is preferable that the amount of the ion exchange rate is reduced.

[0246] The conductor 640 is made of a conductive material mainly composed of tungsten, copper, or aluminum. It is preferable that the conductor 640 has a laminated structure. The body 640 has a circular shape when viewed from above, but is not limited to this. The conductor 640 may have a substantially circular shape such as an ellipse, a polygonal shape such as a rectangle, or a rectangular shape when viewed from above. The corners of a polygon such as a rounded shape may be rounded.

[0247] In addition, when the conductor 640 has a layered structure, impurities such as water or hydrogen and oxygen are not permeable. It is preferable to use a conductive material that has a function of suppressing overheating. For example, tantalum, nitride Tantalum, titanium, titanium nitride, ruthenium, or ruthenium oxide can be used. It is also preferable that the material has a function of suppressing the permeation of impurities such as water or hydrogen, and oxygen. The conductive material may be used in a single layer or a multilayer structure. Impurities such as water or hydrogen diffused from 680, etc., are transferred to oxide 63 through conductor 640. In addition, the oxygen added to the insulator 680 can be further reduced from being mixed into the insulator 680. This can prevent the light from being absorbed by the conductor 640.

[0248] In addition, a conductor 646a is disposed in contact with the upper surface of the conductor 640a and the upper surface of the conductor 640c. The conductor 646b is disposed in contact with the upper surface of the conductor 640b, and the conductor 640d is disposed on the upper surface of the conductor 646b. A conductor 746 is disposed in contact with the surface. 746 uses conductive materials mainly composed of tungsten, copper, or aluminum. In addition, the conductor 646a, the conductor 646b, and the conductor 746 are preferably formed in a laminated structure. For example, it may be a laminate of titanium or titanium nitride and the above conductive material. The conductor may be formed so as to be embedded in an opening provided in the insulator.

[0249] The insulator 685, the conductor 646a, the conductor 646b, and the conductor 746 are covered with an insulator 686 is provided. The insulator 686 may be, for example, silicon oxide, silicon oxynitride, or nitride. Silicon oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum oxide nitride Aluminum, aluminum nitride, hafnium oxide, hafnium oxide nitride, hafnium oxide nitride The material may be aluminum, hafnium nitride, zirconium oxide, or the like, and may be provided as a laminate or a single layer. This can be done.

[0250] For example, the insulator 686 may be made of a material with high dielectric strength, such as silicon oxynitride, and a material with high dielectric constant A stacked structure with a (high-k) material may be used. By using high dielectric constant (high-k) insulators, sufficient capacitance can be ensured and dielectric strength can be improved. By having an insulator with a large capacitance, the dielectric strength is improved and electrostatic breakdown of the capacitance element 655 is suppressed. It is possible.

[0251] In addition, gas oxide is an example of a high dielectric constant (high-k) material (material with a high relative dielectric constant) insulator. Al, hafnium oxide, zirconium oxide, aluminum and hafnium containing oxide oxides with aluminum and hafnium; oxide-nitrides with silicon and hafnium oxide having silicon and hafnium, oxynitride having silicon and hafnium, or oxide and hafnium Nitride containing nium.

[0252] On the other hand, materials with high dielectric strength (materials with low dielectric constant) include silicon oxide and oxynitride. Silicon, silicon oxynitride, silicon nitride, silicon oxide doped with fluorine, carbon doped Silicon oxide doped with carbon and nitrogen, silicon oxide with vacancies Examples include rubber or resin.

[0253] The conductor 656 is disposed so as to overlap at least a portion of the conductor 646a with the insulator 686 interposed therebetween. The conductor 656 may be any conductor that can be used for the conductor 646. .

[0254] In addition, an insulator 688 serving as an interlayer film is provided on the insulator 686 and the conductor 656. The insulator 688 is preferably formed in a manner similar to the insulator 624, which is capable of preventing water or hydrogen from entering the membrane. It is preferable that the concentration of impurities such as these be reduced.

[0255] <<Modification of memory cell>> A modified example of the memory cell will be described below with reference to FIG. 9. FIG. 9A shows a memory cell 8 9B is a cross-sectional view of memory cell 860. 9A corresponds to the area indicated by the dashed line A1-A2 in FIG. A cross section of the transistor 690 in the channel length direction and a cross section of the transistor 790 in the channel width direction are shown. In the top view of FIG. 9A, some elements are omitted for clarity. The X, Y, and Z directions shown in the figure are perpendicular or cross each other. Here, the X and Y directions are parallel or approximately parallel to the substrate surface, and the Z direction is preferably perpendicular or approximately perpendicular to the substrate surface.

[0256] The memory cell 860 shown in FIG. In addition, the transistor 690 and the transistor 790 are used in the 8. The memory cell 860 shown in FIG. 8 differs from the memory cell 860 shown in FIG. 8, in which transistor 790 is the same as transistor 690. The transistors 790 are formed in the same layers and have the same configuration. The description of the components of the transistor 690 can be taken into consideration.

[0257] The transistor 690 has an oxide 630c that is connected to the insulator 680, the insulator 672, and the insulator 673. , conductor 642 (conductor 642a, conductor 642b), and oxide 630b. The transistor 6 is formed in a U-shape along the opening. Different from 00.

[0258] For example, the channel length of a transistor is miniaturized (typically, 5 nm or more and less than 60 nm, preferably When the thickness of the first insulating film is 10 nm or more and 30 nm or less, the transistor 600 has the above structure. By doing so, the effective L length can be increased. When the distance between the first and second electrodes 642b is 20 nm, the effective L length is 40 nm or more and 60 nm or less. The distance between the conductor 642a and the conductor 642b, i.e., the minimum processing dimension is set to 2 times or more and 3 times or more. Therefore, the memory cell 860 shown in FIG. A structure having a transistor 690, a transistor 790, and a capacitor element 655 having excellent It becomes.

[0259] <<Metal oxides>> The oxide 630 is preferably a metal oxide that functions as an oxide semiconductor. Metal oxides applicable to the oxide 630 according to the present invention will be described below.

[0260] The metal oxide preferably contains at least indium or zinc. In addition to these, it is preferable that the metal oxide contains gallium, yttrium, It is preferable that the material contains tin, etc. Also, boron, titanium, iron, nickel, germanium, etc. Cr, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum It may contain one or more of the following: zinc, tungsten, magnesium, etc. good.

[0261] Here, the metal oxide is an In-M-Zn oxide having indium, element M and zinc. Here, the element M is aluminum, gallium, yttrium, or Other elements that can be used for element M include boron, titanium, iron, and nickel. , Germanium, Zirconium, Molybdenum, Lanthanum, Cerium, Neodymium, Hafnium However, the element M is the same as the above. In some cases, a combination of multiple elements may be used.

[0262] In this specification, metal oxides containing nitrogen are also referred to as metal oxides. Nitrogen-containing metal oxides are also called metal oxynitrides (met de). It may also be called tetrahydrofuran (tetrahydrofuran) oxynitride.

[0263] As an oxide semiconductor (metal oxide), CAC-OS (Cloud-Aligned C omposite Oxide Semiconductor), CAAC-OS(c- axis Aligned Crystal Oxide Semiconductor ), polycrystalline oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor), pseudo amorphous oxide semiconductor (a-like OS:amo rhodonite-like oxide semiconductor), and amorphous acid The details of these will be described in the following embodiments. do.

[0264] [impurities] Here, the influence of each impurity in the metal oxide will be described.

[0265] When impurities are mixed into an oxide semiconductor, defect states or oxygen vacancies may be formed. Therefore, when impurities are mixed into the channel formation region of the oxide semiconductor, The electrical characteristics of the transistors used in the manufacturing process may become unstable, resulting in poor reliability. If there are oxygen vacancies in the channel formation region, the transistor is likely to have normally-on characteristics. water.

[0266] The defect levels may include trap levels. Charges trapped at the site take a long time to dissipate and behave as if they were fixed charges. Therefore, it is necessary to use a metal oxide with a high density of trap states in the channel formation region. A transistor having such a gate insulating film may have unstable electrical characteristics.

[0267] Furthermore, when impurities are present in the channel formation region of the oxide semiconductor, the crystallinity of the channel formation region increases. In addition, the crystallinity of the oxide provided in contact with the channel forming region may be deteriorated. If the crystallinity of the channel formation region is low, the stability or In addition, the reliability of the oxide crystals provided in contact with the channel forming region tends to deteriorate. If the conductivity is low, interface states may form, which may deteriorate the stability or reliability of the transistor. be.

[0268] Therefore, in order to improve the stability or reliability of a transistor, It is effective to reduce the impurity concentration in the panel formation region and its vicinity. , hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, etc.

[0269] Specifically, in the channel formation region of the oxide semiconductor and its vicinity, The concentration of the above impurities obtained by 18 atoms / cm 3 Below, preferably 2 ×10 16 atoms / cm 3Alternatively, the channel formation region of the oxide semiconductor may be The concentrations of the above impurities obtained by elemental analysis using EDX in the region and its vicinity were The oxide semiconductor is an oxide semiconductor containing an element M. In the case of using the oxide semiconductor, the element M is The concentration ratio of the impurities to the above-mentioned SiO2 is less than 0.10, preferably less than 0.05. The concentration of element M used in calculating the above concentration ratio is the same as the region in which the concentration of the above impurities was calculated. The concentration may be that of the same region or that of the oxide semiconductor.

[0270] In addition, metal oxides with reduced impurity concentrations have a low defect level density, so the trap level density may also be lower.

[0271] In addition, when hydrogen enters an oxygen vacancy in a metal oxide, the oxygen vacancy and hydrogen combine to form V O H V O H acts as a donor, and electrons, which act as carriers, are generated. In addition, some of the hydrogen atoms bond with oxygen, which bonds with metal atoms, and the carrier electrons may be generated.

[0272] Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is a normally-on transistor. In addition, hydrogen in the oxide semiconductor is easily moved by stress such as heat and electric field. Therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of a transistor decreases. There is also a risk.

[0273] That is, V in metal oxide O Reduce H as much as possible and use high-purity intrinsic or substantially high-purity intrinsic It is preferable to make it more volatile.O To obtain an oxide semiconductor with sufficiently reduced H and removing impurities such as moisture and hydrogen from the oxide semiconductor (dehydration treatment, dehydrogenation treatment, etc.). (Sometimes described as "oxygen supply") and (Oxidation) This is sometimes referred to as "synthesis treatment" and is important. O Impurities such as H have been sufficiently reduced. By using an oxide semiconductor in the channel formation region of a transistor, stable electrical characteristics can be obtained. It can be given.

[0274] In addition, an oxide semiconductor having a low carrier concentration is preferably used for the transistor. In the case of lowering the carrier concentration of the oxide semiconductor, the impurity concentration in the oxide semiconductor is lowered. In this specification, the impurity concentration is low and the defect level density is low. A semiconductor having a low level density is called a high-purity intrinsic semiconductor or a substantially high-purity intrinsic semiconductor. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, etc. Examples include silicon and silica.

[0275] In particular, hydrogen contained in oxide semiconductors reacts with oxygen that bonds with metal atoms to form water. In this case, oxygen vacancies may be formed in the oxide semiconductor. If oxygen vacancies are present in the semiconductor, the transistor may have normally-on characteristics. Furthermore, defects in which hydrogen has entered the oxygen vacancies function as donors, generating electrons as carriers. In addition, some of the hydrogen may bond with oxygen that bonds with metal atoms, forming a carrier. Therefore, it is necessary to use a transistor using an oxide semiconductor that contains a large amount of hydrogen. The transistor tends to have normally-on characteristics.

[0276] A defect in which hydrogen has entered an oxygen vacancy (V O H) can function as a donor in the oxide semiconductor. However, it is difficult to quantitatively evaluate the defects. In some cases, the carrier concentration is used instead of the donor concentration. In the study, the parameter of the oxide semiconductor is not the donor concentration but the condition where no electric field is applied. In other words, the carrier concentration in the present specification and the like is used assuming the above-mentioned state. "Concentration" may sometimes be rephrased as "donor concentration."

[0277] Therefore, it is preferable to reduce hydrogen in the oxide semiconductor as much as possible. In oxide semiconductors, secondary ion mass spectrometry (SIMS) The hydrogen concentration obtained by mass spectrometry was calculated as 1×10 20 a toms / cm 3 Less than 1 x 10 19 atoms / cm 3 Less than, more preferably is 5 x 10 18 atoms / cm 3 less than 1×10 18 atoms / c m 3 The oxide semiconductor in which impurities such as hydrogen are sufficiently reduced is used as the transistor chip. By using it in the channel forming region, stable electrical characteristics can be imparted.

[0278] The carrier concentration of the oxide semiconductor in the channel formation region is 1×10 18 cm -3 Below Preferably, 1×10 17 cm -3 More preferably, it is less than 1×10 1 6 cm -3 More preferably, it is less than 1×10 13 cm -3 It is said that it is less than More preferably, 1×10 12 cm -3 It is more preferable that the channel The lower limit of the carrier concentration of the oxide semiconductor in the formation region is not particularly limited. For example, , 1×10 -9 cm -3 It can be said that:

[0279] According to one embodiment of the present invention, a highly reliable memory device or semiconductor device can be provided. According to one embodiment of the present invention, a memory device or a semiconductor device having favorable electrical characteristics can be provided. According to one embodiment of the present invention, a memory device that can be miniaturized or highly integrated can be provided. In addition, according to one embodiment of the present invention, a low-power memory device or a semiconductor device can be provided. A power storage or semiconductor device may be provided.

[0280] <<Other semiconductor materials>> The semiconductor materials that can be used for the oxide 630 are not limited to the above-mentioned metal oxides. As the object 630, a semiconductor material having a band gap (a semiconductor that is not a zero-gap semiconductor) For example, semiconductors of single elements such as silicon, gallium arsenide, etc. Compound semiconductors, layered materials that function as semiconductors (also called atomic layer materials, 2D materials, etc.) It is preferable to use a layered material that functions as a semiconductor. It is suitable for use as a conductive material.

[0281] In this specification, the term "layered material" is a general term for a group of materials having a layered crystal structure. The layered crystal structure is formed by layers of covalent and ionic bonds, which are connected by van der Waals interactions. The structure is layered through bonds that are weaker than covalent or ionic bonds, such as ruthenium. Layered materials have high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, As a result, a transistor with a large on-state current can be provided.

[0282] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are Chalcogen is a general term for elements in group 16. They include oxygen, sulfur, selenium, tellurium, polonium, and livermorium. The cogenides include transition metal chalcogenides and group 13 chalcogenides.

[0283] For example, a transition metal chalcogenide that functions as a semiconductor may be used as the oxide 630. As the transition metal chalcogenide applicable as the oxide 630, specifically, is molybdenum sulfide (represented by MoS 2 ), molybdenum selenide (represented by MoSe 2 ), molybdenum tellurium (represented by MoTe 2 ), tungsten sulfide (represented by WS 2 ), tungsten selenide (represented by WSe 2 ), tungsten tellurium (representatively W.T.e. 2 ), hafnium sulfide (represented by HfS 2 ), hafnium selenide (representatively HfSe 2 ), zirconium sulfide (typically ZrS 2 ), zirconium selenide (representative ZrSe 2 ) etc.

[0284] <Example of memory cell layout> Next, an example of the arrangement of the memory cells 860 will be described with reference to FIGS. 10 and 11. 10 and 11 show a memory cell in which the memory cells 860 are arranged in 2×2×2 pieces. FIG. 10 is a top view of the memory cell block. FIG. 11 is a top view of the memory cell block. FIG. 11 is a cross-sectional view of the Moricell block, taken along the dashed line B1-B2 in FIG. FIG. 11 shows a cross section of a transistor 600 in the channel length direction and 10 shows a cross section of the sta- 700 in the channel width direction. In addition, the X, Y, and Z directions shown in Fig. 10 are The X and Y directions are perpendicular or intersecting directions. The Z direction is parallel or approximately parallel to the substrate surface, and the Z direction is perpendicular or approximately perpendicular to the substrate surface. It is preferable.

[0285] In the memory cell block shown in FIGS. 10 and 11, A memory cell 860_2 is arranged adjacent to the memory cell 860_1. A memory cell 860_3 and a memory cell 860_4 are adjacent to each other in the Y direction of the memory cell 860_2. _4 is arranged. In addition, the Z direction of the memory cell 860_1 and the memory cell 860_2 Adjacent to this are memory cell 860_5 and memory cell 860_6.

[0286] As shown in FIG. 10 and FIG. 11, the memory cell 860_1 and the memory cell 860_2 are The components can be arranged symmetrically. The transistor 600 and the transistor 600 of the memory cell 860_2 are made of the same oxide 6 30a and oxide 630b. As shown, oxide 643b, conductor 642b, conductor 640b, and conductor 646b are also , the transistor 600 of the memory cell 860_1 and the transistor 600 of the memory cell 860_2 600. In this manner, the memory cell 860_1 and the memory cell The oxide 643b, the conductor 642b, and the conductor 860_2 function as wiring or the like. By making the conductor 640b and the conductor 646b common, the area occupied by the memory cell is further reduced. It can be made smaller.

[0287] As shown in FIG. 10, the memory cell 860_1 and the memory cell 860_2 are shared. The conductor 646b extends in the X direction. The line WBL can be extended in the X direction. Also, as shown in FIG. The conductor 746 of 60_1 is provided extending to the memory cell 860_2. This allows the read bit line RBL to extend in the X direction.

[0288] 10, the conductor 660 of the memory cell 860_1 is In this way, the write word line WWL is extended in the Y direction. Also, as shown in FIG. 10, the conductor 742 of the memory cell 860_1 can be a is provided extending to the memory cell 860_3. The line RWL can be extended in the Y direction. Also, as shown in FIG. The conductor 605 of 60_1 is provided extending to the memory cell 860_3. In addition, as shown in FIG. The conductor 705 of the memory cell 860_1 extends to the memory cell 860_3. In this manner, the wiring BG2 can be extended in the Y direction.

[0289] As shown in FIG. 11, the memory cell 860_1 and the memory cell 860_2 are The memory cell 860_1 and the memory cell 860_2 have the same configuration. A memory cell 860_5 and a memory cell 860_6 may be provided.

[0290] In FIG. 10, the oxide 630c is extended to overlap the conductor 660. However, the memory device described in this embodiment is not limited to this. 600 for each memory cell 860, and oxide 630c for each transistor 600. Alternatively, for example, the oxide 630c may be formed in a two-layer structure. In this case, either the upper or lower layer of the oxide 630c is removed for each transistor 600. Alternatively, the electrodes may be provided at a distance from each other.

[0291] <Storage device configuration example> Next, an example of a memory device in which the above-mentioned memory cells 860 are stacked will be described with reference to FIG. FIG. 12 shows a memory cell layer 870 including memory cells 860 on top of a silicon layer 871. 12 is a cross-sectional view of a storage device in which multiple stacked memory cells 10 are stacked. 1 corresponds to memory device 10, silicon layer 871 corresponds to layer 100, and memory cell layer 87 0 corresponds to layer 200.

[0292] First, the silicon layer 871 will be described. The silicon layer 871 has a plurality of transistors 8 00 is provided, and a peripheral circuit 101 (for example, a bit line driver circuit 13 2, etc.).

[0293] The transistor 800 is provided over a substrate 811 and includes a conductor 816 serving as a gate, An insulator 815 that functions as a gate insulator, a semiconductor region 813 that is a part of a substrate 811 , and a low resistance region 814a serving as a source region or a drain region, and The transistor 800 may be a p-channel or n-channel Either is acceptable.

[0294] Here, the transistor 800 shown in FIG. 12 has a semiconductor region 813 (substrate) in which a channel is formed. A part of the plate 811 has a convex shape. The side and top surfaces of the semiconductor region 813 are insulated The conductor 816 is provided so as to cover the conductor 815 through the conductor 815. Such a transistor 800 may be formed by forming a protruding portion of a semiconductor substrate. Since the transistor uses a fin-type transistor, the transistor is also called a fin-type transistor. In addition, the insulating layer may have an insulating material that functions as a mask for forming the protrusions. In the previous section, we showed how to form a protrusion by processing a part of a semiconductor substrate. A semiconductor film having a convex shape may be formed.

[0295] Note that the transistor 800 shown in FIG. 12 is just an example, and the present invention is not limited to this structure. Appropriate transistors may be used depending on the type and driving method.

[0296] Between each structure, a wiring layer is provided in which an interlayer film, wiring, plugs, etc. are provided. Also, the wiring layer may be provided in a plurality of layers according to the design. Conductors that function as wires or wiring are grouped together and given the same symbol. In addition, in the present specification and the like, a wiring and a plug electrically connected to the wiring may be In other words, a part of the conductor functions as a wiring, and In some cases, a body part may act as the plug.

[0297] For example, an insulator 820, an insulator 822, and an insulator 823 are provided on the transistor 800 as interlayer films. The insulating material 820, the insulating material 824, and the insulating material 826 are laminated in this order. The edge 822, the insulator 824, and the insulator 826 are provided with a plurality of insulating layers 824 and 826, each of which functions as a plug or wiring. Conductor 828, conductor 830, etc. are embedded.

[0298] In addition, the insulator that functions as an interlayer film also functions as a planarizing film that covers the uneven shape underneath. For example, the top surface of the insulator 822 may be chemically mechanically polished (C The surface may be planarized by a planarization process using a MP method or the like.

[0299] A wiring layer may be provided on the insulator 826 and the conductor 830. For example, in FIG. An insulator 850, an insulator 852, and an insulator 854 are stacked in this order. In addition, a conductor 856 is formed in the insulator 850, the insulator 852, and the insulator 854. The conductor 856 functions as a plug or a wiring.

[0300] Insulators that can be used as the interlayer film include oxides, nitrides, and oxides having insulating properties. These include nitrides, nitride oxides, metal oxides, metal oxide nitrides, and metal nitride oxides.

[0301] For example, by using a material with a low relative dielectric constant for the insulator that functions as an interlayer film, Therefore, the material can be selected according to the function of the insulator. It is good to choose.

[0302] For example, insulator 820, insulator 822, insulator 826, insulator 852, and insulator 85 It is preferable that the insulating material has a low dielectric constant. For example, the insulating material is a nitride. Silicon oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon Silicon oxide with added carbon and nitrogen, silicon oxide with voids or resin Alternatively, the insulator may be silicon oxide, silicon oxynitride, or the like. Silicon oxynitride, silicon nitride, silicon oxide with fluorine, silicon oxide with carbon silicon oxide doped with silicon, carbon and nitrogen or silicon oxide having vacancies; It is preferable that the silicon oxide and the silicon oxynitride have a laminated structure with a resin. It is thermally stable, so by combining it with resin, a laminated structure with thermal stability and low dielectric constant can be created. Examples of the resin include polyester, polyolefin, polya, etc. Midi (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, etc. be.

[0303] In addition, a transistor using an oxide semiconductor suppresses the permeation of impurities such as hydrogen and oxygen. By surrounding the transistor with an insulator that has the function of stabilizing the electrical characteristics of the transistor, Therefore, impurities such as hydrogen and acids can be contained in the insulators 824 and 850. An insulator having a function of suppressing the permeation of elements may be used.

[0304] Examples of insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen include HO. Uranium, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine , argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium Insulators containing titanium, hafnium or tantalum may be used in a single layer or in a multilayer configuration. Specifically, it acts as an insulator that suppresses the permeation of impurities such as hydrogen and oxygen. Aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide Zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide or tantalum oxide Metal oxides such as silicon nitride, silicon oxide nitride, silicon nitride, etc. can be used.

[0305] Conductors that can be used for wiring and plugs include aluminum, chromium, copper, silver, and gold. , platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium tungsten, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium Materials containing one or more metal elements selected from the group consisting of phosphorus, arsenic, and tungsten can be used. Semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as A silicide such as nickel silicide may also be used.

[0306] For example, the conductor 828, the conductor 830, the conductor 856, etc. may be made of the above-mentioned materials. Conductive materials such as metals, alloys, metal nitrides, or metal oxides It can be used as a single layer or in a laminated form. Tungsten and It is preferable to use a high melting point material such as molybdenum, and it is more preferable to use tungsten. Alternatively, it is preferable to form the wiring board from a low resistance conductive material such as aluminum or copper. By using a resistive conductive material, the wiring resistance can be reduced.

[0307] An insulator 611 and an insulator 612 are disposed on the silicon layer 871. On the insulator 612, memory cell layers 870_1 to 870_n (n is 1 The value of n is not particularly limited, but is preferably 1 to 20. It is 0 or less, preferably 1 or more and 100 or less, and more preferably 1 or more and 10 or less.

[0308] In each memory cell layer 870, similarly to FIG. 10, memory cells 860 and various wirings are They are arranged in a matrix.

[0309] Also, as shown in FIG. 12, the conductor 646b extending in each memory cell layer 870 is , the conductor 615, the conductor 640e, and the conductor 657 at the end of the memory cell layer 870. The conductor 615 is connected to the conductor 646b in the adjacent upper and lower layers through the conductor 615. The conductor 640e is formed in the same layer as the insulator 622 and has the same structure. , insulator 624, insulator 672, insulator 673, insulator 680, insulator 682, and insulator The conductor 640b is disposed to fill an opening formed in the edge 685 (see FIG. 8B). The conductor 657 has a similar configuration to the insulator 686, the insulator 688, and the insulator The conductive body 614 is disposed so as to fill an opening formed therein, and has a configuration similar to that of the conductive body 640b. has.

[0310] The conductor 640e is provided in contact with the lower surface of the conductor 646b, and A conductor 615 is provided on the lower surface of the conductor 615, and a conductor 657 is provided in contact with the lower surface of the conductor 615. The bottom surface of the conductor 657 contacts the top surface of the conductor 646b in the next lower layer. 46b is connected to the conductor 646b of the adjacent upper and lower layers at the end of the memory cell layer 870. do.

[0311] As shown in FIG. 12, in the bottom memory cell layer 870_1, A conductor 607 is disposed below the insulator 611 and the insulator 612 so as to be embedded therein. The conductor 607 is in contact with a conductor 857 provided in the same layer as the conductor 856. In this manner, the write bit line WBL connected to the memory cell 860 is connected to the conductor 8 57, which is connected to the bit line driver circuit 132. A read bit line RBL, connected to the memory cell 860 in a similar manner as above, is also connected to the conductor 8 57 to the bit line driver circuit 132. As shown in FIG. 2 in the previous embodiment, the wiring BL is connected at the end of the memory cell array. 3 and connects it to the bit line driver circuit 132.

[0312] The memory cell layers 870_1 to 870_n are formed of an insulator 611 and an insulator 6 12, the structure is sealed by the insulator 687, the insulator 683, and the insulator 684. Here, it is preferable that an insulator 611 is disposed on the silicon layer 871, and an insulator 6 An insulator 612 is disposed on the first and second memory cell layers 870_1 to 870_2. The memory cell layer 870_n is arranged, and the insulator 612 is also arranged in the memory cell 870_n in the top view. The insulator 6 is formed in the same pattern as the memory cell layers 870_1 to 870_n. 11, the side surface of the insulator 612, and the memory cell layers 870_1 to 87 An insulator 687 is disposed in contact with the side surface of the memory cell 0_n. The insulating layers 870_1 to 870_n are formed in the shape of sidewalls. The body 611, the insulator 687, and the memory cell layers 870_1 to 870_n are An insulator 683 is disposed thereover. Further, an insulator 684 is disposed thereover. can be.

[0313] The insulators 611, 612, 687, 683, and 684 are insulators. As with the edge 682, it is preferable to use a barrier material.

[0314] Here, each memory cell layer 870 is connected to insulators 614, 687, and 682. The insulators 614, 687, and 682 are made of the same material. It is preferable to use the material of the insulator 614, the insulator 687, and the insulator 682. It is preferable that the film is formed under the same conditions. The contact between the edge 687 and the insulator 682 provides a highly airtight sealing structure. Cut.

[0315] In addition, the insulators 614, 687, and 682 have properties that allow them to capture and fix hydrogen. It is preferable to use a material that has the function of providing the above-mentioned function. Specifically, aluminum oxide, halide, etc. Use of metal oxides such as fluorine, gallium oxide, and indium gallium zinc oxide can be done.

[0316] The insulator 614, the insulator 687, and the insulator 682 that form the encapsulation structure are insulator 680. Therefore, hydrogen mixed in the insulator 680 can be captured and fixed. As a result, the hydrogen concentration in the oxide semiconductor included in the memory cell 860 can be reduced.

[0317] In addition, the insulator 614, the insulator 687, and the insulator 688, which are structures for sealing the memory cell layer 870, The edge 682 is further covered by an insulator 611, an insulator 612, and an insulator 683. For example, as shown in FIG. 12, the memory cell layers 870_1 to 870_n On the outside, the insulator 611 and the insulator 683 come into contact with each other to form a second sealing structure.

[0318] Here, the insulators 611, 612 and 683 have diffusion properties for hydrogen and oxygen. It is preferable to use a material that has a function of suppressing diffusion. In particular, silicon nitride or nitride Silicon oxide has a high barrier property against hydrogen and is therefore preferably used as a sealing material. I wish.

[0319] In addition, an insulator with high coverage is provided above the insulator 683 that covers the upper part of the transistor 600. It is preferable to provide an insulator 684. Note that the insulator 684 is a It is preferable to use the same material as in 3.

[0320] For example, the insulators 612 and 683 can be formed by a sputtering method. The seal can be provided by a membrane having a relatively low hydrogen concentration therein.

[0321] On the other hand, the film formed by the sputtering method has a relatively low coverage. 11 and the insulator 684 are formed by using a CVD method or the like that has high coverage. The sealing performance can be improved.

[0322] Therefore, the insulators 612 and 683 have a higher hydrogen concentration than the insulators 611 and 684. A low degree is preferred.

[0323] In the above manner, the memory cell layers 870_1 to 870_n are formed by the barrier insulating By sealing with a film, hydrogen that diffuses into the oxide semiconductor included in each memory cell 860 is prevented from being diffused. Since the above can be reduced, a highly reliable storage device can be provided.

[0324] Preferably, the insulators 611, 612, 614, 682, and The insulating material 687, the insulator 683, and the insulator 684 are made of a material having a barrier property against oxygen. The sealing structure may have a barrier property against oxygen, so that the insulator 680 is effective. Therefore, the outward diffusion of excess oxygen can be suppressed and the excess oxygen can be efficiently supplied to the transistor 600. do.

[0325] In addition, the memory cell layers 870_1 to 870_n, the insulator 684, etc. It is preferable that an insulator 674 is provided so as to be embedded. As shown in FIG. 12, an insulator 674 and an insulator It is preferable that the height of the upper surfaces of the rims 684 be approximately the same.

[0326] As shown in FIG. 12, the insulators 674, 684, 683, and An opening may be provided in the insulating film 611, and the conductive material 876 may be disposed in the opening. A conductor 878 that functions as a wiring and is in contact with the upper surface of the conductor 876 is in contact with the conductor 856. In addition, the memory cell layer 870_n, the insulator 674, and the conductor 878 may be provided. It is preferable to provide an insulator 689 to cover the insulating layer and function as an interlayer film. By this, the upper wiring (conductor 878) and the silicon layer 8 are connected without going through the memory cell layer 870. 71 circuits can be electrically connected.

[0327] In FIG. 12, the memory cell layers 870_1 to 870_n are formed by insulating layers 611. , the insulator 612, the insulator 687, the insulator 683, and the insulator 684 are collectively sealed. However, the storage device according to the present embodiment is not limited to this configuration. For example, As shown in FIG. 13, each memory cell layer 870 is made up of an insulator 611, an insulator 612, an insulator 6 87, an insulator 683, and an insulator 684 may be used to seal the insulator. Under body 614 are disposed insulator 612 and insulator 611 .

[0328] Insulator 680, insulator 673, insulator 672, insulator 624, insulator 622, insulator 61 6, and an insulator 687 is disposed in contact with the side of the insulator 614. An insulator 683 is provided to cover the insulator 687, and an insulator 684 is provided on the insulator 683. In this case, the capacitor element 655 and the insulator 682 are disposed above the insulator 682. 88 may be disposed on top of insulator 684 .

[0329] Note that this embodiment may be modified in any manner in accordance with the present invention, at least a part of which may be modified in any manner in accordance with the present invention. The present invention can be implemented in appropriate combination with the examples. (Embodiment 3) In this embodiment, a metal oxide semiconductor layer that can be used for the OS transistor described in the above embodiment will be described. CAC-OS (Cloud-Aligned Composite Oxide) xide Semiconductor), and CAAC-OS(c-axis Al The composition of the IG-Crystal Oxide Semiconductor He explains.

[0330] <Metal oxide composition> CAC-OS or CAC-metal oxide is a material that has the function of electrical conductivity. A part of the material has an insulating function, and the whole material has a semiconductor function. In addition, CAC-OS or CAC-metal oxide is used as the channel of a transistor. When used in a hole formation region, the conductive function is to allow the electrons (or holes) that serve as carriers to flow. The function of insulation is to prevent the flow of electrons that act as carriers. The function of switching is achieved by making the function of switching and the function of insulating act in a complementary manner. On / Off function) is added to CAC-OS or CAC-metal oxide In the case of CAC-OS or CAC-metal oxide, By separating their functions, the functionality of both can be maximized.

[0331] In addition, CAC-OS or CAC-metal oxide is used in conductive areas and insulating areas. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In addition, the conductive region and the insulating region in the material are formed by nanoparticle layers. The conductive and insulating regions may be separated by a gap in the material. In addition, the conductive regions are observed as connected clouds with blurred edges. This may be the case.

[0332] In addition, in the CAC-OS or CAC-metal oxide, the conductive region and the insulating region are The peripheral region is 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. The following sizes may be present in the material:

[0333] In addition, CAC-OS or CAC-metal oxide has different band gaps. For example, CAC-OS or CAC-metal oxi de is a component with a wide gap due to the insulating region and a component with a narrow gap due to the conductive region. In the case of this configuration, when a carrier flows, In the narrow gap component, carriers mainly flow. The component having a narrow gap acts complementary to the component having a wide gap. Carriers also flow to the wide gap component in conjunction with the component with a large gap. AC-OS or CAC-metal oxide is placed in the channel formation region of the transistor. When used, the transistor has a high current driving force in the on-state, i.e., a large on-current. And high field effect mobility can be obtained.

[0334] That is, CAC-OS or CAC-metal oxide is a matrix composite material. (matrix composite), or metal matrix composite It can also be called a composite matrix.

[0335] <Metal oxide structure> Oxide semiconductors are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single crystal oxide semiconductor, for example, CAAC-OS (c-axis axially aligned oxide semiconductor) gned crystalline oxide semiconductor), polycrystalline Nanocrystalline oxide semiconductor, nc-OS conductor), pseudo-amorphous oxide semiconductor (a-like OS) us-like oxide semiconductor) and amorphous oxide semiconductor etc.

[0336] In addition, when focusing on the crystal structure, oxide semiconductors may be classified differently from the above. Here, the classification of crystal structures in oxide semiconductors will be explained with reference to FIG. FIG. 14A shows an oxide semiconductor, typically IGZO (containing In, Ga, and Zn). FIG. 1 is a diagram for explaining the classification of crystal structures of metal oxides.

[0337] As shown in Figure 14A, IGZO can be broadly divided into Amorphous and Crystal. They are classified into lline and Crystal. Also, among Amorphous, Completely amorphous. Crystalline Among them, CAAC (c-axis aligned crystalline), nc (nanocrystalline), and CAC (Cloud-Aligned C Crystal also includes single crys Includes stal, and poly crystal.

[0338] The structure within the bold frame in FIG. 14A is in the new crystalline phase. This structure is in the boundary area between Amorphous and Crystal. In other words, the energetically unstable Amorphous and Crystal In other words, it has a completely different structure from ine.

[0339] The crystal structure of the film or substrate was determined by X-ray diffraction (XRD). Here, the quartz glass and Crystal XRD spectrum of IGZO (also called crystalline IGZO) with a crystal structure classified as ine The spectra are shown in Fig. 14B and Fig. 14C. Fig. 14B shows quartz glass, and Fig. 14C shows crystalline This is an XRD spectrum of IGZO. Note that the crystalline IGZO shown in FIG. 14C is I The composition is n:Ga:Zn=4:2:3 [atomic ratio]. For GZO, the thickness is 500 nm.

[0340] As shown by the arrows in FIG. 14B, the peaks in the XRD spectrum of quartz glass are almost symmetrical. On the other hand, as shown by the arrow in Figure 14C, crystalline IGZO has a peak in the XRD spectrum. The asymmetric peaks in the XRD spectrum indicate the presence of crystals. In other words, if the peaks in the XRD spectrum are not symmetrical, then it is an Amorpho It cannot be said that it is us.

[0341] CAAC-OS has a c-axis orientation and multiple nanocrystals are connected in the ab-plane direction. The crystal structure has distortion. The distortion is caused by the area where multiple nanocrystals are connected. In the region, between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement, Indicates the point where the direction is changing.

[0342] Nanocrystals are basically hexagonal, but are not limited to regular hexagons and may be non-regular hexagons. In addition, the distortion may have a lattice arrangement such as a pentagon or a heptagon. In addition, in the CAAC-OS, clear grain boundaries (grain boundaries) are not observed even in the vicinity of the strain. In other words, the grain boundaries are not observed due to the distortion of the lattice arrangement. This is because the CAAC-OS has a high lattice constant in the ab-plane direction. The oxygen atoms are not densely packed, and the bond distance between atoms changes due to the substitution of metal elements. This is thought to be because distortion can be tolerated by making the The crystal structure in which the grain boundaries are observed is called polycrystalline. The grain boundaries act as recombination centers, trapping carriers and causing transistors. This is highly likely to cause a decrease in the on-state current or a decrease in the field effect mobility of the transistor. Therefore, CAAC-OS, which does not have clear grain boundaries, is suitable for the semiconductor layer of transistors. CAAC-OS is one of the crystalline oxides with a crystal structure. For example, In-Zn oxide and In-Ga-Zn oxide are preferable. The material is preferable because it can suppress the generation of crystal grain boundaries more effectively than In oxide.

[0343] In addition, the CAAC-OS has a layer containing indium and oxygen (hereinafter, the In layer) and an element A layered crystal structure in which layers containing M, zinc, and oxygen (hereinafter referred to as the (M,Zn) layer) are stacked. Indium and element M tend to have a layered structure. It is possible, and when the element M in the (M,Zn) layer is replaced with indium, (In,M,Zn) Also, when the indium in the In layer is replaced with element M, (In,M ) layer.

[0344] CAAC-OS is a highly crystalline oxide semiconductor. Since it is not possible to confirm the grain boundaries, the decrease in electron mobility caused by the grain boundaries is unlikely to occur. In addition, the crystallinity of oxide semiconductors can be degraded by the inclusion of impurities or the generation of defects. Therefore, CAAC-OS is an oxide with few impurities and defects (oxygen vacancies, etc.). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors having CAAC-OS have high heat resistance and reliability. CAAC-OS can withstand the high temperatures (so-called thermal budget) in the manufacturing process. Therefore, when CAAC-OS is used for the OS transistor, the manufacturing process can be automated. This makes it possible to expand the degree of freedom.

[0345] The nc-OS is a nano-sized area (e.g., an area of ​​1 nm to 10 nm, especially 1 nm to 3 nm). The atomic arrangement of nc-OS has periodicity in the nanometer range. There is no regularity in the crystal orientation between the crystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be considered to be a-like OS or amorphous oxide semiconductor. It may be indistinguishable from the above.

[0346] The a-like OS is an oxide semiconductor that has a structure between the nc-OS and the amorphous oxide semiconductor. Conductive. A-like OS has voids or low density regions. The OS has a lower crystallinity compared to the nc-OS and CAAC-OS.

[0347] Oxide semiconductors have a variety of structures, each of which has different characteristics. Oxide semiconductors include amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, and nc The compound may have two or more of -OS, CAAC-OS, and CAAC-OS.

[0348] <Transistor Having Oxide Semiconductor> Next, the case where the oxide semiconductor is used for a transistor will be described.

[0349] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility can be realized. In addition, a highly reliable transistor can be realized.

[0350] It is preferable to use an oxide semiconductor having a low carrier concentration for the transistor. When the carrier concentration of the conductive film is to be reduced, the impurity concentration in the oxide semiconductor film is reduced. In the present specification and the like, the impurity concentration is low and the defect level density is low. The low density is referred to as high purity intrinsic or substantially high purity intrinsic.

[0351] In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states. Therefore, the trap level density may be low.

[0352] In addition, it takes a long time for the charges trapped in the trap states of the oxide semiconductor to disappear. Therefore, the trap level density is high. A transistor in which a channel formation region is formed in an oxide semiconductor has unstable electrical characteristics. There are cases.

[0353] Therefore, in order to stabilize the electrical characteristics of a transistor, the impurity concentration in the oxide semiconductor is In order to reduce the impurity concentration in the oxide semiconductor, It is also preferable to reduce the impurity concentration in the adjacent film. These include potassium metal, alkaline earth metals, iron, nickel, silicon, etc.

[0354] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0355] When an oxide semiconductor contains silicon or carbon, which is one of the group 14 elements, it becomes an oxide. Defect levels are formed in the semiconductor. This causes the silicon and carbon in the oxide semiconductor to The concentration of silicon and carbon near the interface with the oxide semiconductor (Secondary Ion Mass Spectroscopy ( By SIMS (Secondary Ion Mass Spectrometry) The resulting concentration is 2 x 10 18 atoms / cm 3 Less than or equal to 2×10 17 at oms / cm 3 The following applies.

[0356] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels are formed. Therefore, alkali metals or alkaline earth metals may form carriers. A transistor using an oxide semiconductor containing such a metal oxide tends to be normally on. Therefore, the concentration of alkali metal or alkaline earth metal in the oxide semiconductor can be reduced. Specifically, the alkali metal or alkali metal in the oxide semiconductor obtained by SIMS is preferably The concentration of alkaline earth metals is increased by 1×10 18 atoms / cm 3 Less than or equal to 2×10 1 6 atoms / cm 3 To the following:

[0357] In addition, when nitrogen is contained in an oxide semiconductor, electrons that act as carriers are generated, and the carriers The concentration increases and it becomes easier to make the oxide semiconductor n-type. The transistor used in the formation region tends to have normally-on characteristics. In the conductor, it is preferable that the nitrogen content is reduced as much as possible. For example, in an oxide semiconductor The nitrogen concentration in the sample was 5×10 19 atoms / cm 3 Less than, preferably 5×10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 The following applies.

[0358] In addition, hydrogen contained in the oxide semiconductor reacts with oxygen that bonds with metal atoms to form water. When hydrogen enters the oxygen vacancy, the electron carrier In addition, some of the hydrogen may combine with the oxygen that is bonded to the metal atom to form a carbide. Therefore, it is necessary to use an oxide semiconductor that contains hydrogen. Therefore, hydrogen in the oxide semiconductor It is preferable that the SIM is reduced as much as possible. The hydrogen concentration obtained by S is 1×10 20 atoms / cm 3 Less than 1x1 0 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than, More preferably, 1×10 18 atoms / cm 3 Less than.

[0359] To use an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor Thus, stable electrical characteristics can be imparted.

[0360] This embodiment may be implemented in appropriate combination with other embodiments described in this specification. It is possible.

[0361] (Embodiment 4) In this embodiment, the electronic components and the like incorporating the storage devices described in the above embodiments are An example of the electronic device will be described.

[0362] <Electronic components> First, an example of an electronic component incorporating the memory device 10 will be described with reference to FIGS. 15A and 15B. do.

[0363] FIG. 15A shows an electronic component 3000 and a substrate on which the electronic component 3000 is mounted (a mounting substrate 30 15A shows a perspective view of the electronic component 3000 stored in a mold 3011. 15A is partially omitted to show the inside of the electronic component 3000. The electronic component 3000 has a land 3012 on the outside of the mold 3011. The bond 3012 is electrically connected to an electrode pad 3013, which is a memory device. 10 and a wire 3014. The electronic component 3000 is, for example, A plurality of such electronic components are assembled and mounted on a printed circuit board 3002. are electrically connected on the printed circuit board 3002 to complete the mounting board 3004 .

[0364] 15B shows a perspective view of the electronic component 3030. The electronic component 3030 is a SiP (System in Package) em in package) or MCM (Multi Chip Module) This is an example. The electronic component 3030 is mounted on a package substrate 3032 (printed circuit board). An interposer 3031 is provided, and a semiconductor device 3035 is provided on the interposer 3031. A number of storage devices 10 are provided.

[0365] In the electronic component 3030, the storage device 10 is a high bandwidth memory (HBM). dth Memory) as a semiconductor device 3035. is CPU (Central Processing Unit), GPU (Graph ics Processing Unit), FPGA (Field Programming Unit) It is possible to use integrated circuits (semiconductor devices) such as the MOS-capable Gate Array. .

[0366] The package substrate 3032 is a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 3031 may be a silicon interposer, A resin interposer or the like can be used.

[0367] The interposer 3031 has multiple wirings and connects multiple integrated circuits with different terminal pitches. The wiring has a function of electrically connecting the wiring. The wiring is provided in a single layer or in multiple layers. The interposer 3031 is a package substrate that supports an integrated circuit provided on the interposer 3031. The electrode 3032 is electrically connected to the electrode 3033. The interposer is sometimes called a "rewiring board" or "intermediate board." A through electrode is provided in the through hole 3031, and the through electrode is used to connect the integrated circuit to the package substrate 303. 2 may be electrically connected. In addition, in silicon interposers, , TSV (Through Silicon Via) can also be used.

[0368] It is preferable to use a silicon interposer as the interposer 3031. Since the C-interposer does not require active elements, it can be manufactured at a lower cost than integrated circuits. On the other hand, the wiring of the silicon interposer is formed by the semiconductor process. This makes it easy to form fine wiring that is difficult to achieve with resin interposers.

[0369] In HBM, many wires must be connected to achieve a wide memory bandwidth. Therefore, the interposer that mounts HBM requires fine and high-density wiring. Therefore, the interposer for mounting HBM should be a silicon interposer. is preferred.

[0370] In addition, in SiP and MCM using silicon interposers, the integrated circuit and the interposer The reliability is less likely to decrease due to the difference in the expansion coefficient between the silicon interposer. The silicon interposer has a high surface flatness, so the integrated circuit and silicon interposer can be mounted on the silicon interposer without any problems. In particular, it is difficult to cause connection failure between interposers. In 2.5D packaging (2.5-dimensional assembly), silicon interposers are used to place It is preferable to use:

[0371] A heat sink (heat dissipation plate) may be provided on top of the electronic component 3030. When providing an integrated circuit on the interposer 3031, it is preferable to align the height of the integrated circuit provided on the interposer 3031. For example, in the electronic component 3030 shown in the present embodiment, the memory device 10 and the semiconductor device 3 It is preferable to align the height of the 035.

[0372] In order to mount the electronic component 3030 on another substrate, electrodes 30 are attached to the bottom of the package substrate 3032. FIG. 15B shows an example in which the electrode 3033 is formed by a solder ball. By providing solder balls in a matrix on the bottom of the package substrate 3032, a BGA In addition, the electrode 3033 can be made of a conductive material. The bottom of the package substrate 3032 may be provided with conductive pins in a matrix. By providing this, PGA (Pin Grid Array) mounting can be achieved.

[0373] The electronic component 3030 is not limited to BGA and PGA, but may be mounted on other substrates using various mounting methods. For example, SPGA (Staggered Pin Grid Arrangement) ray), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ(Quad Flat J-leaded package) or QFN (Quad Flat Non-leaded package) A mounting method can be used.

[0374] <Electronic equipment> Next, examples of electronic devices incorporating the storage device 10 will be described with reference to FIGS. 16A to 16F, 17A, and 1 7B, 18A to 18C, and 20A and 20B.

[0375] A memory device according to one embodiment of the present invention can be used in various electronic devices. The storage device according to the present invention can be used as a built-in memory in an electronic device. Hereinafter, an information terminal will be described as an example of an electronic device that can use a storage device according to an embodiment of the present invention. Finally, the paper gives examples of systems including game consoles, electrical appliances, mobile devices, parallel computers, and servers, and explains them in detail. Reveal.

[0376] For example, an electronic device in which a storage device according to one embodiment of the present invention can be used is an information terminal. The information terminal 5500 is illustrated in FIG. 16A. The information terminal 5500 includes a housing 5510 and a display unit 5511. As an interface, a touch panel is provided on the display unit 5511, and buttons are provided on the housing 55 It is provided at 10.

[0377] For example, a desk is an electronic device in which a storage device according to one embodiment of the present invention can be used. The desktop information terminal 5300 is shown in FIG. The information terminal has a main body 5301, a display 5302, and a keyboard 5303. .

[0378] In Fig. 16A and Fig. 16B, a smartphone and a desktop information terminal are taken as examples. As shown in the figure, other information terminals include, for example, PDAs (Personal Digital Audio Devices). The present invention is applied to the following: A storage device according to one embodiment of the present invention may be used.

[0379] For example, a portable game machine can be used as an electronic device that can use a storage device according to one embodiment of the present invention. A portable game machine 5200 is illustrated in FIG. 16C. The portable game machine 5200 includes a housing 5201, a display 5202, a button 5203, etc.

[0380] In FIG. 16C, a portable game machine is illustrated as an example, but other game machines, such as , home game consoles, and games installed in entertainment facilities (game centers, amusement parks, etc.) Arcade game machines, batting practice pitching machines installed at sports facilities, etc. A storage device according to one embodiment of the present invention may be used.

[0381] For example, an electronic device in which a memory device according to one embodiment of the present invention can be used is an electric cooling device. The electric refrigerator-freezer 5800 is illustrated in FIG. It has a door 5802 for a refrigerator compartment, a door 5803 for a freezer compartment, and the like.

[0382] In FIG. 16D, an electric refrigerator-freezer is illustrated as an example, but other electric appliances such as For example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, IH cookers, water Servers, heating and cooling appliances including air conditioners, washing machines, dryers, audiovisual equipment The memory device according to the present invention is a digital camera, a digital video camera, or the like. A device may be used.

[0383] For example, an electronic device in which a storage device according to one embodiment of the present invention can be used is an automobile. 5700 is shown in FIG. 16E. Also, FIG. 16F shows a front guard in the interior of a vehicle. FIG. 16F shows the display panel 5 attached to the dashboard. 701, display panel 5702, display panel 5703, and other display panels attached to the pillars. 5704 is shown.

[0384] The display panels 5701 to 5703 display a speedometer, a tachometer, a driving Provides various information by displaying distance, fuel gauge, gear status, air conditioning settings, etc. In addition, the display items and layout displayed on the display panel can be customized to suit the user's preferences. The display panel 5 can be changed as needed to suit the needs of the user, improving the design. The display panels 701 to 5703 can also be used as lighting devices.

[0385] The display panel 5704 displays an image from an imaging device (not shown) installed in the automobile 5700. By projecting an image, it is possible to compensate for the blind spot blocked by the pillar. That is, by displaying an image from an imaging device provided on the outside of the automobile 5700 It can compensate for blind spots and increase safety. It can also project images that complement the invisible parts. This allows the driver to check for safety more naturally and without discomfort. can also be used as a lighting device.

[0386] In Figs. 16E and 16F, a vehicle and a vehicle windshield periphery are shown. The display panel is shown as an example, but other moving objects such as trains and monorails can also be used. For example, for vehicles, ships, and aircraft (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets), A storage device according to one embodiment of the present invention may be used.

[0387] For example, an electronic device in which a storage device according to one embodiment of the present invention can be used is an information terminal. The information terminal 7000 is illustrated in FIG. 17A and FIG. 17B. , a monitor unit 7012, a keyboard 7013, a port 7015, etc.

[0388] The keyboard 7013 and the port 7015 are provided on the housing 7010. For example, the 7015 has a USB port, a LAN port, and an HDMI (High-Definition Finalization Multimedia Interface;HDMI is a registered trademark) It has ports, etc.

[0389] The monitor unit 7012 attached to the housing 7010 can be opened and closed. 17B shows the monitor unit 7012 in an open state, and FIG. 17B shows the monitor unit 7012 in a closed state. For example, the maximum angle at which the monitor unit 7012 can be opened is about 135° ( See Figure 17A).

[0390] The housing 7010 is provided with a cover 7011 that can be opened and closed (see FIG. 17B). A storage device 10 according to an embodiment of the present invention is incorporated inside 7010. The storage device 10 is removable. A device for cooling the storage device 10 or A heat dissipation device may be provided. The storage device 10 can be attached and detached by opening the cover 7011. The information terminal 7000 has high expandability. This makes it possible to perform advanced graphic processing, scientific and technological calculations, and artificial intelligence calculations. .

[0391] For example, a large-sized electronic device can be used with a storage device according to one embodiment of the present invention. The parallel computer 5400 is illustrated in FIG. The computer 5420 includes a plurality of rack-mounted computers 5420.

[0392] FIG. 18B is a perspective schematic diagram showing a configuration example of the computer 5420. The motherboard has a plurality of slots 5431. The PC card 5421 is inserted into the connector 5431. 423, a connection terminal 5424, and a connection terminal 5425, is connected to

[0393] FIG. 18C is a perspective schematic diagram showing a configuration example of a PC card 5421. The board 5422 has a connection terminal 5423 and a connection terminal 5424 on the board 5422. , connection terminal 5425, chip 5426, chip 5427, etc.

[0394] The chip 5426, the chip 5427, etc. are memory devices, CPUs, etc. according to one embodiment of the present invention. Equipped with GPU, FPGA, etc. Chip 5426, chip 5427, etc. are signal input The PC card 5421 has a plurality of terminals (not shown) for output. By inserting it into a socket (not shown) that can be used for Alternatively, the terminal may be connected to a wiring provided on the PC card 5421 by, for example, a reflow method. The electrical connection may be achieved by soldering.

[0395] The connection terminals 5423, 5424, and 5425 are, for example, a PC card 542 1, and can be used as an interface for supplying power to the The standard of the connection terminal 5423, the connection terminal 5424, and the connection terminal 5425 may be, for example, US B (Universal Serial Bus), SATA (Serial ATA) , SCSI (Small Computer System Interface), When outputting a video signal, HDMI (registered trademark) is used.

[0396] The PC card 5421 also has a connection terminal 5428 on the board 5422. The connector 5428 is shaped so that it can be inserted into a slot 5431 of a motherboard 5430. The connection terminal 5428 is for connecting the PC card 5421 and the motherboard 5430. It functions as an interface. For example, the standard of the connection terminal 5428 is PCI E xpress (also known as PCIe; PCI Express and PCIe are registered trademarks of ) are mentioned.

[0397] The parallel computer 5400 is required for, for example, large-scale scientific and technological calculations, and artificial intelligence learning and inference. It is possible to perform large-scale calculations that require

[0398] Generally, in semiconductor devices such as computers, various memory devices are used depending on the application. Figure 19 shows various storage devices by hierarchy. Fast access speed is required, and the lower the storage device, the larger the storage capacity and the higher the recording density. In FIG. 19, from the top layer, the CPU or other processor has registers and The memory embedded in the chip is SRAM (Static Random Access Memory). ory), DRAM, and 3D NAND memory.

[0399] The memory embedded as a register in a CPU or other arithmetic processing device is used for temporary storage of calculation results. Therefore, the frequency of access from the processor is high. Fast operating speed is required. Also, registers are used to hold setting information for the arithmetic processing unit. It also has Noh.

[0400] SRAM is used, for example, in caches. Caches are data held in main memory. It has the function of duplicating and storing part of the information that is being used. It stores frequently used data in a cache. By replicating the data, you can increase the speed at which you can access the data.

[0401] DRAM is used, for example, as main memory. Main memory reads data from storage. DRAM has the function of storing programs and data. The recording density of DRAM is approximately .1~0.3Gbit / mm 2 It is.

[0402] 3D NAND memory is used, for example, for storage. Storage is used for data that needs to be stored for a long period of time. It has the function of storing necessary data and various programs used by the processing unit. Therefore, storage requires a large memory capacity and a high recording density rather than an operating speed. The recording density of the memory devices used for storage is approximately 0.6 to 6.0 Gbit / mm 2 It is.

[0403] A memory device according to one embodiment of the present invention has a high operating speed and is capable of retaining data for a long period of time. In one embodiment of the present invention, a storage device is provided that is separated into a hierarchy in which a cache is located and a hierarchy in which a main memory is located. The storage device can be suitably used as a storage device located in a boundary area 901 including both of the hierarchical levels. In addition, the storage device according to one embodiment of the present invention has a hierarchy in which the main memory is located and a storage The storage device may be preferably used as a storage device located in a boundary area 902 including both the hierarchical level where the image data is located. This can be done.

[0404] The storage device according to one embodiment of the present invention is applicable to a server, a notebook PC, a smartphone, a game machine, Image sensors, IoT (Internet of Things), healthcare, etc. The present invention can be suitably used as a storage device.

[0405] For example, a server is an electronic device that can use a storage device according to an embodiment of the present invention. A system including the server 5100 is illustrated in FIG. 20A. FIG. 20A shows a system including the server 5100 and an information A state in which communication 5110 is performed between a terminal 5500 and a desktop information terminal 5300 is shown diagrammatically.

[0406] The user accesses the server 5100 from an information terminal 5500, a desktop information terminal 5300, etc. 5110 via the Internet. The user can receive the services provided by the administrator of the server 5100. For example, e-mail, SNS (Social Networking Services) rvice), online software, cloud storage, navigation system , translation systems, internet games, online shopping, stocks, foreign exchange, bonds, etc. financial transactions, reservation systems for public facilities, commercial facilities, accommodation facilities, hospitals, etc., internet Examples include watching programs, speeches, lectures, etc.

[0407] In addition, the information available to users, such as scientific and technical calculations, and calculations required for learning and inference of artificial intelligence, If the information terminal 5500 or the desktop information terminal 5300 does not have sufficient processing capacity, The user accesses the server 5100 via communication 5110 and executes the calculation on the server 5100. It is possible to perform calculations or operations.

[0408] For example, artificial intelligence can be used in the services provided on the server 5100. For example, by introducing artificial intelligence into a navigation system, the system can: There are cases where guidance can be flexibly adapted to the situation, such as road congestion and train operation information. For example, By introducing artificial intelligence into the translation system, the system can easily interpret unique expressions such as dialects and slang. For example, artificial intelligence can be used to properly translate the phrases in hospital reservation systems. By using this information, the system can determine the user's symptoms and the degree of injury, and provide appropriate We may be able to introduce you to hospitals, clinics, etc.

[0409] In FIG. 20A, a server 5100, an information terminal 5500, and a desktop information terminal 53 5100, the server 5100 and the information terminal For example, the electronic device may communicate with the Internet. It may be in the form of IoT connected to a network.

[0410] FIG. 20B shows, as an example, a server 5100 and electronic devices (an electric refrigerator-freezer 5800, a mobile Communication 511 between the game machine 5200, the automobile 5700, and the television device 5600) 0 is shown diagrammatically.

[0411] In FIG. 20B, each electronic device may utilize artificial intelligence. The calculations and other operations required for the inference can be performed on the server 5100. The data is transmitted from one of the electronic devices to the server 5100 via communication 5110, and The AI ​​calculation is performed on the server 5100, and the output data is transmitted to the server via communication 5110. The server 5100 transmits the information to one of the electronic devices. This allows the electronic device to The data output by the calculation can be used.

[0412] Note that the electronic device shown in FIG. 20B is an example, and the server 5100 and the Communication 5110 may be performed between electronic devices that are not connected to the network.

[0413] As described above, the memory device according to one embodiment of the present invention can be used in various electronic devices. A storage device according to one embodiment of the present invention can be operated with a small number of power supplies. The cost of electronic devices using the storage device can be reduced. The memory device has a small chip area, which allows electronic devices to be made smaller. In addition, the present invention relates to an electronic device having a large number of memory devices. The storage device is designed to operate at high speeds and with less risk of data loss even in high-temperature environments. By using a storage device according to one embodiment of the present invention, It is therefore possible to provide a highly reliable electronic device that operates reliably even when the

[0414] This embodiment may be implemented in appropriate combination with other embodiments described in this specification. It is possible. [Explanation of symbols]

[0415] BG1: Wiring, BG2: Wiring, C11: Capacitor, M12: Transistor, N11: Node 10: memory device, 11: transistor, 12: transistor, 50: circuit, 51: cell Sense amplifier circuit, 52: AND circuit, 53: analog switch, 54: analog switch , 61: transistor, 62: transistor, 63: transistor, 64: transistor , 66: transistor, 100: layer, 101: peripheral circuit, 111: memory cell array, 1 12: memory cell, 113: memory cell, 121: row decoder, 122: word line driver 123: word line driver circuit, 124: pre-decoder, 131: column decoder 132: bit line driver circuit; 133: precharge circuit; 134: sense amplifier 135: output MUX circuit; 136: driver circuit; 138: page buffer; 41: output circuit, 151: control logic circuit, 200: layer, 200_l: layer, 2 00_1: layer, 200_2: layer, 200_3: layer, 600: transistor, 605: conductive 605a: conductor, 605b: conductor, 607: conductor, 611: insulator, 612: Insulator, 614: Insulator, 615: Conductor, 616: Insulator, 622: Insulator, 624: Insulator, 630: oxide, 630a: oxide, 630b: oxide, 630c: oxide, 6 40: conductor, 640a: conductor, 640b: conductor, 640c: conductor, 640d: conductor conductor, 640e: conductor, 642: conductor, 642a: conductor, 642b: conductor, 64 3: oxide, 643a: oxide, 643b: oxide, 646: conductor, 646a: conductor 646b: conductor, 650: insulator, 655: capacitive element, 656: conductor, 657: conductor Electrical conductor, 660: Electrical conductor, 660a: Electrical conductor, 660b: Electrical conductor, 672: Insulator, 673 : Insulator, 674: Insulator, 680: Insulator, 682: Insulator, 683: Insulator, 684 :Insulator, 685:Insulator, 686:Insulator, 687:Insulator, 688:Insulator, 689 : insulator, 690: transistor, 700: transistor, 705: conductor, 705a: Conductor, 705b: Conductor, 730: Oxide, 730a: Oxide, 730b: Oxide, 7 30c: oxide, 742: conductor, 742a: conductor, 742b: conductor, 743: oxide object, 743a: oxide, 743b: oxide, 746: conductor, 750: insulator, 760: Conductor, 760a: Conductor, 760b: Conductor, 790: Transistor, 800: Transistor resistor, 811: substrate, 813: semiconductor region, 814a: low resistance region, 814b: low resistance Area, 815: insulator, 816: conductor, 820: insulator, 822: insulator, 824: insulator 826: insulator, 828: conductor, 830: conductor, 850: insulator, 852: insulator Edge member, 854: insulator, 856: conductor, 857: conductor, 860: memory cell, 860 _1: memory cell, 860_2: memory cell, 860_3: ​​memory cell, 860_4: memory cell, 860_5: memory cell, 860_6: memory cell, 870: memory cell layer, 870_n: memory cell layer, 870_1: memory cell layer, 870_2: memory cell layer, 8 71: silicon layer, 876: conductor, 878: conductor, 901: boundary region, 902: boundary Area, 3000: Electronic components, 3002: Printed circuit boards, 3004: Mounting boards, 3011: Mold, 3012: Land, 3013: Electrode pad, 3014: Wire, 3030: Electrode Sub-component, 3031: interposer, 3032: package substrate, 3033: electrode, 30 35: Semiconductor device, 5100: Server, 5110: Communication, 5200: Portable game machine, 52 01: Housing, 5202: Display unit, 5203: Button, 5300: Desktop information terminal , 5301: Main unit, 5302: Display, 5303: Keyboard, 5400: Parallel counter Calculator, 5410: rack, 5420: calculator, 5421: PC card, 5422: board , 5423: connection terminal, 5424: connection terminal, 5425: connection terminal, 5426: chip, 5427: chip, 5428: connector, 5430: motherboard, 5431: slot 5500: information terminal, 5510: housing, 5511: display unit, 5600: television device station, 5700: automobile, 5701: display panel, 5702: display panel, 5703: display Panel, 5704: Display panel, 5800: Electric refrigerator-freezer, 5801: Housing, 5802 : Refrigerator door, 5803: Freezer door, 7000: Information terminal, 7010: Housing, 7011 : Cover, 7012: Monitor, 7013: Keyboard, 7015: Port

Claims

[Claim 1] A semiconductor substrate; A first layer to an lth layer (l is an integer of 1 or more), a first insulator covering each of the side surfaces of the first layer through the first layer and the top surface of the first layer; A second insulator; and A conductor; having a peripheral circuit is formed on the semiconductor substrate using transistors formed on the semiconductor substrate; a memory cell array is configured in the kth layer (k is an integer of 1 to 1) using thin film transistors formed in the kth layer; the peripheral circuit includes a first word line driver circuit through an lth word line driver circuit and a bit line driver circuit; the memory cell array configured in the kth layer is electrically connected to the kth word line driver circuit; the memory cell arrays are each electrically connected to the bit line driver circuit; Each of the memory cell arrays has a plurality of memory cells, The memory cell includes a first thin film transistor and a second thin film transistor, the first layer is laminated above the semiconductor substrate, the jth layer (j is an integer of 2 or more and 1 or less) is stacked on the j-1th layer, the first insulator comprises silicon nitride or silicon oxynitride; the first insulator and the second insulator are disposed above the transistor; The thickness of the second insulator is greater than a thickness of the second layer to the first layer stacked together, the conductor electrically connected to the transistor is embedded in the openings of the first insulator and the second insulator, Each of the side surfaces of the first layer to the first layer overlaps with the conductor via the first insulator and the second insulator. Semiconductor device.

Images