Successive approximation a / d converter

Abstract

To provide a successive approximation A / D converter which enhances conversion accuracy.SOLUTION: A SAR-ADC 100 comprises a comparator 120 and a CMOS switch 200. One end 202 of the CMOS switch 200 is connected with an input node of the comparator 120. The CMOS switch 200 includes a PMOS transistor MP1, an NMOS transistor MN1, a first driver 210 and a second driver 220. The first driver 210 is configured to make a current source capability lower than a current sink capability, and the second driver 220 is configured to make a current sink capability lower than a current source capability.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a successive approximation type A / D converter. [Background technology]

[0002] Successive approximation registers (SAR) are used as medium to high resolution (e.g. 8 bits or more) A / D converters (ADCs). SAR-ADCs sample and hold the input voltage and compare it with a first threshold voltage. Depending on the comparison result, a second threshold voltage is determined and a comparison is made again. By repeating this operation, the analog voltage is converted into a digital signal by a binary search. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-96375 A Summary of the Invention [Problem to be solved by the invention]

[0004] The SAR-ADC includes a sample-and-hold circuit and a capacitive D / A converter (CDAC), which are composed of a combination of capacitors and switches. The switches are CMOS switches (also called transfer gates).

[0005] A CMOS switch is a parallel circuit of a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and an N-channel MOSFET. MOSFETs have parasitic capacitance, and error charges are mixed in due to clock feedthrough and charge injection.

[0006] The effect of clock feedthrough becomes noticeable when one end of a CMOS switch is connected to a high impedance node. In a SAR-ADC, this effect is particularly noticeable in a CMOS switch connected to the input node (inverting input terminal or non-inverting input terminal) of a voltage comparator. Specifically, when a CMOS switch is turned off, charge flows from the high impedance node, i.e., the input terminal of the comparator, to the gate of the MOSFET, changing the input voltage of the comparator. This reduces the conversion accuracy of the SAR-ADC.

[0007] A known method for reducing the effects of clock feedthrough is to insert a dummy switch in series with the CMOS switch to cancel the error charge. However, if this method is adopted in a SAR-ADC, the capacitance connected to the output of the D / A converter that generates the threshold voltage increases, narrowing the voltage range of the threshold voltage.

[0008] The present disclosure has been made in light of the above-mentioned circumstances, and it is an exemplary purpose of an embodiment of the present disclosure to provide a successive approximation type A / D converter with improved conversion accuracy. [Means for solving the problem]

[0009] An embodiment of the present disclosure relates to a successive approximation A / D converter. The successive approximation A / D converter includes a comparator and a complementary metal oxide semiconductor (CMOS) switch having one end connected to an input node of the comparator. The CMOS switch includes a P-channel metal oxide semiconductor field effect transistor (MOSFET) and an N-channel MOSFET connected in parallel, a first driver that controls a gate voltage of the P-channel MOSFET, and a second driver that controls a gate voltage of the N-channel MOSFET. The first driver is configured to have a current source capability lower than a current sink capability, and the second driver is configured to have a current sink capability lower than a current source capability.

[0010] Any combination of the above components or conversion of the present disclosure between methods, devices, etc. are also effective as aspects of the present invention. Effect of the Invention

[0011] According to certain aspects of the present disclosure, conversion accuracy can be improved. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a block diagram of a successive approximation register A / D converter (SAR-ADC) 100 according to an embodiment. [Diagram 2] FIG. 2 is a circuit diagram of a portion of a SAR-ADC according to an embodiment. [Diagram 3] FIG. 3 is an operational waveform diagram of the CMOS switch of FIG. [Figure 4] FIG. 4 is a circuit diagram of the CMOS switch according to the first embodiment. [Diagram 5] FIG. 5 shows the operational waveforms (simulation results) of a CMOS switch when the driver capacity is changed. [Figure 6] FIG. 6 is a circuit diagram of a CMOS switch according to a second embodiment. [Figure 7] FIG. 7 is a circuit diagram of a CMOS switch according to a third embodiment. [Figure 8] FIG. 8 is a circuit diagram of a SAR-ADC. [Figure 9] FIG. 9 is a circuit diagram of a SAR-ADC. [Figure 10] FIG. 10 is a circuit diagram of a SAR-ADC. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] (Overview of the embodiment) A summary of some exemplary embodiments of the present disclosure will be described. This summary is intended to provide a simplified overview of some concepts of one or more embodiments for a basic understanding of the embodiments as a prelude to the detailed description that follows, and is not intended to limit the scope of the invention or disclosure. This summary is not intended to be an exhaustive overview of all possible embodiments, nor is it intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may be used to refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed in this specification.

[0014] A successive approximation A / D converter according to one embodiment includes a comparator and a complementary metal oxide semiconductor (CMOS) switch having one end connected to an input node of the comparator. The CMOS switch includes a P-channel metal oxide semiconductor field effect transistor (MOSFET) and an N-channel MOSFET connected in parallel, a first driver that controls a gate voltage of the P-channel MOSFET, and a second driver that controls a gate voltage of the N-channel MOSFET. The first driver is configured to have a current source capability lower than a current sink capability, and the second driver is configured to have a current sink capability lower than a current source capability.

[0015] With this configuration, when the CMOS switch is turned off, the rate of change (slew rate) of the gate voltage of each of the P-channel MOSFET and N-channel MOSFET is limited, which makes it possible to suppress the leakage of charge from the input terminal of the comparator, which is a high impedance node, to the gate of the MOSFET, suppressing fluctuations in the input voltage of the comparator and ultimately improving the conversion accuracy of the SAR-ADC.

[0016] In one embodiment, the first driver may include a first inverter and a first current source connected to a P-type transistor of the first inverter, whereby the speed at which the PMOS transistor is turned off can be limited according to the current amount of the first current source.

[0017] In one embodiment, the first driver may include a first inverter, the size of the P-type transistor of the first inverter may be smaller than the size of the N-type transistor, and in this configuration, the speed of turning off the PMOS transistor can be limited according to the size of the P-type transistor.

[0018] In one embodiment, the first driver may include a first inverter and a first resistor connected in series with a P-type transistor of the first inverter, whereby the speed at which the PMOS transistor is turned off can be limited according to the resistance value of the first resistor.

[0019] In one embodiment, the first driver may further include a first power-down switch connected between the power supply line and the gate of the P-channel MOSFET. With this configuration, the P-channel MOSFET can be fixed in an off state by turning on the first power-down switch.

[0020] In one embodiment, the second driver may include a second inverter and a second current source connected to the NMOS transistor of the second inverter, whereby the speed at which the NMOS transistor is turned off can be limited according to the current of the second current source.

[0021] In one embodiment, the second driver may include a second inverter, the size of the NMOS transistor of the second inverter may be smaller than the size of the PMOS transistor, and in this configuration, the speed of turning off the NMOS transistor can be limited depending on the size of the N-type transistor.

[0022] In one embodiment, the second driver may include a second inverter and a second resistor connected in series with the NMOS transistor of the second inverter, whereby the turn-off speed of the NMOS transistor can be limited according to the resistance value of the second resistor.

[0023] In one embodiment, the second driver may further include a second power-down switch connected between the ground line and the gate of the N-channel MOSFET. With this configuration, the N-channel MOSFET can be fixed in an off state by turning on the second power-down switch.

[0024] In one embodiment, the successive approximation A / D converter may be monolithically integrated on a single semiconductor substrate. "Monolithic integration" includes cases where all of the circuit components are formed on a semiconductor substrate, and cases where the main components of the circuit are monolithically integrated, and some resistors, capacitors, etc. may be provided outside the semiconductor substrate for adjusting the circuit constants. By integrating the circuit on a single chip, the circuit area can be reduced and the characteristics of the circuit elements can be kept uniform.

[0025] (Embodiment) In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their combination.

[0026] Similarly, "a state in which component C is connected (provided) between components A and B" includes not only the case in which components A and C, or components B and C, are directly connected to each other, but also the case in which they are indirectly connected to each other via other components that do not substantially affect the electrical connection between them or that do not impair the functions or effects achieved by their combination.

[0027] 1 is a block diagram of a successive approximation register A / D converter (SAR-ADC) 100 according to an embodiment. The SAR-ADC 100 is integrated on a single semiconductor substrate. The SAR-ADC 100 may be a dedicated chip for the A / D converter, or may be integrated into an IC (Integrated Circuit) having other functions. Alternatively, the SAR-ADC 100 may have a digital section and an analog section configured on separate chips.

[0028] The SAR-ADC 100 includes a sample-and-hold circuit 110, a comparator 120, a controller 130, and a capacitive DAC 140. The capacitive DAC 140 receives an input voltage V IN The capacitive DAC 140 samples the control code CODE k The threshold voltage V THk k indicates the cycle of the successive approximation process. The comparator 120 generates the input voltage V IN and the threshold voltage V THk For example, the comparison signal comp is IN is the threshold voltage V THk If it is larger, it is H (high), and if it is smaller, it is L (low). The controller 130 determines the control code CODE k for the next cycle k+1 based on the output comp of the comparator 120. k+1 The SAR-ADC100 repeats this operation.

[0029] 1 is a functional block diagram simply illustrating the processing of the SAR-ADC 100, and does not limit the specific configuration of the SAR-ADC 100. For example, the sample-and-hold circuit 110 and the capacitive DAC 140 may be integrated using a switched capacitor circuit. The comparator 120 also outputs the sample-and-hold input voltage V IN and the threshold voltage V THk By comparing the difference between V and 0, IN and V THk It is also possible to determine whether the values ​​are larger or smaller.

[0030] 2 is a circuit diagram of a portion of a SAR-ADC 100 according to an embodiment. The SAR-ADC 100 includes a comparator 120 and a CMOS switch 200. One end 202 of the CMOS switch 200 is connected to an input node of the comparator 120. The one end 202 of the CMOS switch 200 can be said to be a high impedance node. The other end 204 of the CMOS switch 200 is connected to a certain voltage V A The CMOS switch 200 may be part of the sample and hold circuit 110 or may be part of the capacitive DAC 140.

[0031] The CMOS switch 200 includes a P-channel MOSFET (hereinafter, PMOS transistor) MP1, an N-channel MOSFET (hereinafter, NMOS transistor) MN1, a first driver 210, and a second driver 220. The PMOS transistor MP1 and the NMOS transistor MN1 are connected in parallel.

[0032] The first driver 210 controls the gate voltage V GP Specifically, when the control signal CTRL is at a first level (e.g., high), the first driver 210 controls the gate voltage V GP When the control signal CTRL is at a second level (for example, low), the gate voltage V GP High level (power supply voltage V DD )

[0033] The second driver 220 controls the gate voltage of the NMOS transistor MN1 in response to the control signal CTRL. Specifically, when the control signal CTRL is at a first level, the second driver 220 controls the gate voltage V GN High level (V DD ), and when the control signal CTRL is at the second level, the gate voltage V GN is set to low level (0V).

[0034] The first driver 210 is configured to have a lower current source capability than a lower current sink capability. That is, the source current I SRC1 is the sink current I SNK1 Less than.

[0035] The second driver 220 is configured to have a lower current sink capability than a lower current source capability. SNK2 is the source current I SRC2 Less than.

[0036] The above is the configuration of the CMOS switch 200. Next, the operation will be described.

[0037] 3 is an operation waveform diagram of the CMOS switch 200 in FIG. 2. Before time t0, the control signal CTRL is at the second level (low), and the gate voltage V GP is the power supply voltage V DD , the gate voltage V of the NMOS transistor MN1 GN is 0V and the CMOS switch 200 is in the off state.

[0038] At time t0, the control signal CTRL transitions from the second level (low) to the first level (high). In response to this transition, the first driver 210 increases the gate voltage V GP Towards 0V, the second driver 220 changes the gate voltage V GN supply voltage V DD Change towards.

[0039] At time t1, the control signal CTRL transitions from a first level (high) to a second level (low). In response to this transition, the first driver 210 increases the gate voltage V GP supply voltage V DD , and the second driver 220 changes the gate voltage V GNChange towards 0V.

[0040] As described above, the current source capability of the first driver 210 is low compared to its current sink capability. Therefore, the gate voltage V GP The rising speed is slower than the falling speed, so the turn-off time of the PMOS transistor MP1 is longer than the turn-on time.

[0041] In addition, the current sink capability of the second driver 220 is lower than its current source capability. GN The falling speed is slower than the rising speed. Therefore, the turn-off time of the NMOS transistor MN1 is longer than the turn-on time, similar to the PMOS transistor MP1.

[0042] The above is the operation of the CMOS switch 200. By limiting the turn-off speed (slew rate) of the CMOS switch 200, the time it takes to absorb the charge that has escaped from one end 202 of the CMOS switch 200 via the gate capacitance Cp of the PMOS transistor MP1 and the gate capacitance Cn of the NMOS transistor MN1 becomes longer. As a result, the voltage V B The fluctuation of the input voltage V of the comparator 120 becomes smaller. B By suppressing the fluctuation of the signal, the conversion accuracy of the SAR-ADC 100 can be improved.

[0043] The present disclosure covers various devices and methods that can be understood as the block diagram or circuit diagram in Fig. 2 or derived from the above description, and is not limited to a specific configuration. Below, more specific configuration examples and examples will be described in order to aid in understanding the essence and operation of the present disclosure and the present invention and to clarify them, without narrowing the scope of the present disclosure.

[0044] Example 1 4 is a circuit diagram of a CMOS switch 200A in accordance with Example 1. The first driver 210A includes a first inverter 212, a first current source 214, and a first power-down switch 216.

[0045] The first inverter 212 includes a P-type transistor MP11 and an N-type transistor MN11. The first current source 214 is connected to the P-type transistor MP11 of the first inverter 212. The first current source 214 includes transistors MP12, MP13, and a current source CS1. The transistors MP12, MP13 form a current mirror circuit, which mirrors back a reference current generated by the current source CS1 and supplies a current Ib1 to the P-type transistor MP11.

[0046] The first power-down switch 216 is connected between the power supply line and the gate of the PMOS transistor MP1. The first power-down switch 216 is formed of a P-type transistor MP14.

[0047] The second driver 220A includes a second inverter 222, a second current source 224, and a second power down switch 226. The second inverter 222 includes a P-type transistor MP21 and an N-type transistor MN21. The second current source 224 is connected to the N-type transistor MN21 of the second inverter 222. The second current source 224 includes transistors MN22, MN23, and a current source CS2. The transistors MN22, MN23 form a current mirror circuit, which mirrors the reference current generated by the current source CS2 and supplies a current Ib2 to the N-type transistor MN21.

[0048] 5 is a diagram of operational waveforms (simulation results) of the CMOS switch 200A when the driver capacity is changed. (i) to (v) show waveforms when the mirror ratio of the current mirror circuit formed of the transistors MP13 and MP12 (MN23 and MN22) of the first driver 210A (220B) is set to 1, 2, 4, 8, and 16. A fixed voltage V A5, when the mirror ratio of the current mirror circuit is reduced and the currents Ib1 and Ib2 are reduced, the voltage V B It can be seen that the change in becomes smaller.

[0049] According to this configuration, in the first driver 210A, the current source capability of the first driver 210A can be limited by the current Ib1 supplied to the P-type transistor MP11 of the first inverter 212, and the voltage V B Fluctuations in the temperature can be suppressed.

[0050] Moreover, by turning on the first power-down switch 216, the PMOS transistor MP1 can be fixed in the off state.

[0051] Similarly, in the second driver 220A, the current sink capability of the second driver 220A can be limited by the current Ib2 supplied to the N-type transistor MN21 of the second inverter 222, and the voltage V B Fluctuations in the temperature can be suppressed.

[0052] Moreover, by turning on the second power-down switch 226, the NMOS transistor MN1 can be fixed in the off state.

[0053] Example 2 6 is a circuit diagram of a CMOS switch 200B according to Example 2. The first driver 210B includes a first inverter 212 and a first power-down switch 216. The size W / L (gate width / gate length) of a P-type transistor MP11 of the first inverter 212 is configured to be smaller than the size W / L of an N-type transistor MN11.

[0054] The second driver 220B includes a second inverter 222 and a second power down switch 226. The size W / L of the N-type transistor MN21 of the second inverter 222 is configured to be smaller than the size W / L of the P-type transistor MP21.

[0055] According to the second embodiment, the current source capability can be limited by reducing the size W / L of the P-type transistor MP11 of the first driver 210B. Similarly, the current sink capability can be limited by reducing the size W / L of the N-type transistor MN11 of the second driver 220B.

[0056] Example 3 7 is a circuit diagram of a CMOS switch 200C in accordance with Example 3. The first driver 210C includes a first inverter 212, a first resistor R1, and a power-down switch 216. The first resistor R1 is connected in series with the P-type transistor MP11 of the first inverter 212.

[0057] The second driver 220C includes a second inverter 222, a second resistor R2, and a power-down switch 226. The second resistor R2 is connected in series with the N-type transistor MN11 of the second inverter 222.

[0058] According to the third embodiment, the current source capability of the first driver 210C can be limited by the resistance value of the first resistor R1. Similarly, the current sink capability of the second driver 220C can be limited by the resistance value of the second resistor R2.

[0059] Various circuit configurations have been proposed for the SAR-ADC, and application of the technology according to the present disclosure is not limited to a specific configuration. An example configuration of the SAR-ADC 100 will be described below.

[0060] 8 is a circuit diagram of the SAR-ADC 100a. The SAR-ADC 100a is a differential type and receives a differential input signal V INP ,V INN The circuit includes a comparator 120, a controller 130, and a switched capacitor circuit 300. The switched capacitor circuit 300 has the functions of the sample-and-hold circuit 110 and the capacitive DAC 140 in FIG.

[0061] In this configuration, one end of the switches SW1 and SW2 is connected to an input terminal of the comparator 120. Therefore, the configuration of the CMOS switch 200 described above can be adopted for the switches SW1 and SW2.

[0062] Fig. 9 is a circuit diagram of the SAR-ADC 100b. The SAR-ADC 100b is obtained by modifying the SAR-ADC 100a in Fig. 8 into a single-ended type. In this configuration, one end of the switches SW3 and SW4 is connected to the input terminal of the comparator 120. Therefore, the configuration of the CMOS switch 200 described above can be adopted for the switches SW3 and SW4.

[0063] Fig. 10 is a circuit diagram of the SAR-ADC 100c. The SAR-ADC 100c is a differential type, similar to the SAR-ADC 100a in Fig. 8. In this configuration, one end of each of the switches SW5 and SW6 is connected to an input terminal of the comparator 120. Therefore, the configuration of the CMOS switch 200 described above can be adopted for the switches SW5 and SW6.

[0064] Those skilled in the art will understand that the application of the present disclosure is not limited to the SAR-ADCs 100a to 100c illustrated herein, but may be applied to other SAR-ADCs of various configurations that are known or that will be available in the future.

[0065] (Additional Note) The present specification discloses the following techniques:

[0066] (Item 1) A successive approximation type A / D converter, A comparator; a CMOS (Complementary Metal Oxide Semiconductor) switch having one end connected to an input node of the comparator; Equipped with The CMOS switch is A P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and an N-channel MOSFET connected in parallel, a first driver for controlling a gate voltage of the P-channel MOSFET; a second driver for controlling a gate voltage of the N-channel MOSFET; Equipped with The first driver is configured to have a lower current sourcing capability than a current sinking capability; The second driver is configured to have a lower current sink capability than a current source capability.

[0067] (Item 2) The first driver is A first inverter; a first current source coupled to the P-type transistor of the first inverter; 2. The successive approximation type A / D converter according to item 1, comprising:

[0068] (Item 3) the first driver includes a first inverter; 2. The successive approximation type A / D converter according to item 1, wherein a size of a P-type transistor of the first inverter is smaller than a size of an N-type transistor.

[0069] (Item 4) The first driver is A first inverter; a first resistor connected in series with the P-type transistor of the first inverter; 2. The successive approximation type A / D converter according to item 1, comprising:

[0070] (Item 5) 5. The successive approximation type A / D converter according to any one of items 1 to 4, wherein the first driver further includes a first power-down switch connected between a power supply line and the gate of the P-channel MOSFET.

[0071] (Item 6) The second driver is A second inverter; a second current source coupled to the NMOS transistor of the second inverter; 6. The successive approximation type A / D converter according to any one of items 1 to 5, comprising:

[0072] (Item 7) the second driver includes a second inverter; 6. The successive approximation type A / D converter according to any one of items 1 to 5, wherein a size of an NMOS transistor of the second inverter is smaller than a size of a PMOS transistor.

[0073] (Item 8) The second driver is A second inverter; a second resistor connected in series with the NMOS transistor of the second inverter; 6. The successive approximation type A / D converter according to any one of items 1 to 5, comprising:

[0074] (Item 9) 6. The successive approximation type A / D converter according to any one of items 1 to 5, wherein the second driver further includes a second power-down switch connected between a ground line and the gate of the N-channel MOSFET.

[0075] (Item 10) 10. The successive approximation type A / D converter according to any one of items 1 to 9, which is monolithically integrated on a single semiconductor substrate. [Explanation of symbols]

[0076] 100 SAR-ADC 110 Sample and hold circuit 120 Comparator 130 Controller 140 Capacitive DAC 200 CMOS Switch 210 1st Driver 212 1st inverter 214 1st current source 216 First power down switch R1 First resistor 220 2nd Driver 222 2nd inverter 224 2nd current source 226 Second power down switch R2 2nd resistor MP1 PMOS transistor MN1 NMOS transistor

Claims

1. 1. A successive approximation type A / D converter, A comparator; a complementary metal oxide semiconductor (CMOS) switch having one end connected to an input node of the comparator; Equipped with The CMOS switch is A P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and an N-channel MOSFET connected in parallel; A first driver for controlling a gate voltage of the P-channel MOSFET; A second driver for controlling a gate voltage of the N-channel MOSFET; Equipped with The first driver is configured to have a lower current sourcing capability than a current sinking capability; The second driver is configured to have a lower current sink capability than a current source capability.

2. The first driver is A first inverter; a first current source coupled to the P-type transistor of the first inverter; 2. The successive approximation A / D converter according to claim 1, comprising:

3. The first driver includes a first inverter; 2. The successive approximation A / D converter according to claim 1, wherein a size of a P-type transistor of said first inverter is smaller than a size of an N-type transistor.

4. The first driver is A first inverter; a first resistor connected in series with the P-type transistor of the first inverter; 2. The successive approximation A / D converter according to claim 1, comprising:

5. 5. The successive approximation type A / D converter according to claim 1, wherein the first driver further includes a first power-down switch connected between a power supply line and the gate of the P-channel MOSFET.

6. The second driver is A second inverter; a second current source coupled to the NMOS transistor of the second inverter; 5. The successive approximation type A / D converter according to claim 1, comprising:

7. The second driver includes a second inverter; 5. The successive approximation type A / D converter according to claim 1, wherein a size of an NMOS transistor of said second inverter is smaller than a size of a PMOS transistor of said second inverter.

8. The second driver is A second inverter; a second resistor connected in series with the NMOS transistor of the second inverter; 5. The successive approximation type A / D converter according to claim 1, comprising:

9. 5. The successive approximation type A / D converter according to claim 1, wherein the second driver further includes a second power-down switch connected between a ground line and the gate of the N-channel MOSFET.

10. 5. The successive approximation type A / D converter according to claim 1, which is monolithically integrated on a single semiconductor substrate.

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