Switching drive device

Abstract

To provide a switching drive device capable of suppressing a surge and increasing switching speed while reducing a circuit scale.SOLUTION: A switching drive device 1 includes: a first charging circuit C1, a first discharging circuit C2, and a second discharging circuit C3 relative to a gate terminal Gp of a power semiconductor 41; and a control circuit 30 that controls the circuits C1, C2, and C3. At the time of turn-on, a first turn-on operation mode for performing charging by the first charging circuit C1 and a second turn-on operation mode for performing charging by the first charging circuit C1 and discharging by the second discharging circuit C3 are executed. At the time of turn-off, a first turn-off operation mode is executed in which discharging is performed by the first discharging circuit C2 and the second discharging circuit C3 and a second turn-off operation mode is executed in which discharging is performed by the first discharging circuit C2.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a switching driver. [Background technology]

[0002] To reduce the size and increase the output density of power converters, it is necessary to reduce the loss of power semiconductors. However, there is a trade-off between the reduction in loss due to high-speed switching and the increase in surge voltage during switching. For this reason, a multi-stage gate resistor driver circuit that increases the switching speed while suppressing the surge voltage within an allowable voltage range has been known (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-129396 Summary of the Invention [Problem to be solved by the invention]

[0004] In the technology of Patent Document 1, high-speed switching is achieved through a P-type MOSFET (PMOS) in the charging circuit when turning on, and high-speed switching is achieved through an N-type MOSFET (NMOS) in the discharging circuit when turning off. However, there is a problem that the provision of a PMOS and an NMOS increases the circuit size and circuit cost. [Means for solving the problem]

[0005] A switching driver according to an embodiment of the present invention is a switching driver that supplies a driving voltage or driving current to a gate terminal of a semiconductor device, comprising: a first circuit having a turn-on resistor and a first switching element and charging the gate terminal when the semiconductor device is turned on; a second circuit having a turn-off resistor and a second switching element and discharging the gate terminal when the semiconductor device is turned off; a third circuit connected to the gate terminal, having a gate resistor and a third switching element and discharging or charging the gate terminal; and a control device that controls on / off of the first to third switching elements. The control device controls charging by the first circuit and discharging or charging by the third circuit when the semiconductor device is turned on to execute a first turn-on operation mode, and then executes a second turn-on operation mode slower than the first turn-on operation mode, and controls discharging by the second circuit and discharging or charging by the third circuit when the semiconductor device is turned off to execute the first turn-off operation mode, and then executes the second turn-off operation mode slower than the first turn-off operation mode. Effect of the Invention

[0006] According to the present invention, it is possible to provide a switching driver that can suppress surges and increase the switching speed while keeping the circuit scale small. [Brief description of the drawings]

[0007] [Figure 1] FIG. 2 is a diagram illustrating a portion of the configuration of a power conversion device. [Diagram 2] 2 is a diagram illustrating details of a switching driver according to the first embodiment. FIG. [Diagram 3] 5A, 5B, 5C, 5D, 5E, and 5F are diagrams illustrating examples of waveforms of each signal at turn-off in the first embodiment. [Figure 4] 5A, 5B, 5C, 5D, 5E, and 5F are diagrams illustrating examples of waveforms of signals at turn-on in the first embodiment. [Diagram 5] FIG. 1 is a diagram showing a configuration for detecting the state of a power semiconductor in a switching driver; [Figure 6] 4A shows the relationship between the time width at turn-off and the drain-source voltage, and FIG. 4B shows the relationship between the time width at turn-off and the drain-source current. [Figure 7] 4(a), (b), and (c) are diagrams for explaining a method for setting the time width at turn-on. [Figure 8] FIG. 13 is a diagram showing a modified example of the first embodiment. [Figure 9] FIG. 4 is a diagram illustrating a switching driver according to a second embodiment. [Figure 10] 11A, 11B, 11C, 11D, 11E, and 11F are diagrams illustrating examples of waveforms of signals at turn-off in the second embodiment. [Figure 11] 11A, 11B, 11C, 11D, 11E, and 11F are diagrams illustrating examples of waveforms of signals at turn-on in the second embodiment. [Figure 12] FIG. 13 is a diagram showing a switching driver according to a third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, the embodiment of the present invention will be described with reference to the drawings. The following description and drawings are examples for explaining the present invention, and are omitted and simplified as appropriate for clarity of explanation. In addition, in the following description, the same or similar elements and processes are given the same reference numerals, and duplicate explanations may be omitted. Note that the contents described below are merely examples of the embodiment of the present invention, and the present invention is not limited to the following embodiment, and can be implemented in various other forms.

[0009] (First embodiment) Fig. 1 is a diagram showing an application example of a switching drive device of this embodiment, and is a diagram showing a part of the configuration of a power conversion device. The power conversion device drives, for example, an electric motor mounted on an electric vehicle. The electric motor has a three-phase coil, and the power conversion device is provided with a three-phase switching arm for applying a predetermined current pattern to the three-phase coil. Fig. 1 shows a three-phase switching arm 500U, which is one phase of a three-phase switching arm 500U, 500V, 500W provided in the power conversion device.

[0010] The three-phase switching arm 500U is provided with an upper arm power semiconductor 42 and a lower arm power semiconductor 41. For the power semiconductors 41 and 42, for example, semiconductor elements such as IGBT, Si-MOSFET, and GaN-MOSFET are used. Note that FIG. 1 shows a case where MOSFETs are used for the power semiconductors 41 and 42.

[0011] The power semiconductors 41 and 42 are provided with a high-voltage side terminal for the main circuit (a collector terminal for an IGBT, or a drain terminal for a MOSFET), a low-voltage side terminal for the main circuit (an emitter terminal for an IGBT, or a source terminal for a MOSFET), and a control terminal (a gate terminal). Note that the power semiconductors may be further connected in parallel in accordance with a desired output current value.

[0012] The positive wiring 52 on the upper arm side is connected to the positive terminal of a DC voltage source such as a battery (not shown). The negative wiring 51 on the lower arm side is connected to the negative terminal of the DC voltage source. The positive wiring 52 is connected to a high-voltage side terminal (drain terminal) for the main circuit of the power semiconductor 42. A low-voltage side terminal (source terminal) for the main circuit of the power semiconductor 42 is connected to an output terminal 53 of the three-phase switching arm 500U and a high-voltage side terminal (drain terminal) for the main circuit of the power semiconductor 41. A low-voltage side terminal (source terminal) for the main circuit of the power semiconductor 41 is connected to the negative wiring 51. The output terminal 53 is connected to a load such as an electric motor.

[0013] The gate terminal Gp and the source terminal Sp of the power semiconductor 41 are connected to the gate terminal 13 and the source terminal 14, respectively, of the gate driver 10 that supplies driving power to the power semiconductor 41. The gate terminal Gp and the source terminal Sp of the power semiconductor 42 are connected to the gate terminal 13 and the source terminal 14, respectively, of the gate driver 20 that supplies driving power to the power semiconductor 42.

[0014] The gate drive devices 10, 20 are connected to a control circuit 30. The control circuit 30 is configured, for example, by a microcomputer. The control circuit 30 outputs control commands for each of the gate drive devices 10, 20 based on a drive command input from a higher-level control device (not shown), and individually controls the on / off of each of the power semiconductors 41, 42. As a result, an AC voltage is output to a load such as an electric motor via an output terminal 53.

[0015] Fig. 2 is a diagram for explaining the details of a switching driver. The basic configuration of a switching driver is composed of either one of gate drivers 10 or 20 and a control circuit 30, and in the example shown in Fig. 2, a switching driver 1 composed of a gate driver 10 and a control circuit 30 is shown. A switching driver composed of a gate driver 20 and a control circuit 30 has the same configuration as the switching driver 1 shown in Fig. 2 and operates in the same manner. The following description will be given taking the switching driver 1 as an example.

[0016] Fig. 2 is a diagram showing a power semiconductor 41 and a switching driver 1 corresponding to the power semiconductor 41, and shows details of the gate driver 10. The gate driver 20 in Fig. 1 has a similar configuration to the gate driver 10. The gate driver 10 includes a first charging circuit C1 having a switching element M1, a first discharging circuit C2 having a switching element M2, and a second discharging circuit C3 having a switching element M3. In the following explanation, an example will be described in which the power semiconductor 41 and the switching elements M2 and M3 are N-type MOSFETs, and the switching element M1 is a P-type MOSFET.

[0017] The first charging circuit C1 includes a positive power supply V1, a switching element M1, an on-gate resistor R1, and a reverse current prevention diode Di1. A source terminal S1 of the switching element M1 is connected to the positive power supply V1. A gate terminal G1 of the switching element M1 is connected to a signal terminal 11 of the gate driver 10. A drain terminal D1 of the switching element M1 is connected to one end of the on-gate resistor R1. The other end of the on-gate resistor R1 is connected to the anode of the reverse current prevention diode Di1.

[0018] The first discharge circuit C2 includes a switching element M2, an off-gate resistor R2, and a reverse current prevention diode Di2. A source side terminal S2 of the switching element M2 is connected to a source terminal 14 of the gate driver 10. A gate terminal G2 of the switching element M2 is connected to a signal terminal 11 of the gate driver 10. A drain side terminal D2 of the switching element M2 is connected to one end of the off-gate resistor R2. The other end of the off-gate resistor R2 is connected to the cathode of the reverse current prevention diode Di2.

[0019] The second discharge circuit C3 includes a switching element M3 and a charge / discharge gate resistor R3. One end of the charge / discharge gate resistor R3 is connected to a gate terminal 13 of the gate driver 10. The other end of the charge / discharge gate resistor R3 is connected to a drain terminal D3 of the switching element M3. A source terminal S3 of the switching element M3 is connected to a source terminal 14 of the gate driver 10. A gate terminal G3 of the switching element M3 is connected to a signal terminal 12 of the gate driver 10.

[0020] The cathode of the reverse current prevention diode Di1 is connected to the anode of the reverse current prevention diode Di2, and is also connected to the gate terminal 13 of the gate driver 10 and one end of the charge / discharge gate resistor R3. The first discharge circuit C2 and the second discharge circuit C3 are connected in parallel to the gate terminal 13. Note that the reverse current prevention diodes Di1 and Di2 may be omitted.

[0021] The signal terminals 11, 12 of the gate driver 10 are connected to a control circuit 30. The gate terminal 13 of the gate driver 10 is connected to a gate terminal Gp of the power semiconductor 41. The source terminal 14 of the gate driver 10 is connected to a source terminal Sp of the power semiconductor 41. In the example shown in Fig. 2, the signal terminals 11, 12 are connected to a common control circuit 30, but the signal terminals 11, 12 may be individually connected to two control circuits provided independently.

[0022] (Explanation of turn-off operation) FIG. 3 is a diagram showing an example of the waveforms of each signal when the power semiconductor 41 is turned off. Waveform (A) shows the voltage waveform of the signal terminal 11. Waveform (B) shows the voltage waveform of the signal terminal 12. Waveform (C) shows the voltage between the gate and source (GpSp) of the power semiconductor 41 (hereinafter referred to as the gate-source voltage Vgs). Waveform (D) shows the voltage between the drain and source (DpSp) of the power semiconductor 41 (hereinafter referred to as the drain-source voltage Vds). Waveform (E) shows the current flowing between the drain and source (DpSp) of the power semiconductor 41 (hereinafter referred to as the drain-source current Ids). Waveform (F) shows the waveform of the switching loss of the power semiconductor 41. Note that the waveforms shown by the dashed lines in FIG. 3 show signal waveforms in a configuration in which the second discharge circuit C3 is deleted from the circuit diagram shown in FIG. 2 (hereinafter referred to as the conventional configuration).

[0023] As shown by the solid line in waveform (A), at time t0, a control command to turn off the power semiconductor 41 is input from the control circuit 30 to the signal terminal 11 of the gate driver 10. That is, the voltage of the signal terminal 11 is switched from L level to H level. When this signal is input to the gate terminals G1, G2 of the switching elements M1, M2, the switching element M1, which is a P-type MOSFET, switches from ON to OFF, and the switching element M2, which is an N-type MOSFET, switches from OFF to ON.

[0024] Furthermore, as shown in waveform (B), at time t0, a control command to turn switching element M3 from OFF to ON is input to signal terminal 12. That is, the voltage of signal terminal 12 is switched from L level to H level. When this signal is input to gate terminal G3 of switching element M3, switching element M3, which is an N-type MOSFET, is switched from OFF to ON. Note that the timing at which the control command to turn ON is input to signal terminal 12 may be later than time t0.

[0025] When switching element M2 is turned on (switching element M1 is turned off) at time t0, the gate-source capacitance of the power semiconductor 41 starts to be discharged from the gate terminal Gp of the power semiconductor 41 in Fig. 2 via the reverse current prevention diode Di2, the off gate resistor R2, and the switching element M2. Also, when switching element M3 is turned on at time t0, the gate-source capacitance of the power semiconductor 41 starts to be discharged from the gate terminal Gp of the power semiconductor 41 via the charge / discharge gate resistor R3 and the switching element M3. As a result, as shown by the solid line in waveform (C), the gate-source voltage Vgs of the power semiconductor 41 starts to decrease.

[0026] When the gate-source voltage Vgs of the power semiconductor 41 reaches the mirror period at time t1, the drain-source voltage Vds of the power semiconductor 41 starts to increase, as shown by the solid line in the waveform (D). In the case of a conventional configuration shown by the dashed line in the waveform (C), when the gate capacitance of the power semiconductor 41 is C, the discharge time constant τ1 of the drain-source voltage Vds of the power semiconductor 41 is CR2. On the other hand, in this embodiment, since the switching element M3 is also turned on at time t0 as shown in the waveform (B), the discharge time constant τ2 of the drain-source voltage Vds of the power semiconductor 41 is C(R2 / / R3). Note that R2 / / R3 represents the combined resistance of the resistors R2 and R3 connected in parallel. Therefore, while the switching element M3 is on (t1 to t2), the discharge speed of the gate-source voltage Vgs of the power semiconductor 41 is accelerated, and the drain-source voltage Vds increases rapidly.

[0027] As shown in the waveform (C), when the mirror period of the gate-source voltage Vgs ends at time t2, the current (drain-source current Ids) flowing between the drain and source of the power semiconductor 41 starts to decrease as shown in the waveform (E). At this time t2, a control command to turn off the switching element M3 is input from the control circuit 30 to the signal terminal 12. That is, the voltage of the signal terminal 12 is switched from the H level to the L level. The timing at which the control command to turn off is input to the signal terminal 12 may be later than time t2. After time t2, the discharge time constant of the gate-source voltage Vgs of the power semiconductor 41 becomes CR2, which is the same as that in the conventional configuration. Therefore, the surge voltage between the drain and source of the power semiconductor 41, which is related to the discharge time constant and occurs after time t2, becomes the same as that in the conventional configuration.

[0028] The switching loss amount of the power semiconductor 41 is represented by an integrated total value of the drain-source voltage Vds of the power semiconductor 41 and the drain-source current Ids of the power semiconductor 41. As shown in the waveform (F), in the case of the conventional configuration (dashed line), the off-gate resistance R2 is set large in order to suppress the drain-source voltage Vds of the power semiconductor 41 to an allowable voltage or less, and the switching loss occurs from time t0 to time t3. On the other hand, in this embodiment, the discharge speed is increased by turning on the switching element M3 at time t0, so that the loss occurs in a shorter period from time t1 to time t3 as shown in the waveform (F). In this way, in this embodiment, the period in which the switching loss occurs is shorter than in the case of the conventional configuration (dashed line), so the loss amount, which is the time integral value of the loss, is also smaller than in the case of the conventional configuration. That is, in the first embodiment, the switching loss amount at turn-off can be reduced compared to the case of the conventional configuration.

[0029] (Explanation of turn-on operation) FIG. 4 is a diagram showing example waveforms of each signal when the power semiconductor 41 is turned on. Waveform (A) shows the voltage waveform of signal terminal 11. Waveform (B) shows the voltage waveform of signal terminal 12. Waveform (C) shows the gate-source voltage Vgs of the power semiconductor 41. Waveform (D) shows the drain-source voltage Vds of the upper arm power semiconductor 42 shown in FIG. 1. Waveform (E) shows the drain-source current Ids of the power semiconductor 41. Waveform (F) shows the switching loss of the power semiconductor 41. As in the case of FIG. 3, the waveforms shown by dashed lines show signal waveforms in the case of a conventional configuration.

[0030] As shown by the solid line in the waveform (A), at time t0, a control command to turn on the power semiconductor 41 is input from the control circuit 30 to the signal terminal 11 of the gate driver 10. That is, the voltage of the signal terminal 11 is switched from H level to L level. When this signal is input to the gate terminals G1 and G2 of the switching elements M1 and M2, the switching element M1 is switched from off to on, and the switching element M2 is switched from on to off. When the switching element M1 is turned on, the gate-source capacitance of the power semiconductor 41 in FIG. 2 is charged by a charging current that flows through the positive power supply V1, the switching element M1, the reverse current prevention diode Di1, and the on-gate resistor R1. As a result, the gate-source voltage Vgs of the power semiconductor 41 begins to increase as shown by the solid line in the waveform (C).

[0031] At time t1, when the gate-source voltage Vgs of the power semiconductor 41 exceeds the threshold voltage Vth, as shown by the solid lines in the waveforms (D) and (E), the drain-source voltage Vds of the power semiconductor 42 on the upper arm side in Fig. 1 begins to increase, and the drain-source current Ids of the power semiconductor 41 begins to increase. In other words, when the power semiconductor 41 on the lower arm side is turned on, the drain-source voltage Vds of the power semiconductor 41 decreases, and conversely, the drain-source voltage Vds of the power semiconductor 42 on the upper arm side, which is in the off state, increases.

[0032] As shown in waveform (B), at time t2, a control command to turn on switching element M3 is input from control circuit 30 to signal terminal 12. That is, the voltage of signal terminal 12 is switched from L level to H level. Note that the timing at which the control command to turn on is input to signal terminal 12 may be earlier than time t2.

[0033] When the voltage of the signal terminal 12 becomes H level at time t2, the switching element M3 turns on, and the gate-source capacitance of the power semiconductor 41 is discharged from the gate terminal Gp of the power semiconductor 41 via the charge-discharge gate resistance R3 and the switching element M3. As a result, when the switching element M3 is on, the gate-source voltage Vgs of the power semiconductor 41 converges to a voltage value determined by the ratio of the charge-discharge gate resistance R3 of the second discharge circuit C3 to the on-gate resistance R1 of the first charge circuit C1. As shown by the solid lines in the waveforms (C) and (D), the gate-source voltage Vgs of the power semiconductor 41 is kept constant from time t2 to time t3. Therefore, the change in the drain-source current Ids of the power semiconductor 41 becomes gentle, and the increase in the drain-source voltage Vds of the power semiconductor 42 on the upper arm side becomes gentle and is suppressed.

[0034] As shown in waveform (B), at time t3, a control command to turn off switching element M3 is input from control circuit 30 to signal terminal 12. That is, the voltage of signal terminal 12 is switched from H level to L level. Note that the timing at which the control command to turn off is input to signal terminal 12 may be later than time t3. As shown by the solid line in waveform (F), switching loss in power semiconductor 41 occurs from time t1 to time t4.

[0035] In the case of the conventional configuration (dashed line), the on-gate resistance R1 is set large in order to suppress the drain-source voltage Vds of the power semiconductor 42 on the upper arm side to a tolerable voltage or less. On the other hand, in this embodiment, the charging speed is slowed down by turning on the switching element M3, and the drain-source voltage Vds of the power semiconductor 42 is suppressed to a tolerable voltage or less. Therefore, it is possible to set the on-gate resistance R1 smaller than in the case of the conventional configuration, and the charging speed can be made faster than before during the period when the switching element M3 is off. As a result, as shown in the waveform (F), the period in which loss occurs is shorter than in the case of the conventional configuration (dashed line). That is, in the first embodiment, the amount of switching loss at turn-on can be reduced compared to the case of the conventional configuration.

[0036] (Control command generating method in control circuit 30) Next, a method for generating a control command in the control circuit 30 will be described. The control command from the control circuit 30 described above is preferably generated according to the state of the power semiconductor 41. Fig. 5 shows a circuit configuration related to the switching driver 1, similar to the case of Fig. 2, and includes a means for detecting the state of the power semiconductor 41.

[0037] 5, means for detecting the state of the power semiconductor 41 include an element current detection unit 61 that detects a drain-source current Ids of the power semiconductor 41, an element voltage detection unit 62 that detects a drain-source voltage Vds of the power semiconductor 41, and an element temperature detection unit 63 that detects a temperature Tj of the power semiconductor 41. A drive command S from a higher-level control device and state detection information (Ids, Vds, Tj) of each of the detection units 61 to 63 are input to the control circuit 30.

[0038] The control circuit 30 sends a control command to each of the signal terminals 11 and 12 of the gate driver 10 based on only the drive command S or on both the drive command S and the state detection information (Ids, Vds, Tj). The state detection information of the power semiconductor 41 can be arbitrarily selected from information other than the above, such as the rising edge of the rate of change of the drain-source voltage Vds and the falling edge of the rate of change of the drain-source voltage Vds and the drain-source current Ids. In this way, the control circuit 30 can more appropriately control the switching operation of the power semiconductor 41 by generating a control command according to the detected state of the power semiconductor 41.

[0039] Although not shown in the figure, a control circuit 30A that outputs a control command to the signal terminal 11 and a control circuit 30B that outputs a control command to the signal terminal 12 may be provided separately instead of the control circuit 30. The drive command S from the higher level and state detection information (Ids, Vds, Tj) of the power semiconductor 41 are input separately to each of the control circuits 30A and 30B.

[0040] Next, control using the state detection information (Ids, Vds, Tj) will be described. Note that, for the control command input to the signal terminal 12 of the gate driver 10 in Fig. 2, that is, the H level of the voltage of the signal terminal 12 shown in the waveform (B) in Fig. 3 and Fig. 4, the time width of the H level is Δton. The time width Δton may be set based on the drain-source voltage Vds of the power semiconductor 41 detected by the element voltage detection unit 62 in Fig. 5, or may be set based on the drain-source current Ids detected by the element current detection unit 61. In that case, both the detection values ​​of the element voltage detection unit 62 and the element current detection unit 61 may be used, or only one of them may be used.

[0041] First, a method of generating a control command for the signal terminal 12 when the power semiconductor 41 is turned off will be described. The larger the time width Δton in FIG. 3, the faster the switching when the power semiconductor 41 is turned off. FIG. 6(a) shows a case where the time width Δton at the time of turning off is set based on the drain-source voltage Vds. As shown in FIG. 6(a), the larger the detection value of the element voltage detection unit 62, the smaller the time width Δton is set, and the smaller the detection value, the larger the time width Δton is set. At that time, a maximum value (Δton_max) or a minimum value (Δton_min) may be set for the time width Δton. In addition, the value of the time width Δton does not have to be changed linearly, and a discrete value may be used. The reason for setting in this way is that the smaller the drain-source voltage Vds of the power semiconductor 41, the larger the voltage difference to the allowable voltage, and therefore the faster the switching speed can be. By setting the time width Δton as shown in FIG. 6(a), high-speed switching can be realized in a wider range according to the drain-source voltage Vds of the power semiconductor 41, and switching loss is reduced.

[0042] FIG. 6(b) shows a case where the time width Δton at the time of turn-off is set based on the drain-source current Ids. In this case, the larger the detection value of the element current detection unit 61, the smaller the time width Δton is set, and the smaller the detection value of the element current detection unit 61, the larger the time width Δton is set. In this case, a maximum value (Δton_max) or a minimum value (Δton_min) may be set for the time width Δton. In addition, the value of the time width Δton does not have to be changed linearly, and a discrete value may be used. The reason for setting in this manner is that the smaller the drain-source current Ids of the power semiconductor 41, the larger the voltage difference to the allowable voltage, and therefore the faster the switching speed can be. By setting the time width Δton as shown in FIG. 6(b), high-speed switching can be realized over a wider range according to the drain-source current Ids of the power semiconductor 41, and switching loss is reduced.

[0043] Next, a method of generating a control command for the signal terminal 12 when the power semiconductor 41 is turned on will be described. The smaller the time width Δton shown in the waveform (B) of Fig. 4, the faster the switching when turned on. In Fig. 4, the fall time of the time width Δton of the voltage signal of the signal terminal 12 may be, for example, the turn-on end time of the power semiconductor 41, or a value obtained by adding or subtracting any time from the turn-on end time. In this case, the rise time of the time width Δton is set to a value obtained by subtracting the time width Δton from the fall time.

[0044] FIG. 7(a) shows a case where the time width Δton at the time of turn-on is set based on the drain-source voltage Vds detected by the element voltage detection unit 62. In this case, the larger the detection value of the element voltage detection unit 62, the larger the time width Δton is set, and the smaller the detection value, the smaller the time width Δton is set. In this case, a maximum value (Δton_max) or a minimum value (Δton_min) may be set for the time width Δton. In addition, the value of the time width Δton does not have to be changed linearly, and a discrete value may be used. The reason for setting it in this way is that the smaller the drain-source voltage Vds of the power semiconductor 41, the larger the voltage difference to the allowable voltage becomes, and thus by performing such a turn-on operation, the switching speed can be made faster. By setting the time width Δton as in FIG. 7(a), high-speed switching can be realized in a wider range according to the drain-source voltage Vds of the power semiconductor 41, and switching loss is reduced.

[0045] FIG. 7(b) shows a case where the time width Δton at the time of turn-on is set based on the drain-source current Ids detected by the element current detection unit 61. In this case, the larger the detection value of the element current detection unit 61, the larger the time width Δton is set, and the smaller the detection value of the element current detection unit 61, the smaller the time width Δton is set. In this case, a maximum value (Δton_max) or a minimum value (Δton_min) may be set for the time width Δton. In addition, the value of the time width Δton does not have to be changed linearly, and a discrete value may be used. The reason for setting it in this way is that the smaller the drain-source current Ids of the power semiconductor 41, the larger the voltage difference to the allowable voltage becomes, and thus by performing such a turn-on operation, the switching speed can be made faster. By setting the time width Δton as in FIG. 7(b), high-speed switching can be realized over a wider range according to the drain-source current Ids of the power semiconductor 41, and switching loss is reduced.

[0046] FIG. 7(c) shows a case where the time width Δton at the time of turning on is set based on the temperature Tj of the power semiconductor 41 detected by the element temperature detection unit 63. In this case, the time width Δton is set to be larger as the temperature Tj is higher, and the time width Δton is set to be smaller as the temperature Tj is lower. In this case, a maximum value (Δton_max) or a minimum value (Δton_min) may be set for the time width Δton. In addition, the value of the time width Δton does not have to be changed linearly, and a discrete value may be used. The reason for setting it in this way is that the lower the temperature Tj of the power semiconductor 41 is, the larger the voltage difference to the allowable voltage becomes, and thus by performing such a turn-on operation, the switching speed can be made faster. By setting the time width Δton as shown in FIG. 7(c), high-speed switching can be realized in a wider range according to the temperature Tj of the power semiconductor 41, and switching loss is reduced.

[0047] (Modification) FIG. 8 is a diagram showing a modification of the first embodiment described above. In the modification shown in FIG. 8, the second discharge circuit C3 is configured with two discharge circuits connected in parallel. One of the parallel-connected discharge circuits includes a charge / discharge gate resistor 3R and a switching element M3, and the other includes a charge / discharge gate resistor 5R and a switching element M5. In the example shown in FIG. 8, the charge / discharge gate resistors 3R and 5R are variable resistors, but they do not have to be variable resistors. Note that the number of discharge circuits connected in parallel in the second discharge circuit C3 may be three or more.

[0048] The values ​​of the charge / discharge gate resistors 3R and 5R may be determined according to a control command from the control circuit 30, or may be determined using the detection values ​​of the element current detector 61, element voltage detector 62, and element temperature detector 63 shown in Fig. 5. In the case of the configuration of Fig. 8, for example, in the case of turn-off, all of the switching elements M2, M3, and M5 are turned on, thereby making it possible to further increase the speed. Note that, in the case of the second discharge circuit C3 shown in Fig. 2, by making the charge / discharge gate resistor R3 a variable resistor, for example, by controlling the value of the variable resistor according to the value of the element temperature Tj, it is possible to perform more appropriate charge / discharge control.

[0049] Second embodiment Fig. 9 is a diagram for explaining a switching driver 1 according to a second embodiment of the present invention. The switching driver 1 shown in Fig. 9 includes a control circuit 30 and a gate driver 10A that sends driving power to a power semiconductor 41. Although not shown in the figure, the switching driver for the power semiconductor 42 on the upper arm side also includes a gate driver having a similar configuration to the gate driver 10A.

[0050] The gate driver 10A includes a first charging circuit C1 having a switching element M1, a first discharging circuit C2 having a switching element M2, and a second charging circuit C4 having a switching element M4. In the following description, a case will be described in which the power semiconductor 41 and the switching element M2 are N-type MOSFETs, and the switching elements M1 and M4 are P-type MOSFETs.

[0051] The first charging circuit C1 and the first discharging circuit C2 of the gate driver 10A have the same configuration as the first charging circuit C1 and the first discharging circuit C2 of the gate driver 10 shown in FIG. 2. The second charging circuit C4 includes a switching element M4 and a charge / discharge gate resistor R4. The source terminal S4 of the switching element M4 is connected to the positive power supply V2. The gate terminal G4 of the switching element M4 is connected to a signal terminal 12 of the gate driver 10A. The drain terminal D4 of the switching element M4 is connected to one end of the charge / discharge gate resistor R4. The other end of the charge / discharge gate resistor R4 is connected to the gate terminal 13 of the gate driver 10A.

[0052] The cathode of the reverse current prevention diode Di1 is connected to the anode of the reverse current prevention diode Di2, and is also connected to the gate terminal 13 of the gate driver 10A and the other end of the charge / discharge gate resistor R4. The first charging circuit C1 and the second charging circuit C4 are connected in parallel to the gate terminal 13. Note that the reverse current prevention diodes Di1 and Di2 may be omitted.

[0053] The signal terminals 11 and 12 of the gate driver 10A are connected to a control circuit 30. The gate terminal 13 of the gate driver 10A is connected to a gate terminal Gp of the power semiconductor 41. The source terminal 14 of the gate driver 10A is connected to a source terminal Sp of the power semiconductor 41. In the example shown in FIG. 9, the signal terminals 11 and 12 are connected to a common control circuit 30, but the signal terminals 11 and 12 may be individually connected to two control circuits provided independently. The potentials of the positive power supplies V1 and V2 may be different, but are generally set to be equal, and in this embodiment, a case where they are set to the same potential will be described as an example.

[0054] (Explanation of turn-off operation) Fig. 10 is a diagram showing example waveforms of each signal when the power semiconductor 41 is turned off. Waveform (A) shows the voltage waveform of signal terminal 11. Waveform (B) shows the voltage waveform of signal terminal 12. Waveform (C) shows the gate-source voltage Vgs of the power semiconductor 41. Waveform (D) shows the drain-source voltage Vds of the power semiconductor 41. Waveform (E) shows the drain-source current Ids of the power semiconductor 41. Waveform (F) shows the waveform of the switching loss of the power semiconductor 41. Note that the waveforms shown by dashed lines in Fig. 10 show signal waveforms in the case of a conventional configuration in which the second charging circuit C4 is deleted from the circuit diagram shown in Fig. 9.

[0055] As shown by the solid line in waveform (A), at time t0, a control command to turn off the power semiconductor 41 is input from the control circuit 30 to the signal terminal 11 of the gate driver 10. That is, the voltage of the signal terminal 11 is switched from L level to H level. When this signal is input to the gate terminals G1, G2 of the switching elements M1, M2, the switching element M1, which is a P-type MOSFET, switches from ON to OFF, and the switching element M2, which is an N-type MOSFET, switches from OFF to ON.

[0056] When the switching element M2 is turned on (switching element M1 is turned off) at time t0, the gate-source capacitance of the power semiconductor 41 starts to be discharged from the gate terminal Gp of the power semiconductor 41 via the reverse current prevention diode Di2, the off-gate resistor R2, and the switching element M2. As a result, as shown by the solid line in the waveform (C), the gate-source voltage Vgs of the power semiconductor 41 starts to decrease.

[0057] As described in the first embodiment, in the case of the conventional configuration (dashed line), the value of the off-gate resistance R2 is set large in order to suppress the drain-source voltage Vds of the power semiconductor 41 to an allowable voltage or less. On the other hand, the value of the off-gate resistance R2 of the first discharge circuit C2 in the second embodiment is set smaller than that in the case of the conventional configuration. For example, in the example shown in FIG. 10, the value of the off-gate resistance R2 is set so that the discharge time constant of the gate-source voltage Vgs from time t0 to time t1 is the same as the time constant τ2 shown in FIG. 3. Therefore, the slope of the solid line of the gate-source voltage Vgs from time t0 to time t1 in FIG. 10 is the same as the slope of the solid line from time t0 to t1 in the waveform (C) in FIG. 3.

[0058] When the gate-source voltage Vgs of the power semiconductor 41 reaches the mirror period at time t1, the drain-source voltage Vds of the power semiconductor 41 starts to increase as shown by the solid line in the waveform (D). When the mirror period for the gate-source voltage Vgs of the power semiconductor 41 ends at time t2 as shown by the solid line in the waveform (C), the drain-source current Ids of the power semiconductor 41 starts to decrease as shown in the waveform (E).

[0059] As shown in waveform (B), at time t21, a control command to turn on switching element M4 is input from control circuit 30 to signal terminal 12. That is, the voltage of signal terminal 12 is switched from H level to L level. Note that the timing (time t21) at which the control command to turn on is input to signal terminal 12 may be later than time t2.

[0060] When the switching element M4 is turned on at time t21, a charging current flows through the positive power supply V2, the switching element M4, and the charge / discharge gate resistance R4. As a result, when the switching element M4 is on, the gate-source voltage Vgs of the power semiconductor 41 converges to a voltage value determined by the ratio of the charge / discharge gate resistance R4 of the second charging circuit C4 to the off-gate resistance R2 of the first discharging circuit C2. In this way, by turning on the switching element M4 while discharging is being performed in the first discharging circuit C2, the discharge speed is slowed down, and the drain-source voltage Vds of the power semiconductor 41 is suppressed to the allowable voltage or less.

[0061] Therefore, as described above, it is possible to set the value of the off-gate resistance R2 smaller than in the conventional configuration, and the discharge speed during the period when the switching element M3 is off can be made faster than in the conventional configuration. As a result, as shown by the solid line in the waveform (F), the period during which losses occur is shorter than in the conventional configuration (dashed line) in which the off-gate resistance R2 is large. That is, even in the second embodiment, the amount of switching loss at turn-off can be reduced compared to the conventional configuration.

[0062] In the example shown in FIG. 10, the timing at which an OFF control command is input to the signal terminal 12, i.e., the timing at which the L level switches to the H level, may be simultaneous with the time t3 at which the drain-source current Ids becomes zero, or it may be later than the time t3.

[0063] (Explanation of turn-on operation) FIG. 11 is a diagram showing example waveforms of each signal when the power semiconductor 41 is turned on. Waveform (A) shows the voltage waveform of the signal terminal 11. Waveform (B) shows the voltage waveform of the signal terminal 12. Waveform (C) shows the gate-source voltage Vgs of the power semiconductor 41. Waveform (D) shows the drain-source voltage Vds of the power semiconductor 42 on the upper arm side shown in FIG. 1. Waveform (E) shows the drain-source current Ids of the power semiconductor 41. Waveform (F) shows the switching loss of the power semiconductor 41. Moreover, the waveforms shown by dashed lines show signal waveforms in the case of a conventional configuration in which the second charging circuit C4 is deleted from the circuit diagram shown in FIG. 9.

[0064] As shown in waveform (A), at time t0, a control command to turn on the power semiconductor 41 is input from the control circuit 30 to the signal terminal 11 of the gate driver 10. That is, the voltage of the signal terminal 11 is switched from H level to L level. When this signal is input to the gate terminals G1, G2 of the switching elements M1, M2, the switching element M1 switches from off to on, and the switching element M2 switches from on to off. When the switching element M1 turns on (the switching element M2 turns off) at time t0, a charging current flows via the positive-side power supply V1, the switching element M1, the reverse current prevention diode Di1, and the on-gate resistor R1.

[0065] As shown in waveform (B), at time t0, a control command to turn switching element M4 from OFF to ON is input from control circuit 30 to signal terminal 12. That is, the voltage of signal terminal 12 is switched from H level to L level. When switching element M4 turns ON at time t0, a charging current flows via positive power supply V2, switching element M4, and charge / discharge gate resistor R4. Note that the timing at which the ON control command is input to signal terminal 12 may be later than time t0.

[0066] When charging is performed only by the first charging circuit C1 as in the conventional configuration not including the second charging circuit C4, the charging time constant τ3 of the drain-source voltage Vds of the power semiconductor 41 is CR1, assuming that the gate capacitance of the power semiconductor 41 is C. On the other hand, in the second embodiment, charging is performed by the first charging circuit C1 and the second charging circuit C4 connected in parallel, so that the charging time constant τ4 of the drain-source voltage Vds of the power semiconductor 41 is C(R1 / / R4). Note that R1 / / R4 represents the combined resistance of the resistors R1 and R4 connected in parallel. Therefore, while the switching element M4 is on, the charging speed of the gate-source voltage Vds of the power semiconductor 41 is increased, and the drain-source voltage Vds increases more rapidly than in the conventional configuration.

[0067] As shown by the solid line in waveform (C), at time t1, when the gate-source voltage Vgs of the power semiconductor 41 exceeds the threshold voltage (Vth), as shown by the solid lines in waveforms (D) and (E), the drain-source voltage Vds of the upper arm power semiconductor 42 begins to increase and the drain-source current Ids of the power semiconductor 41 begins to increase.

[0068] As shown in waveform (B), at time t2, a control command to turn off switching element M4 is input from control circuit 30 to signal terminal 12. That is, the voltage of signal terminal 12 is switched from L level to H level. The timing at which the control command to turn off is input to signal terminal 12 may be later than time t2. After time t2, the charging time constant of gate-to-source voltage Vgs of power semiconductor 41 becomes CR1, which is the same as in the conventional configuration. Therefore, the drain-source surge voltage of power semiconductor 41 related to the charging time constant, which occurs after time t2, becomes the same as in the conventional configuration.

[0069] As shown by the solid line in the waveform (F), the switching loss of the power semiconductor 41 occurs between time t1 and time t4, and the loss period can be made shorter than in the case of the conventional configuration (dashed line) in which the on-gate resistance R1 is increased to suppress the drain-source voltage Vds of the power semiconductor 42 in the paired arm. That is, in the second embodiment as well, the amount of switching loss at turn-on can be reduced compared to the case of the conventional configuration.

[0070] After time t3, as shown in the waveform (B), a control command to turn on the switching element M4 may be input from the control circuit 30 to the signal terminal 12 to perform high-speed switching. As a result, when the switching element M4 is on, the gate-source voltage Vgs rises at a high speed as shown in the waveform (C), so that the turn-on operation is accelerated and the switching loss of the power semiconductor 41 is further reduced.

[0071] In the second embodiment, the configuration including the element current detector 61, the element voltage detector 62, and the element temperature detector 63 shown in FIG. 5 can also be applied.

[0072] (Third embodiment) FIG. 12 is a diagram showing a switching driver 1 according to a third embodiment. The gate driver 10 shown in FIG. 2 is a voltage-driven gate driver, but the gate driver 10B shown in FIG. 12 shows an example in which the voltage-driven type is changed to a constant-current-driven type. The switching elements M1, M2, and M3 are replaced with constant-current-driven switching elements. Note that, although FIG. 12 shows a system using an operational amplifier, the system does not have to use an operational amplifier. A control command is input from the control circuit 30 to the positive input terminal of each operational amplifier via signal terminals 11, 12, and 15 of the gate driver 10B.

[0073] Also, instead of using constant current drive type for all of the switching elements M1, M2, and M3, voltage drive type and constant current drive type may be used together. For example, if it is desired to use constant current drive type for turn-off and voltage drive type for turn-on, the switching elements M2 and M3 may be configured as shown in FIG. 12, and the switching element M1 may be configured as shown in FIG. 2. In the case of voltage drive type, the circuit configuration is simple, but the amount of current varies depending on the load. On the other hand, the constant current drive type is easy to control because the current is constant, but the circuit configuration is somewhat more complicated than that of the voltage drive type.

[0074] In addition, in FIG. 12, the voltage-driven switching elements M1, M2, and M3 in the configuration of FIG. 2 are replaced with constant-current-driven switching elements, but it is also possible to apply constant-current-driven switching elements to the configuration of FIG. 9.

[0075] According to the embodiment and modified examples of the present invention described above, the following advantageous effects are achieved.

[0076] (1) As shown in Figures 2 to 4, 9 to 12, etc., a switching drive device 1 that supplies a drive voltage or drive current to a gate terminal Gp of a power semiconductor 41 includes a first circuit (first charging circuit C1) having a turn-on resistor R1 and a first switching element M1 and charging the gate terminal Gp when the power semiconductor 41 is turned on, a second circuit (first discharging circuit C2) having a turn-off resistor R2 and a second switching element M2 and discharging the gate terminal Gp when the power semiconductor 41 is turned off, a third circuit (second discharging circuit C3 or second charging circuit C4) connected to the gate terminal Gp, having a gate resistor (charge-discharge gate resistor R3 or R4) and a third switching element M3 or M4, and discharging or charging the gate terminal Gp, and a control device (control circuit 30) that controls the on / off of the first to third switching elements M1 to M4.

[0077] Then, when the power semiconductor 41 is turned on, the control circuit 30 controls charging by the first circuit (first charging circuit C1) and charging or discharging by the third circuit (second discharging circuit C3 or second charging circuit C4) to execute the first turn-on operation mode from time t0 to t2 in FIG. 4 or FIG. 11, and then executes the second turn-on operation mode from time t2 to t3 in FIG. 4 or from time t2 to t3 in FIG. 11, which is slower than the first turn-on operation mode. By executing the first and second turn-on operation modes in this way, it is possible to shorten the period during which switching loss occurs in the power semiconductor 41 while suppressing the surge voltage at the time of turn-on. As a result, the amount of switching loss at the time of turn-on can be reduced.

[0078] Furthermore, when the power semiconductor 41 is turned off, the discharge by the second circuit (first discharge circuit C2) and the discharge or charge by the third circuit (second discharge circuit C3 or second charge circuit C4) are controlled to execute the first turn-off operation mode from time t0 to t2 in FIG. 3 or from time t0 to t21 in FIG. 10, and then execute the second turn-off operation mode from time t2 to t3 in FIG. 3 or from time t21 to t3 in FIG. 10, which is slower than the first turn-off operation mode. By executing the first and second turn-off operation modes in this manner, it is possible to shorten the period during which switching loss occurs in the power semiconductor 41 while suppressing the surge voltage at the time of turn-off. As a result, the amount of switching loss at the time of turn-off can be reduced.

[0079] As described above, the switching drive device 1 can suppress surges and reduce switching losses at turn-on and turn-off while minimizing cost increases by simply adding a third circuit (second discharge circuit C3 or second charging circuit C4) to the first circuit (first charging circuit C1) and the second circuit (first discharge circuit C2).

[0080] (2) In the above (1), as shown in Fig. 2 and 12, the third circuit is a second discharge circuit C3 provided in parallel with the first discharge circuit C2 (second circuit). In the first turn-on operation mode from time t0 to t2 in Fig. 4, charging is performed by the first charging circuit C1 (first circuit), and in the second turn-on operation mode from time t2 to t3, charging is performed by the first charging circuit C1 and discharging is performed by the second discharge circuit C3. In the first turn-off operation mode from time t0 to t2 in Fig. 3, discharging is performed by the first discharge circuit C2 and discharging is performed by the second discharge circuit C3, and in the second turn-off operation mode from time t2 to t3, discharging is performed by the first discharge circuit C2.

[0081] In the switching driver 1 of Figs. 2 and 12, in the second turn-on operation mode shown in Fig. 4, charging is performed by the first charging circuit C1 while discharging by the second discharging circuit C3 is performed to suppress surges due to slower charging, so that it is possible to set the on-gate resistance R1 smaller than in the past. As a result, the charging speed in the first turn-on operation mode can be made faster than in the past, and the amount of switching loss at turn-on can be reduced. Also, in the first turn-off operation mode shown in Fig. 3, discharging is performed by the first discharging circuit C2 and the second discharging circuit C3, so that the discharge time constant τ2 of the drain-source voltage Vds of the power semiconductor 41 becomes C(R2 / / R3), and the discharge speed of the gate-source voltage Vds of the power semiconductor 41 is increased. As a result, the period during which switching loss occurs is shorter than in the past, and the amount of switching loss at turn-off can be reduced.

[0082] (3) In the above (1), as shown in Fig. 9, the third circuit is a second charging circuit C4 provided in parallel with the first charging circuit C1 (first circuit). In the first turn-on operation mode from time t0 to t2 in Fig. 11, charging is performed by the first charging circuit C1 and by the second charging circuit C4, and in the second turn-on operation mode from time t2 to t3, charging is performed by the first charging circuit C1. In the first turn-off operation mode from time t0 to t21 in Fig. 10, discharging is performed by the first discharging circuit C2, and in the second turn-off operation mode from time t21 to t3, discharging is performed by the first discharging circuit C2 and charging is performed by the second charging circuit C4.

[0083] In the switching driver 1 of FIG. 9, in the first turn-on operation mode from time t0 to t2 in FIG. 11, charging is performed by the first charging circuit C1 and by the second charging circuit C4, so that the charging time constant τ4 of the drain-source voltage Vds of the power semiconductor 41 is C(R1 / / R4). Therefore, the discharge speed of the gate-source voltage Vds of the power semiconductor 41 is increased, the period during which switching loss occurs is shorter than in the past, and the amount of switching loss at the time of turn-on can be reduced. Also, in the second turn-off operation mode shown in FIG. 10, the discharge speed is slowed by turning on the switching element M4 while discharging is being performed by the first discharging circuit C2, so that the off-gate resistance R2 can be set smaller than in the past. As a result, the discharge speed in the first turn-off operation mode is increased, the period during which switching loss occurs is shorter than in the past, and the amount of switching loss at the time of turn-off can be reduced.

[0084] (4) In the above (1), as shown in Fig. 2, when the third circuit is the second discharge circuit C3 that discharges, after the second turn-on operation mode is executed, the first turn-on operation mode in which charging is performed by the first charging circuit C1 (first circuit) is executed again, as shown after time t3 in Fig. 4. Also, when the third circuit is the second charging circuit C4 that charges, as shown in Fig. 9, after the second turn-off operation mode in Fig. 10 is executed, the first turn-off operation mode in which discharging is performed by the first discharge circuit C2 (second circuit) is executed again, as shown after time t3 in Fig. 10. By performing such control, the switching operation of the power semiconductor 41 can be performed at a higher speed.

[0085] (5) In the above (1), as shown in Fig. 5 etc., detection units (element current detection unit 61, element voltage detection unit 62, element temperature detection unit 63) are further provided for detecting at least one of the voltage Vds, current Ids, and temperature Tj of the power semiconductor 41, and the control circuit 30 controls the on / off of the third switching element M3 based on the detection information (voltage Vds, current Ids, and temperature Tj) of the detection units. In this way, by controlling the on / off of the third switching element M3 according to the detected state of the power semiconductor 41, the switching operation of the power semiconductor 41 can be more appropriately controlled.

[0086] (6) For example, in (2) above, the discharge period (time duration Δton) by the third circuit (second discharge circuit C3) in the first turn-off operation mode from time t0 to t2 in FIG. 3 is set to be longer as the input voltage (drain-source voltage Vds) of the power semiconductor 41 or the drain-source current Ids flowing through the power semiconductor 41 becomes lower, as shown in FIGS. 6(a) and 6(b).

[0087] (7) For example, in the above (2), the discharge period (time duration Δton) by the third circuit (second discharge circuit C3) in the second turn-on operation mode from time t2 to t3 in FIG. 4 is set to be longer as the input voltage Vds of the power semiconductor 41, the drain-source current Ids flowing through the power semiconductor 41, or the device temperature Tj of the power semiconductor 41 becomes higher, as shown in FIG. 7.

[0088] The above-described embodiments and various modified examples are merely examples, and the present invention is not limited to these contents as long as the characteristics of the invention are not impaired. In addition, although various embodiments and modified examples have been described above, the present invention is not limited to these contents. Other aspects that are conceivable within the scope of the technical idea of ​​the present invention are also included in the scope of the present invention. [Explanation of symbols]

[0089] 1...switching driver, 10, 10A, 10B, 20...gate driver, 30...control circuit, 41, 42...power semiconductor, 51...negative wiring, 52...positive wiring, 53...output terminal, 61...element current detector, 62...element voltage detector, 63...element temperature detector, C1...first charging circuit, C2...first discharging circuit, C3...second discharging circuit, Di1, Di2...reverse current prevention diode, M1, M2, M3, M4, M5...switching element, R1...on gate resistor, R2...off gate resistor, R3, R4, R5...charge / discharge gate resistor, V1, V2...positive power supply, Δton...time width

Claims

1. A switching driver for supplying a driving voltage or a driving current to a gate terminal of a semiconductor element, a first circuit having a turn-on resistor and a first switching element, and charging the gate terminal when the semiconductor element is turned on; a second circuit having a turn-off resistor and a second switching element, and discharging the gate terminal when the semiconductor element is turned off; a third circuit connected to the gate terminal, the third circuit having a gate resistor and a third switching element, and discharging or charging the gate terminal; a control device that controls the first to third switching elements to be turned on and off, The control device includes: When the semiconductor device is turned on, the charging by the first circuit and the discharging or charging by the third circuit are controlled to execute a first turn-on operation mode, and then a second turn-on operation mode slower than the first turn-on operation mode is executed; A switching driver that, when the semiconductor element is turned off, controls discharging by the second circuit and discharging or charging by the third circuit to execute a first turn-off operation mode, and then executes a second turn-off operation mode that is slower than the first turn-off operation mode.

2. 2. The switching drive device according to claim 1, the third circuit is a discharge circuit provided in parallel with the second circuit, In the first turn-on operation mode, charging is performed by the first circuit; In the second turn-on operation mode, charging is performed by the first circuit and discharging is performed by the third circuit; In the first turn-off operation mode, discharging is performed by the second circuit and discharging by the third circuit; In the second turn-off operation mode, discharging is performed by the second circuit.

3. 2. The switching drive device according to claim 1, the third circuit is a charging circuit provided in parallel with the first circuit, In the first turn-on operation mode, charging is performed by the first circuit and charging by the third circuit; In the second turn-on operation mode, charging is performed by the first circuit; In the first turn-off operation mode, discharging is performed by the second circuit; In the second turn-off operation mode, discharging is performed by the second circuit and charging is performed by the third circuit.

4. 2. The switching drive device according to claim 1, When the third circuit is a circuit that performs discharging, after performing the second turn-on operation mode, the first turn-on operation mode is performed again; A switching driver that, when the third circuit is a circuit that performs charging, executes the first turn-off operation mode again after executing the second turn-off operation mode.

5. 2. The switching drive device according to claim 1, A detection unit that detects at least one of a voltage, a current, and a temperature of the semiconductor element, The control device controls the turning on / off of the third switching element based on the detection information of the detection unit.

6. 3. The switching drive device according to claim 2, A switching driver, wherein a discharge period by the third circuit in the first turn-off operation mode is set to be longer as an input voltage to the semiconductor element or a current flowing through the semiconductor element becomes lower.

7. 3. The switching drive device according to claim 2, A switching driver, wherein a discharge period by the third circuit in the second turn-on operation mode is set to be longer as an input voltage to the semiconductor element, a current flowing through the semiconductor element, or a device temperature of the semiconductor element increases.

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