Plasma processing apparatus

Abstract

To suppress a deviation of an etching rate.SOLUTION: A plasma processing apparatus includes a chamber, a bias power supply, a substrate support configured to support a substrate and an edge ring in the chamber, a plurality of first impedance adjusting mechanisms, and an electrical path. The substrate support includes a first region configured to support the substrate, a second region provided around the first region and configured to support the edge ring, a first bias electrode provided in the first region, a plurality of first impedance adjusting electrodes provided in the first region and grounded, and a second bias electrode provided in the second region. The plurality of first impedance adjusting mechanisms are configured to be respectively connected to the plurality of first impedance adjusting electrodes. The electrical path is configured to connect the bias power supply, the first bias electrode, and the second bias electrode.SELECTED DRAWING: Figure 9

Description

[Technical field]

[0001] The present disclosure relates to a plasma processing apparatus. [Background technology]

[0002] US Pat. No. 5,399,363 discloses that when the plasma sheath lowers adjacent to the edge ring due to erosion of the edge ring, the capacitance of a variable capacitor is adjusted to affect the RF amplitude near the edge of the substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2017-130659 A Summary of the Invention [Problem to be solved by the invention]

[0004] The present disclosure provides a plasma processing apparatus capable of suppressing bias in the etching rate. [Means for solving the problem]

[0005] A plasma processing apparatus according to an embodiment of the present disclosure includes a chamber, a bias power supply, a substrate support for supporting a substrate and an edge ring in the chamber, a plurality of first impedance adjustment mechanisms, and an electrical path, the substrate support is configured to have a first region for supporting a substrate, a second region for supporting the edge ring and provided around the first region, a first bias electrode provided in the first region, a plurality of first impedance adjustment electrodes provided in the first region and grounded, and a second bias electrode provided in the second region, each of the plurality of first impedance adjustment mechanisms is configured to be connected to each of the plurality of first impedance adjustment electrodes, and the electrical path is configured to connect the bias power supply, the first bias electrode, and the second bias electrode. Effect of the Invention

[0006] According to the present disclosure, it is possible to suppress bias in the etching rate. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing an example of a plasma processing apparatus according to a first embodiment of the present disclosure. [Diagram 2] FIG. 2 is a diagram showing an example of the configuration of the electrodes in the first embodiment. [Diagram 3] FIG. 3 is a diagram showing an example of an equivalent circuit of the electrostatic chuck and plasma in the first embodiment. [Figure 4] FIG. 4 is a diagram illustrating an example of a circuit configuration of the impedance adjustment mechanism in the first embodiment. [Diagram 5] FIG. 5 is a diagram showing an example of the bias in the etching rate. [Figure 6] FIG. 6 is a diagram showing an example of a change in etching rate when the impedance adjustment mechanism on the annular region side is changed. [Figure 7] FIG. 7 is a diagram showing an example of a change in etching rate when the impedance adjustment mechanism on the annular region side is changed. [Figure 8] FIG. 8 is a diagram showing an example of the rate of change of the etching rate when the impedance adjustment mechanism on the annular region side is changed. [Figure 9] FIG. 9 is a diagram showing an example of an impedance adjusting electrode in the first embodiment. [Figure 10] FIG. 10 is a diagram showing an example of experimental results of tilt control. [Figure 11] FIG. 11 is a diagram showing an example of an impedance adjusting electrode in the first modification. [Figure 12] FIG. 12 is a diagram illustrating an example of a configuration of an electrical path in the second embodiment. [Figure 13] FIG. 13 is a diagram showing an example of a change in etching rate when feedback control of the bias RF power is not performed. [Figure 14] FIG. 14 is a diagram showing an example of changes in etching rate and substrate potential when feedback control of bias RF power is not performed. [Figure 15] FIG. 15 is a diagram showing an example of a change in etching rate when feedback control of the bias RF power is not performed. [Figure 16] FIG. 16 is a diagram showing an example of changes in etching rate and substrate potential when feedback control of bias RF power is not performed. [Figure 17] FIG. 17 is a diagram showing an example of a change in etching rate when feedback control of bias RF power is performed. [Figure 18] FIG. 18 is a diagram showing an example of changes in the etching rate and the potential of the base when feedback control of the bias RF power is performed. [Figure 19] FIG. 19 is a diagram showing an example of a change in etching rate when feedback control of bias RF power is performed. [Figure 20] FIG. 20 is a diagram showing an example of changes in the etching rate and the potential of the base when feedback control of the bias RF power is performed. [Figure 21] FIG. 21 is a diagram showing an example of a change in current when feedback control of the bias DC power is not performed. [Figure 22] FIG. 22 is a diagram showing an example of a change in etching rate when feedback control of the bias DC power is not performed. [Diagram 23] FIG. 23 is a diagram showing an example of a change in etching rate when feedback control of bias DC power is performed. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the plasma processing apparatus will be described in detail with reference to the accompanying drawings. Note that the disclosed technology is not limited to the following preferred embodiments.

[0009] In a plasma processing apparatus, the thickness of the plasma sheath may vary depending on the potential difference between the substrate and the edge ring. As a result, the direction of the electric field may not be perpendicular to the substrate, and the trajectory of the ions may tilt, causing tilting of the etching hole. In addition, tilting is not only caused by the potential difference between the substrate and the edge ring, but also by global tilting, which is caused by the potential difference caused by the subtle difference in thickness of the electrodes and ceramic plate of the substrate support section, and in which the position dependency of the plasma sheath appears in the radial and circumferential directions over the entire substrate surface. In response to this, for example, it is possible to independently control the potential on the substrate side and the edge ring side. However, depending on the arrangement of the impedance adjustment mechanism provided to control the potential and the arrangement of the conductive section for drawing the impedance adjustment electrode to the outside of the substrate support section, the etching rate may be biased. In addition, when controlling the etching rate of the outer periphery of the substrate, the etching rate of the inner periphery of the substrate may also change at the same time. Therefore, it is expected that the etching rate controllability can be improved to suppress the etching rate bias.

[0010] (First embodiment) [Configuration of plasma processing device 1] An example of the configuration of a plasma processing system will be described below. FIG. 1 is a diagram showing an example of a plasma processing apparatus according to the first embodiment of the present disclosure. The plasma processing system includes an inductively coupled plasma processing apparatus 1 and a control unit 2. The inductively coupled plasma processing apparatus 1 includes a plasma processing chamber 10, a gas supply unit 20, a power supply 30, and an exhaust system 40. The plasma processing chamber 10 includes a dielectric window 101. The plasma processing apparatus 1 also includes a substrate support 11, a gas introduction unit, and an antenna 14. The substrate support 11 is disposed in the plasma processing chamber 10. The antenna 14 is disposed on or above the plasma processing chamber 10 (i.e., on or above the dielectric window 101). The plasma processing chamber 10 has a plasma processing space 10s defined by the dielectric window 101, a sidewall 102 of the plasma processing chamber 10, and the substrate support 11. The plasma processing chamber 10 has at least one gas supply port for supplying at least one processing gas to the plasma processing space 10s and at least one gas exhaust port for exhausting gas from the plasma processing space 10s. The plasma processing chamber 10 is grounded.

[0011] The substrate support 11 includes a main body 111 and a ring assembly 112. The main body 111 has a central region 111a for supporting the substrate W and an annular region 111b for supporting the ring assembly 112. A wafer is an example of a substrate W. The annular region 111b of the main body 111 surrounds the central region 111a of the main body 111 in a plan view. The substrate W is disposed on the central region 111a of the main body 111, and the ring assembly 112 is disposed on the annular region 111b of the main body 111 so as to surround the substrate W on the central region 111a of the main body 111. Therefore, the central region 111a is also called a substrate support surface for supporting the substrate W, and the annular region 111b is also called a ring support surface for supporting the ring assembly 112. The substrate support 11 is an example of a substrate support, the central region 111a is an example of a first region, and the annular region 111b is an example of a second region. In the following description, the central region 111a may be referred to as a substrate support surface 111a, and the annular region 111b may be referred to as a ring support surface 111b.

[0012] In one embodiment, the main body 111 includes a base 1110 and an electrostatic chuck 1111. The base 1110 includes a conductive member. The conductive member of the base 1110 can function as a part of an electrical path 35 connected to a first bias electrode 33 and a second bias electrode 34 described later. The electrostatic chuck 1111 is disposed on the base 1110. The electrostatic chuck 1111 includes a ceramic member 1111a and an electrostatic electrode (not shown) disposed in the ceramic member 1111a. The ceramic member 1111a has a central region 111a. In one embodiment, the ceramic member 1111a also has an annular region 111b. Note that another member surrounding the electrostatic chuck 1111, such as an annular electrostatic chuck or an annular insulating member, may have the annular region 111b. In this case, the ring assembly 112 may be disposed on the annular electrostatic chuck or the annular insulating member, or may be disposed on both the electrostatic chuck 1111 and the annular insulating member. Also, at least one RF / DC electrode coupled to a radio frequency (RF) power supply 31 and / or a direct current (DC) power supply 32 described later may be disposed in the ceramic member 1111a. In this case, at least one RF / DC electrode functions as a bias electrode. That is, a first bias electrode 33 and a second bias electrode 34 described later are electrically connected to the RF power supply 31 and / or the DC power supply 32 via an electrical path 35. Note that the conductive member of the base 1110 and at least one RF / DC electrode may function as multiple bias electrodes. Also, an electrostatic electrode (not shown) may function as a bias electrode, or the first bias electrode 33 may function as an electrostatic electrode. Thus, the substrate support 11 includes at least one bias electrode.

[0013] The ring assembly 112 includes one or more annular members. In one embodiment, the one or more annular members include one or more edge rings and at least one cover ring. The edge rings are formed of a conductive or insulating material, and the cover rings are formed of an insulating material.

[0014] The substrate support 11 may also include a temperature adjustment module configured to adjust at least one of the electrostatic chuck 1111, the ring assembly 112, and the substrate W to a target temperature. The temperature adjustment module may include a heater, a heat transfer medium, a flow passage 1110a, or a combination thereof. A heat transfer fluid such as a brine or a gas flows through the flow passage 1110a. In one embodiment, the flow passage 1110a is formed in the base 1110, and one or more heaters are disposed in the ceramic member 1111a of the electrostatic chuck 1111. The substrate support 11 may also include a heat transfer gas supply configured to supply a heat transfer gas to a gap between the back surface of the substrate W and the central region 111a.

[0015] The electrostatic chuck 1111 includes a first impedance adjustment electrode 50 and a first bias electrode 33 in the lower part of the substrate support surface 111a in this order from the substrate support surface 111a side, and is made of a dielectric material, for example, ceramics. The electrostatic chuck 1111 also includes a second impedance adjustment electrode 51 and a second bias electrode 34 in the lower part of the ring support surface 111b in this order from the ring support surface 111b side. The first bias electrode 33 and the second bias electrode 34 are connected to the base 1110 by a conductive member, and an electrical path 35 is formed. Note that the connection between the first bias electrode 33 and the second bias electrode 34 and the base 1110 is not limited to a conductive member, and may be any method capable of supplying a bias RF signal, such as magnetic resonance, capacitive coupling, and inductive coupling. That is, the electrical path 35 is configured to connect a bias power source (for example, a second RF generating unit 31b described later), the first bias electrode 33, and the second bias electrode 34. In addition, the electrical path 35 may be configured so that the second RF generating unit 31b described later is not connected to the base 1110, and the second RF generating unit 31b is directly connected to the first bias electrode 33 and the second bias electrode 34.

[0016] The first impedance adjustment electrode 50 is grounded via an impedance adjustment mechanism 52. The impedance adjustment mechanism 52 adjusts the amount of a part of the RF signal (electrical bias) supplied from the first bias electrode 33 to be fed to the ground (earth) side. The first impedance adjustment electrode 50 adjusts the amount of the RF signal fed to the ground side, thereby adjusting the potential of the substrate W, and is used to control the tilt angle and / or adjust the etching rate. The first impedance adjustment electrode 50 is provided in the electrostatic chuck 1111. Furthermore, the impedance adjustment mechanism 52 is connected to the first impedance adjustment electrode 50. When a plurality of first impedance adjustment electrodes 50 are provided, for example, two or more are provided in the circumferential direction of the substrate support part 11, and the impedance adjustment mechanisms 52 are also provided in a number corresponding to the number of the first impedance adjustment electrodes 50. Furthermore, two or more first impedance adjustment electrodes 50 may be provided in the radial direction of the substrate support part 11. Furthermore, two or more first impedance adjustment electrodes 50 may be provided in each of the circumferential direction and the radial direction of the substrate support part 11. The first impedance adjusting electrode 50 is disposed so as to be parallel to the first bias electrode 33 .

[0017] The second impedance adjustment electrode 51 is grounded via an impedance adjustment mechanism 53. The impedance adjustment mechanism 53 adjusts the amount of a part of the RF signal (electrical bias) supplied from the second bias electrode 34 to be fed to the ground (earth) side. The second impedance adjustment electrode 51 adjusts the amount of the RF signal fed to the ground side, thereby adjusting the potential of the ring assembly 112, and is used to control the tilt angle and / or adjust the etching rate. The second impedance adjustment electrode 51 is provided in the electrostatic chuck 1111. When a plurality of second impedance adjustment electrodes 51 are provided, for example, two or more are provided in the circumferential direction of the substrate support 11, and the impedance adjustment mechanisms 53 are also provided in a number corresponding to the number of the second impedance adjustment electrodes 51. In addition, two or more second impedance adjustment electrodes 51 may be provided in the radial direction of the substrate support 11. Furthermore, two or more second impedance adjustment electrodes 51 may be provided in each of the circumferential direction and the radial direction of the substrate support 11. The second impedance adjusting electrode 51 is disposed so as to be parallel to the second bias electrode .

[0018] The first bias electrode 33 and the second bias electrode 34 are located as close as possible to the substrate W and the ring assembly 112, thereby reducing the impedance of a capacitor formed by the substrate W, the ring assembly 112, the ceramics of the electrostatic chuck 1111, and the electrodes. This reduces the potential difference between the first bias electrode 33 and the second bias electrode 34 and the substrate W and the ring assembly 112. Similarly, the impedance of a capacitor formed by the first bias electrode 33 and the second bias electrode 34 and the first impedance adjustment electrode 50 and the second impedance adjustment electrode 51, respectively, is also reduced. Furthermore, the impedance of a capacitor formed by the first impedance adjustment electrode 50 and the second impedance adjustment electrode 51 and the substrate W and the ring assembly 112, respectively, is also reduced.

[0019] At least one of the impedance adjustment mechanisms 52, 53 may be provided, or both may be provided. When one of the impedance adjustment mechanisms 52, 53 is not provided, the first impedance adjustment electrode 50 or the second impedance adjustment electrode 51 on the side where the impedance adjustment mechanism is not provided is connected to earth (ground) via a predetermined impedance value, or is not connected to earth and is in a floating state. When one of the impedance adjustment mechanisms 52, 53 is not provided, the first impedance adjustment electrode 50 or the second impedance adjustment electrode 51 on the side where the impedance adjustment mechanism is not provided may not be provided.

[0020] The gas introduction unit is configured to introduce at least one processing gas from the gas supply unit 20 into the plasma processing space 10s. In one embodiment, the gas introduction unit includes a center gas injector (CGI) 13. The center gas injector 13 is disposed above the substrate support 11 and attached to a central opening formed in the dielectric window 101. The center gas injector 13 has at least one gas supply port 13a, at least one gas flow path 13b, and at least one gas inlet port 13c. The processing gas supplied to the gas supply port 13a passes through the gas flow path 13b and is introduced into the plasma processing space 10s from the gas inlet port 13c. Note that the gas introduction unit may include one or more side gas injectors (SGI) attached to one or more openings formed in the sidewall 102 in addition to or instead of the center gas injector 13.

[0021] The gas supply 20 may include at least one gas source 21 and at least one flow controller 22. In one embodiment, the gas supply 20 is configured to supply at least one process gas from a respective gas source 21 to the gas inlet via a respective flow controller 22. Each flow controller 22 may include, for example, a mass flow controller or a pressure-controlled flow controller. Additionally, the gas supply 20 may include one or more flow modulation devices to modulate or pulse a flow rate of the at least one process gas.

[0022] The power source 30 includes an RF power source 31 coupled to the plasma processing chamber 10 via at least one impedance matching circuit. The RF power source 31 is configured to supply at least one RF signal (RF power) to at least one of the first bias electrode 33, the second bias electrode 34, and the antenna 14. This causes a plasma to be formed from at least one processing gas supplied to the plasma processing space 10s. Thus, the RF power source 31 can function as at least a part of a plasma generating unit configured to generate a plasma from one or more processing gases in the plasma processing chamber 10. In addition, by supplying a bias RF signal to at least one of the first bias electrode 33 and the second bias electrode 34, a bias potential is generated on the substrate W, and ions in the formed plasma can be attracted to the substrate W.

[0023] In one embodiment, the RF power supply 31 includes a first RF generating unit 31a and a second RF generating unit 31b. The first RF generating unit 31a is coupled to the antenna 14 and configured to generate a source RF signal (source RF power) for plasma generation via at least one impedance matching circuit. In one embodiment, the source RF signal has a frequency in the range of 10 MHz to 150 MHz. In one embodiment, the first RF generating unit 31a may be configured to generate a plurality of source RF signals having different frequencies. The generated one or more source RF signals are supplied to the antenna 14.

[0024] The second RF generating unit 31b is coupled to at least one of the first bias electrode 33 and the second bias electrode 34 via at least one impedance matching circuit, and is configured to generate a bias RF signal (bias RF power). The frequency of the bias RF signal may be the same as or different from the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency lower than the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency in the range of 100 kHz to 60 MHz. In one embodiment, the second RF generating unit 31b may be configured to generate a plurality of bias RF signals having different frequencies. The generated one or more bias RF signals are supplied to at least one of the first bias electrode 33 and the second bias electrode 34. In various embodiments, at least one of the source RF signal and the bias RF signal may be pulsed.

[0025] The power supply 30 may also include a DC power supply 32 coupled to the plasma processing chamber 10. The DC power supply 32 includes a bias DC generator 32a. In one embodiment, the bias DC generator 32a is connected to at least one of a first bias electrode 33 and a second bias electrode 34 and configured to generate a bias DC signal. The generated bias DC signal is applied to the at least one of the first bias electrode 33 and the second bias electrode 34.

[0026] In various embodiments, the bias DC signal may be pulsed. In this case, a sequence of voltage pulses is applied to at least one of the first bias electrode 33 and the second bias electrode 34. The voltage pulses may have a rectangular, trapezoidal, triangular or combination of these pulse waveforms. In one embodiment, a waveform generator for generating a sequence of voltage pulses from the DC signal is connected between the bias DC generator 32a and the at least one bias electrode. Thus, the bias DC generator 32a and the waveform generator constitute a voltage pulse generator. The voltage pulses may have a positive polarity or a negative polarity. The sequence of voltage pulses may include one or more positive voltage pulses and one or more negative voltage pulses in one period. The bias DC generator 32a may be provided in addition to the RF power supply 31 or may be provided instead of the second RF generator 31b.

[0027] The antenna 14 includes one or more coils. In one embodiment, the antenna 14 may include an outer coil and an inner coil arranged coaxially. In this case, the RF power source 31 may be connected to both the outer coil and the inner coil, or to either the outer coil or the inner coil. In the former case, the same RF generator may be connected to both the outer coil and the inner coil, or separate RF generators may be connected to the outer coil and the inner coil separately.

[0028] The exhaust system 40 may be connected to, for example, a gas exhaust port 10e provided at the bottom of the plasma processing chamber 10. The exhaust system 40 may include a pressure regulating valve and a vacuum pump. The pressure in the plasma processing space 10s is adjusted by the pressure regulating valve. The vacuum pump may include a turbomolecular pump, a dry pump, or a combination thereof.

[0029] The control unit 2 processes computer-executable instructions that cause the plasma processing apparatus 1 to execute various steps described in the present disclosure. The control unit 2 may be configured to control each element of the plasma processing apparatus 1 to execute various steps described herein. In one embodiment, a part or all of the control unit 2 may be included in the plasma processing apparatus 1. The control unit 2 may include a processing unit 2a1, a storage unit 2a2, and a communication interface 2a3. The control unit 2 is realized, for example, by a computer 2a. The processing unit 2a1 may be configured to perform various control operations by reading a program from the storage unit 2a2 and executing the read program. This program may be stored in the storage unit 2a2 in advance, or may be acquired via a medium when necessary. The acquired program is stored in the storage unit 2a2 and is read from the storage unit 2a2 by the processing unit 2a1 and executed. The medium may be various storage media readable by the computer 2a, or may be a communication line connected to the communication interface 2a3. The processing unit 2a1 may be a CPU (Central Processing Unit). The storage unit 2a2 may include a random access memory (RAM), a read only memory (ROM), a hard disk drive (HDD), a solid state drive (SSD), or a combination thereof. The communication interface 2a3 may communicate with the plasma processing apparatus 1 via a communication line such as a local area network (LAN).

[0030] [Electric potential on substrate support 11] Next, the potential on the substrate support part 11 will be described with reference to Fig. 2. Fig. 2 is a diagram showing an example of the configuration of the electrodes in the first embodiment. In Fig. 2, a bias RF signal is supplied to the first bias electrode 33 and the second bias electrode 34 from the second RF generating part 31b via the base 1110 and an electrical path 35 made of a conductive member.

[0031] As shown in FIG. 2, on the substrate support surface 111a, a bias RF signal supplied from the first bias electrode 33 disposed below the substrate support surface 111a is divided into an RF signal 60 and an RF signal 62. The RF signal 60 is an RF signal supplied to the plasma via the first impedance adjustment electrode 50 and the substrate W. The RF signal 62 is an RF signal flowing from the first impedance adjustment electrode 50 to the ground (earth) via the impedance adjustment mechanism 52. On the other hand, on the ring support surface 111b, a bias RF signal supplied from the second bias electrode 34 disposed below the substrate support surface 111a is divided into an RF signal 61 and an RF signal 63. The RF signal 61 is an RF signal supplied to the plasma via the second impedance adjustment electrode 51 and the ring assembly 112. The RF signal 63 is an RF signal flowing from the second impedance adjustment electrode 51 to the ground (earth) via the impedance adjustment mechanism 53.

[0032] At this time, the potential 64, which is a line that represents a predetermined potential above the substrate W, and the potential 65, which is a line that represents a predetermined potential above the ring assembly 112, are assumed to have different heights, for example, as shown in FIG. 2. In this case, for example, by adjusting the impedance adjustment mechanism 53, the height of the potential 65 is adjusted within a range 66. As a result, in the first embodiment, the tilt angle corresponding to the direction of the electric field 67 can be controlled by the ratio between the potential 64 and the potential 65. Also, for example, by adjusting the impedance adjustment mechanism 52 and the impedance adjustment mechanism 53, the etching rate of the outer periphery of the substrate W is controlled, and the etching rate of the inner periphery of the substrate W is also controlled. When the impedance adjustment mechanism 52 is adjusted, the height of the potential 64 is adjusted within a range 68. As a result, in the first embodiment, when controlling the etching rate of the outer periphery of the substrate W, it is possible to suppress the etching rate of the inner periphery of the substrate W from changing at the same time. Note that in FIG. 2, the angle of the direction of the electric field 67 is exaggerated for the sake of explanation. Furthermore, in the first embodiment, since the first impedance adjustment electrode 50 and the second impedance adjustment electrode 51 are embedded in the electrostatic chuck 1111, the structure of the plasma processing apparatus 1 can be made compact.

[0033] Next, an equivalent circuit of a circuit through which a bias RF signal flows will be described with reference to Fig. 3. Fig. 3 is a diagram showing an example of an equivalent circuit of an electrostatic chuck and plasma in the first embodiment. In Fig. 3, a bias RF signal supplied to the first bias electrode 33 and the second bias electrode 34 is V RF The impedance between the first bias electrode 33 and the second bias electrode 34 and the first impedance adjustment electrode 50 and the second impedance adjustment electrode 51 is expressed as Z 1 The impedance between the first impedance adjustment electrode 50 and the second impedance adjustment electrode 51 and the substrate W and the ring assembly 112 is expressed as Z 2 The impedance of the impedance adjustment mechanisms 52 and 53 between the first impedance adjustment electrode 50 and the second impedance adjustment electrode 51 and the ground (earth) is expressed as Z 3 In addition, the impedance of the plasma between the substrate W and the ring assembly 112 and the ground is expressed as Z 4 It is expressed as follows.

[0034] Here, Z 3 The voltage V applied to 3 And Z 4 The voltage V applied to wafer can be expressed by the following formulas (1) and (2), respectively. In formulas (1) to (4), V RF is represented as V.

[0035]

number

number

[0036] Substituting equation (1) into equation (2), Z 4 The voltage V applied to wafer can be expressed by the following formula (3). Also, let us consider the fractional terms of formula (3) as Z 4 , Z 3 Dividing by this gives us the following equation (4).

[0037]

number

number

[0038] The fractional terms in equation (4) are in the form of f(x)=1 / (x+1), where f(x) is a function that approaches 1 as x becomes smaller. Therefore, from equation (4), Z 2 Z 4 The smaller the potential is, the more efficient the electric potential transfer to the plasma will be. 1 Z 3 The smaller Z is, the more efficient the electric potential is in the plasma. 2 In order to reduce Z, it is preferable to place the first impedance adjustment electrode 50 and the second impedance adjustment electrode 51 as close as possible to the substrate W and the ring assembly 112. 1 In order to reduce this, it is preferable to place the first bias electrode 33 and the second bias electrode 34 as close as possible to the first impedance adjustment electrode 50 and the second impedance adjustment electrode 51. In this way, by placing the first bias electrode 33 and the second bias electrode 34, the first impedance adjustment electrode 50 and the second impedance adjustment electrode 51, and the substrate W and the ring assembly 112 as close as possible, the sensitivity of potential control can be increased.

[0039] [Potential control based on equivalent circuit] From the equivalent circuit shown in FIG. 3, the potential control in the plasma processing apparatus 1 is performed by Z between the first bias electrode 33 and the first impedance adjustment electrode 50. 1 Therefore, Z between the first impedance adjusting electrode 50 and ground 3 The impedance adjustment mechanism 52 is adjusted so that Z 3 That is, the control unit 2 of the plasma processing apparatus 1 controls Z 3 By controlling this, the potential of the first impedance adjusting electrode 50 is controlled.

[0040] In addition, the potential control in the plasma processing apparatus 1 is performed by adjusting the Z between the second bias electrode 34 and the second impedance adjustment electrode 51. 1 Therefore, Z between the second impedance adjusting electrode 51 and ground 3 The impedance adjustment mechanism 53 is adjusted so that Z 3 In other words, the control unit 2 of the plasma processing apparatus 1 controls the Z 3 By controlling this, the potential of the second impedance adjusting electrode 51 is controlled.

[0041] [Circuit configuration of impedance adjustment mechanism] Next, variations of the circuit configuration in the impedance adjustment mechanisms 52 and 53 will be described with reference to FIG. 4. FIG. 4 is a diagram showing an example of the circuit configuration of the impedance adjustment mechanism in the first embodiment. As shown in FIG. 4, the impedance adjustment mechanisms 52 and 53 can have various configurations such as circuits 70 to 74. The circuit 70 is an LC series circuit using an inductor and a variable capacitor. The circuit 71 is an RC series circuit using a resistor and a variable capacitor. The circuit 72 is an RR series circuit using a resistor and a variable resistor. The circuit 73 is a circuit that can be switched between an LC series circuit for high frequency and an RR series circuit for low frequency by a switch SW. The circuit 74 is a circuit that can be switched between an LC series circuit for high efficiency and an LC series circuit for low efficiency by a switch SW. As shown in a graph 75, the circuit 74 has a wide adjustment range by switching the switch SW. Although not illustrated in FIG. 4, the impedance adjustment mechanisms 52 and 53 may have a circuit configuration using a variable inductor.

[0042] In this way, the impedance adjustment mechanisms 52 and 53 can use variable resistors, variable capacitors, variable inductors, etc., regardless of the type of circuit constants to be adjusted (R, L, C). Furthermore, the impedance adjustment mechanisms 52 and 53 may combine one or more variable mechanisms (variable resistors, variable capacitors, variable inductors, etc.) in accordance with the frequency, part size, and adjustment range of the bias RF signal. Note that since the impedance adjustment mechanisms 52 and 53 do not need to pass a heater current, variable resistors and variable capacitors can be used. Furthermore, the impedance adjustment mechanisms 52 and 53 may be configured with at least one of a variable resistor, a variable capacitor, a variable inductor, and a DC power supply. For example, when the bias RF signal is high frequency, the above-mentioned Z 1 and Z 2 Since the value of θ becomes small, the potential can be controlled more effectively by controlling the potential using a DC power supply.

[0043] [Etching rate bias] Next, the bias and change of the etching rate will be described with reference to Figs. 5 to 8. Fig. 5 is a diagram showing an example of the bias of the etching rate. Fig. 5 shows the bias of the etching rate of the substrate W in the electrostatic chuck 1111 in a plan view when the impedance adjustment mechanisms 52 and 53 are not adjusted. In Fig. 5, the difference in the etching rate is shown by the difference in hatching. As shown in Fig. 5, the pull-in electrode 34a connected to the second bias electrode 34, the impedance adjustment mechanism 53, and the arc-shaped conductive bar 54 connected to the impedance adjustment mechanism 53 are arranged under the substrate support surface 111a. The pull-in electrode 34a constitutes a part of the electrical path 35 and is connected to the second RF generating unit 31b. The conductive bar 54 is arranged from the connection part with the impedance adjustment mechanism 53 along the inner periphery side of the ring assembly 112, and is connected to the second impedance adjustment electrode 51 in the vicinity of the pull-in electrode 34a. The other end of the impedance adjustment mechanism 53 is electrically connected to the outside of the electrostatic chuck 1111 and is grounded. As shown in Fig. 5, the etching rate of the substrate W is biased in the 9 o'clock to 12 o'clock direction in a plan view where the impedance adjustment mechanism 53 and the conductive bar 54 are located.

[0044] 6 and 7 are diagrams showing an example of the change in etching rate when the impedance adjustment mechanism on the annular region side is changed. A graph 80 shown in FIG. 6 shows the etching rate in the radial direction when CF4 / Ar gas is used as the processing gas for the etching process and the variable capacitor of the impedance adjustment mechanism 53 has a value of 100 pF, 200 pF, and 300 pF. A graph 81 shown in FIG. 7 shows the etching rate in the radial direction when Ar / N2 / C4F8 gas is used as the processing gas for the etching process and the variable capacitor of the impedance adjustment mechanism 53 has a value of 100 pF, 200 pF, and 300 pF. In addition, in the graphs 80 and 81, the etching rate is normalized within a predetermined range. In the following description, the variable capacitor may be referred to as a variable capacitor (VC).

[0045] As shown in graphs 80 and 81, when the value of the variable capacitor of the impedance adjustment mechanism 53 is changed from 100 pF to 200 pF and 300 pF, the etching rate changes not only on the outer periphery (edge ​​side) of the substrate W but also on the center side. In other words, changing the value of the variable capacitor of the impedance adjustment mechanism 53 results in an overall shift in the etching rate.

[0046] FIG. 8 is a diagram showing an example of the rate of change of the etching rate when the impedance adjustment mechanism on the annular region side is changed. Table 82 shown in FIG. 8 summarizes the rate of change of the etching rate with respect to the VC value of the impedance adjustment mechanism 53 (shown as the VC value on the edge ring side in FIG. 8). In Table 82, the etching rate near the center of the substrate W when the VC value is 100 pF is taken as the reference (rate of change 0%). When plasma is generated using Ar gas as the processing gas, the rate of change of the potential of the substrate W is -0.2% when the VC value is 200 pF and -8.0% when the VC value is 300 pF. When CF4 / Ar gas is used as the processing gas, the rate of change of the etching rate is -0.8% when the VC value is 200 pF and -5.0% when the VC value is 300 pF. The change rate of the etching rate when Ar / N2 / C4F8 gas is used as the processing gas is -7.8% when the value of VC is 200 pF, and -24.9% when the value of VC is 300 pF. If the allowable value of the change rate of the potential of the substrate W and the etching rate is, for example, ±3%, when the value of VC is 200 pF and Ar / N2 / C4F8 gas is used as the processing gas, the change rate of the etching rate exceeds the allowable value. Furthermore, when the value of VC is 300 pF, the change rate of the potential of the substrate W, the change rate of the etching rate when CF4 / Ar gas is used, and the change rate of the etching rate when Ar / N2 / C4F8 gas is used exceed the allowable value. Therefore, in the first embodiment, for example, the second impedance adjustment electrode 51 is divided into a plurality of portions in the circumferential direction of the substrate support portion 11, and the impedance adjustment mechanism 53 is connected to each of the plurality of second impedance adjustment electrodes 51.

[0047] [Placement of impedance adjustment electrodes] Next, the arrangement of the second impedance adjustment electrode 51 will be described with reference to FIG. 9. FIG. 9 is a diagram showing an example of the impedance adjustment electrode in the first embodiment. As shown in FIG. 9, the electrostatic chuck 1111 has a plurality of second impedance adjustment electrodes 51a to 51d arranged as the second impedance adjustment electrode 51 below the ring support surface (annular region) 111b. The second impedance adjustment electrodes 51a to 51d are connected to impedance adjustment mechanisms 53, respectively. That is, the electrostatic chuck 1111 can adjust the impedance of each of the second impedance adjustment electrodes 51a to 51d. Although not shown in FIG. 9, the first impedance adjustment electrode 50 is arranged below the substrate support surface 111a, and the impedance adjustment mechanism 52 is connected thereto.

[0048] For example, when the etching rate is biased as shown in Fig. 5, the impedance adjustment mechanism 53 connected to the second impedance adjustment electrode 51d is individually adjusted. This makes it possible to suppress the bias in the etching rate with respect to the region where the second impedance adjustment electrodes 51a to 51c are arranged. Furthermore, the electrostatic chuck 1111 is capable of adjusting the impedance adjustment mechanism 52 and the impedance adjustment mechanisms 53 connected to the second impedance adjustment electrodes 51a to 51d. This makes it possible to suppress the change (shift) in the etching rate over the entire substrate W as shown in graphs 80 and 81 and table 82.

[0049] [Experimental Results] Next, the experimental results of the tilt control will be described with reference to FIG. 10. FIG. 10 is a diagram showing an example of the experimental results of the tilt control. A graph 83 shown in FIG. 10 is a graph obtained by measuring the bottom offset in the OCD (Optical Critical Dimension) of a hole formed in a range of a radius of 120 mm to 150 mm in the radial direction of the substrate W. The example of the graph 83 shows the bottom offset when the VC value of the impedance adjustment mechanism 53 is set to 200 pF, 1000 pF, and 2000 pF. As shown in the graph 83, by changing the VC value of the impedance adjustment mechanism 53, the bottom offset is shifted to the negative side on the outer periphery side of the substrate W (range of a radius of 130 mm to 150 mm). That is, it can be seen that by adjusting the impedance of the impedance adjustment mechanism 53, the potential on the ring assembly 112 side can be changed to perform tilt control of the substrate W. In addition, as shown in FIG. 9, the impedance adjustment mechanism 53 is connected to each of the second impedance adjustment electrodes 51a to 51d, so that the bias of the etching rate can be corrected in addition to the tilt control.

[0050] [Variation 1] Next, Modification 1 will be described with reference to Fig. 11. Fig. 11 is a diagram showing an example of an impedance adjusting electrode in Modification 1. The plasma processing apparatus 1 in Modification 1 has an electrostatic chuck 1111b shown in Fig. 11 instead of the electrostatic chuck 1111. Note that the plasma processing apparatus 1 in Modification 1 is similar to the above-described first embodiment except for the configuration of the electrostatic chuck 1111b, and therefore a description of the overlapping configurations and operations will be omitted.

[0051] 11, in the electrostatic chuck 1111b, similarly to the electrostatic chuck 1111, a plurality of second impedance adjustment electrodes 51a to 51d are arranged as the second impedance adjustment electrodes 51 below the ring support surface (annular region) 111b. An impedance adjustment mechanism 53 is connected to each of the second impedance adjustment electrodes 51a to 51d. In addition, in the electrostatic chuck 1111b, a plurality of first impedance adjustment electrodes 50a to 50c are arranged as the first impedance adjustment electrodes 50 below the substrate support surface 111c. The first impedance adjustment electrodes 50a to 50c are an example of the first impedance adjustment electrodes 50 divided in the radial direction of the electrostatic chuck 1111b.

[0052] The first impedance adjustment electrodes 50a to 50c are further divided in the circumferential direction of the electrostatic chuck 1111b. In the 12 o'clock to 3 o'clock direction of the electrostatic chuck 1111b in plan view, the first impedance adjustment electrodes 50a1, 50b1, and 50c1 are arranged in order from the inside. In the 3 o'clock to 6 o'clock direction of the electrostatic chuck 1111b in plan view, the first impedance adjustment electrodes 50a2, 50b2, and 50c2 are arranged in order from the inside. In the 6 o'clock to 9 o'clock direction of the electrostatic chuck 1111b in plan view, the first impedance adjustment electrodes 50a3, 50b3, and 50c3 are arranged in order from the inside. In the 9 o'clock to 12 o'clock direction of the electrostatic chuck 1111b in plan view, the first impedance adjustment electrodes 50a4, 50b4, and 50c4 are arranged in order from the inside. The impedance adjusting mechanisms 52 are connected to the first impedance adjusting electrodes 50a1 to 50a4, 50b1 to 50b4, and 50c1 to 50c4, respectively.

[0053] In the electrostatic chuck 1111b, when the etching rate is biased, the impedance adjustment mechanisms 53 connected to the second impedance adjustment electrodes 51a to 51d are individually adjusted. In addition, in the electrostatic chuck 1111b, the impedance adjustment mechanisms 52 connected to the first impedance adjustment electrodes 50a1 to 50a4, 50b1 to 50b4, and 50c1 to 50c4 are individually adjusted. This makes it possible to control the potential for each of the regions corresponding to the first impedance adjustment electrodes 50a1 to 50a4, 50b1 to 50b4, and 50c1 to 50c4 and the second impedance adjustment electrodes 51a to 51d. That is, in the first modification, the change in the etching rate can be suppressed over the entire substrate W.

[0054] In the above embodiment, the bias RF signal is supplied from the second RF generating unit 31b as the electric bias, but the present invention is not limited to this. For example, the bias DC signal may be supplied from the bias DC generating unit 32a as the electric bias. In this case, for example, the electrical path 35 includes a first electrical path that connects the second RF generating unit 31b, which is the first bias power supply, to at least one of the first bias electrode 33 and the second bias electrode 34. Also, for example, the electrical path 35 includes a second electrical path that connects the bias DC generating unit 32a, which is the second bias power supply, to at least one of the first bias electrode 33 and the second bias electrode 34. This allows any bias RF signal and bias DC signal to be supplied to the first bias electrode 33 and the second bias electrode 34.

[0055] Second embodiment In the above-described first embodiment, the impedance adjustment mechanisms 52 and 53 are adjusted to suppress the change in the etching rate, but the power of the electric bias output from the second RF generating unit 31b and / or the bias DC generating unit 32a may be controlled. An embodiment in this case will be described as a second embodiment. In the second embodiment, the same components as those in the plasma processing apparatus 1 of the first embodiment are denoted by the same reference numerals, and the description of the overlapping components and operations will be omitted.

[0056] Fig. 12 is a diagram showing an example of the configuration of an electrical path in the second embodiment. As shown in Fig. 12, in the plasma processing apparatus 1 of the second embodiment, a measuring unit 36 ​​is provided in an electrical path 35 between the second RF generating unit 31b and a base 1110. In addition, in the plasma processing apparatus 1 of the second embodiment, a high-voltage probe 37 may be provided between the base 1110 and ground (earth, ground).

[0057] The measurement unit 36 ​​is, for example, a VI probe, and is controlled to measure the voltage and current of the bias RF signal and / or bias DC signal output from the second RF generation unit 31b and / or the bias DC generation unit 32a. That is, the measurement unit 36 ​​is controlled to measure the power of the bias RF signal and / or the bias DC signal. The measurement unit 36 ​​outputs the measured voltage and current to the control unit 2. That is, the measurement unit 36 ​​is configured to measure the voltage and current of the bias RF signal and / or the bias DC signal output from the bias power supply.

[0058] The high voltage probe 37 is controlled to measure the potential (Vpp) of the base 1110. Note that, for example, by measuring in advance the relationship between the voltage of the bias RF signal measured by the measurement unit 36 ​​and the potential (Vpp) of the base 1110 measured by the high voltage probe 37, the high voltage probe 37 may be removed during process execution. In this case, the control unit 2 can estimate the potential (Vpp) of the base 1110 based on the relationship between the voltage of the bias RF signal measured in advance by the measurement unit 36 ​​and the potential (Vpp) of the base 1110 measured in advance.

[0059] [Bias RF power control] In the second embodiment, the control unit 2 controls the second RF generating unit 31b based on the voltage and current input from the measuring unit 36 ​​when at least one impedance adjustment mechanism 53 is adjusted. That is, the second RF generating unit 31b controls (feedback controls) the power of the bias RF signal based on the voltage and current measured by the measuring unit 36 ​​so that the potentials of the first bias electrode 33 and the second bias electrode 34 become preset set values. Here, the preset set value is, for example, a value when the potential (Vpp) of the base 1110 measured by the high voltage probe 37 becomes a desired potential. Note that, in the second embodiment, the potentials of the first bias electrode 33 and the second bias electrode 34 are described as being substantially equal to the potential (Vpp) of the base 1110 and the potential (Vdc) of the substrate W and the ring assembly 112.

[0060] FIG. 13 is a diagram showing an example of the change in etching rate when feedback control of bias RF power is not performed. FIG. 14 is a diagram showing an example of the change in etching rate and substrate potential when feedback control of bias RF power is not performed. Graph 84 in FIG. 13 shows the radial etching rate when Ar / N2 / C4F8 gas is used as the processing gas for the etching process and the variable capacitor (VC) value of the impedance adjustment mechanism 53 is set to 10 pF, 200 pF, and 475 pF. In addition, in graph 84 and table 85 in FIG. 14, the frequency of the bias RF signal is set to 400 kHz and the power is set to 100 W. In addition, in graph 84, the etching rate is normalized within a predetermined range.

[0061] In graph 84 and table 85, a case where the value of the variable capacitor (VC) of the impedance adjustment mechanism 53 is 10 pF is taken as a reference (rate of change 0%). As shown in graph 84 and table 85, when feedback control of the bias RF power is not performed, the rate of change of the etching rate is 1.2% when the VC value is 200 pF and 2.4% when it is 475 pF in a radius range of 0 mm to 135 mm. Also, the rate of change of the potential (Vdc) of the substrate W is 3.8% when the VC value is 200 pF and 9.1% at 475 pF in a radius range of 0 mm to 135 mm.

[0062] FIG. 15 is a diagram showing an example of the change in etching rate when feedback control of bias RF power is not performed. FIG. 16 is a diagram showing an example of the change in etching rate and substrate potential when feedback control of bias RF power is not performed. Graph 86 in FIG. 15 shows the radial etching rate when Ar / N2 / C4F8 gas is used as the processing gas for the etching process and the value of the variable capacitor (VC) of the impedance adjustment mechanism 53 is set to 10 pF, 100 pF, 200 pF, and 475 pF. In addition, in graph 86 and table 87 in FIG. 16, the frequency of the bias RF signal is set to 13 MHz and the power is set to 300 W. In addition, in graph 86, the etching rate is normalized within a predetermined range.

[0063] In graph 86 and table 87, the case where the value of the variable capacitor (VC) of the impedance adjustment mechanism 53 is 10 pF is taken as the reference (change rate 0%). As shown in graph 86 and table 87, when feedback control of the bias RF power is not performed, the change rate of the etching rate is 15.2% when the VC value is 100 pF, 38.0% when it is 200 pF, and 38.9% when it is 475 pF in the radius range of 0 mm to 135 mm. Also, the change rate of the potential (Vdc) of the substrate W is 11.2% when the VC value is 100 pF, 17.7% when it is 200 pF, and 48.0% when it is 475 pF in the radius range of 0 mm to 135 mm. When the frequency of the bias RF signal is 13 MHz, the change rates of both the etching rate and the potential (Vdc) of the substrate W are larger than when it is 400 kHz. If the allowable value of the rate of change in the etching rate is, for example, ±3%, when the frequency of the bias RF signal is 13 MHz and the value of VC is 100 pF, 200 pF, and 475 pF, the rate of change in the etching rate exceeds the allowable value.

[0064] 17 to 20, a case where feedback control of the bias RF power is performed based on the potential of the first bias electrode 33 and the second bias electrode 34 (the potential (Vpp) of the base 1110) will be described. That is, in this case, the control unit 2 controls the second RF generating unit 31b to control the power of the bias RF signal based on the voltage and current input from the measuring unit 36 ​​so that the potential of the first bias electrode 33 and the second bias electrode 34 becomes a preset value.

[0065] FIG. 17 is a diagram showing an example of the change in etching rate when feedback control of bias RF power is performed. FIG. 18 is a diagram showing an example of the change in etching rate and base potential when feedback control of bias RF power is performed. Graph 88 in FIG. 17 shows the radial etching rate when Ar / N2 / C4F8 gas is used as the processing gas for the etching process, and the bias RF power and the VC value of the impedance adjustment mechanism 53 are combined as follows. In addition, in graph 88 and table 89 in FIG. 18, the frequency of the bias RF signal is set to 400 kHz. In addition, in graph 88, the etching rate is normalized within a predetermined range.

[0066] In the graph 88 and the table 89, the case where the bias RF power is 100 W and the VC value is 475 pF is set as a reference (change rate 0%). The potential (Vpp) of the base 1110 (potential of the first bias electrode 33 and the second bias electrode 34) at this time is set as a set value. The graph 88 and the table 89 also show the etching rate in the radial direction, the potential of the base, and the change rate of the etching rate when the bias RF power is 100 W and the VC value is 10 pF, and when the bias RF power is 110 W and the VC value is 10 pF. In the combination when the bias RF power is 110 W and the VC value is 10 pF, the bias RF power is controlled from 100 W to 110 W so that the potential (Vpp) of the base 1110 becomes a preset set value.

[0067] As shown in graph 88 and table 89, the potential (Vpp) of the base 1110 has a rate of change of -3.2% in the combination of 100 W and 10 pF. In addition, in the combination of 110 W and 10 pF, which is the case where feedback control of the bias RF power is performed, the potential (Vpp) of the base 1110 has a rate of change of 2.6%. Furthermore, in the combination of 100 W and 10 pF, the etching rate has a rate of change of -3.8% in the range of radius 0 mm to 135 mm. In addition, in the combination of 110 W and 10 pF, the etching rate has a rate of change of 0.3% in the range of radius 0 mm to 135 mm. That is, when the frequency of the bias RF signal is 400 kHz, in the combination of 110 W and 10 pF where the bias RF power is feedback controlled, the rate of change of the etching rate meets the allowable value.

[0068] FIG. 19 is a diagram showing an example of the change in etching rate when feedback control of bias RF power is performed. FIG. 20 is a diagram showing an example of the change in etching rate and base potential when feedback control of bias RF power is performed. Graph 90 in FIG. 19 shows the radial etching rate when Ar / N2 / C4F8 gas is used as the processing gas for the etching process, and the bias RF power and the VC value of the impedance adjustment mechanism 53 are combined as follows. In addition, in graph 90 and table 91 in FIG. 20, the frequency of the bias RF signal is set to 12.88 MHz. In addition, in graph 90, the etching rate is normalized within a predetermined range.

[0069] In the graph 90 and table 91, the case where the bias RF power is 300 W and the value of VC is 10 pF is set as a reference (change rate 0%). The potential (Vpp) of the base 1110 (potential of the first bias electrode 33 and the second bias electrode 34) at this time is set as a set value. The graph 90 and table 91 also show the etching rate in the radial direction, the potential of the base, and the rate of change of the etching rate when the bias RF power is 300 W and the value of VC is 100 pF, and when the bias RF power is 385 W and the value of VC is 100 pF. In the combination when the bias RF power is 385 W and the value of VC is 100 pF, the bias RF power is controlled from 300 W to 385 W so that the potential (Vpp) of the base 1110 becomes a preset set value.

[0070] As shown in the graph 90 and the table 91, the potential (Vpp) of the base 1110 has a rate of change of -16.0% in the combination of 300 W and 100 pF. In addition, in the combination of 385 W and 100 pF, which is the case where feedback control of the bias RF power is performed, the potential (Vpp) of the base 1110 has a rate of change of -3.4%. Furthermore, in the combination of 300 W and 100 pF, the etching rate has a rate of change of -14.0% in the range of a radius of 0 mm to 135 mm. In addition, in the combination of 385 W and 100 pF, the etching rate has a rate of change of -0.6% in the range of a radius of 0 mm to 135 mm. That is, when the frequency of the bias RF signal is 12.88 MHz, in the combination of 385 W and 100 pF where the bias RF power is feedback controlled, the rate of change of the etching rate satisfies the allowable value. In this way, in the second embodiment, by controlling the bias RF power, the change in the etching rate when the value of VC is changed can be suppressed.

[0071] [Bias DC power control] Next, a case where the power of the bias DC signal output from the bias DC generating unit 32a in the second embodiment is controlled will be described with reference to Fig. 21 to Fig. 23. When the power of the bias DC signal is controlled, the second RF generating unit 31b in Fig. 12 is replaced with the bias DC generating unit 32a, and description of the configuration thereof will be omitted.

[0072] In controlling the power of the bias DC signal, the control unit 2 controls the bias DC generation unit 32a based on the voltage and current input from the measurement unit 36 ​​when at least one impedance adjustment mechanism 53 is adjusted. That is, the bias DC generation unit 32a controls (feedback controls) the power of the bias DC signal based on the voltage and current measured by the measurement unit 36 ​​so that the power supplied to the first bias electrode 33 and the second bias electrode 34 becomes a preset set value. Here, the preset set value is, for example, a value when the potential (Vpp) of the base 1110 measured by the high voltage probe 37 becomes a desired potential. Note that, when determining the set value, a high voltage probe may be connected to the substrate W and the ring assembly 112 instead of the high voltage probe 37.

[0073] Fig. 21 is a diagram showing an example of a change in current when feedback control of bias DC power is not performed. In Table 92 of Fig. 21, the source RF power is 300 W, the bias RF power is 0 W, the voltage (DC pulse voltage) of the bias DC signal is 200 V, 300 V, and 400 V, and the VC value of the impedance adjustment mechanism 53 is changed from 200 pF to 2000 pF. Note that the bias DC signal has one period of the voltage pulse sequence of 400 kHz and a duty ratio of 20%. Table 92 also shows the ratio of the potential of the ring assembly 112 (edge ​​ring) and the substrate W in this case, and the change amount (ΔI) of the current of the bias DC signal for each DC pulse voltage.

[0074] As shown in Table 92, the ratio of the potential of the ring assembly 112 to that of the substrate W is almost unchanged, being 0.71 when the DC pulse voltage is 200V, 0.70 when it is 300V, and 0.71 when it is 400V. On the other hand, the change in the current of the bias DC signal (ΔI) increases according to the voltage, being 0.68A when the DC pulse voltage is 200V, 0.80A when it is 300V, and 1.28A when it is 400V. That is, the change in the bias DC power when the value of VC is changed from 200pF to 2000pF is 136W at 200V, 240W at 300V, and 512W at 400V. That is, when the DC pulse voltage is high, when the value of VC of the impedance adjustment mechanism 53 is changed from 200pF to 2000pF, it is considered that the potential (Vdc) of the substrate W fluctuates, the current of the bias DC signal fluctuates, and the bias DC power also fluctuates. When the value of VC of the impedance adjustment mechanism 53 is changed, the DC pulse voltages are each controlled to be constant voltage.

[0075] Fig. 22 is a diagram showing an example of the change in etching rate when feedback control of bias DC power is not performed. Graph 93 shown in Fig. 22 shows the etching rate in the radial direction when the source RF power is 300 W, the bias RF power is 0 W, the DC pulse voltage is 400 V, and the VC value of the impedance adjustment mechanism 53 is 200 pF and 2000 pF. In addition, in graph 93, Ar / N2 / C4F8 gas is used as the processing gas for the etching process, and the etching rate is normalized within a predetermined range with the value at the center of the substrate W (0 mm in the radial direction) being 1.

[0076] In the graph 93, the case where the value of the variable capacitor (VC) of the impedance adjustment mechanism 53 is 200 pF is set as a reference (change rate 0%). In the graph 93, when the value of VC is changed from 200 pF to 2000 pF, the DC pulse voltage is controlled to be constant at 400 V. At this time, the change rate of the etching rate when the value of VC is 2000 pF is a maximum of 12.9% in the range of a radius of 0 mm to 120 mm. In addition, the change rate of the bias DC power when the value of VC is 2000 pF is 91.5%. That is, according to the table 92 and the graph 93, when the value of VC is changed from 200 pF to 2000 pF, the potential (Vdc) of the substrate W changes, and thus the etching rate also changes. If the allowable value of the change rate of the etching rate is, for example, ±10%, when the value of VC is 2000 pF, the change rate of the etching rate exceeds the allowable value.

[0077] FIG. 23 is a diagram showing an example of the change in etching rate when feedback control of bias DC power is performed. A graph 94 shown in FIG. 23 shows the etching rate in the radial direction when the source RF power is 300 W, the bias RF power is 0 W, and the VC value of the impedance adjustment mechanism 53 is 200 pF and 2000 pF. When the VC value is 200 pF, the DC pulse voltage is 400 V. On the other hand, when the VC value is 2000 pF, the bias DC power is controlled to be constant, and the DC pulse voltage is 350 V. Furthermore, in the graph 94, Ar / N2 / C4F8 gas is used as the processing gas for the etching process, and the etching rate is normalized within a predetermined range with the value at the center of the substrate W (0 mm in the radial direction) being 1.

[0078] In the graph 94, the case where the value of the variable capacitor (VC) of the impedance adjustment mechanism 53 is 200 pF is set as a reference (change rate 0%). In the graph 94, when the value of VC is changed from 200 pF to 2000 pF, the bias DC power is controlled to be constant. At this time, the change rate of the etching rate when the value of VC is 2000 pF is a maximum of 6.7% in the range of a radius of 0 mm to 120 mm. In addition, the change rate of the bias DC power when the value of VC is 2000 pF is 26.4%. That is, by controlling the bias DC power, the change rate of the etching rate when the value of VC is 2000 pF satisfies the allowable value. In this way, in the second embodiment, the change in the etching rate when the value of VC is changed can be suppressed by controlling the bias DC power.

[0079] As described above, according to the first embodiment, the plasma processing apparatus 1 includes a chamber (plasma processing chamber 10), a bias power supply (second RF generating unit 31b), a substrate support (substrate support unit 11) that supports the substrate W and the edge ring (ring assembly 112) in the chamber, a plurality of first impedance adjustment mechanisms (impedance adjustment mechanisms 52), and an electrical path 35. The substrate support is configured to have a first region (central region 111a) that supports the substrate W, a second region (annular region 111b) that is provided around the first region and supports the edge ring, a first bias electrode 33 provided in the first region, a plurality of first impedance adjustment electrodes 50 that are provided in the first region and grounded, and a second bias electrode 34 provided in the second region, and each of the plurality of first impedance adjustment mechanisms is configured to be connected to each of the plurality of first impedance adjustment electrodes 50, and the electrical path 35 is configured to connect the bias power supply, the first bias electrode 33, and the second bias electrode 34. As a result, it is possible to suppress the bias in the etching rate.

[0080] Moreover, according to the first embodiment, the second impedance adjustment mechanism (impedance adjustment mechanism 53) and the second impedance adjustment electrode 51 are further provided, and the second impedance adjustment mechanism is connected to the second impedance adjustment electrode 51. As a result, it is possible to suppress bias in the etching rate.

[0081] According to the first embodiment, two or more of the first impedance adjustment electrodes 50 are provided in the circumferential direction of the substrate support. As a result, the potential of the central region 111a can be adjusted for each region in the circumferential direction, so that the bias of the etching rate can be suppressed. Furthermore, when there is a change (shift) in the etching rate on the center side of the substrate W, the etching rate on the center side of the substrate W can be adjusted.

[0082] Moreover, according to the first embodiment, two or more of the multiple first impedance adjustment electrodes 50 are provided in the radial direction of the substrate support. As a result, the potential of the central region 111a can be adjusted for each region in the radial direction, so that the bias of the etching rate can be suppressed. Furthermore, when there is a change (shift) in the etching rate on the center side of the substrate W, the etching rate on the center side of the substrate W can be adjusted.

[0083] According to the first embodiment, the plurality of first impedance adjustment electrodes 50 are provided in two or more in each of the circumferential and radial directions of the substrate support. As a result, the potential of the central region 111a can be adjusted for each of the circumferential and radial regions, so that the bias of the etching rate can be suppressed. Furthermore, when there is a change (shift) in the etching rate on the center side of the substrate W, the etching rate on the center side of the substrate W can be adjusted.

[0084] Furthermore, according to the first embodiment, a plurality of second impedance adjustment electrodes 51 and a plurality of second impedance adjustment mechanisms are provided, and each of the plurality of second impedance adjustment mechanisms is configured to be connected to a respective one of the plurality of second impedance adjustment electrodes 51. As a result, it is possible to adjust the impedance at a location on the outer periphery side of the substrate W where bias in the etching rate occurs, and therefore it is possible to suppress the bias in the etching rate.

[0085] Moreover, according to the first embodiment, two or more of the second impedance adjustment electrodes 51 are provided in the circumferential direction of the substrate support. As a result, the impedance at the location where the etching rate bias occurs on the outer circumferential side of the substrate W can be adjusted, so that the etching rate bias can be suppressed.

[0086] Moreover, according to the first embodiment, two or more of the multiple second impedance adjustment electrodes 51 are provided in the radial direction of the substrate support. As a result, it is possible to adjust the impedance at a location where the etching rate bias occurs on the outer circumferential side of the substrate W, and therefore it is possible to suppress the etching rate bias.

[0087] Moreover, according to the second embodiment, the plasma processing apparatus 1 further includes a measurement unit 36 ​​configured to measure the voltage and current of a bias RF signal output from the bias power supply (second RF generation unit 31b). The bias power supply is configured to control the power of the bias RF signal based on the voltage and current measured by the measurement unit 36 ​​when at least one second impedance adjustment mechanism (impedance adjustment mechanism 53) is adjusted, so that the potentials of the first bias electrode 33 and the second bias electrode 34 become preset set values. As a result, by controlling the bias RF power, it is possible to suppress a change in the etching rate when the value of VC is changed.

[0088] According to the second embodiment, the plasma processing apparatus 1 further includes a measurement unit 36 ​​configured to measure the voltage and current of a bias DC signal output from the bias power supply (bias DC generation unit 32a). The bias power supply is configured to control the power of the bias DC signal based on the voltage and current measured by the measurement unit 36 ​​when at least one second impedance adjustment mechanism (impedance adjustment mechanism 53) is adjusted, so that the power supplied to the first bias electrode 33 and the second bias electrode 34 becomes a preset set value. As a result, by controlling the bias DC power, it is possible to suppress a change in the etching rate when the value of VC is changed.

[0089] According to the first embodiment, the plasma processing apparatus 1 includes a chamber (plasma processing chamber 10), a bias power supply (second RF generating unit 31b), a substrate support (substrate support unit 11) that supports the substrate W and the edge ring (ring assembly 112) in the chamber, a plurality of impedance adjustment mechanisms (impedance adjustment mechanisms 53), and an electrical path 35. The substrate support is configured to have a first region (central region 111a) that supports the substrate W, a second region (annular region 111b) that is provided around the first region and supports the edge ring, a first bias electrode 33 provided in the first region, a second bias electrode 34 provided in the second region, and a plurality of second impedance adjustment electrodes 51 that are provided in the second region and grounded, and each of the plurality of impedance adjustment mechanisms is configured to be connected to each of the plurality of second impedance adjustment electrodes 51, and the electrical path 35 is configured to connect the bias power supply, the first bias electrode 33, and the second bias electrode 34. As a result, it is possible to suppress the bias in the etching rate.

[0090] Moreover, according to the first embodiment, the semiconductor device further includes a first impedance adjustment mechanism and a first impedance adjustment electrode 50, the first impedance adjustment mechanism is connected to the first impedance adjustment electrode 50, and the plurality of impedance adjustment mechanisms are a plurality of second impedance adjustment mechanisms. As a result, it is possible to suppress bias in the etching rate.

[0091] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The above-described embodiments may be omitted, substituted, or modified in various forms without departing from the scope and spirit of the appended claims.

[0092] In the above embodiment, the plasma processing apparatus 1 is described as an example in which an inductively coupled plasma is used as a plasma source to perform a process such as etching on the substrate W, but the disclosed technology is not limited to this. As long as the apparatus performs a process on the substrate W using plasma, the plasma source is not limited to inductively coupled plasma, and any plasma source such as capacitively coupled plasma, microwave plasma, magnetron plasma, etc. can be used.

[0093] The present disclosure can also be configured as follows. (1) A chamber; A bias power supply; a substrate support for supporting a substrate and an edge ring within the chamber; A plurality of first impedance adjustment mechanisms; An electrical path; Equipped with The substrate support includes: a first region for supporting the substrate; a second region provided around the first region and supporting the edge ring; a first bias electrode provided in the first region; a plurality of first impedance adjustment electrodes provided in the first region and grounded; a second bias electrode provided in the second region; and configured to have each of the plurality of first impedance adjustment mechanisms is configured to be connected to each of the plurality of first impedance adjustment electrodes; the electrical path is configured to connect the bias power supply, the first bias electrode, and the second bias electrode; Plasma processing equipment. (2) Further comprising a second impedance adjustment mechanism and a second impedance adjustment electrode, the second impedance adjustment mechanism is connected to the second impedance adjustment electrode; The plasma processing apparatus according to (1) above. (3) The plurality of first impedance adjustment electrodes are provided in a circumferential direction of the substrate support, and two or more of the first impedance adjustment electrodes are provided in the circumferential direction of the substrate support. The plasma processing apparatus according to (1) or (2). (4) The plurality of first impedance adjustment electrodes are provided in a radial direction of the substrate support, and two or more of the first impedance adjustment electrodes are provided in the radial direction of the substrate support. The plasma processing apparatus according to (1) or (2). (5) The plurality of first impedance adjustment electrodes are provided in two or more in each of the circumferential direction and the radial direction of the substrate support. The plasma processing apparatus according to (1) or (2). (6) The second impedance adjustment electrodes and the second impedance adjustment mechanisms are each provided in plurality, Each of the plurality of second impedance adjustment mechanisms is configured to be connected to each of the plurality of second impedance adjustment electrodes. The plasma processing apparatus according to (2) above. (7) The plurality of second impedance adjustment electrodes are provided in a circumferential direction of the substrate support, and two or more second impedance adjustment electrodes are provided in the circumferential direction of the substrate support. The plasma processing apparatus according to (6) above. (8) The plurality of second impedance adjustment electrodes are provided in a radial direction of the substrate support, The plasma processing apparatus according to (6) or (7) above. (9) A measurement unit configured to measure a voltage and a current of a bias RF signal output from the bias power supply, the bias power supply is configured to control the power of the bias RF signal based on the voltage and the current measured by the measurement unit when at least one of the second impedance adjustment mechanisms is adjusted, so that the potentials of the first bias electrode and the second bias electrode become preset set values. The plasma processing apparatus according to any one of (2) and (6) to (8). (10) A measurement unit configured to measure a voltage and a current of a bias DC signal output from the bias power supply, The bias power supply is configured to control the power of the bias DC signal based on the voltage and the current measured by the measurement unit when at least one of the second impedance adjustment mechanisms is adjusted, so that the power supplied to the first bias electrode and the second bias electrode becomes a preset set value. The plasma processing apparatus according to any one of (2) and (6) to (8). (11) A chamber; A bias power supply; a substrate support for supporting a substrate and an edge ring within the chamber; A plurality of impedance adjustment mechanisms; An electrical path; Equipped with The substrate support includes: a first region for supporting the substrate; a second region provided around the first region and supporting the edge ring; a first bias electrode provided in the first region; a second bias electrode provided in the second region; a plurality of second impedance adjustment electrodes provided in the second region and grounded; and configured to have each of the plurality of impedance adjustment mechanisms is configured to be connected to each of the plurality of second impedance adjustment electrodes; the electrical path is configured to connect the bias power supply, the first bias electrode, and the second bias electrode; A plasma processing apparatus comprising: (12) Further comprising a first impedance adjustment mechanism and a first impedance adjustment electrode, the first impedance adjustment mechanism is connected to the first impedance adjustment electrode; the plurality of impedance adjustment mechanisms are a plurality of second impedance adjustment mechanisms; The plasma processing apparatus according to (11) above. (13) The plurality of second impedance adjustment electrodes are provided in a circumferential direction of the substrate support, and two or more second impedance adjustment electrodes are provided in the circumferential direction of the substrate support. The plasma processing apparatus according to (11) or (12). (14) The plurality of second impedance adjustment electrodes are provided in a radial direction of the substrate support, The plasma processing apparatus according to (11) or (12). (15) The plurality of second impedance adjustment electrodes are provided in two or more in each of the circumferential direction and the radial direction of the substrate support. The plasma processing apparatus according to (11) or (12). (16) The first impedance adjustment electrodes and the first impedance adjustment mechanisms are each provided in plurality, Each of the plurality of first impedance adjustment mechanisms is configured to be connected to each of the plurality of first impedance adjustment electrodes. The plasma processing apparatus according to (12) above. (17) The plurality of first impedance adjustment electrodes are provided in a circumferential direction of the substrate support, and two or more of the first impedance adjustment electrodes are provided in the circumferential direction of the substrate support. The plasma processing apparatus according to (16) above. (18) The plurality of first impedance adjustment electrodes are provided in a radial direction of the substrate support, and two or more of the first impedance adjustment electrodes are provided in the radial direction of the substrate support. The plasma processing apparatus according to (16) or (17). (19) A measurement unit configured to measure a voltage and a current of a bias RF signal output from the bias power supply, The bias power supply is configured to control the power of the bias RF signal based on the voltage and the current measured by the measurement unit when at least one of the impedance adjustment mechanisms is adjusted, so that the potentials of the first bias electrode and the second bias electrode become preset set values. The plasma processing apparatus according to any one of (11) to (18). (20) A measurement unit configured to measure a voltage and a current of a bias DC signal output from the bias power supply, The bias power supply is configured to control the power of the bias DC signal based on the voltage and the current measured by the measurement unit when at least one of the impedance adjustment mechanisms is adjusted, so that the power supplied to the first bias electrode and the second bias electrode becomes a preset set value. The plasma processing apparatus according to any one of (11) to (18). [Explanation of symbols]

[0094] 1. Plasma processing equipment 10 Plasma Processing Chamber 11 Substrate support 31a First RF generation unit 31b Second RF generation unit 32a Bias DC generator 33 First bias electrode 34 Second bias electrode 35 Electrical Path 36 Measuring part 50, 50a to 50c First impedance adjusting electrode 51, 51a to 51d Second impedance adjusting electrode 52,53 Impedance adjustment mechanism 111a,111c central area 111b Annular region 112 Ring Assembly 1111,1111b Electrostatic chuck W substrate

Claims

1. A chamber; A bias power supply; a substrate support for supporting a substrate and an edge ring within the chamber; A plurality of first impedance adjustment mechanisms; An electrical path; Equipped with The substrate support includes: a first region for supporting the substrate; a second region provided around the first region and supporting the edge ring; a first bias electrode provided in the first region; a plurality of first impedance adjustment electrodes provided in the first region and grounded; a second bias electrode provided in the second region; and configured to have each of the plurality of first impedance adjustment mechanisms is configured to be connected to each of the plurality of first impedance adjustment electrodes; the electrical path is configured to connect the bias power supply, the first bias electrode, and the second bias electrode; Plasma processing equipment.

2. Further comprising a second impedance adjustment mechanism and a second impedance adjustment electrode, the second impedance adjustment mechanism is connected to the second impedance adjustment electrode; The plasma processing apparatus according to claim 1 .

3. The plurality of first impedance adjustment electrodes are provided in a circumferential direction of the substrate support, and two or more first impedance adjustment electrodes are provided in the circumferential direction of the substrate support.

3. The plasma processing apparatus according to claim 1 or 2.

4. The plurality of first impedance adjustment electrodes are provided in a radial direction of the substrate support, and two or more of the first impedance adjustment electrodes are provided in the radial direction of the substrate support.

3. The plasma processing apparatus according to claim 1 or 2.

5. The plurality of first impedance adjustment electrodes are provided in two or more in each of a circumferential direction and a radial direction of the substrate support.

3. The plasma processing apparatus according to claim 1 or 2.

6. the second impedance adjustment electrodes and the second impedance adjustment mechanisms are each provided in plurality, Each of the second impedance adjustment mechanisms is configured to be connected to each of the second impedance adjustment electrodes. The plasma processing apparatus according to claim 2 .

7. The plurality of second impedance adjustment electrodes are provided in a circumferential direction of the substrate support, and two or more second impedance adjustment electrodes are provided in the circumferential direction of the substrate support. The plasma processing apparatus according to claim 6 .

8. The plurality of second impedance adjustment electrodes are provided in a radial direction of the substrate support, and two or more second impedance adjustment electrodes are provided in the radial direction of the substrate support. The plasma processing apparatus according to claim 6 or 7.

9. A measurement unit configured to measure a voltage and a current of a bias RF signal output from the bias power supply, the bias power supply is configured to control the power of the bias RF signal based on the voltage and the current measured by the measurement unit when at least one of the second impedance adjustment mechanisms is adjusted, so that the potentials of the first bias electrode and the second bias electrode become preset set values.

8. The plasma processing apparatus according to claim 2, 6 or 7.

10. A measurement unit configured to measure a voltage and a current of a bias DC signal output from the bias power supply, The bias power supply is configured to control the power of the bias DC signal based on the voltage and the current measured by the measurement unit when at least one of the second impedance adjustment mechanisms is adjusted, so that the power supplied to the first bias electrode and the second bias electrode becomes a preset set value.

8. The plasma processing apparatus according to claim 2, 6 or 7.

11. A chamber; A bias power supply; a substrate support for supporting a substrate and an edge ring within the chamber; A plurality of impedance adjustment mechanisms; An electrical path; Equipped with The substrate support includes: a first region for supporting the substrate; a second region provided around the first region and supporting the edge ring; a first bias electrode provided in the first region; a second bias electrode provided in the second region; a plurality of second impedance adjustment electrodes provided in the second region and grounded; and configured to have each of the plurality of impedance adjustment mechanisms is configured to be connected to each of the plurality of second impedance adjustment electrodes; the electrical path is configured to connect the bias power supply, the first bias electrode, and the second bias electrode; A plasma processing apparatus comprising:

12. Further comprising a first impedance adjustment mechanism and a first impedance adjustment electrode, the first impedance adjustment mechanism is connected to the first impedance adjustment electrode; the plurality of impedance adjustment mechanisms are a plurality of second impedance adjustment mechanisms; The plasma processing apparatus according to claim 11 .

13. The plurality of second impedance adjustment electrodes are provided in a circumferential direction of the substrate support, and two or more second impedance adjustment electrodes are provided in the circumferential direction of the substrate support. The plasma processing apparatus according to claim 11 or 12.

14. The plurality of second impedance adjustment electrodes are provided in a radial direction of the substrate support, and two or more second impedance adjustment electrodes are provided in the radial direction of the substrate support. The plasma processing apparatus according to claim 11 or 12.

15. The plurality of second impedance adjustment electrodes are provided in two or more in each of a circumferential direction and a radial direction of the substrate support. The plasma processing apparatus according to claim 11 or 12.

16. a plurality of the first impedance adjustment electrodes and a plurality of the first impedance adjustment mechanisms are provided; Each of the plurality of first impedance adjustment mechanisms is configured to be connected to each of the plurality of first impedance adjustment electrodes. The plasma processing apparatus according to claim 12 .

17. The plurality of first impedance adjustment electrodes are provided in a circumferential direction of the substrate support, and two or more first impedance adjustment electrodes are provided in the circumferential direction of the substrate support. The plasma processing apparatus according to claim 16 .

18. The plurality of first impedance adjustment electrodes are provided in a radial direction of the substrate support, and two or more of the first impedance adjustment electrodes are provided in the radial direction of the substrate support.

18. The plasma processing apparatus according to claim 16 or 17.

19. A measurement unit configured to measure a voltage and a current of a bias RF signal output from the bias power supply, The bias power supply is configured to control the power of the bias RF signal based on the voltage and the current measured by the measurement unit when at least one of the impedance adjustment mechanisms is adjusted, so that the potentials of the first bias electrode and the second bias electrode become preset set values.

18. The plasma processing apparatus according to claim 11, 12, 16, or 17.

20. A measurement unit configured to measure a voltage and a current of a bias DC signal output from the bias power supply, The bias power supply is configured to control the power of the bias DC signal based on the voltage and the current measured by the measurement unit when at least one of the impedance adjustment mechanisms is adjusted, so that the power supplied to the first bias electrode and the second bias electrode becomes a preset set value.

18. The plasma processing apparatus according to claim 11, 12, 16, or 17.

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