Memory controller and memory system

Abstract

To provide a memory controller capable of enhancing a correction function of errors included in data.SOLUTION: A memory controller comprises an interface unit, a holding unit, an acquisition unit, a correction unit, and an error correction unit. When data is read from a semiconductor storage device, the interface unit receives a data signal, which is a signal for data, from a semiconductor storage device, and acquires data from the data signal. The holding unit holds likelihood information of the data. The acquisition unit acquires parameters influencing data acquisition from the data signal. The correction unit corrects the likelihood information on the basis of the parameters acquired by the acquisition unit. The error correction unit performs data error correction processing on the basis of the likelihood information corrected by the correction unit.SELECTED DRAWING: Figure 14

Description

[Technical field]

[0001] SUMMARY OF THE DISCLOSURE The present invention relates to a memory controller and a memory system. [Background technology]

[0002] 2. Description of the Related Art A memory controller is known that detects errors in data read from a nonvolatile memory and corrects the errors. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2021-111826 A Summary of the Invention [Problem to be solved by the invention]

[0004] According to the disclosed embodiments, a memory controller and a memory system are provided that are capable of improving the correction function for errors contained in data. [Means for solving the problem]

[0005] A memory controller according to an embodiment includes an interface unit, a holding unit, an acquisition unit, a correction unit, and an error correction unit. During a data read operation from the semiconductor memory device, the interface unit receives a data signal, which is a signal of data, from the semiconductor memory device and acquires data from the data signal. The holding unit holds likelihood information of the data. The acquisition unit acquires parameters that affect the acquisition of data from the data signal. The correction unit corrects the likelihood information based on the parameters acquired by the acquisition unit. The error correction unit performs an error correction process on the data based on the likelihood information corrected by the correction unit.

[0006] A memory system according to an embodiment includes an interface unit, a holding unit, an acquisition unit, a correction unit, and an error correction unit. During a data read operation from the semiconductor memory device, the interface unit receives a data signal, which is a signal of data, from the semiconductor memory device and acquires the data from the data signal. The holding unit holds likelihood information of the data. The acquisition unit acquires parameters that affect the acquisition of data from the data signal. The correction unit corrects the likelihood information based on the parameters acquired by the acquisition unit. The error correction unit performs an error correction process on the data based on the likelihood information corrected by the correction unit. [Brief description of the drawings]

[0007] [Figure 1] 1 is a block diagram showing a schematic configuration of a memory system according to an embodiment; [Diagram 2] 1 is a block diagram showing a schematic configuration of a memory system according to an embodiment; [Diagram 3] FIG. 2 is a side view showing a hardware configuration of the memory system according to the embodiment. [Figure 4] 4A and 4B are a side view and a plan view, respectively, showing a hardware configuration of a package according to an embodiment. [Diagram 5] 1 is a block diagram showing a schematic configuration of a semiconductor memory device according to an embodiment; [Figure 6] 1 is a circuit diagram showing a configuration of a semiconductor memory device according to an embodiment; [Figure 7] 1 is a cross-sectional view showing a cross-sectional structure of a semiconductor memory device according to an embodiment; [Figure 8] 3A and 3B are diagrams illustrating threshold distributions of memory cell transistors according to the embodiment. [Figure 9] 6 is a graph showing the transition of the potential of each wiring during a read operation of the semiconductor memory device according to the embodiment. [Figure 10] 4 is a timing chart showing an example of an operation when writing data in the semiconductor memory device according to the embodiment. [Figure 11] 11 is a graph showing an example of a transition of a data signal in a memory system of a reference example. [Figure 12]1 is a graph showing an example of a transition of a data signal in the memory system of the embodiment. [Figure 13] 6A and 6B are graphs showing an example of the transition of a data strobe signal and a data signal according to an embodiment. [Figure 14] FIG. 1 is a circuit diagram showing a configuration of a memory system according to an embodiment. [Figure 15] 6 is a graph showing an example of a distribution of threshold voltages of memory cell transistors according to the embodiment. [Figure 16] 10 is a table showing an example of a likelihood information correction process executed by a likelihood information correction unit according to the embodiment. [Figure 17] FIG. 13 is a cross-sectional view showing a cross-sectional structure of a semiconductor memory device according to another embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, an embodiment will be described with reference to the drawings. In order to facilitate understanding of the description, the same components in the drawings are denoted by the same reference numerals as much as possible, and duplicated description will be omitted. 1. Embodiment A memory system according to an embodiment will be described below First, a schematic configuration of the memory system according to the embodiment will be described.

[0009] 1.1 Memory system configuration As shown in Fig. 1, the memory system 3 of this embodiment includes a memory controller (controller chip) 1 and a semiconductor memory device (memory chip) 2. The semiconductor memory device 2 is a non-volatile memory device configured as a NAND type flash memory. The memory system 3 can be connected to a host. The host is, for example, an electronic device such as a personal computer or a mobile terminal. Note that, although only one semiconductor memory device 2 is shown in Fig. 1, a plurality of semiconductor memory devices 2 are provided in the actual memory system 3.

[0010] The memory controller 1 controls writing of data to the semiconductor memory device 2 in accordance with a write request from the host, and also controls reading of data from the semiconductor memory device 2 in accordance with a read request from the host. The following signals are transmitted and received between the memory controller 1 and the semiconductor memory device 2: chip enable signal / CE, ready / busy signal / RB, command latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signals / RE, RE, write protect signal / WP, data signal DQ<7:0>, and data strobe signals DQS, / DQS.

[0011] The chip enable signal / CE is transmitted from the memory controller 1 to the semiconductor memory device 2. The chip enable signal / CE is a signal for enabling the semiconductor memory device 2. The ready / busy signal / RB is transmitted from the semiconductor memory device 2 to the memory controller 1. The ready / busy signal / RB is a signal for indicating whether the semiconductor memory device 2 is in a ready state or a busy state. A "ready state" is, for example, a state in which an external command is accepted. A "busy state" is a state in which an external command is not accepted.

[0012] 2, a chip enable signal / CE is individually transmitted to each of the multiple semiconductor memory devices 2. In Fig. 2, a number is added to the end of each chip enable signal / CE, for example, " / CE0", so that each chip enable signal / CE can be distinguished from each other. Similarly, a ready-busy signal / RB is individually transmitted from each of the multiple semiconductor memory devices 2. In Fig. 2, a number is added to the end of each ready-busy signal / RB, for example, " / RB0", so that each ready-busy signal / RB can be distinguished from each other.

[0013] Signals other than the chip enable signal / CE and the ready / busy signal / RB (such as the command latch enable signal CLE) are transmitted and received between the memory controller 1 and the semiconductor memory device 2 via a signal line shared by multiple semiconductor memory devices 2. The memory controller 1 uses an individual chip enable signal / CE to identify the semiconductor memory device 2 with which it is to communicate.

[0014] The command latch enable signal CLE is transmitted from the memory controller 1 to the semiconductor memory device 2. The command latch enable signal CLE is a signal indicating that the data signal DQ<7:0> is a command. The address latch enable signal ALE is transmitted from the memory controller 1 to the semiconductor memory device 2. The address latch enable signal ALE is a signal indicating that the data signal DQ<7:0> is an address. The write enable signal / WE is transmitted from the memory controller 1 to the semiconductor memory device 2. The write enable signal / WE is a signal for loading a received signal into the semiconductor memory device 2, and is asserted by the memory controller 1 every time a command, address, and data are received. The semiconductor memory device 2 loads the “Low (Low)” level data signal DQ<7:0> in response to the rising edge of the signal / WE.

[0015] For example, when the signal CLE is at “H (High)” level and the signal ALE is at “L (Low)” level, the semiconductor memory device 2 accepts the signal DQ<7:0> as a command in response to a rising edge of the signal / WE and stores it in the register 24. Also, when the signal CLE is at “L” level and the signal ALE is at “H” level, the semiconductor memory device 2 accepts the signal DQ<7:0> as an address in response to a rising edge of the signal / WE and stores it in the register 24. Furthermore, in a data-in operation in a single data rate (SDR) mode, when the signal CLE is at “L” level and the signal ALE is at “L” level, the semiconductor memory device 2 accepts the signal DQ<7:0> as data in response to a rising edge of the signal / WE and stores it in the sense amplifier 28.

[0016] The read enable signal / RE is transmitted from the memory controller 1 to the semiconductor memory device 2. The signal RE is a complementary signal of the signal / RE. The read enable signals / RE and RE are signals for the memory controller 1 to read data from the semiconductor memory device 2. The read enable signals / RE and RE are used to control the operation timing of the semiconductor memory device 2 when outputting, for example, a data signal DQ<7:0>. The data signal DQ<7:0> is the substance of data transmitted and received between the semiconductor memory device 2 and the memory controller 1, and includes a command, an address, and data. The data strobe signal DQS is a timing control signal transmitted and received between the semiconductor memory device 2 and the memory controller 1 along with the data signal DQ<7:0>. The signal / DQS is a complementary signal of the signal DQS. The data strobe signals DQS and / DQS are signals for controlling the timing of input and output of the data signal DQ<7:0>.

[0017] For example, in a data-in operation in a double data rate (DDR) mode, the memory controller 1 toggles the data strobe signals DQS, / DQS between the “L” level and the “H” level while outputting the data signal DQ<7:0>. The phase of the data strobe signal DQS is adjusted so that its rising edge and falling edge coincide with the center of one cycle of the data signal DQ<7:0>. In other words, in the data-in operation, the data strobe signal DQS and the data signal DQ<7:0> are transmitted from the memory controller 1 to the semiconductor memory device 2 with their phases shifted by 90 degrees. The semiconductor memory device 2 accepts the signal DQ<7:0> as data in response to the rising edge and falling edge of the data strobe signal DQS, and causes the sense amplifier 28 to hold the data.

[0018] In a data-out operation in the single data rate mode, the semiconductor memory device 2 outputs the data signal DQ<7:0> to the memory controller 1 in response to the rising edge of the read enable signal / RE. In a data-out operation in the double data rate mode, the memory controller 1 switches (toggles) the read enable signals / RE and RE between the "L" level and the "H" level. The semiconductor memory device 2 outputs the data signal DQ<7:0> to the memory controller 1 while switching (toggles) the data strobe signals DQS and / DQS between the "L" level and the "H" level in response to the rising edge and falling edge of the read enable signal / RE. The phase of the data strobe signal DQS is adjusted so that its rising edge and falling edge coincide with the edges of one cycle of the data signal DQ<7:0>.

[0019] In a data-out operation in double data rate mode, the memory interface 15 of the memory controller 1 accepts the data signal DQ<7:0> of each cycle at the rising and falling timings of a signal that is 90 degrees out of phase with the data strobe signals DQS, / DQS. The write protect signal / WP is transmitted from the memory controller 1 to the semiconductor memory device 2. The write protect signal / WP is a signal for instructing the semiconductor memory device 2 to prohibit writing and erasing of data.

[0020] The memory controller 1 includes a RAM 11, a processor 12, a host interface 13, an ECC (Error Correcting Code) circuit 14, and a memory interface 15. These are connected to each other via an internal bus 16. The host interface 13 outputs requests and user data (write data) received from the host to the internal bus 16. The host interface 13 also transmits user data read from the semiconductor memory device 2 and responses from the processor 12 to the host.

[0021] The memory interface 15 controls the process of writing user data and the like to the semiconductor memory device 2 and the process of reading user data and the like from the semiconductor memory device 2 based on instructions from the processor 12. The processor 12 performs overall control of the memory controller 1. The processor 12 is a CPU, an MPU, or the like. When the processor 12 receives a request from the host via the host interface 13, the processor 12 performs control according to the request. For example, the processor 12 instructs the memory interface 15 to write user data and parity to the semiconductor memory device 2 in accordance with the request from the host. The processor 12 also instructs the memory interface 15 to read user data and parity from the semiconductor memory device 2 in accordance with the request from the host.

[0022] The processor 12 determines a storage area (memory area) on the semiconductor memory device 2 for user data accumulated in the RAM 11. The user data is stored in the RAM 11 via the internal bus 16. The processor 12 determines the memory area for data (page data) in units of pages, which are writing units. User data stored in one page of the semiconductor memory device 2 is also referred to as "unit data" below. The unit data is generally encoded and stored in the semiconductor memory device 2 as a code word. In this embodiment, encoding is not essential. The memory controller 1 may store the unit data in the semiconductor memory device 2 without encoding it, but FIG. 1 shows a configuration in which encoding is performed as an example. When the memory controller 1 does not perform encoding, the page data matches the unit data. In addition, one code word may be generated based on one unit data, or one code word may be generated based on divided data into which the unit data is divided. In addition, one code word may be generated using multiple unit data.

[0023] The processor 12 determines the memory area of ​​the semiconductor memory device 2 to which the unit data is to be written for each unit data. A physical address is assigned to the memory area of ​​the semiconductor memory device 2. The processor 12 manages the memory area to which the unit data is to be written using the physical address. The processor 12 instructs the memory interface 15 to write the user data to the semiconductor memory device 2 by specifying the determined memory area (physical address). The processor 12 manages the correspondence between the logical address of the user data (logical address managed by the host) and the physical address. When the processor 12 receives a read request including a logical address from the host, it identifies the physical address corresponding to the logical address and instructs the memory interface 15 to read the user data by specifying the physical address.

[0024] The ECC circuit 14 generates a codeword by encoding the user data stored in the RAM 11. The ECC circuit 14 also decodes the codeword read from the semiconductor memory device 2. The RAM 11 temporarily stores user data received from the host before storing it in the semiconductor memory device 2, and temporarily stores data read from the semiconductor memory device 2 before transmitting it to the host. The RAM 11 is a general-purpose memory such as an SRAM or a DRAM.

[0025] 1 shows a configuration example in which the memory controller 1 includes an ECC circuit 14 and a memory interface 15. However, the ECC circuit 14 may be built into the memory interface 15. Also, the ECC circuit 14 may be built into the semiconductor memory device 2. The specific configuration and arrangement of each element shown in FIG. 1 are not particularly limited.

[0026] 1 operates as follows when a write request is received from the host. The processor 12 temporarily stores data to be written in the RAM 11. The processor 12 reads the data stored in the RAM 11 and inputs the data to the ECC circuit 14. The ECC circuit 14 encodes the input data and inputs the codeword to the memory interface 15. The memory interface 15 writes the input codeword to the semiconductor memory device 2.

[0027] 1 operates as follows when a read request is received from the host. The memory interface 15 inputs the codeword read from the semiconductor memory device 2 to the ECC circuit 14. The ECC circuit 14 decodes the input codeword and stores the decoded data in the RAM 11. The processor 12 transmits the data stored in the RAM 11 to the host via the host interface 13.

[0028] 1.2 Hardware configuration of memory system Next, the hardware configuration of the memory system 3 will be described. 3 is a side view showing a schematic configuration example of a memory system 3. The memory system 3 includes a system mounting board SSB, a plurality of packages PKG arranged on the system mounting board SSB, and a memory controller (controller chip) 1. The memory controller 1 and some of the packages PKG are arranged on the upper surface of the system mounting board SSB. The other packages PKG are arranged on the lower surface of the system mounting board SSB.

[0029] FIG. 4A is a side view that shows a schematic configuration example of a package PKG, and FIG. 4B is a plan view that shows a schematic configuration example of a package PKG. As shown in FIG. 4(A), the package PKG includes a memory chip mounting substrate MSB and a plurality of semiconductor memory devices (memory chips) 2 stacked on the memory chip mounting substrate MSB. A pad electrode P is provided on the end region in the Y direction of the upper surface of the memory chip mounting substrate MSB, and the remaining region is bonded to the lower surface of the semiconductor memory device 2 via an adhesive or the like. As shown in FIG. 4(A), a pad electrode P is provided on the end region in the Y direction of the upper surface of the semiconductor memory device 2, and the remaining region is bonded to the lower surface of another semiconductor memory device 2 via an adhesive or the like. Corresponding pad electrodes P among the plurality of semiconductor memory devices 2 are commonly connected by a bonding wire B. An electrode terminal T is provided on the lower surface of the memory chip mounting substrate MSB. The pad electrodes P on the upper surface of the memory chip mounting substrate MSB are respectively connected to the electrode terminals T on the lower surface. The memory chip mounting substrate MSB may be, for example, a grid array substrate. On the upper surface of the memory chip mounting substrate MSB, the plurality of semiconductor memory devices 2 and the bonding wires B are covered, for example, with a sealing resin (not shown).

[0030] 4B, the memory chip mounting substrate MSB and the semiconductor memory devices 2 each include a plurality of pad electrodes P arranged in the X direction. The pad electrodes P of each of the semiconductor memory devices 2 correspond to the input / output pads of the signals / CE, CLE, ALE, / WE, / RE, RE, / WP, DQ<7:0>, DQS, and / DQS, respectively.

[0031] The memory chip mounting substrate MSB and the pad electrodes P provided on the semiconductor memory devices 2 are connected to each other via bonding wires B. For example, among the semiconductor memory devices 2, the pad electrodes P corresponding to the command latch enable signal CLE are connected to each other, and the pad electrodes P corresponding to the address latch enable signal ALE are connected to each other. The same is true for the other terminals. Therefore, the pad electrodes P of each semiconductor memory device 2 inside the package PKG are connected to the outside of the package PKG via the electrode terminals T on the lower surface of the memory chip mounting substrate MSB.

[0032] As shown in Fig. 3, the memory controller 1 is provided with a plurality of pad electrodes P. The pad electrodes P of the memory controller 1 are connected to the system mounting board SSB via bonding wires B. The electrode terminals T of the plurality of packages PKG are connected to the system mounting board SSB via solder balls SB. The pad electrodes P of the memory controller 1 and the electrode terminals T of the plurality of packages PKG are connected by wiring (not shown) formed on the upper and lower surfaces of the system mounting board SSB. The upper and lower surfaces of the system mounting board SSB are connected by through electrodes TV.

[0033] A part of the electrode terminals T of the package PKGa arranged on the upper surface of the system mounting board SSB and a part of the electrode terminals T of the package PKGb arranged on the lower surface of the system mounting board SSB may be connected by the through-hole electrodes TV. More specifically, the electrode terminal T corresponding to the data signal DQ<7:0> in the package PKG arranged on the upper surface of the system mounting board SSB and the electrode terminal T corresponding to the data signal DQ<7:0> in the package PKG arranged on the lower surface of the system mounting board SSB may be connected via the through-hole electrodes TV.

[0034] 1.3 Overview of semiconductor memory device As shown in FIG. 5, the semiconductor memory device 2 includes a memory cell array 21, an input / output circuit 22, a logic control circuit 23, a register 24, a sequencer 25, a voltage generation circuit 26, a row decoder 27, a sense amplifier 28, a group of input / output pads 30, a group of logic control pads 31, and a group of power supply input terminals 32.

[0035] The memory cell array 21 is a portion for storing data, and is configured to include a plurality of memory cell transistors associated with a plurality of bit lines and a plurality of word lines. The input / output circuit 22 transmits and receives the data signal DQ<7:0> and the data strobe signals DQS, / DQS to and from the memory controller 1. In addition, the input / output circuit 22 transfers the command and address in the data signal DQ<7:0> to the register 24. Furthermore, the input / output circuit 22 transmits and receives write data and read data to and from the sense amplifier 28.

[0036] The logic control circuit 23 receives a chip enable signal / CE, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal / WE, read enable signals / RE, RE, and a write protect signal / WP from the memory controller 1. In addition, the logic control circuit 23 transfers a ready / busy signal / RB to the memory controller 1 to notify the state of the semiconductor memory device 2 to the outside.

[0037] The register 24 temporarily holds various data. For example, the register 24 holds commands instructing a write operation, a read operation, an erase operation, etc. These commands are input from the memory controller 1 to the input / output circuit 22, and then transferred from the input / output circuit 22 to the register 24 and held therein. The register 24 also holds an address corresponding to the above command. This address is input from the memory controller 1 to the input / output circuit 22, and then transferred from the input / output circuit 22 to the register 24 and held therein.

[0038] The sequencer 25 controls the operation of each part including the memory cell array 21 based on a control signal input from the memory controller 1 to the input / output circuit 22 and the logic control circuit 23 . The voltage generation circuit 26 is a part that generates voltages required for each of the data write operation, read operation, and erase operation in the memory cell array 21. These voltages include, for example, voltages that are applied to each of the multiple word lines and multiple bit lines of the memory cell array 21. The operation of the voltage generation circuit 26 is controlled by the sequencer 25.

[0039] The row decoder 27 is a circuit composed of a group of switches for applying a voltage to each of the word lines of the memory cell array 21. The row decoder 27 receives a block address and a row address from the register 24, selects a block based on the block address, and selects a word line based on the row address. The row decoder 27 switches the open / close state of the group of switches so that a voltage from the voltage generating circuit 26 is applied to the selected word line. The operation of the row decoder 27 is controlled by the sequencer 25.

[0040] The sense amplifier 28 is a circuit for adjusting the voltage applied to the bit lines of the memory cell array 21 and for reading the voltage of the bit lines and converting it into data. When reading data, the sense amplifier 28 acquires data read from the memory cell transistors of the memory cell array 21 to the bit lines, and transfers the acquired read data to the input / output circuit 22. When writing data, the sense amplifier 28 transfers data to be written to the memory cell transistors via the bit lines. The operation of the sense amplifier 28 is controlled by the sequencer 25.

[0041] The input / output pad group 30 is a portion provided with a plurality of terminals (pads) for transmitting and receiving various signals between the memory controller 1 and the input / output circuit 22. Each terminal is provided individually corresponding to each of the data signals DQ<7:0> and the data strobe signals DQS, / DQS.

[0042] The logic control pad group 31 is a portion provided with a plurality of terminals for transmitting and receiving various signals between the memory controller 1 and the logic control circuit 23. The respective terminals are provided individually corresponding to the chip enable signal / CE, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal / WE, the read enable signals / RE, RE, the write protect signal / WP, and the ready / busy signal / RB.

[0043] The power input terminal group 32 is a portion in which a plurality of terminals are provided for receiving the application of each voltage necessary for the operation of the semiconductor memory device 2. The voltages applied to the respective terminals include power supply voltages Vcc, VccQ, Vpp, and a ground voltage Vss. The power supply voltage Vcc is a circuit power supply voltage provided from the outside as an operating power supply, and is, for example, a voltage of about 2.5V. The power supply voltage Vcc is, for example, a voltage for generating a voltage Vdd, which is an internal power supply voltage of the semiconductor memory device 2. The power supply voltage Vdd is, for example, a voltage of about 1.5V. The power supply voltage VccQ is a power supply voltage lower than the power supply voltage Vcc, and is, for example, a voltage of 1.2V. The power supply voltage VccQ is an input / output power supply voltage used when transmitting and receiving a signal between the memory controller 1 and the semiconductor memory device 2. The power supply voltage VccQ is supplied at least to a driver circuit and a receiver circuit (not shown) of the input / output circuit 22. The power supply voltage Vpp is a power supply voltage higher than the power supply voltage Vcc, and is, for example, a voltage of 12V.

[0044] 1.4 Memory cell array circuit configuration Next, the circuit configuration of the memory cell array 21 will be described. As shown in Fig. 6, the memory cell array 21 is composed of a plurality of blocks BLK. Only one of the plurality of blocks BLK is shown in Fig. 6. The configurations of the other blocks BLK in the memory cell array 21 are similar to that shown in Fig. 6.

[0045] 6, the block BLK includes, for example, four string units SU (SU0 to SU3). Each string unit SU includes a plurality of NAND strings NS. Each of the NAND strings NS includes, for example, eight memory cell transistors MT (MT0 to MT7) and select transistors ST1 and ST2.

[0046] The memory cell transistors MT are arranged so as to be connected in series between the select transistors ST1 and ST2. The memory cell transistor MT7 on one end is connected to the source of the select transistor ST1, and the memory cell transistor MT0 on the other end is connected to the drain of the select transistor ST2.

[0047] The gates of the select transistors ST1 of the string units SU0 to SU3 are commonly connected to the select gate lines SGD0 to SGD3, respectively. The gates of the select transistors ST2 are commonly connected to the same select gate line SGS between the multiple string units SU in the same block BLK. The gates of the memory cell transistors MT0 to MT7 in the same block BLK are commonly connected to the word lines WL0 to WL7, respectively. That is, while the word lines WL0 to WL7 and the select gate line SGS are common to the multiple string units SU0 to SU3 in the same block BLK, the select gate line SGD is provided individually for each string unit SU0 to SU3 even within the same block BLK.

[0048] The memory cell array 21 is provided with m bit lines BL (BL0, BL1, ..., BL(m-1)). "m" is an integer corresponding to the number of NAND strings NS included in one string unit SU. The drain of each select transistor ST1 of the NAND string NS is connected to a corresponding bit line BL. The source of each select transistor ST2 of the NAND string NS is connected to a source line SL. The source line SL is common to the sources of the multiple select transistors ST2 in the block BLK.

[0049] Data stored in multiple memory cell transistors MT in the same block BLK is erased collectively. Meanwhile, data is read and written collectively from multiple memory cell transistors MT connected to one word line WL and belonging to one string unit SU. Each memory cell can hold 3 bits of data consisting of an upper bit, a middle bit, and a lower bit.

[0050] That is, the semiconductor memory device 2 according to this embodiment employs the TLC method for writing data to the memory cell transistors MT, in which 3-bit data is stored in one memory cell transistor MT. Alternatively, the method for writing data to the memory cell transistors MT may employ the MLC method for storing 2-bit data in one memory cell transistor MT or the like. The number of bits of data stored in one memory cell transistor MT is not particularly limited.

[0051] In the following description, a set of 1-bit data stored in multiple memory cell transistors MT connected to one word line WL and belonging to one string unit SU is referred to as a "page." In Fig. 6, one of the sets of multiple memory cell transistors MT as described above is denoted by the symbol "MG."

[0052] In the present embodiment, when three bits of data are stored in one memory cell transistor MT, a set of memory cell transistors MT connected to a common word line WL in one string unit SU can store three pages of data. A page consisting of a set of lower bit data is also referred to as a "lower page" below, and data on the lower page is also referred to as "lower page data" below. Similarly, a page consisting of a set of middle bit data is also referred to as a "middle page" below, and data on the middle page is also referred to as "middle page data" below. A page consisting of a set of upper bit data is also referred to as an "upper page" below, and data on the upper page is also referred to as "upper page data" below.

[0053] 1.5 Cross-sectional structure of semiconductor memory device 7, the semiconductor memory device 2 has a structure in which a peripheral circuit PER and a memory cell array 21 are arranged in this order on a semiconductor substrate 40. The semiconductor memory device 2 of this embodiment has a so-called CUA (CMOS under array) structure in which the peripheral circuit PER is arranged below the memory cell array 21.

[0054] In the memory cell array 21, a plurality of NAND strings NS are formed on a conductive layer 520. The conductive layer 520 is also called a buried source line (BSL), and corresponds to the source line SL in FIG. A wiring layer 533 functioning as a select gate line SGS, a plurality of wiring layers 532 functioning as word lines WL, and a wiring layer 531 functioning as a select gate line SGD are stacked above the conductive layer 520. An insulating layer (not shown) is disposed between each of the stacked wiring layers 533, 532, and 531.

[0055] A plurality of memory holes 534 are formed in the memory cell array 21. The memory holes 534 are holes that vertically penetrate the wiring layers 533, 532, and 531 and the insulating layers (not shown) between them, and reach the conductive layer 520. Of the memory hole 534, each portion intersecting with each of the stacked wiring layers 533, 532, and 531 functions as a transistor. Of these multiple transistors, one at the portion intersecting with the wiring layer 531 functions as a selection transistor ST1. Of the multiple transistors, one at the portion intersecting with the wiring layer 532 functions as a memory cell transistor MT (MT0 to MT7). Of the multiple transistors, one at the portion intersecting with the wiring layer 533 functions as a selection transistor ST2.

[0056] A wiring layer 616 functioning as a bit line BL is formed above the memory hole 534. The upper end of the memory hole 534 is connected to the wiring layer 616 via a contact plug 539. A plurality of structures similar to the structure shown in Fig. 7 are arranged in the depth direction of the paper of Fig. 7. A set of a plurality of NAND strings NS aligned in a row in the depth direction of the paper of Fig. 7 forms one string unit SU.

[0057] The semiconductor substrate 40 and the conductive layer 520 (source line SL) are disposed apart from each other, and a part of the peripheral circuit PER is disposed between them. The peripheral circuit PER is a circuit provided for implementing operations such as writing, reading, and erasing data in the memory cell array 21. The sense amplifier 28, row decoder 27, and voltage generating circuit 26 shown in FIG. 5 are parts of the peripheral circuit PER.

[0058] The peripheral circuit PER includes a transistor TR formed on the upper surface of the semiconductor substrate 40, and a plurality of conductors 611-615. The conductors 611-615 are a wiring layer formed of a conductor such as a metal. The conductors 611-615 are formed so as to be distributed at a plurality of height positions, and are electrically connected to each other via contacts 620-623. The conductor 615 is electrically connected to a wiring layer 616 (bit line BL) via a contact 624.

[0059] 1.6 Threshold distribution of memory cell transistors 8 is a diagram showing a schematic diagram of the threshold distribution of the memory cell transistor MT, etc. The diagram in the middle of Fig. 8 shows the correspondence relationship between the threshold voltage of the memory cell transistor MT (horizontal axis) and the number of memory cell transistors MT (vertical axis).

[0060] When the TLC method is adopted as in this embodiment, the memory cell transistors MT form eight threshold distributions as shown in the middle of Fig. 8. These eight threshold distributions (write levels) are called the "ER" level, "A" level, "B" level, "C" level, "D" level, "E" level, "F" level, and "G" level, in order from the lowest threshold voltage. The table in the upper part of Fig. 8 shows an example of 3-bit data assigned to each of the threshold voltage levels.

[0061] In this manner, the threshold voltage of the memory cell transistor MT in this embodiment can take one of eight preset candidate levels, and data is assigned to each candidate level as described above. Between adjacent threshold distributions, a read voltage to be used in a read operation is set. The "read voltage" is a voltage applied to the word line WL connected to the memory cell transistor MT to be read during a read operation, i.e., a selected word line. In a read operation, data is determined based on the determination result of whether the threshold voltage of the memory cell transistor MT to be read is higher than the applied read voltage. For example, as shown in the lower diagram of FIG. 8, the read voltage VrA, which determines whether the threshold voltage of the memory cell transistor MT is included in the "ER" level or the "A" level, is set between the maximum threshold voltage at the "ER" level and the minimum threshold voltage at the "A" level. The other read voltages VrB, VrC, VrD, VrE, VrF, and VrG are also set in the same manner as the above read voltage VrA.

[0062] A read pass voltage VPASS_READ is set to a voltage higher than the maximum threshold voltage of the highest threshold distribution (for example, the “G” level). A memory cell transistor MT to which the read pass voltage VPASS_READ is applied is turned on regardless of the data stored therein.

[0063] When the data allocation described above is applied, in a read operation, one page data of the lower bits (lower page data) can be determined by the read result using read voltages VrA and VrE. One page data of the middle bits (middle page data) can be determined by the read result using read voltages VrB, VrD, and VrF. One page data of the upper bits (upper page data) can be determined by the read result using read voltages VrC and VrG.

[0064] 1.7 Read operation of semiconductor memory device Next, an example of a read operation of the semiconductor memory device 2 will be described. 9 shows the transition of the potential of each wiring during a read operation. In a read operation, a NAND string NS including a memory cell transistor MT to be read is selected. Alternatively, a string unit SU including a page to be read is selected.

[0065] First, the row decoder 27 selects one of the blocks BLK as a target for a read operation, and further selects one of the string units SU. Specifically, for example, 5V is applied from the voltage generating circuit 26 via the row decoder 27 to the select gate line SGD (selected select gate line SGDsel) in the selected string unit SU, the select gate line SGD (unselected select gate line SGDusel) of the unselected string unit SU in the selected block BLK, and the select gate line SGS. As a result, the select transistor ST1 and the select transistor ST2 included in the selected block BLK are turned on. In addition, for example, a read pass voltage VPASS_READ is applied from the voltage generating circuit 26 via the row decoder 27 to the word line WL (selected word line WLsel) to be read and other selected word lines (unselected word lines WLusel). The read pass voltage VPASS_READ is a voltage that can turn on the memory cell transistor MT regardless of the threshold voltage of the memory cell transistor MT, and does not change the threshold voltage. As a result, a current flows through all the NAND strings NS included in the selected block BLK, regardless of whether they are selected string units SU or unselected string units SU.

[0066] Next, a read voltage Vr such as VrA is applied to the word line WL (selected word line WLsel) connected to the memory cell transistor MT that is the target of the read operation from the voltage generation circuit 26 via the row decoder 27. A read pass voltage VPASS_READ is applied to the other word lines (unselected word lines WLusel).

[0067] Furthermore, while maintaining the voltage applied to the selected select gate line SGDsel and the select gate line SGS, the voltage generation circuit 26 applies, for example, a voltage Vss to the unselected select gate line SGDusel via the row decoder 27. As a result, the select transistor ST1 included in the selected string unit SU maintains the on state, but the select transistor ST1 included in the unselected string units SU is turned off. Note that the select transistor ST2 included in the selected block BLK is turned on regardless of whether it is the selected string unit SU or an unselected string unit SU.

[0068] As a result, the NAND string NS included in the unselected string unit SU does not form a current path because at least the selection transistor ST1 is turned off. On the other hand, the NAND string NS included in the selected string unit SU forms or does not form a current path depending on the relationship between the read voltage Vr applied to the selected word line WLsel and the threshold voltage of the memory cell transistor MT.

[0069] The sense amplifier 28 applies a voltage to the bit line BL connected to the selected NAND string NS. In this state, the sense amplifier 28 reads data based on the value of the current flowing through the bit line BL. Specifically, it determines whether the threshold voltage of the memory cell transistor MT that is the target of the read operation is higher than the read voltage Vr applied to the memory cell transistor MT. Note that data reading may be performed based on the change in potential of the bit line BL over time, rather than based on the value of the current flowing through the bit line BL. In the latter case, the bit line BL is precharged to a predetermined potential in advance.

[0070] 1.8 Transmission and reception of signals between the memory controller 1 and the semiconductor memory device 2 Next, an example of signals transmitted and received between the memory controller 1 and the semiconductor memory device 2 when reading data from the semiconductor memory device 2 will be described.

[0071] 10, during a read operation, signals consisting of "05h", multiple "ADD", and "E0h" are input in sequence as data signal DQ<7:0> from the memory controller 1 to the semiconductor memory device 2. "05h" is a command for executing a read operation of data from the memory cell array 21. "ADD" is a signal for specifying the address from which data is to be read. "E0h" is a command for starting the read operation.

[0072] In FIG. 10, the timing when "E0h" is input to the semiconductor memory device 2 is shown as time t0. At time t1, when a predetermined period has elapsed from time t0, the memory controller 1 starts toggling the read enable signal / RE. As described above, the read enable signal / RE is a signal for the memory controller 1 to read data from the semiconductor memory device 2, and is input to the input / output pad group 30 of the semiconductor memory device 2. After time t1, the read enable signal / RE is alternately switched (toggled) between the "H" level and the "L" level. Each of the read enable signals / RE switched in this way is used as a "read signal" for reading data.

[0073] The semiconductor memory device 2 outputs data as the data signal DQ<7:0> and switches the data strobe signal DQS between the "H" level and the "L" level every time the read enable signal / RE is switched (i.e., every time each read signal is input). In FIG. 10, each piece of data output as the data signal DQ<7:0> is indicated as "D". Also, the timing at which the first data is output and the data strobe signal DQS is switched is indicated as time t2. The correspondence between the switching of the read enable signal / RE input from the memory controller 1 and the switching of the data strobe signal DQS output from the semiconductor memory device 2 is indicated by a dotted arrow in FIG. 10.

[0074] The output of read data from the semiconductor memory device 2 is performed by dividing one piece of data into even data consisting of even bits and odd data consisting of odd bits, and outputting them alternately. Each piece of data indicated as "D" in Fig. 10 is output as either even data or odd data.

[0075] When the memory interface 15 of the memory controller 1 receives the data signal DQ<7:0> transmitted from the semiconductor memory device 2, the memory interface 15 acquires data from the data signal DQ<7:0>. Specifically, the memory interface 15 acquires data from the data signal DQ<7:0>, which is one of the data signals DQ<7:0>. <0> For example, when a signal that transitions as shown in FIG. 11 is received from the semiconductor memory device 2, the data signal DQ <0> The memory interface 15 compares the data signal DQS with the determination voltage Vth. The detection timings t20, t21, t22, . . . are set as the rising and falling timings of a signal that is shifted in phase by 90 degrees from the data strobe signal DQS. <0> If the voltage Vth is equal to or lower than the threshold voltage Vth, the data is determined to be “0”, and the data signal DQ <0> is greater than the determination voltage Vth, the data is determined to be "1". In an ideal state, data "0" corresponds to a voltage of the "L" level, and data "1" corresponds to a voltage of the "H" level. Note that the correspondence between logic data and voltage levels is not limited to this, and a different definition may be used.

[0076] In addition, the data signal DQ <0> When the "H" level of is 1.2 V and the "L" level of is 0 V, the determination voltage Vth is set to, for example, 0.6 V. In this embodiment, 0.6 V corresponds to the reference voltage of the determination voltage Vth. On the other hand, in the memory system 3 of this embodiment, the memory controller (controller chip) 1 and the semiconductor memory device (memory chip) 2 are connected via a bonding wire B as shown in FIG. 3 and FIG. 4. In this case, parasitic capacitance and parasitic resistance exist in the signal path between the memory controller 1 and the semiconductor memory device 2. Therefore, as shown in FIG. 11, the data signal DQ <0> The rising and falling edges of the data signal DQ are not ideally vertical, but have a slight slope. <0> It takes a short time for the signal to transition between the "L" and "H" levels.

[0077] Incidentally, in such a memory system 3, the data rate tends to be set high (the signal period is short) in order to increase the speed of the operation. When the data rate is set high, the data signal DQ <0> Deterioration of the waveform may cause errors in reading data. FIG. 12 shows the data signal DQ when the data rate is increased (the signal period is shortened). <0> 12. In FIG. 12, the time t30 to t41 is an example of the waveform of the data signal DQ <0> 12 shows the timing at which the signal indicating each data changes, that is, the timing of the boundary between "D" and "D" shown in Fig. 10. Fig. 12 also shows whether each data is "0" or "1".

[0078] As shown in FIG. 12, during the period from time t30 to time t33, the data signal DQ <0> When the data included in the data signal DQ <0> The data signal DQ then remains at 0V. <0> When the data in the data signal DQ changes in the order of "1" and "0", <0> After rising to a predetermined voltage V1 at time t34, it falls to 0 V at time t35. The voltage V1 is a voltage lower than 1.2 V which is the actual "H" level voltage. This is because when the data rate becomes higher (when the signal period becomes shorter), the data signal DQ <0> Before the data signal DQ <0> This is because the voltage changes toward the “L” level.

[0079] Subsequently, during the period from time t35 to time t39, the data signal DQ <0> When the data included in the data signal DQ <0> After rising to 1.2V, the data signal DQ <0> When the data in the data signal DQ changes in the order of "0" and "1", <0> At time t40, the voltage V2 drops to a predetermined voltage V2, and then at time t41, the voltage V2 rises to 1.2 V. The voltage V2 is a voltage higher than 0 V, which is the actual "L" level voltage.

[0080] Such a data signal DQ <0> For example, during the period from time t32 to time t34 and the period from time t39 to time t41, the data signal DQ <0> When the data in the data signal DQ changes from "0" to "1", <0> When comparing the waveforms of the respective periods, the data signal DQ <0> The timing at which the data signal DQ reaches the determination voltage Vth occurs during the period from time t40 to time t41. <0> This is because the timing at which the data signal DQ reaches the determination voltage Vth is slightly delayed from the timing at which the data signal DQ reaches the determination voltage Vth during the period from time t33 to time t34. <0> The waveform of the data signal DQ starts rising from 0V, while the data signal DQ is rising from time t40 to time t41. <0> This is because the waveform of the data signal DQ starts to rise from V1. <0> For example, in the example shown in FIG. 12, during the period from time t33 to time t34, the data signal DQ <0> Since the timing at which the data signal DQ exceeds the determination voltage Vth is slightly delayed, the memory controller 1 is more likely to acquire data of “0” even though the actual data is “1”, and the likelihood decreases. <0> reaches the determination voltage Vth with a slight delay, the memory controller 1 is more likely to acquire data of "1" even though the actual data is "0", and the likelihood decreases.

[0081] In addition, the above-mentioned data signal DQ <0> In addition to the distortion of the signal waveform, there are other factors that can cause errors in reading data, such as distortion of the data strobe signal DQS and a deviation in the determination voltage Vth. As shown by the dashed line in Fig. 13A, the duty value of the data strobe signal DQS is usually set to 50%, but there is a possibility that the duty value may deviate from 50% due to some factor. For example, if the duty value becomes smaller than 50% as shown in Fig. 13A, the falling edge timing of the data strobe signal DQS will be advanced from time t51 to time t50. As described above, the data signal DQ <0> The timing of detecting data from the data strobe signal DQS is set based on, for example, the timing of the falling edge of the data strobe signal DQS, so if the timing of the falling edge of the data strobe signal DQS advances, the timing of detecting data also advances. In this case, for example, in a situation where data changes from "1" to "0", the data signal DQ <0> If data detection is performed before the data becomes lower than the judgment voltage Vth, there is a possibility that the memory controller 1 may obtain data of “1” even though the actual data is “0”, which reduces the likelihood.

[0082] On the other hand, as shown in FIG. 13B, the judgment voltage Vth is usually set to 0.6 V, but the judgment voltage Vth may deviate due to changes in the power supply voltage, temperature, etc. For example, as shown in FIG. 13B, when the judgment voltage Vth changes to a voltage Vth10 higher than 0.6 V, the data signal DQ <0> It is highly likely that the voltage of the data signal DQ is determined to be equal to or lower than the threshold voltage Vth. <0> is more likely to be determined to be an “L” level signal. As a result, the memory controller 1 is more likely to acquire data of “0” even though the actual data is “1”, and the likelihood decreases.

[0083] As described above, when detecting data from the data signal DQ<7:0>, errors may occur due to influences such as distortion of the waveform of the data signal DQ<7:0>, deviation in the duty value of the data strobe signal DQS, and deviation in the determination voltage Vth, and the likelihood decreases. In consideration of this, in the memory system 3 of this embodiment, such data errors are corrected by the error correction process by the ECC circuit 14, so that the data loss can be compensated for.

[0084] The configuration for correcting data errors in the memory system 3 of this embodiment will be specifically described below. 1.9 Memory system circuit configuration Fig. 14 shows a circuit configuration of the memory system 3. Note that Fig. 14 shows only the configuration related to reading data from the semiconductor memory device 2, and for example, the configuration related to writing data to the semiconductor memory device 2 is omitted.

[0085] 14, the memory interface 15 of the memory controller 1 includes an interface circuit 70 and a PHY circuit 80. In this embodiment, the memory interface 15 corresponds to an interface unit. The interface circuit 70 includes a driver circuit 71 and receiver circuits 72, and 730-737.

[0086] The driver circuit 71 converts a clock signal generated by a PLL (Phase Locked Loop) circuit (phase-locked circuit) 81 of the PHY circuit 80 into a read enable signal / RE, and transmits the converted read enable signal / RE to the semiconductor memory device 2.

[0087] The receiver circuit 72 receives the data strobe signal DQS transmitted from the semiconductor memory device 2 and outputs the received data strobe signal DQS to the PHY circuit 80 . The receiver circuits 730 to 737 receive the data signal DQ<7:0> transmitted from the semiconductor memory device 2. Note that the receiver circuits 731 to 736 are omitted from FIG. 14. The receiver circuits 730 to 737 are provided in a number corresponding to the number of bits of data included in the data signal DQ<7:0>. In this embodiment, since the data signal DQ<7:0> includes 8-bit parallel data, eight receiver circuits 730 to 737 are provided in the interface circuit 70. Each of the receiver circuits 730 to 737 compares the data signal DQ<7:0> transmitted from the semiconductor memory device 2 with the determination voltage Vth generated by the voltage generation circuit 82 of the PHY circuit 80, and obtains data of "0" or "1" from the data signal DQ<7:0>. For example, the receiver circuit 730 receives the data signal DQ<7:0>, which is one of the data signals DQ<7:0>. <0> By comparing the data signal DQ with the judgment voltage Vth, <0> Each of the receiver circuits 730 to 737 outputs the acquired data to the PHY circuit 80.

[0088] The PHY circuit 80 includes a PLL circuit 81, a voltage generating circuit 82, sampler circuits 830 to 837, a read FIFO (First In First Out) circuit 84, a duty detection circuit 85, data counter circuits 860 to 867, and a voltage detection circuit 87.

[0089] The PLL circuit 81 intermittently outputs a clock signal having a predetermined frequency to the driver circuit 71 and the read FIFO circuit 84 . A plurality of sampler circuits 830-837 are provided corresponding to the plurality of receiver circuits 730-737. Note that the sampler circuits 831-836 are omitted from FIG. 14. The sampler circuits 830-837 receive the data output from the receiver circuits 730-737, respectively, and also receive the data strobe signal DQS received by the receiver circuit 72. The sampler circuits 830-837 sample the data output from the receiver circuits 730-737, respectively, at a timing based on the data strobe signal DQS, thereby outputting data D0-D7 corresponding to the data signal DQ<7:0>. For example, the sampler circuit 830 samples the data output from the receiver circuit 730 based on the timing of the rising and falling edges of a signal that is shifted in phase by 90 degrees from the data strobe signal DQS, thereby outputting the data signal DQ<7:0>. <0> As the data D0 corresponding to this, data "0" or "1" is output to the read FIFO circuit 84. The other sampler circuits 831-837 operate in a similar manner to output the sampled data D1-D7 to the read FIFO circuit 84.

[0090] The read FIFO circuit 84 is a buffer circuit. The read FIFO circuit 84 stores the data D0 to D7 output from each of the sampler circuits 830 to 837 in a FIFO format. The read FIFO circuit 84 transmits the data D0 to D7 to the ECC circuit 14 in the order in which they were input. As a result, the data read from the semiconductor memory device 2 is input to the ECC circuit 14.

[0091] The duty detection circuit 85 detects the duty value of the data strobe signal DQS output from the receiver circuit 72, and transmits information about the detected duty value to the ECC circuit . The data counter circuits 860 to 867 are provided to correspond to the plurality of sampler circuits 830 to 837, respectively. Note that in FIG. 14, the data counter circuits 861 to 866 are omitted from illustration. The data counter circuits 860 to 867 monitor the values ​​of the data D0 to D7 output from the sampler circuits 830 to 837, respectively, and when the same value is consecutive, transmit information on the number of consecutive values ​​to the ECC circuit 14. For example, when the sampler circuit 830 outputs values ​​of a pattern such as "1", "0", "0", and "0" as the value of the data D0, the data counter circuit 860 transmits information such as "1", "1", "2", and "3" as information on the number of consecutive values ​​corresponding to those values ​​to the ECC circuit 14. Also, when the sampler circuit 830 outputs values ​​of a pattern such as "0", "1", "1", "1", and "1" as the data D0, the data counter circuit 860 transmits information "3" as information on the number of consecutive values ​​to the ECC circuit 14. When data of a pattern such as "1", "0", "1", "0" is output as data D0 from the sampler circuit 830, the data counter circuit 860 transmits information of "1", "1", "1", "1" as information on the continuity number to the ECC circuit 14. The other data counter circuits 861 to 867 operate in a similar manner.

[0092] The voltage detection circuit 87 detects the voltage value of the determination voltage Vth generated by the voltage generation circuit 82, and transmits information on the detected voltage value of the determination voltage Vth to the ECC circuit . In this embodiment, the duty value of the data strobe signal DQS, the number of consecutive data D0 to D7, and the voltage value of the determination voltage Vth correspond to parameters that affect the acquisition of data from the data signal DQ<7:0>. The duty detection circuit 85, the data counter circuits 860 to 867, and the voltage detection circuit 87 correspond to an acquisition unit 90 that acquires these parameters.

[0093] The ECC circuit 14 performs error detection and correction on the data received from the semiconductor memory device 2 using the ECC. When the semiconductor memory device 2 employs the TLC method, the distribution of the threshold voltage of the memory cell transistor MT may overlap the distribution A1 of the threshold voltage that is "1" and the distribution A0 of the threshold voltage that is "0" as shown in FIG. 15. In such a case, when the center of each distribution A1, A0 is set as the read voltage Vr as shown in FIG. 15, if the data read from the memory cell transistor MT based on the read voltage Vr is "1", the probability that the data is actually "1" is, for example, 90%, and the probability that the data is actually "0" is 10%. Similarly, if the data read from the memory cell transistor MT based on the read voltage Vr is "0", the probability that the data is actually "0" is, for example, 90%, and the probability that the data is actually "1" is 10%. In this way, when the distribution of the threshold voltage of the memory cell transistor MT has the distribution shown in FIG. 15, the data read from the semiconductor memory device 2 may contain an error.

[0094] The ECC circuit 14 detects and corrects errors in the read data by performing an error detection process and an error correction process on the data read from the semiconductor memory device 2. The ECC circuit 14 performs an error detection process and an error correction process based on soft decision using likelihood information PL indicating the likelihood of "0" or "1" as the error detection process and the error correction process. For example, an LDPC (Low-Density Parity-Check) code is used as the error correction code. Information expressing the likelihood of "0" or "1" as a percentage value is used as the likelihood information PL. For example, when the likelihood information PL is 100%, it means that the data is definitely "0" or "1". When the likelihood information PL is 90%, it means that the probability that the data is "0" is 90% and the probability that the data is "1" is 10%, or the probability that the data is "1" is 90% and the probability that the data is "0" is 10%. Note that the likelihood information PL is not limited to a percentage value, and for example, a log likelihood ratio (LLR) or the like may be used.

[0095] As shown in FIG. 14, the ECC circuit 14 includes a likelihood information holding unit 140, a likelihood information correction unit 141, a decoding unit 142, and a FTL (Flash Translation Layer) 143. The decoding unit 142 decodes data read from the semiconductor memory device 2 to restore the codeword written to the semiconductor memory device 2. At that time, the decoding unit 142 performs error correction on the read data based on a soft decision algorithm of the LDPC code using the likelihood information PL. The data decoded by the decoding unit 142 is transmitted to the host via the FTL 143 and the host interface 13. The FTL 143 is configured to perform data management and block management of the semiconductor memory device 2. In this embodiment, the decoding unit 142 corresponds to an error correction unit that performs error correction processing on the data.

[0096] The likelihood information holding unit 140 stores basic likelihood information PLb, which is basic information of the likelihood information PL used in the decoding unit 142. For example, when the memory cell transistor MT of the semiconductor memory device 2 has a threshold voltage distribution as shown in FIG. 15, the basic likelihood information PLb is preset to a value of 90% and stored in the likelihood information holding unit 140. The basic likelihood information PLb is stored in, for example, the semiconductor memory device 2. The processor 12 of the memory controller 1 stores the basic likelihood information PLb in the semiconductor memory device 2, and caches the basic likelihood information PLb stored in the semiconductor memory device 2 in the RAM 11 for use. In this case, the likelihood information holding unit 140 is realized by the processor 12 and the RAM 11.

[0097] The likelihood information correction unit 141 corrects the basic likelihood information PLb based on the information transmitted from the duty detection circuit 85, the data counter circuits 860 to 867, and the voltage detection circuit 87, and transmits the corrected likelihood information PL to the decoding unit 142. The decoding unit 142 performs error correction processing using the likelihood information PL corrected by the likelihood information correction unit 141. The likelihood information correction unit 141 may be realized by a hardware circuit, or may be realized by the processor 12 executing firmware stored in the semiconductor storage device 2.

[0098] 16 shows an example of the correction process of the basic likelihood information PLb executed by the likelihood information correction unit 141. Note that, in the following, an example will be described in which the likelihood information PL of the data D0 is corrected. The likelihood information correction unit 141 calculates the first correction value ΔPL1 based on the information on the number of consecutive data transmitted from the data counter circuit 860. For example, the likelihood information correction unit 141 sets the first correction value ΔPL1 to a value obtained by adding a negative sign to the information on the number of consecutive data transmitted from the data counter circuit 860. For example, it is assumed that data d1 to d9 as shown in FIG. 16 are sequentially read out from the semiconductor memory device 2 as data D0. At this time, when the data d1 to d4 are consecutive data of "0", the data counter circuit 860 outputs information of "3" as information on the number of consecutive data. Therefore, the likelihood information correction unit 141 sets "-3" obtained by adding a negative sign to the information on the number of consecutive data output from the data counter circuit 860 as the first correction value ΔPL1. In such a case where data of "0" are lined up, as described with reference to FIG. 12(A), for example, data of "0" immediately before switching to data of "1" may be erroneously acquired as data of "0" even though it is actually data of "1". That is, since the reliability of the data decreases, the first correction value ΔPL1 is set to a negative value in order to correct the basic likelihood information PLb by decreasing it. Also, the probability of erroneously acquiring data increases as the number of consecutive data items increases. Therefore, the likelihood information correction unit 141 decreases the first correction value ΔPL1 more as the number of consecutive data items increases. Note that the likelihood information correction unit 141 may set the lower limit of the first correction value ΔPL1 to, for example, "-3".

[0099] The likelihood information correction unit 141 calculates the second correction value ΔPL2 based on the duty value of the data strobe signal DQS detected by the duty detection circuit 85. For example, the likelihood information correction unit 141 determines whether the duty value detected by the duty detection circuit 85 is 50%. If the duty value detected by the duty detection circuit 85 is not 50%, the likelihood information correction unit 141 reduces the likelihood information corresponding to the data at the timing of the shifted rising edge and / or falling edge. For example, assuming that the timing of the rising edge of the data strobe signal DQS does not change and the timing of the falling edge changes, the likelihood information correction unit 141 reduces the likelihood information corresponding to the even-numbered data d2, d4, d6, d8 among the data d1 to d9 while maintaining the likelihood information corresponding to the odd-numbered data d1, d3, d5, d7, d9. For example, as shown in FIG. 16, the likelihood information corrector 141 sets the second correction values ​​ΔPL2 corresponding to the even-numbered data d2, d4, d6, and d8 to "-1."

[0100] The likelihood information correction unit 141 may change the adjustment method of the second correction value ΔPL2 according to the timing of the rising edge and / or the falling edge. For example, assuming that the timing of the falling edge of the data strobe signal DQS does not change and the timing of the rising edge changes, the likelihood information correction unit 141 may maintain the likelihood information corresponding to the even-numbered data d2, d4, d6, d8 while decreasing the likelihood information corresponding to the odd-numbered data d1, d3, d5, d7, d9 among the data d1 to d9. In addition, when the timing of the rising edge and the timing of the falling edge of the data strobe signal DQS change, the likelihood information corresponding to the odd-numbered data d1, d3, d5, d7, d9 and the likelihood information corresponding to the even-numbered data d2, d4, d6, d8 may be decreased according to the degree of the change. In this case, the amount of decrease in likelihood information corresponding to odd-numbered data d1, d3, d5, d7, and d9 may be the same as or different from the amount of decrease in likelihood information corresponding to even-numbered data d2, d4, d6, and d8.

[0101] The likelihood information correction unit 141 calculates the third correction value ΔPL3 based on the judgment voltage Vth detected by the voltage detection circuit 87. For example, the likelihood information correction unit 141 determines whether or not the judgment voltage Vth deviates from a reference voltage (0.6 V). If the judgment voltage Vth deviates from the reference voltage, the likelihood information correction unit 141 sets the third correction value ΔPL3 based on the amount of deviation.

[0102] Specifically, when the judgment voltage Vth satisfies "Vth>0.6V", the likelihood information correction unit 141 sets the third correction value ΔPL3 corresponding to the data of "0" to "-1" so that the likelihood information for the data of "0" is lowered. This is because, as described with reference to FIG. 13B, when the judgment voltage Vth is higher, the possibility of acquiring data of "0" increases even though the original data is "1". On the other hand, the likelihood information correction unit 141 sets the third correction value ΔPL3 corresponding to the data of "1" to "+1" so that the likelihood information for the data of "1" is higher. This is because, when data of "1" is acquired even though the situation is one in which the possibility of acquiring data of "0" is high, the likelihood of the data is higher than usual.

[0103] When the judgment voltage Vth satisfies "Vth>0.6V", the likelihood information correction unit 141 may set the third correction value ΔPL3 corresponding to the data of "0" to a negative value, and increase the absolute value of the negative value as the deviation (Vth-0.6) between them increases. When the judgment voltage Vth satisfies "Vth>0.6V", the likelihood information correction unit 141 may set the third correction value ΔPL3 corresponding to the data of "1" to a positive value, and increase the absolute value of the positive value as the deviation (Vth-0.6) between them increases.

[0104] Furthermore, the likelihood information correction unit 141 may further determine whether the judgment voltage Vth satisfies "Vth<0.6V". In this case, the likelihood information correction unit 141 sets the third correction value ΔPL3 corresponding to data of "0" to a positive value, and increases the absolute value of the positive value as the deviation therebetween (0.6-Vth) increases. Also, the likelihood information correction unit 141 sets the third correction value ΔPL3 corresponding to data of "1" to a negative value, and increases the absolute value of the negative value as the deviation therebetween (0.6-Vth) increases.

[0105] After calculating the correction values ​​ΔPL1-ΔPL3 as described above, the likelihood information correction unit 141 adds the correction values ​​ΔPL1-ΔPL3 to the basic likelihood information PLb to calculate corrected likelihood information PL corresponding to each of the data d1-d9. For example, for data d4, the likelihood information correction unit 141 calculates "PLb+ΔPL1+ΔPL1+ΔPL3" to calculate "85" as the likelihood information PL corresponding to the data d4, and inputs the calculated likelihood information PL to the decoding unit 142.

[0106] 1.10 Functions and Effects of the Memory System of the Present Embodiment As shown in FIG. 14, the memory controller 1 of the present embodiment includes a memory interface 15, a likelihood information holding unit 140, an acquisition unit 90, a likelihood information correction unit 141, and a decoding unit 142. The receiver circuits 730-737 of the memory interface 15 receive the data signal DQ<7:0> from the semiconductor memory device 2 during a data read operation from the semiconductor memory device 2, and acquire the data D0-D7 from the data signal DQ<7:0>. The likelihood information holding unit 140 holds the likelihood information PL of the data D0-D7. The acquisition unit 90 acquires parameters that affect the acquisition of data from the data signal DQ<7:0>. The likelihood information correction unit 141 corrects the likelihood information PL based on the parameters acquired by the acquisition unit 90. The decoding unit 142 performs an error correction process on the data read from the semiconductor memory device 2 based on the likelihood information PL corrected by the likelihood information correction unit 141.

[0107] According to this configuration, data loss occurring when the memory controller 1 acquires data from the data signal DQ<7:0> can be corrected together with errors originally contained in the data stored in the semiconductor memory device 2 by error correction processing. Therefore, it is possible to improve the correction function of errors contained in the data. In addition, as a method for suppressing data loss occurring when acquiring data from the data signal DQ<7:0>, for example, a method of separately providing a correction circuit for correcting distortion of the waveform of the data signal DQ<7:0> as shown in FIG. 12 can be considered. However, according to the above configuration, data loss can be corrected without providing such a correction circuit, so that the structure can be simplified. Furthermore, since the likelihood information PL is only corrected, the calculation load of the decoding unit 142 does not increase. Moreover, it is possible to expect an improvement in the data restoration ability and restoration efficiency of the decoding unit 142 by increasing the accuracy of the likelihood information PL.

[0108] The data counter circuits 860-867 of the acquiring unit 90 acquire information regarding the continuity of data acquired from the data signal DQ<7:0> by the memory interface 15 as a parameter that affects the acquisition of data from the data signal DQ<7:0>. The likelihood information correcting unit 141 corrects the likelihood information PL when the acquired data is continuous with the same value. Specifically, the likelihood information correcting unit 141 changes the correction amount of the likelihood information PL based on the number of consecutive data with the same value. For example, the likelihood information correcting unit 141 corrects the likelihood information PL to a greater extent as the number of consecutive data with the same value increases.

[0109] This configuration makes it possible to more appropriately correct data errors that occur due to distortion of the data signal DQ<7:0>. The duty detection circuit 85 of the acquiring unit 90 detects the duty value of the data strobe signal DQS as a parameter that affects the acquisition of data from the data signal DQ<7:0>. The likelihood information correcting unit 141 corrects the likelihood information PL based on the duty value of the data strobe signal DQS.

[0110] According to this configuration, it is possible to more appropriately correct data errors that occur due to changes in the duty value of the data strobe signal DQS. The voltage detection circuit 87 of the acquiring unit 90 acquires information on the voltage value of the judgment voltage Vth as a parameter that affects the acquisition of data from the data signal DQ<7:0>. The likelihood information correcting unit 141 corrects the likelihood information PL based on the deviation of the voltage value of the judgment voltage Vth acquired by the acquiring unit 90 from the reference value of the judgment voltage Vth (e.g., 0.6 V).

[0111] According to this configuration, it is possible to more appropriately correct data errors that occur due to fluctuations in the determination voltage Vth. 2. Other embodiments The present disclosure is not limited to the above specific examples.

[0112] For example, the duty detection circuit 85 may detect the duty value of the data signal DQ<7:0> instead of the data strobe signal DQS. In this case, the likelihood information correction unit 141 corrects the likelihood information PL based on the duty value of the data signal DQ<7:0>. When the “H” level voltage of the data signal DQ<7:0> deviates from 1.2V or when the “L” level voltage of the data signal DQ<7:0> deviates from 0V, erroneous data may be acquired from the data signal DQ<7:0>. That is, parameters that affect the acquisition of data from the data signal DQ<7:0> may include deviations in the “H” level voltage and deviations in the “L” level voltage. Therefore, the likelihood information correction unit 141 may correct the likelihood information PL based on deviations in the “H” level voltage value from a reference value and deviations in the “L” level voltage value from a reference value. In short, it is sufficient for the likelihood information correction unit 141 to correct the likelihood information PL based on any parameter that affects the acquisition of data from the data signal DQ<7:0>.

[0113] The semiconductor memory device 2 is not limited to the structure shown in FIG. 7, and may have a CBA (CMOS directly bonded to array) structure as shown in FIG. 17. In the semiconductor memory device 2 shown in FIG. 17, a memory section 180 in which a memory cell array 110 is provided and a control circuit section 190 in which a peripheral circuit PER is provided are manufactured separately. This semiconductor memory device 2 is constructed by bonding the memory section 180 and the control circuit section 190, which are manufactured separately, to each other at a bonding surface B1. A bonding pad 800 of the control circuit section 190 and a bonding pad 801 of the memory section 180, which are provided on the bonding surface B1, are bonded to each other. The memory cell array 110 and the peripheral circuit PER are electrically connected to each other through the bonding pads 800, 801 and vias 810, 811.

[0114] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0115] 1: memory controller, 2: semiconductor memory device, 3: memory system, 15: memory interface (interface section), 85: duty detection circuit (acquisition section), 87: voltage detection circuit (acquisition section), 90: acquisition section, 140: likelihood information holding section, 141: likelihood information correction section, 142: decoding section (error correction section), 860-867: data counter circuit (acquisition section).

Claims

1. an interface unit that receives a data signal, which is a signal for the data, from the semiconductor memory device during a data read operation from the semiconductor memory device and acquires data from the data signal; A storage unit for storing likelihood information of the data; an acquisition unit for acquiring parameters influencing acquisition of the data from the data signal; a correction unit that corrects the likelihood information based on the parameters acquired by the acquisition unit; an error correction unit that performs error correction processing on the data based on the likelihood information corrected by the correction unit; Memory controller.

2. the acquisition unit acquires, as the parameter, information regarding continuity of data acquired from the data signal by the interface unit; The correction unit corrects the likelihood information when the data has the same value continuously. The memory controller of claim 1 .

3. The correction unit changes a correction amount of the likelihood information based on the number of consecutive data pieces with the same value when the data pieces have the same value. The memory controller of claim 2 .

4. the interface unit receives a data strobe signal together with the data signal, and acquires the data from the data signal based on the timing of at least one of a rising edge and a falling edge of the data strobe signal; the acquiring unit acquires, as the parameter, information on a duty value of the data strobe signal; The correction unit corrects the likelihood information based on a duty value of the data strobe signal. The memory controller of claim 1 .

5. the acquiring unit acquires, as the parameter, information on a duty value of the data signal; The correction unit corrects the likelihood information based on a duty value of the data signal. The memory controller of claim 1 .

6. the interface unit acquires data from the data signal by comparing the data signal with a determination voltage; the acquisition unit acquires, as the parameter, information on a voltage value of the determination voltage; The correction unit corrects the likelihood information based on a deviation of the voltage value of the determination voltage acquired by the acquisition unit from a reference value of the determination voltage. The memory controller of claim 1 .

7. The likelihood information is a log-likelihood ratio. The memory controller of claim 1 .

8. The semiconductor memory device is a NAND type flash memory. The memory controller of claim 1 .

9. an interface unit that receives a data signal, which is a signal for the data, from the semiconductor memory device during a data read operation from the semiconductor memory device and acquires data from the data signal; A storage unit for storing likelihood information of the data; an acquisition unit for acquiring parameters influencing acquisition of the data from the data signal; a correction unit that corrects the likelihood information based on the parameters acquired by the acquisition unit; an error correction unit that performs error correction processing on the data based on the likelihood information corrected by the correction unit; Memory system.

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