Method for forming an epitaxial wafer

Abstract

A method for preparing an epitaxial wafer is disclosed, the method comprising controlling (i) the growth rate v and / or (ii) the axial temperature gradient G during growth of an ingot segment such that v / G is less than a critical v / G. The epitaxial layer is deposited on a substrate cut from a silicon ingot.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. Provisional Patent Application No. 63 / 184,424, filed May 5, 2021, the entirety of which is incorporated herein by reference.

[0002] The field of the disclosure relates to methods for forming epitaxial wafers, and in particular to methods that include forming epitaxial wafers having a relatively thick denude zone in the substrate below the interface between the epitaxial layer and the substrate. [Background technology]

[0003] An epitaxial wafer comprises a single crystal silicon substrate having an epitaxial layer deposited on the surface of the substrate. Epitaxial wafers may be used to form electronic devices suitable for microelectronics (integrated circuits or power applications) or photovoltaic applications.

[0004] Epitaxial wafers can have surface defects that degrade performance. Heavily doped epitaxial wafers (e.g., p / p+) offer good protection against latch-up, good slip resistance, and good gettering properties due to enhanced metal solubility in highly doped silicon and internal gettering promoted by the high concentration of boron. Heavily doped boron substrates are prone to the formation of dense oxygen precipitates (BMDs). Oxygen precipitates exacerbate dislocations and slip, such as in power semiconductor devices that use deep trenches for isolation.

[0005] A need exists for a highly doped epitaxial wafer that forms a relatively thick denude zone beneath the epitaxial layer during subsequent high temperature annealing.

[0006] This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure that are described and / or claimed below. This discussion is believed to be helpful in providing the reader with background information to better understand the various aspects of the present disclosure. As such, it should be understood that these statements are to be read in this light, and not as admissions of prior art. Summary of the Invention

[0007] One aspect of the present disclosure relates to a method for forming an epitaxial wafer comprising a substrate and an epitaxial layer disposed on the substrate. An initial charge of polycrystalline silicon is added to a crucible. The crucible containing the initial charge of polycrystalline silicon is heated to form a silicon melt in the crucible. Boron is added to the crucible to produce a doped silicon melt. A silicon seed crystal is contacted with the doped silicon melt. The silicon seed crystal is withdrawn to grow a single crystal silicon ingot. The ingot has a constant diameter portion. The constant diameter portion of the ingot is at least about 2.8×10 18 atoms / cm 3 During growth of a constant diameter segment of the ingot, the growth rate, v, and / or the axial temperature gradient, G, are controlled such that v / G is less than a critical v / G. A plurality of silicon substrates are cut from the single crystal silicon ingot. A surface of one of the plurality of silicon substrates is contacted with a silicon-containing gas. The silicon-containing gas decomposes to form an epitaxial silicon layer on the silicon substrate.

[0008] Various refinements exist in the features described in relation to the above-mentioned aspects of the disclosure. Likewise, further features may be incorporated into the above-mentioned aspects of the disclosure. These refinements and additional features may exist individually or in any combination. For example, various features described below in relation to any of the illustrated embodiments of the disclosure may be incorporated into any of the above-mentioned aspects of the disclosure, alone or in any combination. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a cross-sectional view of an ingot pulling apparatus prior to growth of a silicon ingot. [Diagram 2] FIG. 2 is a cross-sectional view of the ingot pulling apparatus shown in FIG. 1 during growth of a silicon ingot. [Diagram 3] FIG. 3 is a schematic cross-sectional view of a single crystal silicon ingot showing the axial trends of vacancy-rich and interstitial-rich regions at three boron doping levels (increasing from (a) to (c)). [Figure 4] FIG. 4 is a cross-sectional view of a silicon substrate cut from a silicon ingot. [Diagram 5] FIG. 5 is a cross-sectional view of a silicon substrate having a denude zone formed on its surface. [Figure 6] FIG. 6 is a cross-sectional view of an epitaxial silicon wafer having a denuded zone formed on its surface. [Figure 7] FIG. 7 is a graph showing denude zone thickness as a function of Δ (i.e., v / G−(v / G)crit), where filled symbols have resistivity greater than 20 mΩ*cm and open symbols have resistivity less than 20 mΩ*cm.

[0010] Corresponding reference characters indicate corresponding parts throughout the drawings. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] The present disclosure provides a method for forming a heavily doped epitaxial wafer having a relatively deep denude zone disposed below an epitaxial layer. According to an embodiment of the present disclosure, the ratio (v / G) of the growth rate (v) to the axial temperature gradient (G) may be controlled to be less than a critical v / G for a given boron concentration in the substrate during growth of a segment or the entire constant diameter portion of a monocrystalline silicon ingot. An epitaxial layer is deposited on a substrate cut from such an ingot, and the resulting heavily doped epitaxial wafer can form a relatively thick denude zone during a subsequent high temperature anneal, such as during device fabrication.

[0012] The methods of the present disclosure may generally be performed by any ingot pulling apparatus configured to pull a monocrystalline silicon ingot. An example of an ingot pulling apparatus (or more simply, an "ingot puller") is generally designated "100" in FIG. 1. The ingot pulling apparatus 100 includes a crucible 102 supported by a susceptor 106 for holding a melt 104 of semiconductor or solar grade material, such as silicon. The ingot pulling apparatus 100 includes a crystal pulling housing 108 defining a growth chamber 152 for pulling a silicon ingot 113 (FIG. 2) from the melt 104 along a pulling axis A.

[0013] Crucible 102 includes a floor 129 and a sidewall 131 that extends upwardly from floor 129. Sidewall 131 is generally vertical. Floor 129 includes a curved portion of crucible 102 that extends below sidewall 131. Within crucible 102 is a silicon melt having a melt surface 111 (i.e., a melt-ingot interface).

[0014] In some embodiments, the crucible 102 is layered. For example, the crucible 102 may be made of a quartz-based layer and a synthetic quartz layer disposed on the quartz-based layer.

[0015] The susceptor 106 is supported by a shaft 105. The susceptor 106, crucible 102, shaft 105, and ingot 113 (FIG. 2) have a common longitudinal axis A or "pull axis" A.

[0016] A pulling mechanism 114 is provided within the ingot pulling apparatus 100 for growing and pulling the ingot 113 from the melt 114. The pulling mechanism 114 includes a pulling cable 118, a seed holder or chuck 120 coupled to one end of the pulling cable 118, and a silicon seed crystal 122 coupled to the seed holder or chuck 120 for initiating crystal growth. One end of the pulling cable 118 is connected to a pulley (not shown) or drum (not shown), or any other suitable type of lifting mechanism, e.g., a shaft, and the other end is connected to the chuck 120 that holds the seed crystal. During operation, the seed crystal is lowered into contact with the melt 114. The pulling mechanism 114 is operated to raise the seed crystal 122. This causes the single crystal ingot 113 (FIG. 2) to be pulled from the melt 104.

[0017] During heating and crystal pulling, a crucible drive unit 107 (e.g., a motor) rotates the crucible 102 and the susceptor 106. A lifting mechanism 112 raises and lowers the crucible 102 along the pulling axis A during the growth process. For example, as shown in FIG. 1, the crucible 102 may be in a bottom position (near the bottom heater 126) where an initial charge of solid phase polycrystalline silicon previously added to the crucible 102 melts. Crystal growth begins when the melt 104 contacts the seed crystal 122 and the pulling mechanism 114 lifts the seed crystal 122. As the ingot grows, the silicon melt 104 is consumed and the height of the melt in the crucible 102 decreases. The crucible 102 and the susceptor 106 may be elevated to maintain the melt surface 111 at or near the same position relative to the ingot pulling apparatus 100 (FIG. 2).

[0018] A crystal drive unit (not shown) may rotate the pulling cable 118 and ingot 113 ( FIG. 2 ) in a direction opposite to the direction that the crucible drive unit 107 rotates the crucible 102 (e.g., counter-rotation). In embodiments using equal rotation, the crystal drive unit may rotate the pulling cable 118 in the same direction that the crucible drive unit 107 rotates the crucible 102. The crystal drive unit also raises and lowers the ingot 113 relative to the melt surface 111 as desired during the growth process.

[0019] The ingot pulling apparatus 100 may include an inert gas system for introducing and withdrawing an inert gas, such as argon, into and from the growth chamber 152. The ingot pulling apparatus 100 may also include a dopant delivery system (not shown) for introducing dopants into the melt 104.

[0020] According to the Czochralski single crystal growth process, a quantity of polycrystalline silicon, or polysilicon, is charged into a crucible 102. An initial semiconductor or solar grade material introduced into the crucible melts with heat provided by one or more heating elements to form a silicon melt within the crucible. The ingot pulling apparatus 100 includes bottom insulation 110 and side insulation 124 for retaining heat within the puller. In the illustrated embodiment, the ingot pulling apparatus 100 includes a bottom heater 126 disposed below the crucible floor 129. The crucible 102 may be moved into close proximity to the bottom heater 126 to melt the polycrystalline silicon charged into the crucible 102.

[0021] To form an ingot, the seed crystal 122 is contacted with the surface 111 of the melt 104. A pulling mechanism 114 is operated to pull the seed crystal 122 from the melt 104. Referring to FIG. 2, the ingot 113 includes a crown portion 142 where the ingot transitions outward from the seed crystal 122 and tapers to reach a target diameter. The ingot 113 includes a constant diameter portion 145 or cylindrical "body" of the crystal that is grown by increasing the pulling rate. The body 145 of the ingot 113 has a relatively constant diameter. The ingot 113 includes a tail or end cone (not shown) where the ingot tapers in diameter after the body 145. When the diameter is small enough, the ingot 113 is separated from the melt 104.

[0022] The ingot pulling apparatus 100 includes a side heater 135 and a susceptor 106 that surrounds the crucible 102 to maintain the temperature of the melt 104 during crystal growth. The side heater 135 is disposed radially outward of the crucible sidewall 131 as the crucible 102 moves up and down the pulling axis A. The side heater 135 and the bottom heater 126 may be any type of heater that enables the side heater 135 and the bottom heater 126 to operate as described herein. In some embodiments, the heaters 135, 126 are resistive heaters. The side heater 135 and the bottom heater 126 may be controlled by a control system (not shown) such that the temperature of the melt 104 is controlled throughout the growth process.

[0023] The ingot pulling apparatus 100 may include a heat shield 151. The heat shield 151 may cover the ingot 113 and may be positioned within the crucible during crystal growth (FIG. 2).

[0024] In some embodiments, the silicon substrate produced by the methods described herein is doped (e.g., relatively heavily doped) with boron. For example, the silicon melt may contain at least 2.8×10 18 atoms / cm 3The silicon ingot may be doped with boron to produce a doped silicon ingot (or at least a segment thereof) having a boron concentration of at least 3.8×10 18 atoms / cm 3 At least 2.8 × 10 at the seed end is achieved by doping the melt with boron at a concentration of 18 atoms / cm 3 The resulting ingot (and sliced ​​wafers) have a concentration of at least 2.8×10 18 atoms / cm 3 In some embodiments, the melt is not doped with carbon (and in some embodiments, no dopants other than boron are used). In some embodiments, the ingot has an oxygen concentration of less than 12 nppma.

[0025] According to an embodiment of the present disclosure, (i) the growth rate, v, and / or (ii) the axial temperature gradient, G, are controlled during the growth of at least an axial segment of the ingot such that v / G is less than a critical value of v / G. In other words, the growth rate, v, and / or (ii) the axial temperature gradient, G, v / G, are controlled such that Δ, as defined below, is negative. Δ=(v / G)-(v / G) crit (1) Stated further, the growth rate, v, and / or (ii) the axial temperature gradient, G, are controlled such that the ratio (R) of v / G to a critical v / G, as defined below, is less than 1. R = (v / G) / (v / G) crit (2)

[0026] By controlling the ratio of v / G during silicon growth, the dominant defect type can be controlled. When v / G is high, point defect convection dominates over diffusion and the vacancy concentration at the interface is higher than the interstitial concentration, so vacancies remain the dominant point defect. When v / G is low, diffusion dominates over convection and fast diffusing interstitials can be incorporated as the dominant point defect. When v / G is close to a critical value (i.e. the transition between vacancy dominated and interstitial dominated materials), both point defects are incorporated at very low and comparable concentrations.

[0027] According to embodiments of the present disclosure, (i) the growth rate, v, and / or (ii) the axial temperature gradient, G, may be controlled during growth of a constant diameter axial segment of the ingot such that the ratio, v / G, is below a critical value of v / G (e.g., across the entire radius) to reduce or eliminate the vacancy concentration in the ingot. Because v / G is typically highest at the center of the ingot, in some embodiments, v / G at the center is controlled (e.g., calculated) to be below the critical value of v / G such that the entire radius of the ingot is below the critical value of v / G.

[0028] The critical v / G generally varies based on the amount of doped boron (see, e.g., Dornberger et al., "Influence of Boron Concentration on the Oxidation-induced Stacking Fault Ring in Czochralski Silicon Crystals," Journal of Crystal Growth, 180, pp. 343-352 (1997), incorporated by reference herein for all relevant consistent purposes). Boron shifts the equilibrium toward the interstitial regime. With higher boron concentrations (i.e., lower resistivity), the vacancy-dominated regions shrink and disappear entirely at the crystal center (FIGS. 3B-3C). In this regard, the critical v / G may be determined based on the target boron concentration of the single crystal silicon ingot, compared to literature values ​​of critical v / G for a given boron concentration (see, e.g., Dornberger et al.), and / or according to the following equation: (v / G) crit =1.34×10 -3 +1.2×10 -22 *C B (cm 2 / min*K) (3) Here, C B is the boron concentration.

[0029] As discussed above, v / G may be controlled such that interstitials are the predominant intrinsic point defect for at least one segment of the ingot (e.g., an axial segment). This segment of the ingot may have a length that is at least 0.5 times (0.5*D) the length (D) of the constant diameter portion of the ingot. In other embodiments, the length of the segment is at least 0.75*D or at least 0.9*D. In some embodiments, the segment is the entire constant diameter portion of the ingot.

[0030] Once the ingot is grown, it is cut into a number of silicon substrates (i.e., wafers). Referring to Figure 4, each silicon substrate 1 has a front surface 3, a back surface 5, an imaginary central plane 7 between the front surface and the back surface, and a wafer bulk 9 having a wafer volume between the front surface and the back surface.

[0031] The resulting substrate 1 has a distribution of grown oxygen precipitate nuclei that form during ingot cooling. Generally, in p+ ingots, the density of grown precipitates is relatively uniform. During subsequent heat treatment, these grown precipitates may grow or break down. The stability of these precipitates is influenced by the distribution and concentration of intrinsic point defects. Without being bound to a particular theory, vacancies promote the stabilization and growth of oxygen precipitates (by stress relaxation), making it harder for the oxygen precipitates to break down, thereby reducing the depth of the denuded zone. When v / G is slightly above a critical value, the residual vacancy concentration becomes high (vacancies that are not effectively consumed by voids due to their low initial concentration grow) and the oxygen nuclei become more stable. Ingot growth parameters may be controlled to create a residual defect point distribution at the surface that is suitable for the formation of a denuded zone in the subsurface region and the formation of oxygen precipitates in the wafer bulk. Such substrates are capable of internal gettering while having deep denuded zones that can reduce or eliminate dislocations and slip during subsequent device fabrication (e.g., during fabrication of deep trenches).

[0032] For example, referring to FIG. 5 , after a subsequent heat treatment (e.g., a typical customer heat treatment) that includes a relatively high temperature step (e.g., above 1150° C.), the depth distribution of oxygen precipitates in the resulting wafer is characterized by distinct regions of oxygen precipitate-free material (precipitate-free zones or “denude zones”) 13, 13′ that extend to depths t, t′ from the front and back surfaces 3, 5, respectively. Stated another way, the denude zone is the surface layer 13 that includes the area of ​​the wafer 1 between the front surface 3 and a distance D1, where the distance D1 is measured from the front surface 3 toward the central surface 7. Between these oxygen precipitate-free regions 13, 13′ is a precipitate zone 15 that includes a substantially uniform density of oxygen precipitates. Typically, the precipitate density is on the order of about 1×10 8 Larger, about 1×10 11 pieces / cm 3 Less than 1 cm 3 Approximately 5 x 10 per 9 or 5×10 10 A precipitate density of is typical in some embodiments.

[0033] The distances t, t' (sometimes referred to herein as distance D1) of the oxygen precipitate-free material (i.e., denude zones 13, 13') from the front and back sides, respectively, are a function, in part, of the oxygen concentration, resistivity (e.g., dopant concentration), other ingot growth conditions (e.g., residual point defect concentration), and heat treatment temperature. In some embodiments, the depths t, t' (i.e., denude zone depth D1) are at least 15 μm, or, as in other embodiments, at least about 20 μm, at least 30 μm, at least about 40 μm, or at least 50 μm (e.g., from about 15 μm to about 100 μm, from about 20 μm to about 100 μm, from about 30 μm to about 100 μm).

[0034] In this regard, the Denuded Zone is generally defined as: (i) the current detection limit (currently, ca. 10 6 Oxygen precipitates / cm 3) and (ii) occupy an area near the surface of the wafer that is low in concentration, preferably substantially free, of oxygen precipitate centers that will be converted to oxygen precipitates when subjected to an oxygen precipitation heat treatment. The presence (or density) of oxygen precipitate nucleation centers cannot be measured directly using currently available techniques. However, it can be indirectly measured by subjecting the silicon to an oxygen precipitation heat treatment, which stabilizes the oxygen precipitate nucleation centers and, if oxygen precipitates grow at these locations. When oxygen precipitation heat treatment is performed at temperatures above about 700°C, the denude zone expands to approximately 1×10 6 cm -3 The bulk layer has an oxygen precipitate density of about 1×10 6 cm -3 In some embodiments, when annealed at a temperature of 800° C. for 4 hours and then at a temperature of 1000° C. for 16 hours, the denude zone has an oxygen precipitate density of about 10 6 pieces / cm 3 has less than 100% oxygen precipitates.

[0035] Once the wafer has been cut from the ingot and processed (e.g., various steps to smooth and / or reduce surface roughness), an epitaxial layer 25 (FIG. 6) can be disposed on the surface 3 (FIG. 5) of the substrate 1 by contacting the surface 3 with a silicon-containing gas that decomposes to form an epitaxial layer 25 on the substrate 1. In general, any method available to one skilled in the art for depositing a silicon epitaxial layer on a silicon substrate can be used unless otherwise noted. Silicon may be deposited by epitaxy to any suitable thickness depending on the device application. For example, silicon may be deposited using metal-organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), or molecular beam epitaxy (MBE). Silicon precursors (i.e., silicon-containing gases) for LPCVD or PECVD include methylsilane, silicon tetrahydride (silane), trisilane, disilane, pentasilane, neopentasilane, tetrasilane, dichlorosilane (SiH2Cl2), trichlorosilane (SiHCl3), silicon tetrachloride (SiCl4), etc. For example, silicon can be deposited on a surface by pyrolyzing silane (SiH4) at a temperature range between about 550° C. and about 690° C., e.g., between about 580° C. and about 650° C. Chamber pressures can range from about 70 to about 400 mTorr.

[0036] A boron-containing gas may be introduced into the epitaxial reactor to dope the epitaxial layers with boron. For example, B2H6 may be added to the deposition gas. The mole fraction of B2H6 in the atmosphere used to obtain the desired properties (e.g., resistivity) depends on several factors, such as the amount of boron out-diffusion from the particular substrate during epitaxial deposition, the amount of p-type and n-type dopants present in the reactor and substrate as contaminants, and the pressure and temperature of the reactor. In some embodiments, the resulting epitaxial structure (i.e., substrate and epitaxial layers) may be p / p+ epitaxial wafers (e.g., 2×10 16 atoms / cm 3The epitaxial layer is doped with boron at a concentration sufficient to achieve a boron concentration of 0.1 to 0.5%.

[0037] The resulting epitaxial wafer 20 (FIG. 6) has a relatively thick denude zone 13 (e.g., at least about 15 μm thick, at least about 20 μm thick, at least about 30 μm thick, at least about 40 μm thick, or at least about 50 μm thick) below the epitaxial layer (i.e., below the interface between the substrate and the epitaxial layer) and extending toward the center surface.

[0038] Compared to other methods for forming epitaxial wafers, the disclosed method has several advantages: The substrate is heavily doped with boron (e.g., 2.8×10 18 atoms / cm 3 It has been found that doping the substrate with high boron concentrations (e.g., boron concentrations of 1000 nm or more) suppresses the formation of interstitial dislocation loops. It has also been found that highly doping the substrate with boron promotes oxygen precipitation. By maintaining v / G below a critical value in a relatively highly doped substrate, vacancies can be substantially eliminated and the depth of the denude zone formed after an oxygen precipitation heat treatment (e.g., a high temperature step above 1150° C.) can be increased. Such denude zones can form even at relatively high oxygen concentrations (e.g., up to 12 nppma).

[0039] (Example) The processes of the present disclosure are further illustrated by the following examples, which should not be construed in a limiting sense.

[0040] Example 1: Δ(v / G-(v / G) crit ) as a function of denude zone depth Boron-doped monocrystalline silicon ingot test crystals (200 mm) were grown by the Czochralski method on an ingot puller similar to the ingot puller shown in Figure 1-2. The ingots were 2.7 × 10 18 atoms / cm 3 From 4.0×1018 atoms / cm 3 (resistivity was 22.42mΩ*cm to 17.2mΩ*cm, respectively). The oxygen concentration of the single crystal silicon ingots was 10.01 to 11.8nppma.

[0041] The parameter Δ (i.e., (v / G)-(v / G) crit Crystals were grown under different process conditions to explore a wide range of values ​​of G. This was achieved by varying the pull rate in the same hot zone and by choosing different hot zones (with different values ​​of the axial temperature gradient G). The crystals were cut into wafers and polished. Epitaxial layers were grown on the polished wafers under standard conditions. The epitaxial wafers were then subjected to thermal cycles typical of silicon semiconductor device manufacturing, in particular a thermal cycle that included a high-temperature denuding step at 1150 °C. After the thermal cycles, the denuded zone (DZ) was characterized by a cleave etch method.

[0042] The results are shown in FIG. 7 as a function of the parameter Δ (black symbols have resistivity greater than 20 mΩ*cm, open symbols have resistivity less than 20 mΩ*cm). For samples with resistivity less than 20 mΩ*cm (open symbols), the denuded zone was thickest (28-40 μm) when Δ was negative. For positive Δ, the denuded zone was generally smaller, with Δ being less than 0.02 mm. 2 The minimum average thickness (10-12 μm) was reached at around 100 / K*min. Without being bound to any particular theory, it is believed that this value of Δ represents the condition where the residual vacancy concentration (after annihilation of interstitials and consumption by voids) is at a maximum. It is believed that the high residual vacancy concentration promotes oxygen precipitation and that under these conditions the denude zone is less likely to form. When Δ is very small but positive (≈0.005-0.025 mm 2 / K*min), the denudation zone thickness is more scattered, showing both large and narrow denudation zones. This is attributed to the narrow Δ range where the transition between the best and worst conditions for the denudation zone thickness occurs. There are at least three factors that contribute to the scatter in the data: (i) small variations in the actual pulling speed can give small deviations from the estimated Δ (furthermore, the estimated Δ is an average Δ estimated per ingot and not a constant value); (ii) the temperature gradient G is calculated by FEM simulations which require some simplifications that limit the accuracy in influencing the values ​​of v / G and Δ; (iii) the oxygen concentration has a strong effect even in the relatively narrow range of 10.01 to 11.8 nppma, with wafers with less oxygen having larger denudation zones. To increase the denudation zone width (and reduce the scatter), the critical value of 0.02 mm was used. 2 A value of the parameter Δ can be selected that is relatively far from / K*min, and preferably a negative value of the parameter Δ is selected.

[0043] The group of samples with resistivity greater than 20 mΩ*cm (black circles) has an overall thicker denude zone compared to the previous samples (those with resistivity less than 20 mΩ*cm) due to the lower boron concentration, which favors less oxygen precipitation. This group of samples shows the same trend as a function of the parameter Δ. In this case, the maximum denude zone thickness is reached when the parameter Δ is negative or zero, indicating the absence of excessive vacancy incorporation, and the same critical value of Δ of 0.02 mm is reached. 2 / K*min, which confirms the conclusions drawn from the first sample group (the variability considerations mentioned above are applicable).

[0044] Various Δ (i.e. (v / G)-(v / G) crit The average denude zone thickness for the range of thicknesses is shown in Table 1 below.

[0045] [Table 1] Table 1: Average denudation zone thickness in samples with resistivity greater than 20 mΩ*cm and samples with resistivity less than 20 mΩ·m.

[0046] The same conclusion can be drawn when the ratio (R) is taken into account: when R<1, the crystal grows in the interstitial-rich regime, and when R>1, the crystal grows in the vacancy regime. The worst case for the denude zone thickness (maximum residual vacancy concentration) was R≈1.13.

[0047] As used herein, the terms "about," "substantially," "essentially," and "approximately," when used in connection with a range of a dimension, density, temperature, or other physical or chemical property or characteristic, are meant to encompass variations that may exist at the upper and / or lower limits of the range of the property or characteristic, including, for example, variations that result from rounding, measurement methods, or other statistical variations.

[0048] When introducing elements of the present disclosure or embodiments of the present disclosure, the articles "a," "an," "the," and "said" are intended to mean that there are one or more of the elements. The terms "comprising," "including," "containing," and "having" are intended to be inclusive and mean that there may be additional elements other than the listed elements. The use of specific orientation terms (e.g., "top," "bottom," "side") is for convenience of description and does not require a specific orientation of the articles being described.

[0049] Because various changes may be made in the structure and methods described above without departing from the scope of the present disclosure, it is intended that all matter contained in the above description and shown in the accompanying drawings be interpreted in an illustrative and not a limiting sense.

Claims

1. 1. A method for forming an epitaxial wafer comprising a substrate and an epitaxial layer disposed on the substrate, the method comprising: adding an initial charge of polycrystalline silicon to the crucible; heating the crucible containing the initial charge of polycrystalline silicon to form a silicon melt within the crucible; adding boron to the crucible to produce a doped silicon melt; contacting a silicon seed crystal with the doped silicon melt; The silicon seed crystal is withdrawn to grow a single crystal silicon ingot, wherein the ingot has a constant diameter portion, the constant diameter portion of the ingot being at least about 2.8×10 １８ atoms / cm ３ and having a boron concentration of controlling (i) the growth rate, v, and / or (ii) the axial temperature gradient, G, during growth of the constant diameter segment of the ingot, such that v / G is less than a critical v / G; Cutting a plurality of silicon substrates from the single crystal silicon ingot; A silicon-containing gas is brought into contact with a surface of one of the plurality of silicon substrates, and the silicon-containing gas is decomposed to form an epitaxial silicon layer on the silicon substrate. The method includes:

2. The method of claim 1 , wherein the critical v / G varies with the boron concentration of the silicon ingot.

3. 3. The method of claim 2, wherein the critical v / G is determined based on a target boron concentration in the single crystal silicon ingot.

4. 10. The method of claim 1, wherein the single crystal silicon ingot has an oxygen concentration of less than 12 nppma.

5. The method of claim 1 , wherein the constant diameter portion has a length D, and the length of the segment is at least 0.5*D.

6. The method of claim 1 , wherein the constant diameter portion has a length D, and the length of the segment is at least 0.9*D.

7. The method of claim 1 , wherein the length of the segment is the entire constant diameter portion of the ingot.

8. The method of claim 1 , wherein the melt is not doped with carbon.

9. Each of the plurality of silicon substrates has a front surface, a back surface, and a center surface that is approximately equidistant between the front surface and the back surface; Each of the plurality of silicon substrates is a surface layer having an area of ​​the wafer between the surface and a distance D1, the distance D1 being at least about 15 μm, measured from the surface toward the central plane; a bulk layer extending from the front surface layer toward the rear surface; The method of claim 1 , comprising:

10. When subjected to an oxygen precipitation heat treatment at a temperature exceeding about 700° C., the silicon substrate has a denude zone in the surface layer, and the surface layer has a denude zone of about 1×10 ６ pieces / cm ３ and the bulk layer has less than about 1×10 oxygen precipitates. ６ pieces / cm ３ 10. The method of claim 9, having more than 100% oxygen precipitates.

11. The bulk layer is about 1×10 ８ pieces / cm ３ 10. The method of claim 9, having more than 100% oxygen precipitates.

12. The method of claim 9 , wherein the surface layer has an interstitial oxygen concentration of less than 12 nppma.

13. 10. The method of claim 9, wherein the surface layer comprises an area of ​​the wafer between the surface and a distance D1, the distance D1 being measured from the surface toward the central surface and being at least about 20 μm, at least 30 μm, at least 40 μm, or at least 50 μm, from about 15 μm to about 100 μm, from about 20 μm to about 100 μm, from about 30 μm to about 100 μm.

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