Sampling Phase Locked Loop

Abstract

In a particular aspect, the sampler includes a sampling capacitor, a pre-charge switch coupled to the sampling capacitor, one or more discharge circuits coupled to the sampling capacitor, and a reference voltage circuit coupled to the sampling capacitor, The reference voltage circuit is configured to generate a reference voltage based on a supply voltage and generate a voltage difference between the voltage on the sampling capacitor and the reference voltage.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to and the benefit of nonprovisional application No. 17 / 340,914, filed in the United States Patent Office on June 7, 2021, and issued by the United States Patent Office as Patent No. 11,277,140 on March 15, 2022, the entire contents of which are incorporated herein by reference as if fully set forth below in its entirety, and for all applicable purposes. BACKGROUND OF THE INVETION

[0002] Field Aspects of the present disclosure relate generally to phase-locked loops (PLLs), and more particularly to sampling PLLs. [Background technology]

[0003]

[0003] A phase-locked loop (PLL) can be used to generate a signal having a desired frequency by multiplying the frequency of a reference signal by a corresponding amount. For example, a PLL can be used in a wireless device to generate a local oscillator signal having a desired frequency. Summary of the Invention

[0004]

[0004] Below, a simplified summary of one or more implementations is presented to provide a basic understanding of such implementations. This "Summary" is not an extensive overview of all contemplated implementations, and is not intended to identify key or critical elements of all implementations or to delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the "Description of the Preferred Embodiments" presented later.

[0005] A first aspect relates to a sampler including a sampling capacitor, a precharge switch coupled to the sampling capacitor, one or more discharge circuits coupled to the sampling capacitor, and a reference voltage circuit coupled to the sampling capacitor. The reference voltage circuit is configured to generate a reference voltage based on a supply voltage and generate a voltage difference between the voltage on the sampling capacitor and the reference voltage.

[0006]

[0006] A second aspect relates to an apparatus. The apparatus includes a sampling capacitor, a precharge switch coupled to the sampling capacitor, one or more discharge circuits coupled to the sampling capacitor, and a reference voltage circuit coupled to the sampling capacitor. The reference voltage circuit includes a first capacitor, a second capacitor, a first switch coupled between the first capacitor and the second capacitor, a second switch coupled in parallel to the second capacitor, and a difference circuit coupled to the sampling capacitor and the first capacitor.

[0007] A third aspect relates to a method of sampling, the method including charging a sampling capacitor to a supply voltage, discharging a portion of the charge on the sampling capacitor based on a phase error to generate a sampling voltage, generating a reference voltage based on the supply voltage, and generating a difference voltage between the sampling voltage and the reference voltage.

[0008] A fourth aspect relates to an apparatus for sampling, the apparatus including means for charging a sampling capacitor to a supply voltage, means for discharging a portion of the charge on the sampling capacitor based on a phase error to generate a sampling voltage, means for generating a reference voltage based on the supply voltage, and means for generating a difference voltage between the sampling voltage and the reference voltage. [Brief description of the drawings]

[0009] [Figure 1] 1 illustrates an example of a phase-locked loop (PLL) in accordance with certain aspects of the present disclosure. [Diagram 2]

[0010] 1 illustrates an example implementation of a loop filter in accordance with certain aspects of the present disclosure. [Diagram 3]

[0011] 1 illustrates an example implementation of a sampler in accordance with certain aspects of the present disclosure. [Figure 4]

[0012] 1 illustrates an example implementation of a sampler using phase interpolation in accordance with certain aspects of the present disclosure. [Diagram 5]

[0013] 1 illustrates one embodiment of a reference voltage circuit in accordance with certain aspects of the present disclosure. [Figure 6]

[0014] 1 illustrates another example of a reference voltage circuit in accordance with certain aspects of the present disclosure. [Figure 7]

[0015] 1 illustrates an example implementation of a switch in a sampler in accordance with certain aspects of the present disclosure. [Figure 8]

[0016] 8 is a timing diagram illustrating example signals in the example sampler shown in FIG. 7 in accordance with certain aspects of the present disclosure. [Figure 9]

[0017] 1 illustrates an example implementation of a phase detector in accordance with certain aspects of the present disclosure. [Figure 10]

[0018] 1 illustrates an exemplary wireless device in accordance with certain aspects of the present disclosure. [Figure 11]

[0019] 1 is a diagram of an environment including an electronic device including a transceiver, in accordance with certain aspects of the present disclosure. [Figure 12]

[0020] 1 is a flow chart illustrating a method of sampling according to certain aspects of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010]

[0021] The detailed description of the present invention, described below in connection with the accompanying drawings, is intended as an illustration of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description of the present invention includes specific details intended to provide a thorough understanding of the various concepts. However, it will be apparent to one skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

[0011]

[0022] 1 illustrates an example of a phase-locked loop (PLL) 110 according to certain aspects of the present disclosure. The PLL 110 may be used to generate a local oscillator signal (e.g., for frequency up-conversion and / or frequency down-conversion) in, for example, a wireless device. In this example, the PLL 110 includes a phase detector 120, a sampler 130, a loop filter 135, a voltage controlled oscillator (VCO) 140, and a frequency divider 150. The phase detector 120 may also be referred to as a phase frequency detector (PFD), a phase comparator, or another term.

[0012]

[0023] The phase detector 120 has a first input 122, a second input 124, and an output 126. The first input 122 is configured to receive a reference signal (labeled “ref”). The reference signal (e.g., a reference clock signal) may come from a crystal oscillator (not shown) or another source. The sampler 130 has an input 132 that is coupled to the output 126 of the phase detector 120, and an output 134. A loop filter 135 is coupled between the output 134 of the sampler 130 and a control input 142 of the VCO 140. As will be discussed further below, the VCO 140 has a frequency ("f") that is controlled by a voltage at the control input 142 of the VCO 140. VCO"), which is output at output 144 of VCO 140, which is coupled to output 112 of PLL 110. Thus, in this embodiment, the output signal of VCO 140 provides the output signal of PLL 110.

[0013]

[0024] The divider 150 has an input 152 and an output 154. The input 152 of the divider 150 is coupled to the output 144 of the VCO 140, and the output 154 of the divider 150 is coupled to the second input 124 of the phase detector 120. Thus, in this embodiment, the output signal of the VCO 140 is fed back through the divider 150 to the second input 124 of the phase detector 120 via a feedback loop 155. In one embodiment, the divider 150 is configured to divide the frequency of the output signal of the VCO 140 by a division ratio N to generate a feedback signal (labeled "fb"). Thus, in this embodiment, the feedback signal is f VCO The feedback signal is output at an output 154 of the frequency divider 150 and input to a second input 124 of the phase detector 120.

[0014]

[0025] In operation, phase detector 120 receives a reference signal at a first input 122 and a feedback signal at a second input 124. Phase detector 120 is configured to detect a phase error between the reference signal and the feedback signal, generate a phase error signal indicative of the detected phase error, and output the phase error signal at output 126. In some implementations, the phase error signal includes a pulse having a width that is a function of the detected phase error. In one example, the detected phase error can be expressed as a time error (i.e., a time difference) between an edge (e.g., a rising edge or a falling edge) of the feedback signal and an edge (e.g., a rising edge or a falling edge) of the reference signal. In this example, the width of the pulse is equal to or proportional to the time error between an edge of the feedback signal and an edge of the reference signal.

[0015]

[0026] Sampler 130 is configured to sample the phase error signal from phase detector 120 and output the sampled phase error signal to loop filter 135. The sampled phase error signal may be a voltage or a current. Loop filter 135 filters the sampled phase error signal into a voltage that is input to a control input 142 of VCO 140 to control the output frequency of VCO 140.

[0016]

[0027] Feedback loop 155 of PLL 110 causes phase detector 120, sampler 130, and loop filter 135 to adjust the voltage at control input 142 of VCO 140 in a direction that reduces the phase error between the feedback signal and the reference signal. When PLL 110 is locked, the output frequency of VCO 140 is approximately equal to the frequency of the reference signal multiplied by the division ratio N of divider 150. In other words, the output frequency is given by: f VCO = N f ref (1) where f ref is the reference frequency (i.e., the frequency of the reference signal). Therefore, in this embodiment, the output frequency of the VCO 140 is a multiple of the reference frequency, and can be set to a desired frequency by appropriately setting the division ratio N of the frequency divider 150 based on equation (1).

[0017]

[0028] In one embodiment, the division ratio N of divider 150 is an integer greater than or equal to 2. In this embodiment, the output frequency of VCO 140 is an integer multiple of the reference frequency.

[0018]

[0029] In some implementations, the PLL 110 further includes a delta-sigma modulator (DSM) 160 to achieve a non-integer division ratio using the divider 150. As used herein, the term "non-integer division ratio" may refer to a division ratio that includes a fractional portion. In this embodiment, the DSM 160 has an input 162 and an output 164. The output 164 of the DSM 160 is coupled to a control input 156 of the divider 150. In this embodiment, the divider 150 is configured to set the division ratio N of the divider 150 to any one of a number of integer values ​​based on a division ratio control signal received from the DSM 160 via the control input 156.

[0019]

[0030] In operation, the DSM 160 is configured to receive a frequency control signal (e.g., a frequency control word) that indicates a desired non-integer division value. The DSM 160 then modulates the division ratio of the divider 150 such that the average value of the division ratio is approximately equal to the desired non-integer division value over multiple cycles of the reference signal. The DSM 160 can modulate the division ratio by varying the integer value of the division ratio over multiple cycles of the reference signal using the division ratio control signal such that the average value of the division ratio is approximately equal to the desired non-integer division value. For example, the DSM 160 can achieve an average non-integer division value of 6.25 over four cycles of the reference signal by setting the division ratio of the divider 150 to 6 for three of the four cycles and 7 for one of the four cycles. The DSM 160 can be implemented using a first-order DSM, a second-order multi-state noise shaping (MASH) DSM, a third-order MASH DSM, or another type of DSM. In this embodiment, divider 150 and DSM 160 implement a "fractional-N divider."

[0020]

[0031] 2 illustrates an example implementation of loop filter 135 in accordance with certain aspects. In this embodiment, loop filter 135 includes a capacitor 210 and an integration path 220. Furthermore, control input 142 of VCO 140 includes a first control input 142-1 and a second control input 142-2.

[0021]

[0032] In this embodiment, a first terminal 212 of capacitor 210 is coupled to a node between output 134 of sampler 130 and a first control input 142-1 of VCO 140, and a second terminal 214 of capacitor 210 is coupled to ground (or some reference voltage configured to function as ground). The voltage on capacitor 210 (labeled "vtune") is input to a first control input 142-1 of VCO 140 to adjust the output frequency of VCO 140.

[0022]

[0033] The integration path 220 is coupled between the output 134 of the sampler 130 and the second control input 142-2 of the VCO 140. The integration path 220 is configured to integrate the voltage vtune and further adjust the output frequency of the VCO 140 via the second control input 142-2 based on the integration. In the embodiment of FIG. 2, the integration path 220 includes an analog-to-digital converter (ADC) 225 and an accumulator 230. The ADC 225 is configured to convert the voltage vtune to a digital signal, and the accumulator 230 is configured to integrate the digital signal. Therefore, in this embodiment, the integration path 220 performs integration in the digital domain.

[0023]

[0034] It should be understood, however, that the loop filter 135 is not limited to the exemplary implementation shown in Figure 2. For example, in other implementations, the loop filter 135 may include a low-pass filter (e.g., a resistor-capacitor (RC) filter) coupled to the output 134 of the sampler 130.

[0024]

[0035] In one embodiment, the VCO 140 may include an inductor-capacitor (LC) tank (not shown), where the output frequency of the VCO 140 is adjusted by adjusting the capacitance of the LC tank. In this embodiment, the LC tank may include one or more capacitors (e.g., varactors) whose capacitance is adjusted by a voltage vtune via a first control input 142-1, and one or more capacitors (e.g., a capacitor bank) whose capacitance is adjusted by the output of the integration path 220 via a second control input 142-2. However, it should be understood that the VCO 140 is not limited to this embodiment, and that the VCO 140 may be implemented using other types of VCO circuits.

[0025]

[0036] 3 illustrates an example implementation of the sampler 130 in accordance with certain aspects. In this example, the sampler 130 includes a discharge circuit 308, a sampling capacitor 320, a pre-charge switch 325, and a sampling switch 330.

[0026]

[0037] As discussed further below, the discharge circuit 308 is configured to discharge the sampling capacitor 320 based on the phase error signal from the phase detector 120 to generate a sampled voltage (labeled “Vs”) indicative of a phase error between the reference signal and the feedback signal. In the embodiment shown in FIG. 3, the discharge circuit 308 includes a transistor 310 and a resistor 315. A gate of the transistor 310 is coupled to the input 132 of the sampler 130, and the resistor 315 is coupled between the drain of the transistor 310 and a first terminal 322 of the sampling capacitor 320. In this embodiment, a source of the transistor 310 is coupled to ground, and a second terminal 324 of the sampling capacitor 320 is coupled to ground. However, it should be understood that the sampler 130 is not limited to the embodiment shown in FIG. 3. In other implementations, the resistor 315 can be coupled between the source of the transistor 310 and the first terminal 322 of the sampling capacitor 320, and the drain of the transistor 310 can be coupled to ground. Although one discharge circuit 308 is shown in FIG. 3, it should be understood that the sampler 130 may include multiple discharge circuits coupled in parallel, in which case each discharge circuit may include a respective resistor and a respective transistor.

[0027]

[0038] The pre-charge switch 325 is coupled between an output 344 of the voltage regulator 340 and the first terminal 322 of the sampling capacitor 320, and the sampling switch 330 is coupled between the first terminal 322 of the sampling capacitor 320 and the output 134 of the sampler 130. In this embodiment, the voltage regulator 340 has an input 342 coupled to a power supply rail 350. The voltage regulator 340 is configured to generate a regulated supply voltage Vdd at an output 344 of the voltage regulator 340 from a voltage on the power supply rail 350. Thus, in this embodiment, the supply voltage Vdd is provided to the sampler 130. The voltage regulator 340 can be implemented using a low-dropout (LDO) regulator, a switching regulator, or another type of voltage regulator.

[0028]

[0039] In this embodiment, the pre-charge switch 325 and the sampling switch 330 are controlled by a controller 360. In this regard, the controller 360 is coupled to a control input 327 of the pre-charge switch 325 and is coupled to a control input 332 of the sampling switch 330. In this embodiment, the controller 360 is configured to control an on / off state of the pre-charge switch 325 via the control input 327 and to control an on / off state of the sampling switch 330 via the control input 332. The pre-charge switch 325 may be implemented using a transistor, a transmission gate, or another type of switch having a gate coupled to the control input 327. Similarly, the sampling switch 330 may be implemented using a transistor, a transmission gate, or another type of switch having a gate coupled to the control input 332.

[0029]

[0040] To sample the phase error signal, the sampling capacitor 320 is first precharged to the supply voltage Vdd during a precharge phase. To accomplish this, the controller 360 turns on the precharge switch 325, allowing the sampling capacitor 320 to be precharged to the supply voltage Vdd via the precharge switch 325. The controller 360 may also turn off the sampling switch 330 during the precharge phase. After the sampling capacitor 320 is precharged, the controller 360 turns off the precharge switch 325.

[0030]

[0041] After the precharge phase, the gate of transistor 310 is driven by the phase error signal from phase detector 120. In one embodiment, the phase error signal comprises a pulse having a width that is a function of the detected phase error between the reference signal and the feedback signal (e.g., the time error between an edge of the feedback signal and an edge of the reference signal). In this embodiment, the phase error signal turns on transistor 310 for a duration equal to the width of the pulse, which is a function of the detected phase error. Thus, transistor 310 is turned on for a duration that is a function of the detected phase error.

[0031]

[0042] When transistor 310 is turned on by the phase error signal, it couples resistor 315 to ground. This causes a portion of the charge on sampling capacitor 320 to be discharged to ground through resistor 315. During this phase, precharge switch 325 and sampling switch 330 remain turned off. The sampled voltage as a function of time is given by the following equation:

[0032]

number

[0033] where Vs(t) is the sampled voltage as a function of time, t is the time from the start of discharge, R is the resistance of resistor 315, and C is the capacitance of sampling capacitor 320.

[0034]

[0043] The amount of charge discharged from sampling capacitor 320 is a function of the duration that transistor 310 is turned on by a phase error signal that is a function of the detected phase error. As a result, the amount of charge discharged from sampling capacitor 320 is a function of the detected phase error. Therefore, the sampled voltage Vs on sampling capacitor 320 at the end of discharge is a function of the detected phase error, and therefore provides phase error information. In one embodiment, the sampled voltage Vs at the end of discharge is given by the following equation:

[0035]

number

[0036] where Δt is the pulse width of the phase error signal and Vs in equation (3) is the sampled voltage at the end of the discharge. In this embodiment, the pulse width Δt may be approximately equal to the time error between the edge of the feedback signal and the edge of the reference signal. After the phase error signal is sampled (i.e., after transistor 310 is turned off at the end of the pulse), controller 360 turns on sampling switch 330 to couple sampling capacitor 320 to output 134 of sampler 130.

[0037]

[0044] In certain embodiments, during each cycle of the reference signal, phase detector 120 detects the phase error between the reference signal and the feedback signal and outputs a corresponding phase error signal to sampler 130, which samples the phase error signal and outputs a corresponding sampled voltage Vs. Thus, in these embodiments, the phase error is detected and sampled once every cycle of the reference signal.

[0038]

[0045] As described above, the DSM 160 can be used to achieve non-integer division values ​​by modulating the division ratio of the divider 150. However, modulating the division ratio of the divider 150 introduces quantization error into the feedback signal. The quantization error degrades performance by causing a variation in the time error between the reference signal and the feedback signal. The quantization error can be substantially cancelled out by performing phase interpolation in the sampler 130, as discussed further below.

[0039]

[0046] 4 illustrates an exemplary implementation of the sampler 130 and phase detector 120 employing phase interpolation according to certain aspects of the disclosure. In this example, the sampler 130 includes a plurality of discharge circuits 308-1 to 308-M coupled in parallel between a first terminal 322 of a sampling capacitor 320 and ground. Each of the discharge circuits 308-1 to 308-M includes a respective transistor 310-1 to 310-M and a respective resistor 315-1 to 315-M coupled between the drain or source of the respective transistor 310-1 to 310-M and the first terminal 322 of the sampling capacitor 320. In this embodiment, input 132 of sampler 130 includes multiple inputs 132-1 to 132-M, where each of inputs 132-1 to 132-M is coupled to a respective one of discharge circuits 308-1 to 308-M, and more particularly, to the gate of transistor 310-1 to 310-M of a respective one of discharge circuits 308-1 to 308-M.

[0040]

[0047] In this embodiment, the phase detector 120 includes a delay circuit 410, a first pulse circuit 420, a second pulse circuit 430, and a number of multiplexers 450-1 to 450-M. The first pulse circuit 420 has a first input 422, a second input 424, and an output 426. The first input 422 is coupled to the first input 122 of the phase detector 120, and the second input 424 is coupled to the second input 124 of the phase detector 120. Thus, the first input 422 receives a reference signal and the second input 424 receives a feedback signal. In FIG. 4, this feedback signal is called "fb1" inside the phase detector 120.

[0041]

[0048] The second pulse circuit 430 has a first input 432, a second input 434, and an output 436. The first input 432 is coupled to the first input 122 of the phase detector 120 and therefore receives the reference signal. The delay circuit 410 is coupled between the second input 124 of the phase detector 120 and the second input 434 of the second pulse circuit 430. The delay circuit 410 is configured to delay the feedback signal (e.g., by a delay equal to about one cycle (i.e., period) of the VCO 140) and output the resulting delayed feedback signal (labeled “fb2”) to the second input 434 of the second pulse circuit 430. In one embodiment, the delay circuit 410 can be implemented using a delay flip-flop clocked by the output signal of the VCO 140.

[0042]

[0049] Each of the multiplexers 450-1 to 450-M has a first input 452-1 to 452-M, a second input 454-1 to 454-M, an output 456-1 to 456-M, and a selection input 458-1 to 458-M. The first input 452-1 to 452-M of each of the multiplexers 450-1 to 450-M is coupled to the output 426 of the first pulse circuit 420, and the second input 454-1 to 454-M of each of the multiplexers 450-1 to 450-M is coupled to the output 436 of the second pulse circuit 430. In the embodiment of FIG. 4, the output 126 of the phase detector 120 includes a plurality of outputs 126-1 through 126-M, where each of the outputs 126-1 through 126-M is coupled to a respective one of the inputs 132-1 through 132-M of the sampler 130. In this embodiment, each of the outputs 456-1 through 456-M of the multiplexers 450-1 through 450-M is coupled to a respective one of the outputs 126-1 through 126-M. As shown in FIG. 4, each of the outputs 456-1 through 456-M of the multiplexers 450-1 through 450-M is coupled to a respective one of the discharge circuits 308-1 through 308-M, and more particularly, is coupled to a gate of a transistor 310-1 through 310-M of a respective one of the discharge circuits 308-1 through 308-M.

[0043]

[0050] The selection inputs 458-1 to 458-M of the multiplexers 450-1 to 450-M are digitally coded d <m-1:0>Each of the multiplexers 450-1 to 450-M is configured to receive a respective bit of a digital code d. Each of the multiplexers 450-1 to 450-M is configured to select a respective first input 452-1 to 452-M or a respective second input 454-1 to 454-M based on the bit value of the respective bit and couple the selected input to a respective output 456-1 to 456-M. For example, a high bit value may trigger a selection of a respective first input 452-1 to 452-M, while a low bit value may trigger a selection of a respective second input 454-1 to 454-M, or vice versa. As discussed further below, the digital code d <m-1:0>controls the phase interpolation in sampler 130.

[0044]

[0051] In operation, the first pulse circuit 420 is configured to detect a first time error between the reference signal and the feedback signal fb1, generate a first pulse having a width approximately equal to the first time error, and output the first pulse at the output 426. For example, the first pulse circuit 420 can be configured to generate a rising edge of the first pulse on an edge (e.g., a rising edge or a falling edge) of the feedback signal fb1 and generate a falling edge of the first pulse on an edge (e.g., a rising edge or a falling edge) of the reference signal.

[0045]

[0052] The second pulse circuit 430 is configured to detect a second time error between the reference signal and the feedback signal fb2, generate a second pulse having a width approximately equal to the second time error, and output the second pulse at the output 436. For example, the second pulse circuit 430 can be configured to generate a rising edge of the second pulse at an edge (e.g., a rising edge or a falling edge) of the feedback signal fb2 and generate a falling edge of the second pulse at an edge (e.g., a rising edge or a falling edge) of the reference signal. Due to the presence of the delay circuit 410, the rising edge of the second pulse is shifted in delay (e.g., about one cycle of the VCO 140) with respect to the rising edge of the first pulse. In combination with the multiplexers 450-1 to 450-M, the delay circuit 410 enables phase interpolation to counteract the effects of quantization errors caused by modulation of the division ratio of the divider 150, as discussed further below.

[0046]

[0053] Thus, in this embodiment, a first input 452-1 to 452-M of each of the multiplexers 450-1 to 450-M receives a first pulse from the first pulse circuit 420, and a second input 454-1 to 454-M of each of the multiplexers 450-1 to 450-M receives a second pulse from the second pulse circuit 430. Each of the multiplexers 450-1 to 450-M receives a digital code d <m-1:0>Based on the bit value of each bit of the digital code d, the digital code selects the first pulse or the second pulse, and outputs the selected pulse to the gate of each of the transistors 310-1 to 310-M. <m-1:0>controls the number of transistors 310-1 to 310-M driven by the first pulse and the number of transistors 310-1 to 310-M driven by the second pulse by controlling the pulse selection of multiplexers 450-1 to 450-M.

[0047]

[0054] In this embodiment, the sampler 130 performs phase interpolation between the feedback signal fb1 and the feedback signal fb2, in this case the digital code d <m-1:0>controls the phase interpolation by controlling the number of transistors 310-1 to 310-M driven by the first pulse and the number of transistors 310-1 to 310-M driven by the second pulse. The phase interpolation results in a sampled voltage Vs given by the following equation:

[0048]

number

[0049] Here, k is the number of transistors 310-1 to 310-M driven by the first pulse, M is the total number of transistors 310-1 to 310-M, and T VCO is one cycle (i.e., period) of the VCO 140, and Δt is the time error between the feedback signal fb2 and the reference signal. In this embodiment, the rising edge of the feedback signal fb1 and the rising edge of the feedback signal fb2 are timed to each other by T VCO The first pulse is T VCO Note that the first pulse has a width approximately equal to +Δt, and the second pulse has a width approximately equal to Δt.

[0050]

[0055] As shown in equation (4), phase interpolation is performed by <m-1:0>The sampled voltage Vs is adjusted by adjusting the number k of transistors 310-1 to 310-M driven by the first pulse using phase interpolation. In a particular embodiment, the sampled voltage Vs can be adjusted using phase interpolation to offset the effects of quantization error caused by modulating the division ratio of the divider 150.

[0051]

[0056] In this regard, the PLL 110 may include a phase interpolation (PI) control circuit 470 configured to offset quantization error using phase interpolation according to certain aspects. In the embodiment of FIG. 4, the PI control circuit 470 has a plurality of outputs 472-1 through 472-M, where each of the outputs 472-1 through 472-M is coupled to a selection input 458-1 through 458-M of a respective one of the multiplexers 450-1 through 450-M. For ease of illustration, the individual connections between the PI control circuit 470 and the multiplexers 450-1 through 450-M are not explicitly shown in FIG.

[0052]

[0057] In operation, the PI control circuit 470 determines the number k of transistors 310-1 to 310-M that need to be driven by a first pulse to offset the effect of the quantization error caused by the modulation of the division ratio by the DSM 160. For example, the DSM 160 may generate a DSM error signal indicative of the quantization error resulting from the modulation of the division ratio and input the DSM error signal to the PI control circuit 470. In this example, the PI control circuit 470 may determine the number k of transistors 310-1 to 310-M that need to be driven by a first pulse to offset the quantization error indicated by the DSM error signal. The PI control circuit 470 then generates a digital code d corresponding to the determined number k. <m-1:0>Generate the digital code d <m-1:0>to multiplexers 450-1 through 450-M via respective outputs 472-1 through 472-M. In response, multiplexers 450-1 through 450-M drive k of transistors 310-1 through 310-M with a first pulse and drive the remaining transistors 310-1 through 310-M (i.e., Mk of transistors 310-1 through 310-M) with a second pulse.

[0053]

[0058] To sample the phase error signal in this embodiment, controller 360 turns on precharge switch 325 to precharge sampling capacitor 320 to the supply voltage Vdd via precharge switch 325. After sampling capacitor 320 is precharged, controller 360 turns off precharge switch 325 and the gates of transistors 310-1 through 310-M are turned on, in this case providing digital code d, as described above. <m-1:0>Based on the above, k of the transistors 310-1 to 310-M are driven by the first pulse, and the remaining transistors 310-1 to 310-M (i.e., Mk of the transistors 310-1 to 310-M) are driven by the second pulse. This causes a portion of the charge on the sampling capacitor 320 to be discharged to ground via the resistors 315-1 to 315-M, resulting in the sampled voltage Vs given by equation (4) above. After the phase error signal is sampled, the controller 360 turns on the sampling switch 330 to couple the sampling capacitor 320 to the output 134 of the sampler 130. By performing the above procedure for each cycle of the reference signal, a phase error can be detected and the detected phase error can be sampled for each cycle of the reference signal.

[0054]

[0059] A challenge with the sampler 130 is that the supply voltage Vdd provided by the voltage regulator 340 (e.g., an LDO regulator) to precharge the sampling capacitor 320 varies due to the finite bandwidth of the voltage regulator 340. Fluctuations (i.e., variations) of the supply voltage Vdd degrade the performance of the sampler 130 by causing the sampled voltage Vs to change from cycle to cycle of the reference signal for a given phase error, resulting in phase noise. Therefore, there is a need to reduce the dependency of the sampled voltage Vs of the sampler 130 on cycle-to-cycle variations of the supply voltage Vdd from the voltage regulator 340.

[0055]

[0060] Aspects of the present disclosure reduce the effects of supply voltage variations by generating a reference voltage based on the supply voltage. A control voltage vtune is generated by subtracting the reference voltage Vref from the sampled voltage Vs. Because the reference voltage Vref is generated based on the supply voltage, the reference voltage tracks changes in the sampled voltage Vs due to supply voltage variations. As a result, as will be further discussed below, the effects of supply voltage variations are cancelled out by subtracting the reference voltage Vref from the sampled voltage Vs.

[0056]

[0061] 5 illustrates an example in which the sampler 130 further includes a reference voltage circuit 515, according to certain aspects of the present disclosure. The reference voltage circuit 515 is configured to generate a reference voltage Vref based on a supply voltage and generate a voltage difference between the sampling voltage Vs and the reference voltage Vref, as will be discussed further below.

[0057]

[0062] The reference voltage circuit 515 includes a first capacitor 530, a second pre-charge switch 550, a second capacitor 540, a first switch 560, a second switch 570, and a difference circuit 520. The second pre-charge switch 550 is coupled between a first terminal 532 of the first capacitor 530 and an output 344 of the voltage regulator 340. A second terminal 534 of the first capacitor 530 is coupled to ground. The second capacitor 540 and the second switch 570 are coupled in parallel. The first switch 560 is coupled between the first terminal 532 of the first capacitor 530 and a first terminal 542 of the second capacitor 540. A second terminal 544 of the second capacitor 540 is coupled to ground.

[0058]

[0063] In this embodiment, the controller 360 controls the second pre-charge switch 550, the first switch 560, and the second switch 570. In this regard, the controller 360 is coupled to a control input 552 of the second pre-charge switch 550, a control input 562 of the first switch 560, and a control input 572 of the second switch 570. In this embodiment, the controller 360 is configured to control an on / off state of the second pre-charge switch 550 via the control input 552, an on / off state of the first switch 560 via the control input 562, and an on / off state of the second switch 570 via the control input 572. The second pre-charge switch 550, the first switch 560, and the second switch 570 may each be implemented using a transistor, a transmission gate, or another type of switch. In the following discussion, the pre-charge switch 325 is referred to as the first pre-charge switch 325.

[0059]

[0064] The difference circuit 520 has a first input 522 coupled to the sampling capacitor 320, a second input 524 coupled to the first capacitor 530, and an output 526 coupled to the output 134 of the sampler 130. As discussed further below, the difference circuit 520 is configured to generate a voltage difference between the sampled voltage Vs on the sampling capacitor 320 and a reference voltage Vref (e.g., subtract the reference voltage Vref from the sampled voltage Vs) and output the voltage difference at the output 526.

[0060]

[0065] During the precharge phase, the controller 360 turns off the first switch 560 to isolate the first capacitor 530 from the second capacitor 540 and turns on the second switch 570 to discharge the second capacitor 540 to ground. The controller 360 also turns on the first precharge switch 325 to precharge the sampling capacitor 320 to the supply voltage Vdd and turns on the second precharge switch 550 to precharge the first capacitor 530 to the supply voltage Vdd. Thus, during the precharge phase, the sampling capacitor 320 and the first capacitor 530 are both precharged to the supply voltage Vdd. In some implementations, the first precharge switch 325 and the second precharge switch 550 can be turned on and off synchronously.

[0061]

[0066] During the sampling phase, the controller 360 turns off the first pre-charge switch 325. The discharge circuits 308-1-308-M discharge a portion of the charge on the sampling capacitor 320 based on the phase error detected by the phase detector 120 (not shown in FIG. 5) to generate the sampled voltage Vs (e.g., based on Equation (4)). In some implementations, the discharge circuits 308-1-308-M perform phase interpolation (e.g., to offset quantization error) as discussed above with reference to FIG. 4. However, it should be appreciated that in other implementations, the discharge circuits 308-1-308-M may discharge the sampling capacitor 320 based on the detected phase error without performing phase interpolation (e.g., all of the transistors 310-1-310-M may be driven by the same pulse). It should also be appreciated that the sampler 130 may include any number of discharge circuits.

[0062]

[0067] During the charge sharing phase, the controller 360 turns off the second switch 570 and the second pre-charge switch 550, and turns on the first switch 560. Turning on the first switch 560 allows charge sharing between the first capacitor 530 and the second capacitor 540. This charge sharing generates a reference voltage Vref given by the following equation:

[0063]

number

[0064] where C1 is the capacitance of the first capacitor 530 and C2 is the capacitance of the second capacitor 540. As shown in equation (5), the reference voltage Vref is based on the supply voltage Vdd and therefore tracks the changes in the sampled voltage Vs due to variations in the supply voltage Vdd. This is because the first capacitor 530 is precharged with the same supply voltage Vdd as the sampling capacitor 320 and therefore experiences the same variations in the supply voltage Vdd as the sampled voltage Vs. In some implementations, the charge sharing phase may overlap with the sampling phase. In other implementations, the charge sharing phase may be after the sampling phase, as discussed further below.

[0065]

[0068] The difference circuit 520 then subtracts the reference voltage Vref from the sampled voltage Vs and outputs the voltage difference (i.e., Vs-Vref) at the output 526. Because the reference voltage Vref tracks the changes in the sampled voltage Vs due to supply voltage variations, this subtraction cancels out the effects of supply voltage variations when the condition Vs-Vref=0 is satisfied. The condition Vs-Vref=0 can be maintained by the PLL loop itself when the PLL 110 is locked.

[0066]

[0069] For embodiments in which the PLL 110 includes an integrator path 220, this condition can be maintained by the integrator path 220 when the PLL 110 is locked. This is because the integrator path 220 adjusts the output frequency of the VCO 140 to reduce the voltage vtune to approximately zero at low frequencies, resulting in the condition Vs-Vref=0. The condition Vs-Vref=0 locks the phase error between the reference signal and the feedback signal to a fixed phase error based on the ratio of the capacitance of the first capacitor 530 to the capacitance of the second capacitor 540 (i.e., C1 and C2). Because this phase error is fixed, it has little or no effect on the ability of the PLL to maintain a VCO output frequency equal to the reference frequency multiplied by the desired division value.

[0067]

[0070] Charge sharing between the first capacitor 530 and the second capacitor 540 allows the reference voltage Vref to be set to a desired ratio of the supply voltage Vdd by appropriately setting the capacitance of the first capacitor 530 and / or the capacitance of the second capacitor 540 according to equation (5). In one embodiment, the reference voltage Vref can be set to a voltage that maximizes the gain of the sampler 130 when the condition Vs-Vref=0 is satisfied. In this embodiment, the gain of the sampler 130 can be maximized when the discharge time of the sampling capacitor 320 during the sampling phase is approximately equal to the RC time constant of the sampler 130. Substituting the RC time constant for the time t in equation (2) results in a voltage approximately equal to Vdd / e. Therefore, in this embodiment, the gain can be maximized by setting the voltage of the reference voltage Vref to approximately Vdd / e by appropriately setting the capacitance of the first capacitor 530 and / or the capacitance of the second capacitor 540 according to equation (5).

[0068]

[0071] 6 illustrates an exemplary implementation of a difference circuit 520 according to certain aspects. In this example, the difference circuit 520 includes a third switch 610 coupled between the first terminal 322 of the sampling capacitor 320 and the first terminal 532 of the first capacitor 530, and a fourth switch 620 coupled between the second terminal 534 of the first capacitor 530 and the output 134 of the sampler 130. In this example, the sampler 130 may also include a fifth switch 630 coupled between the second terminal 534 of the first capacitor 530 and ground. The fifth switch 630 may also be coupled between the second terminal 544 of the second capacitor 540 and ground, as shown in the example of FIG. 6.

[0069]

[0072] In this embodiment, a controller 360 controls the third switch 610, the fourth switch 620, and the fifth switch 630. In this regard, the controller 360 is coupled to a control input 612 of the third switch 610, a control input 622 of the fourth switch 620, and a control input 632 of the fifth switch 630. In this embodiment, the controller 360 is configured to control an on / off state of the third switch 610 via the control input 612, an on / off state of the fourth switch 620 via the control input 622, and an on / off state of the fifth switch 630 via the control input 632. Each of the third switch 610, the fourth switch 620, and the fifth switch 630 may be implemented using a transistor, a transmission gate, or another type of switch.

[0070]

[0073] In this example, the second pre-charge switch 550 is omitted because the first capacitor 530 can be pre-charged via the third switch 610 of the difference circuit 520, as discussed further below. However, it should be understood that in other implementations, the second pre-charge switch 550 can be included to pre-charge the first capacitor 530.

[0071]

[0074] During the precharge phase, the controller 360 turns on the precharge switch 325, the third switch 610, the fifth switch 630, and the second switch 570. The controller 360 turns off the fourth switch 620 and the first switch 560. During the precharge phase, the sampling capacitor 320 is precharged to the supply voltage Vdd through the precharge switch 325, the first capacitor 530 is precharged to the supply voltage Vdd through the precharge switch 325 and the third switch 610, and the second capacitor 540 is discharged to ground through the second switch 570 and the fifth switch 630. Therefore, during the precharge phase, the sampling capacitor 320 and the first capacitor 530 are both precharged to the supply voltage Vdd. In some implementations, the precharge switch 325 and the third switch 610 can be turned on synchronously.

[0072]

[0075] During the sampling phase, controller 360 turns off pre-charge switch 325 and turns off third switch 610. Discharge circuits 308-1 through 308-M discharge a portion of the charge on sampling capacitor 320 based on the phase error detected by phase detector 120 (not shown in FIG. 6) to generate a sampled voltage Vs (e.g., based on equation (4)).

[0073]

[0076] During the charge-sharing phase, the controller 360 turns off the second switch 570 and turns on the first switch 560. Turning on the first switch 560 allows charge sharing between the first capacitor 530 and the second capacitor 540, which generates the reference voltage Vref (e.g., based on equation (4)). During the charge-sharing phase, the controller 360 turns off the third switch 610 and the fourth switch 620, and turns on the fifth switch 630. In some implementations, the charge-sharing phase may overlap with the sampling phase. In other implementations, the charge-sharing phase may start after the end of the sampling phase. For example, the sampling phase may generate noise on the ground rail. To prevent noise on the ground rail from affecting the charge-sharing phase in this embodiment, the charge-sharing phase may start after the end of the sampling phase.

[0074]

[0077] During the differential phase, the controller 360 turns on the third switch 610 and the fourth switch 620 and turns off the fifth switch 630. This couples the first capacitor 530 in series with the sampling capacitor 320, and subtracts the reference voltage Vref on the first capacitor 530 from the sampled voltage Vs on the sampling capacitor 320 to obtain a voltage difference Vs-Vref at the output 134 of the sampler 130. During the differential phase, the precharge switch 325 and the second switch 570 are turned off. In some implementations, the first switch 560 can be turned on during the differential phase because the reference voltage is also present on the second capacitor 540 due to charge sharing. In other implementations, the first switch 560 can be turned off during the differential phase.

[0075]

[0078] By executing the above switching sequence once per cycle of the reference signal, the phase error can be sampled once per cycle of the reference signal. As described above, since the reference voltage Vref tracks the supply voltage variations, the voltage difference Vs-Vref improves the performance of the PLL 110 by countering the effects of cycle-to-cycle supply voltage variations.

[0076]

[0079] 7 illustrates an exemplary implementation of switches according to certain aspects of the disclosure. In this example, the precharge switch 325 is implemented using a p-type field effect transistor (PFET) 710, the second switch 570 is implemented using an n-type field effect transistor (NFET) 745, the fourth switch 620 is implemented using an NFET 740, and the fifth switch 630 is implemented using an NFET 750. Also in this example, the third switch 610 is implemented using a transmission gate including an NFET 722 and a PFET 727 coupled in parallel, and the first switch 560 is implemented using a transmission gate including an NFET 732 and a PFET 737 coupled in parallel.

[0077]

[0080] The control inputs of each of the switches 325, 570, 620, and 630 are located at the gates of the respective transistors. In the embodiment of FIG. 7, the control inputs of the switches 325, 570, 620, and 630 are driven by control signals preb, pre, ph4, and ph2, respectively, where preb and pre are complementary signals. The gates of the NFET 722 and PFET 727 in the third switch 610 are driven by complementary control signals ph3 and ph3b, respectively. The gates of the NFET 732 and PFET 737 in the first switch 560 are driven by complementary control signals ph1 and ph1b, respectively. These control signals are generated by the controller 360 (not shown in FIG. 7).

[0078]

[0081] 8 is a timing diagram illustrating an example of signals in the sampler 130 according to certain aspects of the disclosure. During time t1 to t2 (e.g., a precharge phase), the precharge switch 325 is turned on and the third switch 610 is turned on. As a result, the sampling capacitor 320 is precharged to the supply voltage Vdd via the precharge switch 325, thereby raising the voltage Vs on the sampling capacitor 320 to Vdd. Furthermore, the first capacitor 530 is precharged to the supply voltage Vdd via the precharge switch 325 and the third switch 610.

[0079]

[0082] In this embodiment, a rising edge 810 of the control signal preb triggers a falling edge 815 of the control signal ph3. This is done such that the third switch 610 is left on for a short period of time after the precharge switch 325 is turned off to help ensure that the voltages on the sampling capacitor 320 and the first capacitor 530 are approximately the same after precharge.

[0080]

[0083] Also, between times t1 and t2, the second switch 570 is turned on because the second switch 570, which in this embodiment is implemented using an NFET 745, is driven by a control signal pre (not shown in FIG. 8) that is the complement of the control signal preb. As a result, the second capacitor 540 is discharged to ground.

[0081]

[0084] During time t3 to t4 (e.g., a sampling phase), the discharge circuits 308-1 to 308-M discharge a portion of the charge on the sampling capacitor 320 based on the phase error detected by the phase detector 120 to generate a sampled voltage Vs indicative of the sampled phase error. In this example, k of the discharge circuits 308-1 to 308-M are driven by a first pulse (labeled “Pulse 1”) and the remaining discharge circuits 308-1 to 308-M (i.e., Mk of the discharge circuits 308-1 to 308-M) are driven by a second pulse (labeled “Pulse 2”) to perform phase interpolation, as described above with reference to FIG. 4 . In this example, the rising edge 820 of the first pulse and the rising edge 825 of the second pulse are separated by one cycle T of the VCO 140. VCO are spaced apart by an interval of

[0082]

[0085] At time t5, the first switch 560 is turned on to allow charge sharing between the first capacitor 530 and the second capacitor 540 to generate the reference voltage Vref (e.g., based on equation (5)). In one embodiment, the turning on of the first switch 560 may be triggered by a rising edge of a reference signal.

[0083]

[0086] At time t6, the fifth switch 630 is turned off, which disconnects the second terminal 534 of the first capacitor 530 and the second terminal 544 of the second capacitor 540 from ground, thereby floating the first capacitor 530 and the second capacitor 540. Also, the third switch 610 is turned on, which generates a voltage difference Vs-Vref.

[0084]

[0087] At time t7, the fourth switch 620 is turned on, thereby coupling the voltage difference Vs-Vref to the output 134 of the sampler 130. As a result, the voltage difference Vs-Vref is transferred to the output 134 of the sampler 130. At time t8, the fourth switch 620 is turned off to sample the phase error for the next cycle of the reference signal.

[0085]

[0088] 9 illustrates another exemplary implementation of phase detector 120 supporting phase interpolation according to a particular embodiment. In this embodiment, phase detector 120 includes a delay circuit 910, a number of multiplexers 950-1 to 950-M, and a number of flip-flops (FFs) 960-1 to 960-M.

[0086]

[0089] Each of the multiplexers 950-1 to 950-M has a first input 952-1 to 952-M, a second input 954-1 to 954-M, an output 956-1 to 956-M, and a selection input 958-1 to 958-M. The first input 952-1 to 952-M of each of the multiplexers 950-1 to 950-M is coupled to the second input 124 of the phase detector 120 and therefore receives a feedback signal. In FIG. 9, this feedback signal is referred to as "fb1" internally to the phase detector 120.

[0087]

[0090] The delay circuit 910 is coupled between the second input 124 of the phase detector 120 and the second inputs 954-1 to 954-M of each of the multiplexers 950-1 to 950-M. The delay circuit 910 is configured to delay the feedback signal (e.g., by a delay equal to about one cycle (i.e., period) of the VCO 140) and output the resulting delayed feedback signal (labeled “fb2”) to the second inputs 954-1 to 954-M of each of the multiplexers 950-1 to 950-M. In one embodiment, the delay circuit 910 may be implemented using a delay flip-flop clocked by the output signal of the VCO 140.

[0088]

[0091] The selection inputs 958-1 to 958-M of the multiplexers 950-1 to 950-M are each provided with a digital code d <m-1:0>As described above, the digital code d <m-1:0>controls the phase interpolation. Each of the multiplexers 950-1 to 950-M is configured to select a respective first input 952-1 to 952-M or a respective second input 954-1 to 954-M based on the bit value of the respective bit and couple the selected input to a respective output 956-1 to 956-M. Each of the multiplexers 950-1 to 950-M is therefore configured to select a feedback signal fb1 or a feedback signal fb2 based on the respective bit and output the selected feedback signal at a respective output 956-1 to 956-M.

[0089]

[0092] Each of the flip-flops 960-1 to 960-M has a respective signal input 962-1 to 962-M, a respective clock input 966-1 to 966-M, a respective reset input 968-1 to 968-M, and a respective output 964-1 to 964-M. Each of the signal inputs 962-1 to 962-M of the flip-flops 960-1 to 960-M is coupled to an output 956-1 to 956-M of a respective one of the multiplexers 950-1 to 950-M. Each of the multiplexers 950-1 to 950-M therefore outputs a digital code d <m-1:0>Based on each bit of the , it is controlled whether the feedback signal fb1 or the feedback signal fb2 is input to the signal inputs 962-1 to 962-M of the respective flip-flops 960-1 to 960-M.

[0090]

[0093] Respective clock inputs 966-1 to 966-M of flip-flops 960-1 to 960-M receive a clock signal (labeled "clk"). In a particular aspect, the clock signal may be an output signal of VCO 140. Respective reset inputs 968-1 to 968-M of flip-flops 960-1 to 960-M are coupled to first inputs 122 of phase detector 120 and therefore receive the reference signal. In a particular aspect, each flip-flop 960-1 to 960-M is configured to reset a respective output 964-1 to 964-M to zero on a rising edge of the reference signal. Respective outputs 964-1 to 964-M of flip-flops 960-1 to 960-M are coupled to respective ones of outputs 126-1 to 126-M of phase detector 120, which in turn are coupled to the gates of transistors 310-1 to 310-M of respective ones of discharge circuits 308-1 to 308-M.

[0091]

[0094] In operation, each of multiplexers 950-1 through 950-M outputs a digital code d <m-1:0>The feedback signal fb1 or the feedback signal fb2 is selected based on each bit of the flip-flops 960-1 to 960-M, and the selected feedback signal is output to the signal inputs 962-1 to 962-M of the flip-flops 960-1 to 960-M, respectively.

[0092]

[0095] Each of the flip-flops 960-1 to 960-M retimes the selected feedback signal from each of the multiplexers 950-1 to 950-M with the clock signal and outputs the rising edge of the respective pulse at an edge of the retimed feedback signal. The edge of the retimed feedback signal may be a rising edge or a falling edge. Each of the flip-flops 960-1 to 960-M then outputs the falling edge of the respective pulse at a rising edge of a reference signal received at a respective reset input 968-1 to 968-M. This is because each of the flip-flops 960-1 to 960-M is configured to reset a respective output 964-1 to 964-M to zero at a rising edge of the reference signal.

[0093]

[0096] The pulse from each of the flip-flops 960-1 to 960-M drives the gate of a transistor 310-1 to 310-M in a respective one of the discharge circuits 308-1 to 308-M. In this embodiment, the digital code d <m-1:0>controls the number of transistors 310-1 to 310-M driven by pulses generated from the feedback signal fb1 and the number of transistors 310-1 to 310-M driven by pulses generated from the feedback signal fb2. This is done by the digital code d <m-1:0>This is because the number of flip-flops 960-1 to 960-M that receive the feedback signal fb1 and the number of flip-flops 960-1 to 960-M that receive the feedback signal fb2 are controlled. <m-1:0>A phase interpolation of the feedback signal fb1 and the feedback signal fb2 is provided, the phase interpolation being controlled by:

[0094]

[0097] Digital Code D <m-1:0>can be generated by the PI control circuit 470, described above in accordance with certain embodiments with reference to FIG. 4. As described above, the PI control circuit 470 adjusts the digital code d <m-1:0>can be generated.

[0095]

[0098] In the above example, delay circuit 910 may have a delay of approximately one cycle of VCO 140 and may be implemented using a delay flip-flop clocked by the output of VCO 140. However, it should be understood that delay circuit 910 is not limited to this example. In other implementations, delay circuit 910 may have a delay approximately equal to two cycles of VCO 140, or another multiple of a cycle of VCO 140.

[0096]

[0099] FIG. 10 illustrates a wireless device 1010 that can use an example PLL 110, according to certain aspects. The wireless device 1010 may include a transmitter 1030 and a receiver 1035 for wireless communication (e.g., with a base station). The wireless device 1010 may also include a baseband processor 1070, a radio frequency (RF) coupling circuit 1025, an antenna 1015, a reference signal generator 1090, a first PLL 1080, and a second PLL 1085. Although one transmitter 1030, one receiver 1035, and one antenna 1015 are shown in FIG. 10, it should be understood that the wireless device 1010 may include any number of transmitters, receivers, and antennas.

[0097]

[0100] In the embodiment of FIG. 10, the transmitter 1030 has an input 1032 coupled to the baseband processor 1070 and an output 1034 coupled to the antenna 1015 via the RF coupling circuit 1025. The transmitter 1030 may include a mixer 1040 and a power amplifier 1045. The mixer 1040 is coupled between the input 1032 and the power amplifier 1045, which is coupled between the mixer 1040 and the output 1034. In one embodiment, the mixer 1040 is configured to receive a baseband signal from the baseband processor 1070 via the input 1032 and frequency upconvert the baseband signal to an RF transmit signal by mixing the baseband signal with a local oscillator signal. The power amplifier 1045 is configured to amplify the RF transmit signal and output the amplified RF transmit signal at the output 1034 for transmission via the antenna 1015. It should be understood that the transmitter 1030 may include one or more additional components not shown in Figure 10. For example, in some implementations, the transmitter 1030 may include one or more filters, phase shifters, and / or one or more additional amplifiers in the signal path between the input 1032 and the output 1034 of the transmitter 1030.

[0098]

[0101] In the embodiment of FIG. 10, the receiver 1035 has an input 1036 coupled to the antenna 1015 via the RF coupling circuitry 1025 and an output 1038 coupled to the baseband processor 1070. The receiver 1035 may include a low noise amplifier 1050 and a mixer 1055. The low noise amplifier 1050 is coupled between the input 1036 and the mixer 1055, and the mixer 1055 is coupled between the low noise amplifier 1050 and the output 1038. In one embodiment, the low noise amplifier 1050 is configured to receive an RF signal from the antenna 1015 via the RF coupling circuitry 1025, amplify the RF signal, and output the amplified RF signal to the mixer 1055. The mixer 1055 is configured to frequency downconvert the RF signal to a baseband signal by mixing the RF signal with a local oscillator signal. It should be appreciated that the receiver 1035 may include one or more additional components not shown in FIG. 10. For example, in some implementations, the receiver 1035 may include one or more filters, phase shifters, and / or one or more additional amplifiers in the signal path between the input 1036 and the output 1038 of the receiver 1035.

[0099]

[0102] The RF coupling circuit 1025 is coupled between an output 1034 of the transmitter 1030 and the antenna 1015. The RF coupling circuit 1025 is also coupled between the antenna 1015 and an input 1036 of the receiver 1035. In one embodiment, the RF coupling circuit 1025 may be implemented with a duplexer configured to couple an RF signal from the output 1034 of the transmitter 1030 to the antenna 1015 and to couple an RF signal received from the antenna 1015 to the input 1036 of the receiver 1035. In other implementations, the RF coupling circuit 1025 may include one or more switches configured to couple the transmitter 1030 and the receiver 1035 to the antenna 1015 one at a time.

[0100]

[0103] The reference signal generator 1090 is configured to generate and output a reference signal for the first PLL 1080 and the second PLL 1085. The reference signal generator 1090 may include a crystal oscillator or another type of circuit configured to generate a reference signal.

[0101]

[0104] The first PLL 1080 is coupled between the reference signal generator 1090 and the mixer 1040 of the transmitter 1030. The first PLL 1080 is configured to receive a reference signal from the reference signal generator 1090 and generate a local oscillator signal for the mixer 1040 by multiplying the frequency of the reference signal. The first PLL 1080 can be implemented using the exemplary PLL 110 according to any one or more of the aspects shown in FIGS. 1-9, where the first input 122 is coupled to the reference signal generator 1090 to receive the reference signal and the output 112 is coupled to the mixer 1040.

[0102]

[0105] The second PLL 1085 is coupled between the reference signal generator 1090 and the mixer 1055 of the receiver 1035. The second PLL 1085 is configured to receive a reference signal from the reference signal generator 1090 and generate a local oscillator signal for the mixer 1055 by multiplying the frequency of the reference signal. The second PLL 1085 can be implemented using the exemplary PLL 110 according to any one or more of the aspects shown in FIGS. 1-9, where the first input 122 is coupled to the reference signal generator 1090 to receive the reference signal and the output 112 is coupled to the mixer 1055.

[0103]

[0106] 11 is a diagram of an environment 1100 including an electronic device 1102 and a base station 1104. The electronic device 1102 includes a wireless transceiver 1196, which may include the example transmitter 1030, receiver 1035, and PLL 1080 and PLL 1085 shown in FIG. 10. In certain aspects, the electronic device 1102 may correspond to the wireless device 1010 shown in FIG.

[0104]

[0107] Within the environment 1100, an electronic device 1102 communicates with a base station 1104 via a wireless link 1106. As illustrated, the electronic device 1102 is shown as a smartphone. However, the electronic device 1102 may be implemented as any suitable computing device or other electronic device, such as a cellular base station, a broadband router, an access point, a cellular or mobile phone, a gaming device, a navigation device, a media device, a laptop computer, a desktop computer, a tablet computer, a server computer, a network-attached storage (NAS) device, a smart appliance, a vehicle-based communication system, an Internet of Things (IoT) device, a sensor or security device, an asset tracker, or the like.

[0105]

[0108] The base station 1104 communicates with the electronic device 1102 via a wireless link 1106, which may be implemented as any suitable type of wireless link. Although shown as a base station tower of a cellular wireless network, the base station 1104 may represent or be implemented as another device, such as a satellite, a terrestrial broadcast tower, an access point, a peer-to-peer device, a mesh network node, a fiber optic line, or another electronic device generally as described above. Thus, the electronic device 1102 may communicate with the base station 1104 or another device via a wired connection, a wireless connection, or a combination thereof. The wireless link 1106 may include a downlink of data or control information communicated from the base station 1104 to the electronic device 1102, and an uplink of other data or control information communicated from the electronic device 1102 to the base station 1104. The wireless link 1106 may be implemented using any suitable communications protocol or standard, such as 3rd Generation Partnership Project Long-Term Evolution (3GPP® LTE®, 3GPP NR 5G), IEEE 802.11, IEEE 802.11, Bluetooth®, etc.

[0106]

[0109] The electronic device 1102 includes a processor 1180 and a memory 1182. The memory 1182 may be part of or form a part of a computer-readable storage medium. The processor 1180 may include any type of processor, such as an application processor or a multi-core processor, configured to execute processor-executable instructions (e.g., code) stored by the memory 1182. The memory 1182 may include any suitable type of data storage medium, such as volatile memory (e.g., random access memory (RAM)), non-volatile memory (e.g., flash memory), optical media, magnetic media (e.g., disk or tape), etc. In the context of the present disclosure, the memory 1182 is implemented to store instructions 1184, data 1186, and other information for the electronic device 1102.

[0107]

[0110] The electronic device 1102 may also include input / output (I / O) ports 1190. The I / O ports 1190 enable data exchange or interaction with other devices, networks, or users, or between components of the device.

[0108]

[0111] The electronic device 1102 may further include a signal processor (SP) 1192 (e.g., a digital signal processor (DSP), etc.), which may function similarly to the processor 1180 and may be capable of executing instructions and / or processing information in conjunction with the memory 1182.

[0109]

[0112] For communication purposes, the electronic device 1102 also includes a modem 1194, a wireless transceiver 1196, and one or more antennas (e.g., antenna 1015). The wireless transceiver 1196 provides connectivity to a respective network and to other electronic devices connected to that network using RF wireless signals. The wireless transceiver 1196 may facilitate communication over any suitable type of wireless network, such as a wireless local area network (LAN) (wireless local area network (WLAN)), a peer to peer (P2P) network, a mesh network, a cellular network, a wireless wide area network (WWAN), a navigation network (e.g., a North American Global Positioning System (GPS) or another Global Navigation Satellite System (GNSS)), and / or a wireless personal area network (WPAN).

[0110]

[0113] 12 illustrates a method 1200 of sampling in accordance with certain aspects. The method 1200 may be performed by the sampler 130.

[0111]

[0114] At block 1210, a sampling capacitor is charged to a supply voltage. For example, the sampling capacitor (e.g., sampling capacitor 320) may be charged to a supply voltage (e.g., Vdd) by turning on a pre-charge switch (e.g., pre-charge switch 325) coupled between the supply voltage and the sampling capacitor. The pre-charge switch may be turned on by controller 360. The supply voltage may be provided by voltage regulator 340.

[0112]

[0115] At block 1220, a portion of the charge on the sampling capacitor is discharged based on the phase error to generate a sampling voltage. For example, the sampling capacitor may be discharged by one or more discharge circuits (e.g., discharge circuits 308-1 through 308-M) based on the phase error. The phase error may be a phase error between a reference signal and a feedback signal of a phase-locked loop (PLL). The feedback signal may be generated by dividing an output signal of a VCO (e.g., VCO 140) of the PLL.

[0113]

[0116] At block 1230, a reference voltage is generated based on the supply voltage. For example, the reference voltage may be generated by the reference voltage circuit 515.

[0114]

[0117] At block 1240, a difference voltage between the sampled voltage and the reference voltage is generated. For example, this difference voltage may be generated by the difference circuit 520.

[0115]

[0118] In certain aspects, discharging a portion of the charge on the sampling capacitor based on the phase error may include receiving a phase error signal indicative of the phase error and driving one or more discharge circuits with the phase error signal, the one or more discharge circuits being coupled to the sampling capacitor. In one embodiment, each of the one or more discharge circuits includes a respective transistor (e.g., a respective one of transistors 310-1 through 310-M) and a respective resistor (e.g., a respective one of resistors 315-1 through 315-M) coupled between the sampling capacitor and the respective transistor. In this embodiment, the phase error signal may include one or more pulses (e.g., pulse 1 and / or pulse 2 of FIG. 8), where a rising edge of the first pulse and a rising edge of the second pulse are separated by one or more cycles of the VCO 140. In this embodiment, as described above, in order to cancel out the quantization error, k gates of transistors 310-1 to 310-M are driven by a first pulse and Mk gates of transistors 310-1 to 310-M are driven by a second pulse based on the DSM error signal.

[0116]

[0119] In certain aspects, generating the reference voltage may include charging a first capacitor (e.g., first capacitor 530) to a supply voltage, discharging a second capacitor (e.g., second capacitor 540), and sharing charge between the first capacitor and the second capacitor to generate the reference voltage. For example, the charge sharing may include turning on a switch (e.g., first switch 560) coupled between the first capacitor 530 and the second capacitor 540. In one embodiment, charging of the first capacitor overlaps in time with charging of the sampling capacitor such that variations in the supply voltage over time are at least partially tracked in the reference voltage.

[0117]

[0120] In certain aspects, generating a difference voltage between the sampling voltage and the reference voltage may include turning on a first switch (e.g., the third switch 610) coupled between the sampling capacitor (e.g., the sampling capacitor 320) and a first terminal (e.g., the first terminal 532) of the first capacitor (e.g., the first capacitor 530) and turning on a second switch (e.g., the fourth switch 620) coupled between an output (e.g., the output 134) of the sampler (e.g., the sampler 130) and a second terminal (e.g., the second terminal 534) of the first capacitor. In these aspects, charging the first capacitor to the supply voltage may include turning on a pre-charge switch (e.g., the pre-charge switch 325) coupled between the supply voltage and the sampling capacitor and turning on the first switch (e.g., the third switch 610).

[0118]

[0121] In certain aspects, generating a difference voltage between the sampled voltage and the reference voltage may include subtracting the reference voltage from the sampled voltage.

[0119]

[0122] It should be understood that the present disclosure is not limited to the exemplary terminology used above to describe aspects of the present disclosure. For example, a phase detector may also be referred to as a phase comparator, a phase frequency detector (PFD), or other terms. A divider may also be referred to as a divide-by-N circuit, or other terms. A division ratio of a divider may also be referred to as a divisor, or other terms.

[0120]

[0123] The controller 360 and the PI control circuit 470 may each be implemented using a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete hardware components (e.g., logic gates), or any combination thereof, designed to perform the functions described herein. The functions described herein may be performed by a processor executing software comprising codes for performing those functions. The software may be stored on a computer-readable storage medium, such as a RAM, a ROM, an EEPROM, an optical disk, and / or a magnetic disk.

[0121]

[0124] Example implementations are described in the following numbered clauses:

[0125] 1. A sampler comprising:

[0126] A sampling capacitor;

[0127] a precharge switch coupled to the sampling capacitor;

[0128] one or more discharge circuits coupled to the sampling capacitor;

[0129] a reference voltage circuit coupled to the sampling capacitor,

[0130] generating a reference voltage based on a supply voltage;

[0131] a reference voltage circuit configured to generate a voltage difference between a voltage on the sampling capacitor and a reference voltage.

[0132] 2. The sampler of clause 1, wherein the pre-charge switch is coupled between the voltage regulator and the sampling capacitor, the voltage regulator being configured to provide the supply voltage.

[0133] 3. Each of the one or more discharge circuits is

[0134] Each transistor,

[0135] 3. The sampler of clause 1 or 2, comprising a sampling capacitor and a respective resistor coupled between the respective transistor.

[0136] 4. The sampler of clause 3, wherein for each of the one or more discharge circuits, a gate of the respective transistor is coupled to a phase detector.

[0137] 5. The reference voltage circuit is

[0138] at least one capacitor;

[0139] 5. The sampler of any one of clauses 1 to 4, comprising: a sampling capacitor; and a differential circuit coupled to the at least one capacitor, the differential circuit configured to generate a voltage difference.

[0140] 6. A method for switching a power supply voltage on a power supply, comprising:

[0141] a first capacitor coupled to the differential circuit;

[0142] and a second capacitor, wherein the first switch is coupled between the first capacitor and the second capacitor, and the second switch is coupled in parallel with the second capacitor.

[0143] 7. One or more discharge circuits are coupled to the phase detector;

[0144] a difference circuit coupled to the filter;

[0145] A sampler of clause 5 or 6.

[0146] 8. An apparatus comprising:

[0147] A sampling capacitor;

[0148] a precharge switch coupled to the sampling capacitor;

[0149] one or more discharge circuits coupled to the sampling capacitor;

[0150] a reference voltage circuit coupled to the sampling capacitor,

[0151] A first capacitor;

[0152] A second capacitor;

[0153] a first switch coupled between the first capacitor and the second capacitor;

[0154] a second switch coupled in parallel with the second capacitor;

[0155] and a reference voltage circuit comprising a difference circuit coupled to the sampling capacitor and the first capacitor.

[0156] 9. The apparatus of clause 8, further comprising a voltage regulator, the pre-charge switch being coupled between the voltage regulator and the sampling capacitor.

[0157] 10. The apparatus of clause 8 or 9, further comprising a controller, wherein during a precharge phase, the controller is configured to turn on the precharge switch, turn off the first switch, and turn on the second switch.

[0158] 11. The apparatus of clause 10, wherein in a charge sharing phase, the controller is configured to turn off the pre-charge switch, turn on the first switch, and turn off the second switch.

[0159] 12. A differential circuit is

[0160] a third switch coupled between the sampling capacitor and the first terminal of the first capacitor;

[0161] 10. The apparatus of clause 8 or 9, comprising: a fourth switch coupled between the second terminal of the first capacitor and the output of the sampler.

[0162] 13. The apparatus of clause 12, further comprising a controller, wherein during a precharge phase, the controller is configured to turn on the precharge switch, turn off the first switch, turn on the second switch, turn on the third switch, and turn off the fourth switch.

[0163] 14. The apparatus of clause 13, wherein during a charge sharing phase, the controller is configured to turn off the pre-charge switch, turn on the first switch, turn off the second switch, turn off the third switch, and turn off the fourth switch.

[0164] 15. The apparatus of clause 13 or 14, wherein during a sampling phase, the controller is configured to turn off the pre-charge switch, turn off the third switch, and turn off the fourth switch.

[0165] 16. The apparatus of any one of clauses 13-15, wherein in a differential phase, the controller is configured to turn off the precharge switch, turn off the second switch, turn on the third switch, and turn on the fourth switch.

[0166] 17. The apparatus of any one of clauses 12-16, wherein the reference voltage circuit further comprises a fifth switch coupled between the second terminal of the first capacitor and ground.

[0167] 18. The apparatus of clause 8, further comprising a second pre-charge switch coupled to the first capacitor.

[0168] 19. The apparatus of clause 18, further comprising a voltage regulator, a first pre-charge switch coupled between the voltage regulator and the sampling capacitor, and a second pre-charge switch coupled between the voltage regulator and the first capacitor.

[0169] 20. The apparatus of clause 18 or 19, further comprising a controller, wherein during a precharge phase, the controller is configured to turn on the first precharge switch, turn on the second precharge switch, turn off the first switch, and turn on the second switch.

[0170] 21. The apparatus of clause 20, wherein during a charge sharing phase, the controller is configured to turn off the first pre-charge switch, turn off the second pre-charge switch, turn on the first switch, and turn off the second switch.

[0171] 22. The apparatus of any one of clauses 8 to 21, further comprising a phase detector having an output coupled to one or more discharge circuits.

[0172] 23. Voltage controlled oscillator (VCO) and

[0173] a loop filter coupled between the difference circuit and the input of the VCO;

[0174] a frequency divider coupled between the output of the VCO and the input of the phase detector.

[0175] Apparatus of clause 22.

[0176] 24. The apparatus of clause 23, wherein the loop filter comprises an integration path coupled between the difference circuit and the input of the VCO.

[0177] 25. A phase detector having a first input configured to receive a reference signal and a second input configured to receive a feedback signal, the phase detector comprising:

[0178] a delay circuit having an input coupled to the second input of the phase detector and an output;

[0179] a first pulse circuit having a first input coupled to the first input of the phase detector, a second input coupled to the second input of the phase detector, and an output;

[0180] a second pulse circuit having a first input coupled to the first input of the phase detector, a second input coupled to the output of the delay circuit, and an output;

[0181] 25. The apparatus of any one of clauses 22-24, comprising a plurality of multiplexers, each multiplexer having a first input coupled to the output of the first pulse circuit, a second input coupled to the output of the second pulse circuit, and an output coupled to a respective one of the one or more discharge circuits.

[0182] 26. The apparatus of clause 25, wherein each multiplexer comprises a selection input configured to receive a respective bit of the digital code, and each multiplexer is configured to select either a respective first input or a respective second input of the multiplexer based on a bit value of the respective bit, and to couple the selected input to a respective output.

[0183] 27. Voltage controlled oscillator (VCO) and

[0184] a loop filter coupled between the difference circuit and the input of the VCO;

[0185] a frequency divider coupled between the output of the VCO and the second input of the phase detector.

[0186] Devices according to clauses 25 or 26.

[0187] 28. A phase detector having a first input configured to receive a reference signal and a second input configured to receive a feedback signal, the phase detector comprising:

[0188] a delay circuit having an input coupled to the second input of the phase detector and an output;

[0189] a plurality of multiplexers, each multiplexer having a first input coupled to the second input of the phase detector, a second input coupled to the output of the delay circuit, and an output;

[0190] 25. The apparatus of any one of clauses 22-24, comprising a plurality of flip-flops, each flip-flop having a signal input coupled to an output of a respective one of the plurality of multiplexers, a reset input coupled to a first input of the phase detector, a clock input configured to receive a clock signal, and an output coupled to a respective one of the one or more discharge circuits.

[0191] 29. The apparatus of clause 28, wherein the clock signal comprises an output signal of a voltage controlled oscillator (VCO).

[0192] 30. The apparatus of clause 28 or 29, wherein each multiplexer comprises a selection input configured to receive a respective bit of the digital code, and each multiplexer is configured to select either a respective first input or a respective second input of the multiplexer based on the bit value of the respective bit, and to couple the selected input to a respective output.

[0193] 31. A voltage controlled oscillator (VCO) and

[0194] a loop filter coupled between the difference circuit and the input of the VCO;

[0195] a frequency divider coupled between the output of the VCO and the second input of the phase detector.

[0196] Any one of the devices in clauses 28 to 30.

[0197] 32. Each of one or more discharge circuits:

[0198] Each transistor,

[0199] The apparatus of any one of clauses 8-31, comprising a respective resistor coupled between the sampling capacitor and the respective transistor.

[0200] 33. The apparatus of clause 32, further comprising a phase detector, and for each of the one or more discharge circuits, a gate of a respective transistor is coupled to an output of the phase detector.

[0201] 34. A phase detector having a first input, a second input, and an output, the first input configured to receive a reference signal, and the output coupled to one or more discharge circuits;

[0202] A voltage controlled oscillator (VCO) and

[0203] a loop filter coupled between the difference circuit and the input of the VCO;

[0204] a frequency divider coupled between the output of the VCO and a second input of the phase detector, the frequency divider configured to divide the output signal of the VCO to generate the feedback signal.

[0205] Any one of the devices of clauses 8 to 21, 32 and 33.

[0206] 35. The apparatus of clause 34, wherein the phase detector is configured to generate a phase error signal indicative of a phase error between the reference signal and the feedback signal.

[0207] 36. The apparatus of clause 35, wherein the phase error signal comprises one or more pulses, and each of the one or more discharge circuits is driven by one of the one or more pulses.

[0208] 37. The apparatus of clause 36, wherein the one or more pulses comprise a first pulse and a second pulse, and the phase detector is configured to selectively output the first pulse or the second pulse to each of the one or more discharge circuits.

[0209] 38. The phase detector comprises a delay circuit configured to generate a delayed feedback signal based on the feedback signal;

[0210] the phase detector is further configured to generate a first pulse based on a phase error between the reference signal and the feedback signal, and to generate a second pulse based on a phase error between the reference signal and the delayed feedback signal.

[0211] Apparatus of Article 37.

[0212] 39. A method of sampling comprising the steps of:

[0213] charging a sampling capacitor to a supply voltage;

[0214] discharging a portion of the charge on the sampling capacitor based on the phase error to generate a sampling voltage;

[0215] generating a reference voltage based on a supply voltage;

[0216] generating a difference voltage between the sampled voltage and a reference voltage.

[0217] 40. The method of clause 39, wherein generating the reference voltage comprises charging at least one capacitor to a supply voltage.

[0218] 41. Discharging a portion of the charge on the sampling capacitor based on the phase error;

[0219] receiving a phase error signal indicative of a phase error;

[0220] 41. The method of clause 39 or 40, comprising driving one or more discharge circuits with the phase error signal, the one or more discharge circuits being coupled to the sampling capacitor.

[0221] 42. Each of one or more discharge circuits:

[0222] Each transistor,

[0223] 42. The method of clause 41, comprising a respective resistor coupled between the sampling capacitor and the respective transistor.

[0224] 43. The method of clause 42, wherein the phase error signal comprises one or more pulses, and wherein a transistor of each of the one or more discharge circuits is driven by one of the one or more pulses.

[0225] 44. Generating a reference voltage

[0226] charging a first capacitor to a supply voltage;

[0227] Discharging the second capacitor; and

[0228] 44. The method of any one of clauses 39-43, comprising sharing a charge between the first capacitor and the second capacitor to generate the reference voltage.

[0229] 45. Generating a difference voltage between a sampling voltage and a reference voltage

[0230] turning on a first switch coupled between the sampling capacitor and the first terminal of the first capacitor;

[0231] and turning on a second switch coupled between an output of the sampler and a second terminal of the first capacitor.

[0232] 46. ​​Charging a first capacitor to a supply voltage

[0233] turning on a precharge switch coupled between a supply voltage and the sampling capacitor;

[0234] and turning on the first switch.

[0235] 47. The method of any one of clauses 39-46, wherein generating a difference voltage between the sampled voltage and the reference voltage comprises subtracting the reference voltage from the sampled voltage.

[0236] 48. An apparatus for sampling comprising:

[0237] means for charging a sampling capacitor to a supply voltage;

[0238] means for discharging a portion of the charge on the sampling capacitor based on the phase error to generate a sampling voltage;

[0239] means for generating a reference voltage based on a supply voltage;

[0240] and means for generating a difference voltage between the sampled voltage and a reference voltage.

[0241] 49. The apparatus of clause 48, wherein the means for generating the reference voltage comprises means for charging at least one capacitor to the supply voltage.

[0122]

[0242] Within the scope of this disclosure, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" should not necessarily be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the discussed feature, advantage, or mode of operation. The term "coupled" is used herein to refer to a direct or indirect electrical coupling between two structures. It should also be understood that the term "ground" can refer to a DC ground or an alternating current (AC) ground, and therefore the term "ground" encompasses both possibilities.

[0123]

[0243] The above description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: A sampling capacitor; a precharge switch coupled to the sampling capacitor; one or more discharge circuits coupled to the sampling capacitor; a reference voltage circuit coupled to the sampling capacitor, wherein the reference voltage circuit A first capacitor; A second capacitor; a first switch coupled between the first capacitor and the second capacitor; a second switch coupled in parallel with the second capacitor; a difference circuit coupled to the sampling capacitor and the first capacitor. An apparatus comprising:

2. a voltage regulator, wherein the pre-charge switch is coupled between the voltage regulator and the sampling capacitor; or a controller, wherein in a pre-charge phase, the controller is configured to turn on the pre-charge switch, turn off the first switch, and turn on the second switch, and in a charge sharing phase, the controller is configured to turn off the pre-charge switch, turn on the first switch, and turn off the second switch; The apparatus of claim 1 further comprising:

3. The difference circuit is a third switch coupled between the sampling capacitor and the first terminal of the first capacitor; 2. The apparatus of claim 1 , further comprising: a fourth switch coupled between a second terminal of the first capacitor and an output of the apparatus.

4. a controller configured to turn on the precharge switch, turn off the first switch, turn on the second switch, turn on the third switch, and turn off the fourth switch in a precharge phase; or, during a charge sharing phase, the controller is configured to turn off the pre-charge switch, turn on the first switch, turn off the second switch, turn off the third switch, and turn off the fourth switch; or or during a sampling phase, the controller is configured to turn off the pre-charge switch, turn off the third switch, and turn off the fourth switch; or 4. The apparatus of claim 3, wherein in a differential phase, the controller is configured to turn off the precharge switch, turn off the second switch, turn on the third switch, and turn on the fourth switch.

5. 4. The apparatus of claim 3, wherein the reference voltage circuit further comprises a fifth switch coupled between the second terminal of the first capacitor and ground.

6. a second pre-charge switch coupled to the first capacitor; a voltage regulator, the first pre-charge switch being coupled between the voltage regulator and the sampling capacitor, and the second pre-charge switch being coupled between the voltage regulator and the first capacitor; or a controller, wherein during a precharge phase, the controller is configured to turn on the first precharge switch, turn on the second precharge switch, turn off the first switch, and turn on the second switch; or 2. The apparatus of claim 1, wherein during a charge sharing phase, the controller is configured to turn off the first pre-charge switch, turn off the second pre-charge switch, turn on the first switch, and turn off the second switch.

7. The apparatus of claim 1 , further comprising a phase detector having an output coupled to the one or more discharge circuits.

8. A voltage controlled oscillator (VCO); a loop filter coupled between the difference circuit and an input of the VCO; a frequency divider coupled between the output of the VCO and the input of the phase detector; The apparatus of claim 7 further comprising:

9. The phase detector has a first input configured to receive a reference signal and a second input configured to receive a feedback signal, the phase detector comprising: a delay circuit having an input coupled to the second input of the phase detector and an output; a first pulse circuit having a first input coupled to the first input of the phase detector, a second input coupled to the second input of the phase detector, and an output; a second pulse circuit having a first input coupled to the first input of the phase detector, a second input coupled to the output of the delay circuit, and an output; a plurality of multiplexers, each multiplexer having a first input coupled to the output of the first pulse circuit, a second input coupled to the output of the second pulse circuit, and an output coupled to a respective one of the one or more discharge circuits; Equipped with 8. The apparatus of claim 7, wherein each multiplexer comprises a selection input configured to receive a respective bit of a digital code, and each multiplexer is configured to select either the respective first input or the respective second input of the multiplexer based on a bit value of the respective bit, and to couple the selected input to the respective output.

10. The phase detector has a first input configured to receive a reference signal and a second input configured to receive a feedback signal, the phase detector comprising: a delay circuit having an input coupled to the second input of the phase detector and an output; a plurality of multiplexers, each multiplexer having a first input coupled to the second input of the phase detector, a second input coupled to the output of the delay circuit, and an output; a plurality of flip-flops, each flip-flop having a signal input coupled to the output of a respective one of the plurality of multiplexers, a reset input coupled to the first input of the phase detector, a clock input configured to receive a clock signal, and an output coupled to a respective one of the one or more discharge circuits. Equipped with 8. The apparatus of claim 7, wherein each multiplexer comprises a selection input configured to receive a respective bit of a digital code, and each multiplexer is configured to select either the respective first input or the respective second input of the multiplexer based on a bit value of the respective bit, and to couple the selected input to the respective output.

11. Each of the one or more discharge circuits: Each transistor, a respective resistor coupled between the sampling capacitor and the respective transistor; 2. The apparatus of claim 1, further comprising a phase detector, for each of the one or more discharge circuits, a gate of the respective transistor coupled to an output of the phase detector.

12. a phase detector having a first input, a second input, and an output, wherein the first input is configured to receive a reference signal, and the output is coupled to the one or more discharge circuits; A voltage controlled oscillator (VCO); a loop filter coupled between the difference circuit and an input of the VCO; a frequency divider coupled between an output of the VCO and the second input of the phase detector, wherein the frequency divider is configured to divide the output signal of the VCO to generate a feedback signal. The apparatus of claim 1 further comprising:

13. A method of sampling comprising the steps of: charging a sampling capacitor to a supply voltage; discharging a portion of the charge on the sampling capacitor based on a phase error to generate a sampling voltage; generating a reference voltage based on the supply voltage; generating a difference voltage between the sampled voltage and the reference voltage; generating the reference voltage charging a first capacitor to the supply voltage; discharging the second capacitor; sharing charge between the first capacitor and the second capacitor to generate the reference voltage; A method comprising:

14. generating the reference voltage comprises charging at least one capacitor to the supply voltage; or The method of claim 13 , wherein generating the difference voltage between the sampled voltage and the reference voltage comprises subtracting the reference voltage from the sampled voltage.

15. generating the difference voltage between the sampled voltage and the reference voltage; turning on a first switch coupled between the sampling capacitor and a first terminal of the first capacitor; turning on a second switch coupled between an output of the sampler and a second terminal of the first capacitor; charging the first capacitor to the supply voltage comprises: turning on a pre-charge switch coupled between the supply voltage and the sampling capacitor; turning on the first switch; The method of claim 13 comprising:

Images