Method and system for high precision, low Allan deviation atomic clocks

Abstract

The system includes a digital processing circuit (325), a frequency modulator (360), an amplitude modulator (370), and an adder (390). The digital processing circuit (325) receives an input signal and a correlation signal and generates a frequency tuning parameter and an amplitude modulation parameter. The frequency modulator (360) generates a frequency modulation signal and a correlation signal. The amplitude modulator (370) receives the amplitude modulation parameter and generates an amplitude modulation signal. The adder (390) receives the frequency tuning parameter and the frequency modulation signal and generates a control signal. In some implementations, the system further includes a DC feedback circuit (330) that receives the input signal and generates a DC compensation signal. In some implementations, the system further includes a temperature sensor (345), a temperature compensation circuit (360), and a second adder (355).

Description

[Background technology]

[0001] Molecular clocks are used to generate highly accurate clock signals for global positioning systems, global navigation satellite systems, and high-capacity, high-density, and low-latency wireless access networks, among others. For molecular clocks using radio frequency (RF) signals, reflections at the physical cell of the molecular clock or frequency modulation to amplitude modulation (FM to AM) conversion by the transmitter of the molecular clock can result in frequency-dependent variations, called bias (also known as tilt), in the signal output by the physical cell detector. The sensitivity of the bias to process, voltage, and temperature variations can correspondingly cause the tuning frequency of the molecular clock to deviate from the absorption frequency of the physical cell. To address this issue, some molecular clocks reduce their sensitivity to bias by correlating with higher odd harmonics of the frequency modulated signal, which results in a smaller signal-to-noise ratio compared to correlating with the fundamental. Also, some sensitivity to bias remains, which can affect the frequency precision and Allan deviation of the molecular clock. Summary of the Invention

[0002] The system includes a digital processing circuit, a frequency modulator, an amplitude modulator, and a summer. The digital processing circuit receives an input signal and a correlation signal and generates a frequency tuning parameter and an amplitude modulation parameter. The frequency modulator generates a frequency modulation signal and a correlation signal. The amplitude modulator receives the amplitude modulation parameter and generates an amplitude modulation signal. The summer receives the frequency tuning parameter and the frequency modulation signal and generates a control signal.

[0003] In some implementations, the system further includes a DC feedback circuit that receives the input signal and generates a DC compensation signal. In some implementations, the summer is a first summer, and the system further includes a temperature sensor, a temperature compensation circuit, and a second summer. The temperature sensor measures a system temperature and provides the system temperature to the temperature compensation circuit, which generates the temperature compensation signal. The second summer receives the temperature compensation signal and the frequency tuning parameter, generates a modified frequency tuning parameter, and provides it to the first summer.

[0004] The system includes a molecular clock in some implementations, the molecular clock includes a frequency signal generator, a transmitter, a physical cell, a receiver, and an analog-to-digital converter (ADC). The frequency signal generator receives a control signal from the summer and generates a frequency modulated transmit frequency signal. The transmitter receives the frequency modulated transmit frequency signal and the amplitude modulated signal and generates an amplitude modulated and frequency modulated transmit frequency signal. The physical cell receives the amplitude modulated and frequency modulated transmit frequency signal and generates an absorption signal. The receiver receives the absorption signal and generates a received signal, and the ADC converts the received signal to an input signal.

[0005] In some implementations, the adder is a first adder, and the system further includes a DC feedback circuit that receives the input signal and generates a DC compensation signal. The molecular clock further includes a second adder that subtracts the DC compensation signal from the received signal to obtain a difference signal. The ADC converts the difference signal to the input signal. In some implementations, an anti-aliasing filter filters the difference signal before the ADC converts the difference signal to the input signal.

[0006] In some implementations, the digital processing circuit includes two correlators and two filters. The first correlator receives the input signal and generates a first correlation output. The first filter filters the first correlation output to obtain a frequency tuning parameter. The second correlator receives the first correlation output and the correlation signal and generates a second correlation output. The second filter filters the second correlation output to obtain an amplitude modulation parameter. [Brief description of the drawings]

[0007] [Figure 1A] FIG. 1 shows a block diagram of an example molecular clock including the presence of bias.

[0008] [Figure 1B] 1B illustrates a graph of a frequency modulated signal generated in the example molecular clock shown in FIG. 1A.

[0009] [Figure 2A] 1B shows a graph of the transfer function of a physical cell included in the molecular clock shown in FIG. 1A.

[0010] [Figure 2B] 1B shows a graph of the transfer function of a physical cell included in the molecular clock shown in FIG. 1A and its response to a mismatch between the tuning frequency and the absorption frequency of the physical cell. [Figure 2C] 1B shows a graph of the transfer function of a physical cell included in the molecular clock shown in FIG. 1A and its response to a mismatch between the tuning frequency and the absorption frequency of the physical cell.

[0011] [Figure 2D] 1B shows a graph of the transfer function of a physical cell included in the molecular clock shown in FIG. 1A with bias caused by reflections in the molecular clock and / or FM-AM conversion in the transmitter.

[0012] [Figure 3A] 1 shows a block diagram of an example bias correction circuit that uses both frequency modulation and amplitude modulation.

[0013] [Figure 3B] 3B illustrates a graph of a frequency modulated signal generated in the example bias correction circuit shown in FIG. 3A.

[0014] [Figure 3C] 3B illustrates a graph of an amplitude modulated signal produced in the example bias correction circuit shown in FIG. 3A.

[0015] [Figure 4A] 3B shows a block diagram of an example molecular clock including the example bias correction circuit shown in FIG. 3A. [Figure 4B] 3B shows a block diagram of an example molecular clock including the example bias correction circuit shown in FIG. 3A. [Figure 4C] 3B shows a block diagram of an example molecular clock including the example bias correction circuit shown in FIG. 3A. [Figure 4D] 3B shows a block diagram of an example molecular clock including the example bias correction circuit shown in FIG. 3A.

[0016] [Figure 4E] 4A-4D show graphs of the duty cycle signal generated in the molecular clock shown in FIG.

[0017] [Diagram 5] FIG. 3B shows a block diagram of a signal chain in the DC feedback system shown in FIG. 3A.

[0018] [Figure 6A] 3B illustrates the example bias correction circuit shown in FIG. 3A with continuous tuning of the scaling factor of the amplitude modulated signal.

[0019] [Figure 6B] 6B illustrates a graph of the basis_bias(t) signal in the example bias correction circuit shown in FIG. 6A.

[0020] [Figure 7]6B illustrates the example bias correction circuit shown in FIG. 6A with continuous tuning of the phase of the amplitude modulated signal.

[0021] [Figure 8A] 8 illustrates the example bias correction circuit shown in FIG. 7 with continuous tuning of the phasing of the correlation signal.

[0022] [Figure 8B] 8B illustrates a graph of gated and ungated receiver output signals produced in the example bias correction circuit shown in FIG. 8A.

[0023] [Figure 9] 3B illustrates a block diagram of the example bias correction circuit shown in FIG. 3A with in-phase and quadrature based amplitude modulation.

[0024] [Figure 10A] 1 shows a block diagram of an example bias correction circuit with digital processing of even and odd harmonics obtained by digital filtering;

[0025] [Figure 10B] 10B illustrates a graph of a signal generated in the example bias correction circuit shown in FIG. 10A.

[0026] [Figure 11A] 13 shows a block diagram of another example bias correction circuit with digital filtering. [Figure 11B] 13 shows a block diagram of another example bias correction circuit with digital filtering.

[0027] [Figure 12A] 1 shows a block diagram of an example bias correction circuit using Fast Fourier Transform (FFT) based processing.

[0028] [Figure 12B] 12B illustrates a graph of a signal generated in the example bias correction circuit shown in FIG. 12A. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] The same reference numerals are used to refer to features that are the same or similar (in function and / or structure).

[0030] The bias correction circuit described uses both frequency modulation and amplitude modulation to compensate for the effects of process, voltage, and temperature (PVT) variations on the bias (also known as "tilt") in the physical cells. The bias correction circuit includes a digital processing circuit, a frequency modulator, an amplitude modulator, and a summer.

[0031] The digital processing circuit generates a frequency modulation (FM) waveform and an amplitude modulation (AM) waveform similar to the FM wavelength but modified according to the amplitude and phase modulation parameters. To calculate the amplitude and phase modulation parameters in either the continuous or duty cycle operation modes, the digital processing circuit performs correlations between the received output of the physical cell and components of the frequency modulation signal, for example, between quadrature sinusoidal signals at odd and even harmonics of the modulation frequency Fmod and a modulation index signal at the bias frequency Fbias. In some implementations, the digital processing circuit performs correlations with only the fundamental frequency Fmod or with only selected higher odd harmonics, for example the third harmonic, triple Fmod. In some implementations, the digital processing circuit performs even harmonic correlations to achieve proper phase matching for the odd harmonic correlations. In some implementations, the digital processing circuitry performs correlation only with the second harmonic, 2x Fmod, or only with a selected higher even harmonic, such as the fourth harmonic, 4x Fmod.

[0032] The digital processing circuit also uses the correlation to calculate a frequency tuning signal that corrects for a frequency error between the average frequency of the RF signal input to the physical cell and the spectral lines of the physical cell itself. The frequency tuning signal is added to the frequency modulation signal such that the instantaneous frequency of the RF signal to the physical cell is responsive to both the FM modulation and the frequency correction. In some implementations, the digital processing circuit includes a first correlator and filter for generating the frequency tuning signal, a second correlator and filter for generating an amplitude modulation scale factor tuning parameter, and a third correlator and filter for generating an amplitude modulation phase tuning parameter.

[0033] FIG. 1A shows a block diagram of a conventional molecular clock 100 affected by bias. The molecular clock 100 includes a frequency signal generator 110, a transmitter 120, a physical cell 130, a receiver 150, a correlator 165, a filter 170, a frequency modulator 180, and an adder 190. The frequency signal generator 110 includes a timing core 112, a fractional-N synthesizer 116, and a multiplier 118. The timing core 112 may be a bulk acoustic wave oscillator, a crystal oscillator, an oven-controlled crystal oscillator, a temperature-compensated oscillator, etc., and generates a reference frequency signal Fref 114 that is provided to the fractional-N synthesizer 116. The fractional-N synthesizer 116 also receives the output of the adder 190 and multiplies Fref 114 based on the output of the adder 190. In some embodiments, the resulting signal is output as an output clock signal Fouf 115. Multiplier 118 receives the resulting signal from fractional-N synthesizer 116, further multiplies it, and provides the multiplied signal to transmitter 120, which creates an RF signal.

[0034] The output of the transmitter 120 is coupled to the physics cell 130. The physics cell 130 can be a tube or a waveguide with a low pressure dipole gas that absorbs the interrogation electromagnetic RF signal at a particular frequency via a quantum rotational transition. The output signal Fout 115 can be made to track the absorption lines of the gas, shown as frequency fnotch 135, by adjusting the average frequency of the RF signal to align with the absorption lines. The range of absorbed frequencies 2Γ 145 influences the selection of the modulation depth for the FM of the RF signal from the transmitter 120. The physics cell 130 is modeled with a bias transfer function Hbias(f) 124 and an absorption transfer function Hnotch(f) 128. The bias transfer function Hbias(f) 124 represents the bias 140 introduced into the absorption transfer function Hnotch(f) 128 by reflections at the physics cell 130 and / or FM-AM conversion of the transmitter 120. The bias 140 introduces a frequency-dependent variation in the amplitude of Hnotch(f) 128 that breaks the even symmetry about the frequency fnotch 135 generally provided by Hnotch(f) 128 itself.

[0035] The output of the physical cell 130 is provided to a receiver 150, represented as a detector 154 and a low pass filter 158 with a transfer function H_LP(f). The received signal Vdet(t) 160 is provided to a correlator 165, which correlates it with the fundamental or higher odd harmonics of a frequency modulated signal Fmod 188 provided by the frequency modulator 180. The frequency modulated signal Fmod 188 is shown in FIG. 1B and can be expressed as follows: TIFF2024524245000002.tif843 where Δf 194 represents the FM exponent and Tmod198 represents the period of Fmod188.

[0036] The fundamental or higher odd harmonic is labeled Fcorr 184 and in some embodiments may be expressed as: TIFF2024524245000003.tif742 where N is equal to 1 for the fundamental and is greater than or equal to 3 and odd for the higher odd harmonics, and φ align represents the phase offset. By using a higher odd harmonic for Fcorr 184 rather than the fundamental, the correlation between Vdet(t) 160 and Fcorr 184 is less sensitive to bias 140. However, correlating to the higher odd harmonic Fmod 188 reduces the signal-to-noise ratio (SNR) of the molecular clock compared to correlating to the fundamental Fmod 188, which may result in an increase in noise-induced Allan deviations. Also, bias sensitivity is only reduced, not eliminated, which may affect the frequency accuracy and Allan deviation of Fout 115.

[0037] Filter 170, which may include one or more accumulators and may also include low pass filtering, is coupled to the output of correlator 165 and generates tuning signal Ftune 175. Frequency modulator 180 also generates a frequency modulated signal Fmod 188, which summer 190 combines with tuning signal Ftune 175. The output of summer 190 is provided to fractional-N synthesizer 116, as described above with respect to frequency signal generator 110.

[0038] 2A-2D show graphs of the frequency modulated signal Fmod(t) 288, the transfer function Hnotch(f) 210 of the physical cell 130, and the output signal Vnotch(t) 230 of the physical cell 130, all of which are included in the molecular clock 100 shown in FIG. 1A. Fmod(t) 288 has a period Tmod 298 and an average frequency corresponding to the tuning frequency ftune 205. The transfer function Hnotch(f) 210 has an absorption frequency fnotch 215. In FIG. 2A, graph 200A shows the transfer function Hnotch(f) 210A of the physical cell 130 without bias 140, and the perfect match between ftune 205A of Fmod(t) 288A and fnotch 215 of Hnotch(f) 210A. Assuming perfect matching between ftune 205A and fnotch 215 and symmetry of Hnotch(f) 210A around fnotch 215, the output signal Vnotch(t) 230A contains only even harmonics. In practice, ftune 205 is sensitive to changes in response to process, voltage, and temperature (PVT) variations, posing challenges to maintaining the matching between ftune 205 and fnotch 215. Assuming no bias is present, the consequences of mismatch between ftune 205 and fnotch 215 are shown in Figures 2B-2C.

[0039] In FIG. 2B, a graph 200B shows Fmod(t) 288B, Hnotch(f) 210B, and the resulting Vnotch(t) 230B with ftune 205B less than fnotch 215. The difference between ftune 205B and fnotch 215 is represented as foffset 220B. In FIG. 2C, a graph 200C shows Fmod(t) 288C, Hnotch(f) 210C, and the resulting Vnotch(t) 230C with ftune 205C greater than fnotch 215. The difference between ftune 205C and fnotch 215 is represented as foffset 220C. The frequency difference foffset 220B and 220C results in amplitude modulation on Vnotch(t) 230B and Vnotch(t) 230C, respectively. A correlation of Vnotch(t) 230B with the fundamental or odd harmonics of Fmod(t) 288B and a correlation of Vnotch(t) 230C with the fundamental or odd harmonics of Fmod(t) 288C provides an error signal.

[0040] 2D, graph 200D shows Fmod(t) 288D, Hnotch(f) 210D, and the resulting Vnotch(t) 230D with perfect matching between ftune 205B and fnotch 215, but with bias 140 causing frequency dependent variation in the amplitude of Hnotch(f) 210D. Bias 140 causes amplitude modulation with odd harmonic content in Vnotch(t) 230D, resulting in zero foffset, even with perfect matching between ftune 205B and fnotch 215.

[0041] 3A shows a block diagram of an example bias correction circuit 300 incorporating both frequency modulation and amplitude modulation. The bias correction circuit 300 includes the frequency signal generator 110, the transmitter 120, the physical cell 130, the receiver 150, and the adder 190 described herein with respect to the molecular clock 100 shown in FIG. 1A, as well as an adder 305, an analog-to-digital converter (ADC) 310, digital-to-analog converters (DACs) 335 and 380, a correction circuit 320, and an optional temperature sensor 345. The correction circuit 320 includes a digital processing circuit 325, a DC feedback circuit 330, a frequency modulator 360, and an amplitude modulator 370.

[0042] The summer 305, DC feedback circuit 330, and DAC 335 form a DC feedback loop 375. In implementations that include an optional temperature sensor 345, the correction circuit 320 also includes a compensation circuit 350 and a summer 355. In some embodiments, the DAC 335 may be implemented in the receiver 150 with digital voltage or current control, e.g., explicitly with a DAC circuit or implicitly with a selectable resistor or other digital bias control in the implementation of the receiver 150. Also, in some embodiments, the DAC 380 may be implemented in the transmitter 120 with digital voltage or current control, e.g., explicitly with a DAC circuit or implicitly with a selectable resistor or other digital bias control in the implementation of the transmitter 120.

[0043] The receiver output Vdet(t) 160 is provided to a summer 305, which combines its output with a DC correction signal DCcancel(t) 340. The summer 305 may be implemented in the analog domain using appropriate circuits such as op-amps and passive elements (including resistors and capacitors), or controlled current or voltage sources to adjust the DC bias of the detector. The ADC 310 is coupled to the output of the summer 305, and the digital processing circuit 325 and DC feedback circuit 330 in the correction circuit 320 are coupled to the output of the ADC 320. The DC feedback circuit 330 determines the DC bias at a particular frequency modulation index and generates a digital DC correction signal, which is converted to an analog DCcancel(t) 340 by a DAC 335 and provided to the negative input of the summer 305 to keep the ADC input within its valid operating range.

[0044] In an embodiment without optional temperature sensor 345, compensation circuit 350, and summer 355, digital processing circuit 325 directly generates tuning signal Ftune 175. In an implementation including optional temperature sensor 345, compensation circuit 350, and summer 355, temperature sensor 345 provides temperature information to compensation circuit 350. Temperature compensation circuit 350 generates a temperature compensation signal, and digital processing circuit 325 generates a residual frequency tuning signal to compensate for residual errors after temperature compensation by using tracing of the spectral lines of physical cell 130. The temperature compensation signal and the residual frequency tuning signal are combined by summer 355 to generate tuning signal Ftune 175.

[0045] The digital processing circuit 325 also generates a control signal for the frequency modulator 360, which generates the FM signal Fmod(t) 388 shown in FIG. 3B. Fmod(t) 388 has a period Tmod 398 and alternates between a first frequency modulation index Δf0 394A and a second frequency modulation index Δf1 394B. The frequency modulator 360 generates Fmod(t) 388 such that the alternation between the first modulation index Δf0 394A and the second modulation index Δf1 394B occurs with a period Tbias 390A, with Δf0 394A being used for approximately half of Tbias 390B and Δf1 394B being used for approximately half of Tbias 390B. In some applications, the duty cycle of alternating between Δf0 and Δf1 can be changed from exactly half of Tbias 390A for improved system performance. Summer 190 combines Ftune 175 and Fmod(t) 388 and provides the result to fractional-N synthesizer 116 in frequency signal generator 110 .

[0046] The digital processing circuit 325 also provides amplitude modulation parameters for the amplitude modulator 370. The amplitude modulation parameters 365 may include an amplitude scaling factor Atune, a phase parameter φtune, or both for polar modulation, or an in-phase (I) parameter Itune, a quadrature (Q) parameter Qtune, or both for I / Q amplitude modulation. The amplitude modulator 370 generates a digital amplitude modulation signal, which is converted by the DAC 380 to an analog amplitude modulation signal Amod(t) 385 shown in FIG. 3C. The Amod(t) 385 alternates between a first amplitude modulation index Δa0 396A and a second amplitude modulation index Δa1 396B with a period Tbias. The amplitude modulation signal Amod(t) 385 may be provided to the transmitter 120 for transmitter-based FM-AM bias correction or to the receiver 150 for receiver-based bias correction. In some implementations, transmitter-based FM-AM bias compensation is used because it makes the bias compensation less sensitive to nonlinearities in the signal path from TX 120 to RX 150.

[0047] For transmitter-based FM-AM bias correction, and assuming that the multiplication of the transmitter bias correction with the bias 140 is flat in frequency, Vdet(t) 160 will only include even harmonics despite the presence of nonlinearities in the voltage or current at the receiver 150, and the correlation for odd harmonics (including the fundamental) will be zero in response to the tuning frequency ftune being equal to fnotch 135. For receiver-based bias correction, and assuming that the multiplication of the receiver bias correction with the bias 140 is flat in frequency, Vdet(t) 160 may still include odd harmonics due to the presence of nonlinearities in the voltage or current at the receiver 150, and the correlation for odd harmonics (including the fundamental) may not be zero in response to the tuning frequency ftune being equal to fnotch 135.

[0048] Thus, in implementations where Amod(t) 385 is provided to receiver 150, receiver 150 may be selected to have higher linearity than in implementations where Amod(t) 385 is provided to transmitter 120. Bias correction circuit 300 uses both frequency modulation with a varying frequency modulation index and amplitude modulation to track absorption frequency fnotch 135 in the presence of bias 140. Tuning signal Ftune 175 and amplitude modulation parameters 365 may be updated to maintain accuracy over PVT variations.

[0049] Figures 4A-4D show block diagrams of an example molecular clock including the example bias correction circuit 300 shown in Figure 3A. For ease of explanation, Figures 4A-4E are described herein with reference to Figure 3A. As previously described herein with respect to Figure 3A, DACs 335 and 380 may be incorporated within receiver 150 and transmitter 120, respectively, for example, explicitly with DAC circuitry, or implicitly with digital voltage or current control using a selectable resistor array or other digital bias control.

[0050] In FIG. 4A, the molecular clock 400A includes the bias correction circuit 300 and a fractional-N frequency divider 410. The output 405 of the fractional-N synthesizer 116 in the frequency signal generator 110 is locked to fnotch 135, and the fractional-N frequency divider 410 uses a frequency modulation cancellation signal Fmod_cancel(t) 407 from the frequency modulator 360 to cancel the unwanted frequency modulation in Fsyn 405 and generate the output clock signal Fout 415A. Dithering noise due to dynamic division value variation from the fractional-N frequency divider 410 can be reduced by including a digital-to-time converter to cancel the dithering noise and obtain low jitter in Fout 415A. Multiple fractional-N frequency dividers, each with a respective Fmod-cancel(t) signal, can be used to generate one or more output frequencies in addition to Fout 415A. Temperature compensation as shown in FIG. 3A can be used by adding a temperature compensation signal to Ftune 175 such that Ftune 175 represents the residual frequency tuning signal.

[0051] 4B, the molecular clock 400B includes the bias correction circuit 300 and a fractional-N synthesizer 420. The fractional-N synthesizer 420 receives the reference frequency signal Fref 114 output by the timing core 112 in the frequency signal generator 110 and a second tuning signal Ftune_out 425 from the digital processing circuit 325. Ftune_out 425 is a function of Ftune 175. For example, Ftune_out 425 can be expressed as follows: Ftune_out425=(a)(Ftune 175)+b where a and b are constants selected based on Fref 114, Fsyn 405, and the desired output clock signal Fout 415B. The fractional-N synthesizer 420 then generates the output clock signal Fout 415B. The molecular clock 400B provides a straightforward means of avoiding the effect of the FM modulation signal Fmod(t) 388 on Fout 412B, compared to requiring Fmod cancellation used in the molecular clock 400A shown in FIG. 4A. The molecular clock 400B can be combined with one or more frequency divider circuits to generate multiple output frequencies based on Fout 415B. The temperature compensation shown in FIG. 3A can be used by adding a first temperature compensation signal to Ftune 175 so that Ftune 175 represents the first residual frequency tuning signal, and adding a second temperature compensation signal to Ftune_out 425 so that Ftune_out represents the second residual frequency tuning signal.

[0052] In FIG. 4C, the molecular clock 400C includes the bias correction circuit 300, and the frequency signal generator 110 includes an additional fractional-N synthesizer 435. The fractional-N synthesizer 435 receives the reference frequency signal Fref 114 output by the timing core 112 and the tuning signal Ftune 175 from the digital processing circuit 325. The fractional-N synthesizer 435 generates an output clock signal Fout 415C. The digital processing circuit 325 generates a signal Fc 430 and provides it to the summer 190, which combines Fc 430 with Fmod(t) 388 from the frequency modulator 360. The fractional-N synthesizer 116 in the frequency signal generator 110 receives the output of the summer 190 and Fout 415C and generates a combined signal Fsyn 405. Signal Fc 430 can be set to a certain frequency value based on the desired frequency of Fsyn 405 relative to Fout 415C. Molecular clock 400B can be combined with one or more frequency divider circuits to generate multiple output frequencies based on Fout 415C. Temperature compensation as shown in FIG. 3A can be used by adding a temperature compensation signal to Ftune 175 such that Ftune 175 represents the residual frequency tuning signal.

[0053] 4D, the molecular clock 400D includes the bias correction circuit 300 and the DAC 440, which receives the tuning signal Ftune 175 from the digital processing circuit 325. Analog tuning allows the timing core 112 to generate a high-precision reference frequency signal Fref 114, which can be directly output as the clock signal Fout 415D. In some embodiments, the molecular clock 400D includes an optional temperature sensor 345, a compensation circuit 350, and a summer 355, and the tuning signal Ftune 175 includes a temperature compensation signal. In some implementations, the DAC 440 can be implemented within the timing core 112, for example, explicitly with a DAC circuit or implicitly with digital frequency control using a fractional-N synthesizer or a selectable capacitor array within the implementation of the timing core 112.

[0054] FIG. 4E shows a graph of the duty cycled Fmod(t) 388 and the duty cycled Amod(t) 385 generated in the molecular clock 400 shown in FIGS. 4A-4D. Fmod(t) 388 and Amod(t) 385 are duty cycled to conserve power during the time period 460. The frequency correction of the timing core 112 may be performed on a duty cycled basis to balance the power used by the molecular clock 400 and the amount of noise that can be tolerated. The timing core 112 and the clock signal output path remain on, while other components of the molecular clock 400 are appropriately turned off or transitioned to a low power operating mode. For example, the transmitter 120, the receiver 150, the ADC 310, the DACs 335 and 380, and the summer 305 may be turned off during the time period 460.

[0055] FIG. 5 shows a block diagram of a signal chain 500 in the DC feedback system 375 shown in FIG. 3A. The receiver 150 outputs a signal Vdet(t) 160 shown at offset 535. The frequency modulation with a time-varying FM index of period Tbias 390 results in an amplitude modulation of Vdet(t) with a time-varying peak-to-peak amplitude of period Tbias 390. Vdet(t) 160 is input to a positive input of a summer 305, and DCcancel(t) 340 is provided to a negative input of the summer 305. An anti-aliasing filter 540, represented as Haa(f), is coupled to the output of the summer 305. The output of the anti-aliasing filter 540 is Vadc_in(t) 550 shown at offset 545, which is coupled to the input of the ADC 310. The output adc_out 570 of the ADC 310 is provided to the DC feedback circuit 330 and to the digital processing circuit 325, not shown.

[0056] The DC feedback circuit 330 determines the DC bias at a particular FM index value and generates a digital DC correction signal that is converted by the DAC 335 to an analog DCcancel(t) 340. DCcancel(t) 340 is shown at offset 555 and has a first magnitude DC0 560A for the first FM index Δf0 394A and a second magnitude DC1 560B for the second FM index Δf1 394B. The DC bias depends on the particular FM index, Δf0 394A or Δf1 394B, so a separate DC correction value is calculated for each FM index and subtracted before Vdet(t) 160 is input to the ADC 310 to reduce transient response as Vdet(t) 160 transitions from one FM index to another.

[0057] In some implementations where DCcancel(t) 340 is further filtered to remove undesired noise or interference from DAC 335, DC0 560A may be set equal to DC1 560B as long as the transients from anti-aliasing filter Haa(f) 540 from transitions from one value of FM index to another still allow acceptable system performance. As previously described herein with respect to FIG. 3A, DAC 335 may be implemented within receiver 150, for example, with an explicit DAC circuit, or with implicit digital voltage or current control, using an array of selectable resistors or other digital bias control within the implementation of receiver 150.

[0058] 6A shows a block diagram of an example bias correction circuit 600 with continuous tuning of a scaling factor Atune 630 of an amplitude modulated signal Amod(t) 385. The bias correction circuit 600 is similar to the bias correction circuit 300 shown in FIG. 3A, but includes a frequency modulator 680 instead of the frequency modulator 360, and a digital processing circuit 625 instead of the digital processing circuit 325. The digital processing circuit 625 includes the correlator 165 and filter 170 shown in FIG. 1A, as well as the correlator 610 and filter 620. For ease of explanation, the optional temperature sensor 345, compensation circuit 350, summer 305, DC feedback circuit 330, and DACs 335 and 380 are omitted.

[0059] The correlator 165 receives the output of the ADC 310 (which digitizes the Vdet(t) 160 from the receiver 150) and Fcorr 684 from the frequency modulator 680. Fcorr 684 can be expressed as: JPEG2024524245000004.jpg843Fcorr 684 can use the fundamental of Fmod(t) 388 so that N=1, or it can use higher odd harmonics (N=3, 5, ...) similar to Fcorr 184 shown in Figure 1A. Filter 170 accumulates the correlation output from correlator 165 to generate Ftune 175.

[0060] The correlator 610 further correlates the correlation output from the correlator 165 with a bias signal basisbias(t) 605 shown in FIG. 6B. Basisbias(t) 605 is a square wave that alternates between positive and negative in alternating portions of Tbias 390A according to the alternation of the FM index between Δf0 394A and Δf1 394B in Fmod(t) 388. The example basisbias(t) 605 shown in FIG. 6B has a regular duty cycle approximately equal to half of Tbias 390B, although in some implementations an irregular duty cycle may be used. The filter 620 is coupled to the output of the correlator 610 and accumulates the output of the correlator 610 to generate a scaling factor Atune 630. In some implementations, Atune 630 is expressed as: JPEG2024524245000005.jpg741Continuous calculation of Atune 630 allows bias cancellation to remain accurate despite PVT variations. AM modulator 370 receives Fmod(t) 388 and Atune 630 and produces Amod(t) 385.

[0061] Filter delays in the bias correction circuit 600 can cause phase differences between the FM and AM modulation paths, resulting in errors in the bias correction. Figure 7 shows a block diagram of an example bias correction circuit 700 with continuous tuning of the phase of the amplitude modulated signal Amod(t) 385. The bias correction circuit 700 is similar to the bias correction circuit 600 shown in Figure 6A, but includes a frequency modulator 780 instead of the frequency modulator 680, and a digital processing circuit 725 instead of the digital processing circuit 625. The digital processing circuit 725 is similar to the digital processing circuit 625, but also includes a correlator 710 and a filter 720. For ease of explanation, the optional temperature sensor 345, compensation circuit 350, summer 305, ADC 310, DC feedback circuit 330, and DACs 335 and 380 are omitted.

[0062] The correlator 710 receives adc_out 570 from the output of the ADC 310, which digitizes Vdet(t) 160, and Fcorr_q 705 from a frequency modulator 780. Fcorr_q 705 can be expressed as: JPEG2024524245000006.jpg853, where φ quad is selected such that Fcorr_q 705 is phase shifted by 90 degrees relative to Fcorr 684. The filter 720 accumulates the correlation output from the correlator 710 to produce φ tune 730, which may be calculated independently for each modulation index Δf0 394A and Δf1 394B. tune 730 adjusts the phase of Amod(t) 385 by using the in-phase and quadrature components of Fmod(t) 388. The AM modulator 370 includes Fmod(t) 388, Atune 630, and φ tune 730 and generate Amod(t)385. φ tune Continued calculations at 730 can cause the bias correction circuit 700 to adjust Amod(t) 385 until the correlation between adc_out 570 and Fcorr_q 705 reaches approximately zero.

[0063] As previously described with respect to FIG. 6A, Fcorr684 can be expressed as: JPEG2024524245000007.jpg742Fcorr684 and Fcorr_q705 are both phase offset terms φ align The PVT variation is the phase offset term φ of the correlation signals Fcorr 684 and Fcorr_q 705. align This can lead to errors in the calculation to match ftune to fnotch, and therefore a non-zero f offset.

[0064] FIG. 8A illustrates the phase offset term φ of the correlation signals Fcorr 684 and Fcorr_q 705. align8A shows a block diagram of an example bias correction circuit 800 that includes continuous tuning of Fmod(t) 388. FIG. 8A also includes a gating circuit 850 that prevents undesired transients from FM index fluctuations from affecting the correlation results. While the frequency tuning and bias correction drives odd harmonics (including the fundamental) of Fmod(t) 388 toward zero in the gated detector output Vdet_gated(t) 860 during steady state operation, the even harmonics of Fmod(t) 388 remain present in Vdet_gated(t) 860 and contribute to the phase offset term φ align In this example, the bias correction circuit 800 uses a correlator 810 to correlate Vdet_gated(t) 860 with the second harmonic of Fmod(t) 388 with an appropriate phase shift, denoted as Fcorr_2x 885.

[0065] Filter 820 accumulates the correlation output of correlator 810 and filters the phase offset term φ for proper phase alignment of Fcorr and Forr_q. align The phase offset term φ align may be adjusted in value until the average value of the correlation output of the correlator 810 is zero. The bias correction circuit 800 is similar to the bias correction circuit 700 shown in FIG. 7, but includes an optional gate 850, a frequency modulator 880 instead of the frequency modulator 780, and a digital processing circuit 825 instead of the digital processing circuit 725. The digital processing circuit 825 is similar to the digital processing circuit 725, but also includes the correlator 810 and the filter 820. For ease of explanation, the optional temperature sensor 345, the compensation circuit 350, the summer 305, the DC feedback circuit 330, and the DACs 335 and 380 are omitted.

[0066] The change in FM index from Δf0 394A to Δf1 394B and vice versa can cause transients in Vdet(t) 160, which can introduce errors into the correlation calculations performed by the correlators 165, 610, 710, and 810. The digitized Vdet(t) 160, adc_out 570, can be gated for a predetermined number of modulation cycles to avoid the effects of transients on the correlation calculations. FIG. 8B shows the ungated digitized Vdet(t) 160 from the output of the ADC 310 and the resulting gated Vdet_gated(t) 860, which is set to zero while the FM index changes from Δf0 394A to Δf1 394B and vice versa at 865A.

[0067] An optional gate 850 may be used to generate a gated signal Vdet_gated(t) 860 based on the digitized Vdet(t) 160, adc_out 570, from the output of the ADC 310. The correlators 165, 610, 710, and 810 receive the gated signal Vdet_gated(t) 860 from the optional gate 850. Alternatively, the correlation outputs from the correlators 165, 610, 710, and 810 may be set to zero during the transition from Δf0 394A to Δf1 394B at 865A and vice versa at 865B.

[0068] The correlator 810 receives a second harmonic based signal Fcorr_2x 885 and a gated signal Vdet_gated(t) 860. The second harmonic based signal 885 can be expressed as: JPEG2024524245000008.jpg861, where φ quad_2x is chosen to be nominally 90 degrees phase shifted relative to the second harmonic of Fmod(t) 388 present in Vdet_gated(t) 860. In some implementations, f(φ align ) is the φ for setting the average correlation output from the correlator 810 equal to zero. alignφ such that adjustments to also appropriately adjust Fcorr84 and Fcorr_2x 885 in response to PVT variations. align In some implementations, the phase adjustment of Fcorr_2x 885 is implemented via an in-phase and quadrature (I / Q) based phase shift using a second harmonic based signal expressed as: Similarly, the phase adjustment of Fcorr684 and Fcorr_q705 can be implemented based on an (I / Q) based phase shift using fundamental or odd harmonic based signals as expressed as follows: TIFF2024524245000010.tif1985Here, N is an odd integer greater than or equal to 1, corresponding to the fundamental or a given odd harmonic of Fmod(t)388. In an implementation without the optional gate 850, a correlation of adc_out 570 with the second harmonic based signal Fcorr_2x 885 is provided to the filter 820. In an implementation with the optional gate 850, a correlation of Vdet_gated(t) 860 with the second harmonic based signal Fcorr_2x 885 is provided to the filter 820.

[0069] Filter 820 accumulates the output of correlator 810 and filters the phase offset φ for use in phase matching Fcorr 684, Fcorr_q 705, and Fcorr_2x 885. align 830 is provided to a frequency modulator 880. align 830 may be calculated independently for each FM modulation index Δf0 394A and Δf1 394B and adjusted such that the correlation of the second harmonic based signal Fcorr_2x 885 with adc_out 570 or Vdet_gated(t) 860 averages to zero over PVT variations.

[0070] 9 shows a block diagram of an example bias correction circuit 900 having in-phase and quadrature-based AM parameters for Amod(t) 385. The bias correction circuit 900 is similar to the bias correction circuit 300 shown in FIG. 3A, but includes the frequency modulator 780 shown in FIG. 7 instead of the frequency modulator 360, and the digital processing circuit 925 instead of the digital processing circuit 325. The digital processing circuit 925 includes the correlator 165 and the filter 170 shown in FIG. 1A, and also includes a controller 910. The frequency modulator 780 generates the correlation-based signals Fcorr 684, as described herein with respect to FIG. 6A, and Fcorr_q 705, as described herein with respect to FIG. 7.

[0071] The frequency modulator 780 provides Fcorr 684 to the correlator 165 and both Fcorr 684 and Fcorr_q 705 to the controller 910, which also receives the digitized Vdet(t) 160, adc_out 570 from the ADC 310, and basisbias(t) 605 as described herein with respect to Figure 6A. The controller 910 performs the correlation and filtering as described herein with respect to Figure 7 to determine Atune and φ tune 8A . The controller 910 may optionally use gating as described herein with respect to FIG. 8A . Itune 920 and Qtune 930 are provided to the AM modulator 370 in addition to Fmod(t) 388 and Fmod_q(t) 905. Fmod_q(t) 905 represents a quadrature version of Fmod(t) 388. The AM modulator 370 then generates Amod(t) 385 based on Fmod(t) 388, Fmod_q(t) 905, Itune 920, and Qtune 930.

[0072] FIG. 10A shows a block diagram of an example bias correction circuit 1000 having a digital filtering system that separates even and odd harmonics for digital processing. The example bias correction circuit 1000 is similar to the bias correction circuit 800 shown in FIG. 8A, but includes a frequency modulator 1080 instead of the frequency modulator 880 and a digital processing circuit 1025 instead of the digital processing circuit 825. For ease of illustration, the correlation and accumulation performed by the correlators 165, 610, and 710 and the filters 170, 620, and 720 are shown as a digital processing circuit 1060 for odd harmonics, and the correlation and accumulation performed by the correlators 810 and the filters 820 are shown as a digital processing circuit 1070 for even harmonics. The bias correction circuit 1000 has been described with respect to FIGS. 3A, 5, and 8A. The DC cancellation loop 375 shown in FIG. 5 may be included in the exemplary bias correction circuit 1000, but is omitted for ease of illustration.

[0073] The frequency modulator 1080 provides the second harmonic signal Fcorr_2x 885 to the digital processing circuit 1070 for even harmonics and phase-matches φ align 830. The frequency modulator 1080 also provides a timing signal 1085 and a correlation signal Fcorr 1090 to the digital processing circuit for odd harmonics 1060. The correlation signal Fcorr 1090 includes correlation signals Fcorr 684 and Fcorr_q 705. The timing signal 1085 includes a first timing signal mod_bool 1085A and a second timing signal mod_bias_bool 1085B, which are further described herein with respect to FIG.

[0074] The signal Vdet(t) 160 is input to the ADC 310, which outputs a signal adc_out 570 to a delay circuit 1030 and to the positive inputs of adders 1040 and 1050 in the digital filtering system 1020. The delay circuit 1030 introduces a delay of Tmod(t) 398 divided by two and provides a delayed signal 1035 to the negative input of adder 1040 and the positive input of adder 1050. The output of adder 1040 is a difference signal diff(t) 1045, which contains only the odd harmonics, including the fundamental, of Fmod(t) 388 present in adc_out 570. Not including even harmonics in the signal diff(t) 1045 can reduce the bit width requirements of the multipliers and other calculations performed by the digital processing circuit 1060 for the odd harmonics. Similarly, the output of summer 1050 is a sum signal sum(t) 1055, which contains only even harmonics and is scaled by φ for timing alignment. align It can be used to calculate 830.

[0075] 10B illustrates a graph 1090 of timing signals 1085, Fmod(t) 388, and adc_out 570 generated in the example bias correction circuit shown in FIG. 10A. Signal adc_out 570 has a period corresponding to approximately half the period Tmod 398 of Fmod(t) 388, assuming steady state operation of frequency tuning and bias correction suppressing the fundamental and odd harmonics of Fmod(t) 388 present in adc_out 570. Both mod_bool signal 1085A and Fmod(t) signal 388 have period Tmod 398. mod_bias_bool signal 1085B has period Tbias 390A, the same as the period of basisbias(t) signal 605.

[0076] 11A shows a block diagram of an example bias correction circuit 1100A that includes a digital filtering system 1020. For ease of illustration, the bias correction circuit 1100A is described with reference to the bias correction circuit 1000 shown in FIG. 10A and includes the digital filtering system 1020, the correlators 165, 610, 710, the filters 170, 620, and 720, and 1145, the gate 850, the controller 1110, the sign detector 1150, and the multiplier 1160. The digital filtering system 1020 receives the adc_out 570 and the first clocking signal clk 1105 and outputs a difference signal diff(t) 1045 to the correlators 165 and 710 and a sum signal 1055 to the controller 1110. The controller 1110 represents the digital processing circuitry 1070 for the even harmonics and the frequency modulator 1080 , which generates the correlation signal Fcorr 684 for the correlator 165 and the correlation signal Fcorr_q 705 for the correlator 710 .

[0077] The output correlation corr(t) 1115 from the correlator 165 and the output correlation corrq(t) 1120 from the correlator 710 are provided to a gate 850 which provides a timing signal mod_bias_bool 1125 that is used to zero the values ​​of corr(t) 1115 and corrq(t) 1120 following a bias modulation transition. The gated correlation corr(t) 1115 is referred to as error(t) 1135 and is provided to a filter 170 and a correlator 610. The filter 170 accumulates the error(t) 1135 to generate a tuning signal Ftune(t) 175. The correlator 610 also receives a timing signal mod_bias_bool 1125 and provides the correlation to a filter 620 which accumulates it to generate an Atune(t) 630.

[0078] The gated correlation corrq(t) 1120 from gate 850 is called errorq(t) 1140 and is provided to a correlator 1145. The output of the correlator 1145 is provided to a multiplier 1160. Atune(t) 630 is provided to a sign detector 1150 which generates a signal 1155 which is either positive or negative based on the sign of Atune(t) 630. Signal 1155 is provided to a multiplier 1160 which multiplies it with the correlation output from the correlator 1145. The result is provided to filter 720 which accumulates it to generate a phase tuning signal φ tune (t) 730. The AM phase tuning signal path is stabilized by changing the sign of the feedback loop via signal 1155, as controlled by the instantaneous sign of Atune(t) 630.

[0079] 11B shows a block diagram of another example bias correction circuit 1100B with a digital filtering system 1020. The bias correction circuit 1100B is similar to the bias correction circuit 1100A shown in FIG. 11A, but includes a limiter circuit 1165 instead of the sign detector 1150. The limiter circuit 1165 receives Atune(t) 630 from the filter 620 and scales its inverse to be applied as a scaling factor for the AM phase tuning feedback loop, and also implements maximum and minimum thresholds to prevent excessively large gain, which can improve the bandwidth consistency, i.e., the consistency of the convergence time of the AM phase tuning signal path. The output 1170 of the limiter circuit 1165 can be expressed as follows: TIFF2024524245000011.tif747 where K φ represents a scaling factor applied to the inverse of Atune(t) 630, and the limit function implements positive and negative limits according to the sign of Atune(t) 630.

[0080] 12A shows a block diagram of an example bias correction circuit 1200 with fast Fourier transform (FFT) based processing. The bias correction circuit 1200 is described herein with respect to the bias correction circuit 1000 shown in FIG. 10A and includes an ADC 310, an FFT processor 1210, a digital processing circuit 1060 for odd harmonics, a digital processing circuit 1070 for even harmonics, and a frequency modulator 1240. Vdet(t) 160 is input to the ADC 310, which outputs adc_out 570. The FFT processor 1210 receives adc_out 570 and performs a frame-based FFT to separate odd and even harmonics for FM indices Δf0 394A and Δf1 394B. The FFT processor 1210 may be implemented in hardware or in software, and a frame-based FFT may be selected based on the desired latency of the bias correction circuit 1200.

[0081] The odd harmonics are output as signal 1220 to the digital processing circuit for odd harmonics 1060, which also receives a timing signal 1085 from the frequency modulator 1240 and controls Ftune 175, Atune 630, and φ tune The even harmonics are output as signal 1230 to a digital circuit for even harmonics 1070, which also receives a timing signal 1085 from the frequency modulator 1240 and generates a phase alignment signal φ align The frequency modulator 1240 also generates Fmod(t) 388.

[0082] In some implementations, the FFT processor 1210 can be used to simultaneously extract even and odd harmonics of multiple FM indices, and Fmod(t) 388 can simultaneously include multiple FM indices at different modulation frequencies. For example, adc_out 570 can be affected by Fmod(t) 388 such that Fmod(t) 388 is expressed as follows: Fmod(t)388=Δf(t)=Δf0(t)1255+Δf1(t)1260 The waveforms of Δf0(t) 1255 and Δf1(t) 1260 are shown in FIG. 12B, and the signal Δf0(t) 1255 can be expressed as follows: Δf0(t)1255=(Δf0 394A)sin(2π(fm0)t) where fm0 is the first modulation frequency. The signal Δf1(t) 1260 can be expressed as: Δf1(t)1260=(Δf1 394B)sin(2π(fm1)t) where fm1 is the first modulation frequency. The modulation frequencies fm0 and fm1 can be chosen so that these frequencies and their intermodulation products fall into the correct FFT bins. For example, fm0 can be equal to four times f0, where f0 is the smallest FFT bin, and fm1 can be equal to six times f0.

[0083] In this description, the term "couple" may encompass a connection, communication, or signal path that enables a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform a certain action, (a) in a first example, device A is coupled to device B by a direct connection, or (b) in a second example, device A is coupled to device B via an intervening component C such that device B is controlled by device A via a control signal generated by device A, where intervening component C does not change the functional relationship between device A and device B.

[0084] A device that is "configured to" perform a certain task or function may be configured (e.g., programmed and / or hardwired) at the time of manufacture by a manufacturer to perform that function and / or may be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Such configuration may be through firmware and / or software programming of the device, through the construction and / or layout of the hardware components and interconnections of the device, or a combination thereof.

[0085] The circuits described herein are reconfigurable to include additional or different components to provide functionality at least partially similar to that available prior to the replacement of the components. A component shown as a resistor generally represents any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the resistor shown, unless otherwise stated. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as a single resistor or capacitor.

[0086] In this description, unless otherwise stated, "about," "approximately," or "substantially" preceding a parameter means within plus or minus ten percent of that parameter.

[0087] Modifications in the described embodiments are possible, and other embodiments are possible, within the scope of the appended claims.

Claims

1. A system, comprising: A signal generator having a frequency modulation input and a signal generator output; A transmitter having a signal input coupled to the signal generator output, an amplitude modulation input, and a transmitter output; A frequency modulator having a frequency modulation control input and a frequency modulation output coupled to the frequency modulation input; An amplitude modulator having an amplitude modulation control input and an amplitude modulation output coupled to the amplitude modulation input; A processing circuit having a processing circuit input, an amplitude modulation control output coupled to the amplitude modulation control input, and a frequency modulation control output coupled to the frequency modulation control input; The system.

2. The system according to claim 1, wherein the signal generator is configured to provide a first signal to the signal generator output in response to a frequency modulation signal at the frequency modulation input; the transmitter is configured to provide a second signal to the transmitter output in response to the first signal at the signal input and an amplitude modulation signal at the amplitude modulation input.

3. The system according to claim 1, wherein the processing circuit further has a sensor input; the processing circuit is configured to receive a temperature sensor signal at the sensor input and provide a frequency modulation control signal to the frequency modulation control output in response to the temperature sensor signal.

4. The system according to claim 1, further comprising a gas cell having a first terminal coupled to the transmitter output and a second terminal coupled to the processing circuit input, the gas cell being configured to receive a first signal at the first terminal and provide a second signal to the second terminal by removing a specific frequency component of the first signal.

5. The system according to claim 1, wherein A feedback circuit having a gas cell input and a feedback output coupled to the processing circuit input, further comprising the feedback circuit configured to provide a DC bias correction signal to the feedback output in response to a first signal at the gas cell input. A system configured such that the processing circuit provides at least one of a frequency modulation control signal at the frequency modulation control output and an amplitude modulation control signal at the amplitude modulation control output in response to a difference between the first signal and the DC bias correction signal.

6. The system according to claim 5, wherein the processing circuit includes an anti-aliasing filter configured to filter the difference. A system further configured such that the processing circuit provides at least one of the frequency modulation control signal and the amplitude modulation control signal in response to the filtered difference.

7. The system according to claim 2, wherein the signal generator is a first fractional-N synthesizer having a first reference signal input, a first synthesizer control input coupled to the frequency modulation input, and a first synthesizer output, configured to provide a third signal to the first synthesizer output by multiplying the frequency of the reference signal at the first reference signal input based on the state of the first synthesizer control input; the fractional-N synthesizer; a frequency multiplier having a multiplier input coupled to the first synthesizer output and a multiplier output coupled to the signal generator output; and including.

8. The system according to claim 7, further comprising a fractional-N frequency divider having a frequency divider input coupled to the first synthesizer output, a frequency divider control input, and a frequency divider output. The system, wherein the processing circuit further has a third control output coupled to the divider control input, and the processing circuit is configured to provide a frequency modulation cancellation signal to the third control output. **Claim 9**: The system according to claim 7, further comprising a second fractional-N synthesizer having a frequency adjustment input, a second synthesizer control input, and a second synthesizer output, wherein the frequency modulation signal includes a frequency adjustment component and a frequency modulation signal component, the processing circuit further has a third control output coupled to the frequency adjustment input, and the processing circuit is configured to provide a third control signal to the third control output based on the frequency adjustment component. **Claim 10**: The system according to claim 7, further comprising a second fractional-N synthesizer having a second reference signal input, a second synthesizer control input, and a second synthesizer output coupled to the first reference signal input, wherein the frequency modulation signal includes a frequency adjustment component and a frequency modulation signal component, the processing circuit further has a third control output coupled to the second synthesizer control input, and the processing circuit is configured to provide a third control signal to the third control output based on the frequency adjustment component. **Claim 11**: The system according to claim 7, wherein the frequency modulation signal includes a frequency adjustment component and a frequency modulation signal component, the processing circuit further has a third control output, and the processing circuit is configured to provide a third control signal to the third control output based on the frequency adjustment component, the signal generator includes a reference signal generator having a frequency adjustment input coupled to the third control output and a reference signal output coupled to the reference signal input. **Claim 12**: The system according to claim 11, wherein the processing circuit further has a sensor input, A system configured such that the processing circuit receives a temperature sensor signal in the sensor input and provides the third control signal to the third control output in response to the temperature sensor signal. **Claim 13**: The system according to claim 1, wherein the frequency modulation control signal includes a frequency adjustment component and a frequency modulation signal component, and the processing circuit provides a frequency modulation control signal to the frequency modulation control output, performs a first correlation between a first signal at the processing circuit input and a second signal having a first frequency within a first interval and a second frequency within a second interval and including the frequency modulation signal component to generate a first correlation output signal, generates the frequency adjustment component based on the first correlation output signal, performs a second correlation between the first correlation output signal and a third signal alternating between a first state within the first interval and a second state within the second interval to generate a second correlation output signal, and generates an amplitude modulation control signal for the amplitude modulation control output based on the second correlation output signal. A system configured as such. **Claim 14**: The system according to claim 1, wherein the frequency modulation control signal includes a frequency adjustment component and a frequency modulation signal component, and the processing circuit is configured to provide a frequency modulation control signal to the frequency modulation control output and generate the frequency adjustment component, and the amplitude modulation control signal at the amplitude modulation control output is based on odd harmonic components of the signal at the processing circuit input. **Claim 15**: The system according to claim 1, wherein the processing circuit is configured to provide an amplitude modulation control signal to the amplitude modulation control output, and the amplitude modulation control signal includes an in-phase parameter component and a quadrature parameter component. **Claim 16**: A system, A signal generator having a frequency modulation input and a signal generator output, A transmitter having a signal input coupled to the signal generator output and a transmitter output, A receiver having a receiver input, an amplitude modulation input, and a receiver output, A frequency modulator having a frequency modulation control input and a frequency modulation output coupled to the frequency modulation input, An amplitude modulator having an amplitude modulation control input and an amplitude modulation output coupled to the amplitude modulation input, A processing circuit having a processing circuit input coupled to the receiver output, an amplitude modulation control output coupled to the amplitude modulation control input, and a frequency modulation control output coupled to the frequency modulation control input, A system comprising.

17. The system according to claim 16, Wherein the signal generator is configured to provide a first signal to the signal generator output in response to a frequency modulation signal at the frequency modulation input.

18. The system according to claim 16, Wherein the processing circuit further has a sensor input, Wherein the processing circuit is configured to receive a temperature sensor signal at the sensor input and provide a frequency modulation control signal to the frequency modulation control output in response to the temperature sensor signal.

19. The system according to claim 16, A gas cell having a first terminal coupled to the transmitter output and a second terminal coupled to the receiver input, the gas cell being configured to receive a first signal at the first terminal and provide a second signal by removing a specific frequency component of the first signal.

20. The system according to claim 16, A feedback circuit having a feedback input coupled to the receiver input and a feedback output coupled to the processing circuit input, the feedback circuit being configured to provide a DC bias correction signal to the feedback output in response to a first signal at the receiver input, further comprising the feedback circuit. The system is configured such that the processing circuit provides at least one of a frequency modulation control signal at the frequency modulation control output and an amplitude modulation control signal at the amplitude modulation control output in response to a difference between the first signal and the DC bias correction signal.

21. The system according to claim 16, wherein The system further includes a gate circuit coupled between the processing input and at least one of the amplitude modulation control output and the frequency modulation control output.

22. An apparatus, comprising A signal generator having a frequency modulation input and a signal generator output, A transmitter having a signal input coupled to the signal generator output and a transmitter output, A receiver having a receiver input, an amplitude modulation input, and a receiver output, A gas cell coupled between the transmitter output and the receiver input, A frequency modulator having a frequency modulation control input and a frequency modulation output coupled to the frequency modulation input, An amplitude modulator having an amplitude modulation control input and an amplitude modulation output coupled to the amplitude modulation input, A processing circuit having a processing circuit input coupled to the receiver output, an amplitude modulation control output coupled to the amplitude modulation control input, and a frequency modulation control output coupled to the frequency modulation control input, An apparatus including.

23. The apparatus according to claim 22, wherein The signal generator is configured to provide a frequency modulation signal to the signal generator output in response to a frequency modulation signal at the frequency modulation input. An apparatus configured such that the transmitter provides a first signal to the transmitter output in response to a second signal at the signal input and a frequency modulation signal at the amplitude modulation input. **Claim 24.** The apparatus according to claim 23, further comprising a feedback circuit having a feedback input coupled to the receiver output and a feedback output coupled to the processing circuit input, the feedback circuit being configured to provide a DC bias correction signal to the feedback output in response to a third signal at the receiver input, wherein the processing circuit is configured to provide at least one of a frequency modulation control signal at the frequency modulation control output and an amplitude modulation control signal at the amplitude modulation control output in response to a difference between the third signal and the DC bias correction signal. **Claim 25.** The apparatus according to claim 22, further comprising a gate device coupled between the processing circuit and at least one of the frequency modulation control output and the amplitude modulation control output. **Claim 26.** The apparatus according to claim 22, wherein the processing circuit further has a sensor input, and the processing circuit is configured to receive a temperature sensor signal at the sensor input and provide a frequency modulation control signal to the frequency modulation control output in response to the temperature sensor signal.

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