Reduced impedance board

Abstract

Disclosed is an apparatus including a substrate and techniques for manufacturing the apparatus. The substrate may include a first metal layer having signal interconnects on a first side of the substrate. A second metal layer may include a ground plane portion on a second side of the substrate. A conductive channel may be formed in the substrate and coupled to the ground plane portion. The conductive channel is configured to extend the ground plane portion toward the signal interconnects to reduce the distance from the individual signal interconnects to the individual conductive channel. The distance may be within a range of 75%-50% of the substrate thickness between the first metal layer and the second metal layer.

Description

[Technical field]

[0001] 1. Field of disclosure Aspects of the present disclosure relate generally to integrated circuits (ICs), and more particularly, to reducing impedance on a substrate for high speed data signals.

[0002] 2. Description of Related Art

[0002] A semiconductor (also known as a chip or integrated circuit (IC)) can include a Molded Embedded Package (MEP) with a laminate substrate. The MEP can include a Package-on-Package (POP) with connections for a Dynamic Random Access Memory (DRAM). In traditional designs, the substrate forming the connection between the memory (e.g., DRAM) and the processor can be limited by the high impedance of the signal interconnects coupling the memory to the processor.

[0003]

[0003] Therefore, there is a need for systems, devices and methods that overcome the shortcomings of conventional substrate designs, including the methods, systems and devices provided herein in the disclosure that follows. Summary of the Invention

[0004]

[0004] The following provides a simplified summary relating to one or more aspects disclosed herein. As such, the following summary should not be considered an extensive overview of all contemplated aspects, nor should it be considered to identify key or critical elements of all contemplated aspects or to define the scope relating to any particular aspect. Thus, the sole purpose of the following summary is to present some concepts of one or more aspects of the mechanisms disclosed herein in a simplified form prior to the detailed description presented below.

[0005] At least one aspect includes an apparatus comprising a substrate comprising: a first metal layer comprising a plurality of signal interconnects on a first side of the substrate; a second metal layer comprising a plurality of ground plane portions on a second side of the substrate; and a plurality of conductive channels in the substrate coupled to the plurality of ground plane portions, the plurality of conductive channels configured to extend the plurality of ground plane portions toward the signal interconnects to reduce a distance from each of the signal interconnects to each of the conductive channels, the distance being within a range of 75%-50% of a substrate thickness between the first metal layer and the second metal layer.

[0006]

[0006] At least one other second aspect includes a method of manufacturing a device, the method including providing a substrate including a first metal layer and a second metal layer, forming a plurality of signal interconnects on a first side of the substrate, forming a plurality of ground plane portions on a second side of the substrate, and forming a plurality of conductive channels in the substrate coupled to the plurality of ground plane portions, the plurality of conductive channels being configured to extend the plurality of ground plane portions toward the signal interconnects to reduce a distance from each of the signal interconnects to each of the conductive channels, the distance being within a range of 75%-50% of a substrate thickness between the first metal layer and the second metal layer.

[0007]

[0007] Other objects and advantages associated with the embodiments disclosed herein will become apparent to those skilled in the art based on the accompanying drawings and detailed description. [Brief description of the drawings]

[0008]

[0008] The accompanying drawings are presented to aid in the explanation of various aspects of the present disclosure and are provided only for illustration of the aspects, not for limiting the aspects. A more complete understanding of the present disclosure can be obtained by referring to the following detailed description in conjunction with the accompanying drawings. In the figures, the left-most digit(s) of a reference number identifies the figure in which that reference number first appears. The same reference number in different figures indicates similar or identical items. [Figure 1]

[0009] 1 illustrates an exemplary package having a core according to various aspects of the present disclosure. [Diagram 2]

[0010] 1 illustrates an exemplary coreless package according to various aspects of the present disclosure. [Diagram 3]

[0011] 1 illustrates an exemplary package including a molded embedded package (MEP) having a laminate substrate according to various aspects of the present disclosure. [Figure 4A]

[0012] 1 illustrates a first set of stages for forming a cored substrate of a package according to various aspects of the present disclosure. [Figure 4B] 1 illustrates a first set of stages for forming a cored substrate of a package according to various aspects of the present disclosure. [Figure 4C] 1 illustrates a first set of stages for forming a cored substrate of a package according to various aspects of the present disclosure. [Figure 4D] 1 illustrates a first set of stages for forming a cored substrate of a package according to various aspects of the present disclosure. [Figure 5A]

[0013] 13 illustrates a second set of stages for forming a cored substrate of a package according to various aspects of the present disclosure. [Figure 5B] 13 illustrates a second set of stages for forming a cored substrate of a package according to various aspects of the present disclosure. [Figure 5C] 13 illustrates a second set of stages for forming a cored substrate of a package according to various aspects of the present disclosure. [Figure 5D] 13 illustrates a second set of stages for forming a cored substrate of a package according to various aspects of the present disclosure. [Figure 6]

[0014] 1 illustrates a process including forming a cored substrate of a package according to various aspects of the present disclosure. [Figure 7]

[0015] 1 illustrates various electronic devices that may be integrated with an integrated or semiconductor device in accordance with one or more aspects of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009]

[0016] Aspects of the present disclosure are provided in the following description and associated drawings, directed to various examples provided for illustrative purposes. Alternative aspects may be devised without departing from the scope of the present disclosure. Additionally, well-known elements of the present disclosure will not be described in detail or will be omitted so as not to obscure the relevant details of the present disclosure.

[0010]

[0017] The terms "exemplary" and / or "example" are used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" and / or "example" is not necessarily to be construed as preferred or advantageous over other aspects. Similarly, the term "aspects of the disclosure" does not require that all aspects of the disclosure include the described feature, advantage or mode of operation.

[0011]

[0018] Various aspects disclosed herein include devices and techniques for reducing the impedance of a substrate (cored or coreless) to enable the use of high speed signals, e.g., signals transmitted at approximately 200 megahertz (MHz) to 12 gigahertz (GHz). In some aspects, the high speed signals may include high speed data (DQ) signals used to access dynamic random access memory (DRAM). For example, package-on-package (POP) DRAM uses high speed DQ signals for data transfer to and from a memory array. Various aspects disclosed herein include devices and techniques for controlling impedance in a substrate to facilitate high speed communication.

[0012]

[0019] The devices and techniques described herein can be used with packages having cored or coreless substrates (e.g., prepregs). Glass fibers pre-impregnated with resin are called prepregs. The cores in the cored substrates can be formed, for example, using copper clad laminates (CCLs), e.g., copper with epoxy material reinforced with glass fibers. The copper clad laminates are soaked in resin with glass fibers (or other reinforcing materials), and copper cladding is added to either one or both sides. In some exemplary embodiments, the core thickness can range from 40 micrometers (um or microns) to 1.2 millimeters (mm).

[0013]

[0020] In some embodiments, a semiconductor (also known as a chip or integrated circuit (IC)) can include a molded embedded package (MEP) with a laminated substrate. The MEP can include a package-on-package (POP) with connections for dynamic random access memory (DRAM). In some embodiments, the MEP uses a two-layer substrate, with a first layer (M1) used for signal routing and a second layer (M2) generally used as a ground shield plane. For example, when the thickness of the cored substrate is typically about 40 micrometers (μm or microns), the cored substrate can have an impedance of at least 50 ohms (Ω). Such a relatively high impedance can affect the speed of signals in the signal routing.

[0014]

[0021] For high speed signals, impedances below 50 ohms are preferred, especially as DRAM access speeds increase. One way to lower the impedance is to shorten the distance between the high speed signal (e.g., first layer) and the ground plane (e.g., second layer). However, for cored boards with thicknesses of about 40 microns, using a thinner core may not be an option, as thinner cores may cause warping. The devices and techniques described herein may be used to reduce impedance by shortening the distance between the high speed signal (e.g., first layer) and the ground plane (e.g., second layer) without changing the thickness of the board. It will be understood that the various aspects are not limited to the exemplary configurations described above. For example, in some configurations, layers may be inverted, some signal and / or power lines may be included in the M2 layer, the core may be of different thickness, etc.

[0015]

[0022] 1 illustrates an exemplary package 100 having a cored substrate 101 according to various aspects of the present disclosure. The package 100 includes the cored substrate 101 having a core 112, a first metal layer 102 (also referred to as M1) above the core 112, and a second metal layer 104 (also referred to as M2) below the core 112.

[0016]

[0023] The first metal layer 102 may include structures such as signal interconnects 114, which may be traces or lines within the first metal layer. The first metal layer includes a number of signal interconnects and adjacent grounds 106(1), pads, and other metal structures. The second metal layer 104 may include a ground plane portion 106(2), which may be on the opposite side of the signal interconnects 114. The ground plane portions 106(2) are coupled to a ground potential and collectively form a ground reference plane. Vias 108 may be plated or filled through the substrate vias and may be configured to electrically couple adjacent grounds 106(1) in the first metal layer 102 to ground plane portions 106(2) in the second metal layer 104. It will be appreciated that in various aspects, the metal planes 106 may be coupled to a power line (Vdd) or ground, and the metal planes 106 shown in FIG. 1 should be understood to be ground plane portions.

[0017]

[0024] Conductive channel 110 is disposed within core 112 of cored substrate 101. Although one metal layer (e.g., 102, 104) is shown, it will be understood that the various disclosed aspects are not limited to this configuration. In some aspects, cored substrate 101 can have two or more metal layers on either side of core 112. In some aspects, as shown in FIG. 1, first metal layer 102 (M1), plated through via 108, conductive channel 110, and second metal layer 104 (M2) can use any highly conductive material, such as, for example, copper (Cu), cobalt (Co), ruthenium (Ru), tungsten (W), molybdenum (Mo), gold (Au), silver (Ag), aluminum (Al), tin (Sn), or any combination thereof.

[0018]

[0025] In the example shown in FIG. 1 , each conductive channel 110 is disposed below and approximately aligned with each of the signal interconnects 114. The conductive channels are formed in trenches 109, which are shown only as boundaries of the conductive channels 110. The signal interconnects 114 may be configured to carry high-speed signals. In some embodiments, the high-speed signals may include DQ (data) signals for dynamic random access memory (DRAM). In some embodiments, the core 112 has a thickness 116 (e.g., substrate thickness) of about 40 microns. In some embodiments, each conductive channel 110 has a channel width 120 that is about the same width as each signal interconnect 114 to about 5 microns wider than each signal interconnect 114. The additional width may be used to compensate for slight misalignment between the signal interconnects 114 and the conductive channels 110. As described herein, the addition of the conductive channel 110 electrically coupled to the ground plane portion 106(2) results in an effective reduction in the distance 118 between the signal interconnect 114 and the ground plane portion 106(2). Additionally, in the portion below the signal interconnect 114, the core 112 is reduced from the thickness 116 to the distance 118. The distance 118 can be considered to be approximately 25%-50% less than the thickness 116, or 75%-50% (i.e., a 25%-50% reduction) of the substrate thickness between the first metal layer 102 and the second metal layer 104. For example, if the thickness 116 is approximately 40 microns, the distance 118 can be approximately 20-30 microns, or generally less than approximately 30 microns.

[0019]

[0026] In some aspects, the substrate 101 may be a printed circuit board (PCB) and may include a prepreg and a core 112. The core 112 may use a prepreg such as FR4, where FR indicates a flame retardant material and the "4" indicates a glass-reinforced epoxy resin, and the core 112 has a uniform specified thickness (e.g., 40 microns). The core 112 is used to provide structural stability (e.g., prevent warping, deformation, etc.) and signals travel through the signal interconnects 114 on the first layer 102 and the ground plane on the second layer 104. The uniform thickness of the core 112 provides a uniform impedance. The conductive channel 110 can lower the impedance without reducing the thickness 116 of the core 112 or substantially reducing the structural stability.

[0020]

[0027] The conductive channel 110 is formed in the core 112 beneath a signal interconnect 114 that is electrically coupled to the ground plane portion 106(2) and configured to transmit high speed data. This provides a technical advantage in that the distance between the signal interconnect 114 and the ground plane portion 106(2) can be effectively reduced through the conductive channel 110. The reduced distance 118 provides a lower impedance, as described herein. The lower impedance provides a technical advantage in that the signal interconnect 114 can be configured to transmit high speed data signals, such as DQ signals used to access a DRAM. In this manner, the signal interconnect 114 can be used to access a faster DRAM (e.g., compared to a substrate that does not include a conductive channel), thereby providing improved performance for a given substrate design.

[0021]

[0028] According to various disclosed aspects, the devices and techniques described herein may be used with a coreless substrate. Figure 2 shows an example coreless substrate 201 of a package 200 according to various aspects of the present disclosure. The package 200 includes a coreless substrate 201 having a dielectric 212, a first metal layer 202 (also referred to as M1) above the dielectric 212, and a second metal layer 204 (also referred to as M2) below the dielectric 212.

[0022]

[0029] The first metal layer 202 may include structures such as signal interconnects 214 and other metal structures such as adjacent grounds 206(1). The second metal layer 204 may include a ground plane portion 206(2), which may be on the opposite side of the signal interconnects 214. The ground plane portion 206(2) is connected to a ground potential. A via 208 may connect the adjacent grounds 206(1) in the first metal layer 202 to the ground plane portion 206(2) in the second metal layer 204.

[0023]

[0030] The conductive channel 210 is disposed within the dielectric 212 of the coreless substrate 201. Although one metal layer (e.g., 202, 204) is shown, it will be understood that the various disclosed aspects are not limited to this configuration. In some aspects, the coreless substrate 201 can have two or more metal layers on either side of the dielectric 212. In some aspects, as shown in FIG. 2, the first metal layer 202 (M1), the via 208, the conductive channel 210, and the second metal layer 204 (M2) can use any highly conductive material, such as, for example, copper (Cu), cobalt (Co), ruthenium (Ru), tungsten (W), molybdenum (Mo), gold (Au), silver (Ag), aluminum (Al), tin (Sn), or any combination thereof.

[0024]

[0031] In the example shown in FIG. 2, each conductive channel 210 is disposed below and substantially aligned with each of the signal interconnects 214. The signal interconnects 214 may be configured to transmit high-speed signals. In some embodiments, the high-speed signals may include DQ (data) signals for dynamic random access memory (DRAM). In some embodiments, each conductive channel 210 has a channel width 220 that is approximately the same width as each signal interconnect 214 to approximately 5 microns wider than each signal interconnect 214. The additional width may be used to compensate for slight misalignment between the signal interconnects 214 and the conductive channels 210. As described herein, the addition of the conductive channels 210 electrically coupled to the ground plane portion 206(2) results in an effective reduction in the distance 218 between the signal interconnects 214 and the ground plane portion 206(2). Additionally, in the portion below signal interconnect 214, dielectric 212 is reduced from thickness 216 (substrate thickness) to a distance 218. Distance 218 is approximately 25%-50% less than thickness 216, or 75%-50% of thickness 216. For example, if thickness 216 is approximately 25 microns, distance 218 may be approximately 12.5-19 microns.

[0025]

[0032] The thickness 216 of the coreless substrate 201 may be between about 25 microns and 50 microns. The coreless substrate 201 may, in some embodiments, include one or more layers of dielectric 212. In some embodiments, the dielectric 212 may be a prepreg having a thickness between about 25 microns and 50 microns. The width 220 of the conductive channel 210 may be between about 8 μm and 100 μm, and in some embodiments, may be within a range of 25% to 75% of the substrate thickness. In some embodiments, the conductive channel 210 may have a depth of about 12 microns and may be disposed within the dielectric 212 to lower the impedance of the signal interconnect 214 in a manner similar to that described above with respect to the cored substrate.

[0026]

[0033] FIG. 3 illustrates an example package 300 including a molded embedded package (MEP) 304 with a laminated substrate according to various aspects of the disclosure. The package 300 includes a dynamic random access memory (DRAM) 302 electrically coupled to the MEP 304. The MEP 304 includes a substrate 310, an application processor (AP) die 306, and a package substrate 308. In some aspects, the substrate 310 may be configured as an interposer for coupling the AP die 306 to the DRAM 302 and may be designed according to the cored substrate 101 of FIG. 1 or the coreless substrate 201 of FIG. 2. It will be understood that the illustrated configuration is provided only as one example of a configuration to help illustrate various aspects disclosed herein, and that other configurations are included in the various aspects disclosed. For example, the AP die 306 may be a standalone device rather than part of the MEP 304 and still be coupled to the DRAM 302 using the substrate 310. Accordingly, the various disclosed aspects should not be construed as limited to the examples shown, as other arrangements and configurations of the various components will be apparent from the disclosure herein.

[0027]

[0034] 4A, 4B, 4C, and 4D illustrate a partial manufacturing process according to one or more embodiments of the present disclosure. In FIG. 4A, the manufacturing process may begin by providing a copper core laminate (CCL) substrate 401 including a first metal layer 402, a second metal layer 404, and a core 412 (e.g., FR4). In FIG. 4B, the manufacturing process may continue with performing a patterning and etching 405 on the second metal layer 404 to form a metal opening in the second metal layer 404 to expose the core 412. Additionally, in some embodiments, the etching 405 may form other metal structures in the second metal layer 404. In FIG. 4C, the manufacturing process may continue with patterning a trench 409 in the core 412 through the opening in the second metal layer 404. In FIG. 4D, the manufacturing process may continue with applying a layer of photoresist 407 to the second metal layer 404 on which the etching 405 has been performed. A layer of photoresist 407 may fill the trenches 409 through the openings in the second metal layer 404 .

[0028]

[0035] 5A, 5B, 5C, and 5D show a partial manufacturing process according to one or more embodiments of the present disclosure. In FIG. 5A, the manufacturing process can continue from FIG. 4D with removing the photoresist 407 from the openings of the trenches 409 and the second metal layer 404. In FIG. 5B, the manufacturing process continues with a metal filling process 510. A metal, which may be copper or the like, is used to fill each of the trenches 409 to form a conductive channel 410. In addition to forming the conductive channel 410, the metal filling process 510 may fill the openings of the second metal layer 404. It will be understood that the conductive channel 410 is closer to the first metal layer 402 as shown in FIG. 5B. In FIG. 5C, the manufacturing process can continue with removing the remaining portions of the photoresist. Now, the substrate 401 includes the conductive channel 410 together with the first metal layer 402, the second metal layer 404, and the core 412. In FIG. 5D, the manufacturing process can continue with conventional processing on the substrate 401. For example, vias 408 are formed by drilling and filling or plating holes to form vias 408 between the first metal layer 402 and the second metal layer 404. Lithography processes can be performed to pattern and etch the first metal layer 402 to form signal interconnects 414, adjacent ground 406(1), and any other metal structures in the first metal layer 402. Similarly, lithography processes can be performed to pattern and etch the second metal layer 404 to form ground plane portion 406(2) and any other metal structures in the first metal layer 402. It will be appreciated that the substrate 401 (FIG. 5D) is similar to the substrate 101 (FIG. 1), except that it is rotated 180 degrees, with the first metal layer 402 at the bottom and the second metal layer 404 at the top. Therefore, a detailed description of the various aspects of the substrate 401 will not be provided.

[0029]

[0036] Therefore, as understood from the above disclosure, additional processes for manufacturing the various embodiments disclosed herein will be apparent to those skilled in the art, and a literal representation of each of the various processes is not provided or illustrated in the included drawings. For example, it will be understood that in some embodiments, the manufacturing process of the coreless substrate can generally follow the manufacturing process described above. Furthermore, it is understood that the order of the manufacturing processes is not necessarily in any order, and that later processes can be described first for the convenience of describing the various embodiments disclosed.

[0030]

[0037] As can be seen from the above, there are various methods for manufacturing the devices disclosed herein. FIG. 6 shows a flow chart of a method / process 600 for manufacturing a device / apparatus including a low impedance substrate according to at least one embodiment of the present disclosure. In the flow diagram of FIG. 6, each block represents one or more operations that may be implemented in hardware, software, or a combination thereof. In the context of software, the blocks represent computer executable instructions that, when executed by one or more processors, cause the processors to perform the recited operations. The order in which the blocks are described is not intended to be construed as limiting, and any number of the described operations may be combined in any order and / or in parallel to perform the process. For illustrative purposes, the process 600 is described with reference to FIGS. 1, 2, 3, 4A, 4B, 4C, 4D, 5A, 5B, 5C, and 5D as described above, although other models, configurations, systems, and environments may be used to implement the process. In some embodiments, the process 600 may be partially performed during a semiconductor manufacturing process.

[0031]

[0038] At block 602, the process 600 begins with providing a substrate comprising a first metal layer and a second metal layer. At block 604, the process 600 continues with forming a plurality of signal interconnects on a first side of the substrate. For example, in FIG. 5D, patterning is used to create the signal interconnect 114 or 214 in the first metal layer 102 or 202. At block 606, the process 600 continues with forming a plurality of ground plane portions on a second side of the substrate. For example, ground plane portions 106(2), 206(2) in the first metal layer 102, 202. At block 608, the process 600 continues with forming a plurality of conductive channels in the substrate coupled to the plurality of ground plane portions. The plurality of conductive channels are configured to extend the plurality of ground plane portions toward the signal interconnects to reduce the distance from the individual signal interconnects to the individual conductive channels. For example, in FIG. 5A, FIG. 5B, and FIG. 5C, conductive channels 410 are created and plated or filled with metal to create conductive channels 410 in contact with the ground plane portion (e.g., 406(2) in FIG. 5D). Each conductive channel is disposed below each signal interconnect. Further, in block 608, the distance in some embodiments is within a range of 75%-50% of the substrate thickness between the first metal layer and the second metal layer. For example, as shown in FIG. 1, each conductive channel 110 is disposed below one of the signal interconnects 114. The distance 118 from each conductive channel 110 to the signal interconnect 114 disposed directly above each conductive channel 110 can be considered to be at least 25% less than the thickness 116 of the core 112, or 75%-50% of the substrate thickness. For example, if the substrate thickness 116 of the core 112 is 40 microns, then the distance 118 between the signal interconnects 114 and the conductive channels disposed below the signal interconnects 114 is approximately 20-30 microns, e.g., 50%-25% of the thickness 116 of the core 112. As another example, in FIG. 2, each of the conductive channels 210 is disposed below one of the signal interconnects 214.The distance 218 from each of the conductive channels 210 to the signal interconnects 214 disposed directly above each conductive channel 210 is less than 75%-50% of the substrate thickness 216 of the substrate 201 .

[0032]

[0039] Thus, a conductive channel in contact with the ground plane is disposed in the substrate (e.g., cored or coreless) below the signal interconnect capable of transmitting high speed data, providing the technical advantage of reducing the distance between the signal interconnect and the ground plane. The shorter distance provides the further technical advantage of lower impedance. The lower impedance provides the technical advantage of allowing the signal interconnect to transmit high speed data signals, such as DQ signals used to access DRAM. In this manner, the signal interconnect can be used to access faster DRAM (e.g., compared to a substrate not including a conductive channel), thereby enabling faster performance.

[0033]

[0040] Other technical advantages may be recognized from the various aspects disclosed herein, and these technical advantages are provided merely as examples and should not be construed as limiting any of the various aspects disclosed herein.

[0034]

[0041] The foregoing disclosed devices and functions can be designed and stored in computer files (e.g., register transfer level (RTL), geometric data stream (GDS) Gerber, etc.) stored on a computer readable medium. Some or all of such files may be provided to a fabricator who fabricates devices based on such files. The resulting products can include a variety of components, including semiconductor wafers, which are then cut into semiconductor dies and packaged into semiconductor packages, integrated devices, package-on-package devices, system-on-chip devices, etc., which can then be used in the various devices described herein.

[0035]

[0042] It will be appreciated that various aspects disclosed herein may be described as functional equivalents of structures, materials, and / or devices described and / or recognized by those skilled in the art. For example, in one aspect, an apparatus may comprise means for performing various functions described above. It will be understood that the foregoing aspects are provided by way of example only, and that the various aspects claimed are not limited to the specific content and / or figures cited as examples.

[0036]

[0043] 7 illustrates various electronic devices that may be integrated with any of the aforementioned packages or semiconductor devices according to various examples of the present disclosure. For example, a mobile phone device 702, a laptop computer device 704, and a stationary terminal device 706 may each be generally considered user equipment (UE) and may include a package 700 having a cored substrate as described herein. The package 700 may be, for example, any of the integrated circuits, dies, integrated devices, integrated device packages, integrated circuit devices, device packages, integrated circuit (IC) packages, and package-on-package devices described herein. The devices 702, 704, 706 illustrated in FIG. 7 are merely examples. Other devices may also include package 700, including, but are not limited to, a group of devices (e.g., electronic devices) including mobile devices, handheld personal communications system (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, stationary data units such as meter reading equipment, communications devices, smartphones, tablet computers, computers, wearable devices, servers, routers, electronic devices implemented in automobiles (e.g., autonomous vehicles), Internet of Things (IoT) devices, or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0037]

[0044] It should be noted that although specific frequencies, integrated circuits (ICs), hardware, and other features are described in the embodiments herein, alternative embodiments may vary. That is, alternative embodiments may utilize additional or alternative frequencies (e.g., other 60 GHz and / or 28 GHz frequency bands), antenna elements (e.g., having antenna element arrays of different sizes / shapes), scanning periods (including both static and dynamic scanning periods), electronic devices (e.g., WLANAPs, cellular base stations, smart speakers, IoT devices, mobile phones, tablets, personal computers (PCs), etc.), and / or other features. Such variations will be understood by those skilled in the art.

[0038]

[0045] It should be understood that any reference to an element herein using a designation such as "first," "second," etc., does not generally limit the quantity or order of those elements. Rather, these designations may be used herein as a convenient way of distinguishing between two or more elements or instances of an element. Thus, reference to a first element and a second element does not imply that only two elements may be employed therein, or that the first element must precede the second element in some manner. Also, unless otherwise stated, a set of elements may comprise one or more elements. In addition, a term of the form "at least one of A, B, or C" or "one or more of A, B, or C" or "at least one of the group consisting of A, B, and C" as used in the present description or claims means "A or B or C, or any combination of these elements." For example, the term may include A, or B, or C, or A and B, or A and C, or A and B and C, or 2A, or 2B, or 2C, etc.

[0039]

[0046] In light of the above description and explanations, those skilled in the art will appreciate that the various exemplary logic blocks, modules, circuits, and algorithm steps described in connection with the aspects disclosed herein may be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability of hardware and software, various exemplary components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in various ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0040]

[0047] In the above detailed description, it can be seen that various features are grouped together in each example. This mode of disclosure should not be understood as an intention that the exemplary clauses have more features than are expressly stated in each clause. Rather, various aspects of the disclosure may include fewer than all features of each disclosed exemplary clause. Thus, the following clauses should be considered as incorporated in the description, and each clause may stand alone as a separate example. Although each dependent clause may refer to a specific combination with one of the other clauses in the clause, the aspects of that dependent clause are not limited to that specific combination. It will be understood that other exemplary clauses may also include combinations of aspects of the dependent clause with the subject matter of any other dependent clause or independent clause, or any combination of features with other dependent clauses and independent clauses. Unless it is expressly expressed or readily inferred that a specific combination is not intended (e.g., conflicting aspects such as defining an element as both an insulator and a conductor), the various aspects disclosed herein expressly include these combinations. It is further intended that aspects of a clause may be included in any other independent clause, even if the clause is not directly dependent on the independent clause.Example implementations are described in the following numbered clauses.

[0041]

[0048] Clause 1. An apparatus comprising a substrate, the substrate comprising: a first metal layer comprising a plurality of signal interconnects on a first side of the substrate; a second metal layer comprising a plurality of ground plane portions on a second side of the substrate; and a plurality of conductive channels in the substrate coupled to the plurality of ground plane portions, the plurality of conductive channels being configured to extend the plurality of ground plane portions towards the signal interconnects to reduce a distance from an individual signal interconnect to an individual conductive channel, the distance being within a range of 75%-50% of a substrate thickness between the first metal layer and the second metal layer.

[0042] Clause 2. The apparatus of clause 1, wherein the plurality of signal interconnects are configured to transmit high speed data signals.

[0043] Clause 3. The apparatus of clause 2, wherein the plurality of signal interconnects are coupled to a dynamic random access memory (DRAM).

[0044] Clause 4. The apparatus of clause 3, further comprising a processor die coupled to the DRAM by the substrate.

[0045] Clause 5. The apparatus of clause 4, further comprising a Molded Embedded Package (MEP) comprising the processor die, the substrate, and the DRAM.

[0046] Clause 6. The device of any one of clauses 1-5, wherein the first metal layer, the second metal layer, and the plurality of conductive channels comprise at least one of copper (Cu), cobalt (Co), ruthenium (Ru), wolfram (W), molybdenum (Mo), gold (Au), silver (Ag), aluminum (Al), tin (Sn), or any combination thereof.

[0047] Clause 7. The apparatus of any one of clauses 1 to 6, wherein the substrate is a cored substrate.

[0048] Clause 8. The apparatus of clause 7, wherein the substrate thickness is in the range of 40 micrometers to 1.2 millimeters.

[0049] Clause 9. The device of clause 7 or 8, wherein a plurality of conductive channels are formed within the core of the cored substrate, the substrate thickness is about 40 micrometers, and the distance is about 20 micrometers to about 30 micrometers.

[0050] Clause 10. An apparatus described in any one of clauses 1 to 9, wherein the substrate is a coreless substrate having a dielectric between the first metal layer and the second metal layer.

[0051] Clause 11. The apparatus of clause 10, wherein the substrate thickness is in the range of 25 micrometers to 50 micrometers.

[0052] Clause 12. The device of clause 10 or 11, wherein a plurality of conductive channels are formed within a dielectric of a coreless substrate, the substrate thickness being about 25 micrometers, and the distance being about 12.5 micrometers to about 19 micrometers.

[0053] Clause 13. An apparatus as described in any one of clauses 1 to 12, wherein the impedance of each of the plurality of signal interconnects is less than 50 ohms.

[0054] Clause 14. A device according to any one of clauses 1 to 13, wherein a width of each of the plurality of conductive channels is no more than 5 micrometers greater than a width of each of the plurality of signal interconnects.

[0055] Clause 15. The apparatus of any one of clauses 1 to 14, wherein the apparatus is selected from the group consisting of a package, a Molded Embedded Package (MEP), a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a stationary terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, a base station, and a device in an automobile.

[0056] Clause 16. A method of manufacturing a device, the method comprising: providing a substrate having a first metal layer and a second metal layer; forming a plurality of signal interconnects on a first side of the substrate; forming a plurality of ground plane portions on a second side of the substrate; and forming a plurality of conductive channels in the substrate coupled to the plurality of ground plane portions, the plurality of conductive channels being configured to extend the plurality of ground plane portions towards the signal interconnects to reduce a distance from an individual signal interconnect to an individual conductive channel, the distance being within a range of 75%-50% of a substrate thickness between the first metal layer and the second metal layer.

[0057] Clause 17. The method of clause 16, wherein the plurality of signal interconnects are configured to transmit high speed data signals.

[0058] Clause 18. The method of clause 17, wherein the plurality of signal interconnects are coupled to a dynamic random access memory (DRAM).

[0059] Clause 19. The method of clause 18, further comprising coupling the processor die to the DRAM using the substrate.

[0060] Clause 20. The method of clause 19, further comprising forming a molded embedded package (MEP) comprising the processor die, the substrate, and the DRAM.

[0061] Clause 21. The method of any one of clauses 16 to 20, wherein the first metal layer, the second metal layer, and the plurality of conductive channels comprise at least one of copper (Cu), cobalt (Co), ruthenium (Ru), Wolfram (W), molybdenum (Mo), gold (Au), silver (Ag), aluminum (Al), tin (Sn), or any combination thereof.

[0062] Clause 22. The method of any one of clauses 16 to 21, wherein the substrate is a cored substrate having a core.

[0063] Clause 23. The method of clause 22, wherein the substrate thickness is in the range of 40 micrometers to 1.2 millimeters.

[0064] Clause 24. The method of clause 23, wherein the plurality of conductive channels are formed within a core of a cored substrate, the substrate thickness is about 40 micrometers, and the distance is about 20 micrometers to about 30 micrometers.

[0065] Clause 25. The method of any one of clauses 16 to 24, wherein the substrate is a coreless substrate having a dielectric between the first metal layer and the second metal layer.

[0066] Clause 26. The method of clause 25, wherein the substrate thickness is in the range of 25 micrometers to 50 micrometers.

[0067] Clause 27. The method of clause 25 or 26, wherein a plurality of conductive channels are formed in a dielectric of a coreless substrate, the substrate thickness being about 25 micrometers, and the distance being about 12.5 micrometers to about 19 micrometers.

[0068] Clause 28. The method of any one of clauses 16-27, wherein the impedance of each of the plurality of signal interconnects is less than 50 ohms.

[0069] Clause 29. The method of any one of clauses 16-28, wherein a width of each of the plurality of conductive channels is no more than 5 micrometers greater than a width of each of the plurality of signal interconnects.

[0070] Clause 30. The method of any one of clauses 16 to 29, wherein the apparatus is selected from the group consisting of a package, a Molded Embedded Package (MEP), a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a stationary terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, a base station, and a device in an automobile.

[0071]

[0049] For example, it will be understood that a device or any component of a device may be configured (or enabled or adapted) to provide functionality as taught herein. This may be accomplished, for example, by fabricating (e.g., manufacturing) the device or component to provide the functionality, by programming the device or component to provide the functionality, or by using some other suitable implementation technique. As one example, an integrated circuit may be manufactured to provide the requisite functionality. As another example, an integrated circuit may be manufactured to support the requisite functionality and then configured (e.g., by programming) to provide the requisite functionality. As yet another example, a processor circuit may execute code to provide the necessary functionality.

[0072]

[0050] Moreover, the methods, sequences, and / or algorithms described in relation to the aspects disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software module may reside in a random access memory (RAM), a flash memory, a read-only memory (ROM), an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be integral to the processor (e.g., cache memory).

[0073]

[0051] Although the above disclosure shows various exemplary aspects, it should be noted that various changes and modifications may be made to the illustrated examples without departing from the scope defined by the appended claims. The present disclosure is not limited to only the specifically illustrated examples. For example, unless otherwise specified, the functions, steps, and / or actions of the method claims according to the aspects of the present disclosure described herein need not be performed in a particular order. Furthermore, although some aspects may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.

Claims

1. An apparatus comprising a substrate, the substrate comprising: a first metal layer having a plurality of signal interconnects on a first side of the substrate; a second metal layer on a second side of the substrate, the second metal layer comprising a plurality of ground plane portions; a plurality of conductive channels in the substrate coupled to a plurality of ground plane portions configured to extend the plurality of ground plane portions toward individual signal interconnects to reduce a distance from the individual signal interconnects to the individual conductive channels, wherein the distance is within a range of 75% to 50% of a substrate thickness between the first metal layer and the second metal layer; Equipped with each of the plurality of conductive channels is substantially aligned with each of the plurality of signal interconnects, and a width of each of the plurality of conductive channels is substantially the same as a width of each of the plurality of signal interconnects; Device.

2. 10. The apparatus of claim 1, wherein the plurality of signal interconnects are configured to carry high speed data signals, the plurality of signal interconnects being coupled to a dynamic random access memory (DRAM).

3. a processor die coupled to the DRAM by the substrate; a molded embedded package (MEP) comprising the processor die, the substrate, and the DRAM; The apparatus of claim 2 further comprising:

4. 2. The apparatus of claim 1, wherein the first metal layer, the second metal layer, and the plurality of conductive channels comprise at least one of copper (Cu), cobalt (Co), ruthenium (Ru), wolfram (W), molybdenum (Mo), gold (Au), silver (Ag), aluminum (Al), tin (Sn), or any combination thereof.

5. The substrate is a cored substrate, the substrate thickness is in the range of 40 micrometers to 1.2 millimeters; or 2. The apparatus of claim 1 , wherein the plurality of conductive channels are formed within a core of the cored substrate, the substrate thickness is about 40 micrometers, and the distance is from about 20 micrometers to about 30 micrometers.

6. the substrate is a coreless substrate having a dielectric between the first metal layer and the second metal layer; the substrate thickness is in the range of 25 micrometers to 50 micrometers; or 2. The apparatus of claim 1, wherein the plurality of conductive channels are formed in the dielectric of the coreless substrate, the substrate thickness is about 25 micrometers, and the distance is about 12.5 micrometers to about 19 micrometers.

7. The apparatus of claim 1 , wherein the impedance of each of the plurality of signal interconnects is less than 50 ohms.

8. 2. The device of claim 1, wherein the width of each of the plurality of conductive channels is no more than 5 micrometers greater than the width of each of the plurality of signal interconnects.

9. 10. The apparatus of claim 1, wherein the apparatus is selected from the group consisting of a package, a Molded Embedded Package (MEP), a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a stationary terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, a base station, and a device in an automobile.

10. 1. A method of manufacturing a device, comprising: Providing a substrate comprising a first metal layer and a second metal layer; forming a plurality of signal interconnects on a first side of the substrate; forming a plurality of ground plane portions on a second side of the substrate; forming a plurality of conductive channels in the substrate coupled to a plurality of ground plane portions configured to extend the plurality of ground plane portions toward the signal interconnects to reduce a distance from the individual signal interconnects to the individual conductive channels, wherein the distance is within a range of 75% to 50% of a substrate thickness between the first metal layer and the second metal layer; Equipped with wherein each of the plurality of conductive channels is substantially aligned with each of the plurality of signal interconnects, and a width of each of the plurality of conductive channels is substantially the same as a width of each of the plurality of signal interconnects.

11. the plurality of signal interconnects are configured to transmit high speed data signals; the plurality of signal interconnects are coupled to a dynamic random access memory (DRAM), the method comprising: bonding a processor die to the DRAM using the substrate; forming a molded embedded package (MEP) comprising the processor die, the substrate, and the DRAM; The method of claim 10 further comprising:

12. 11. The method of claim 10, wherein the first metal layer, the second metal layer, and the plurality of conductive channels comprise at least one of copper (Cu), cobalt (Co), ruthenium (Ru), wolfram (W), molybdenum (Mo), gold (Au), silver (Ag), aluminum (Al), tin (Sn), or any combination thereof.

13. The substrate is a cored substrate having a core, the substrate thickness is in the range of 40 micrometers to 1.2 millimeters; The method of claim 12 , wherein the plurality of conductive channels are formed in a core of the cored substrate, the substrate thickness is about 40 micrometers, and the distance is from about 20 micrometers to about 30 micrometers.

14. the substrate is a coreless substrate having a dielectric between the first metal layer and the second metal layer; the substrate thickness is in the range of 25 micrometers to 50 micrometers; 13. The method of claim 12, wherein the plurality of conductive channels are formed in the dielectric of the coreless substrate, the substrate thickness is about 25 micrometers, and the distance is about 12.5 micrometers to about 19 micrometers.

15. The method of claim 12 , wherein the width of each of the plurality of conductive channels is no more than 5 micrometers greater than the width of each of the plurality of signal interconnects.

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