Extreme ultraviolet lithography patterning method

Abstract

A method for manufacturing a semiconductor device is described, the method including: forming a base layer on a top layer of a substrate, the base layer comprising a silicon-based dielectric having a thickness of 5 nm or less and 0.5 nm or more; forming a photoresist layer on the base layer, the photoresist having a first side and an opposite second side; exposing a first portion of the photoresist layer to a pattern of extreme ultraviolet (EUV) radiation from the first side; exposing a second portion of the photoresist layer to a pattern of electron flux from the second side, the electron flux being directed from the base layer into the photoresist layer in response to the EUV radiation; developing the exposed photoresist layer to form a patterned photoresist layer; and transferring the pattern of the patterned photoresist layer to the base layer and the top layer.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Patent Application No. 17 / 406,612, filed August 19, 2021, which is incorporated herein by reference.

[0002] The present invention relates generally to methods for manufacturing semiconductor devices, and in a particular embodiment to a method for patterning a layer using extreme ultraviolet (EUV) lithography. [Background technology]

[0003] Generally, semiconductor integrated circuits (ICs) are fabricated by sequentially depositing dielectric, conductive or semiconducting layers on a semiconductor substrate and patterning the layers using photolithography and etching to form electronic and interconnect elements such as transistors, resistors, capacitors, metal lines, contacts and vias in one monolithic structure. To reduce costs, feature sizes are reduced and packing densities double with each new technology node. A straightforward way to print higher resolution patterns is to use shorter wavelength light sources. The 248 nm deep ultraviolet (DUV) KrF lasers used to print marginal patterns at the 250 nm and 130 nm nodes have been replaced by 193 nm ArF lasers starting at the 90 nm node. Features down to 35 nm may be printed using 193 nm lithography with resolution enhancement techniques such as immersion lithography. 193 nm optics will be further extended to the 14 nm and even 10 nm nodes using multiple patterning techniques, but with the high costs and processing complexities associated with additional masks. In the sub-10 nm regime, DUV can be replaced by the shorter 13.5 nm wavelength extreme ultraviolet (EUV) technology. While EUV promises high resolution patterning using fewer masks, it must overcome the engineering hurdle of bringing together all the components of photolithography (radiation source, scanner, mask and resist) into a system with the reliability and throughput of a manufacturing system. One factor limiting the throughput of EUV patterning is the required exposure dose, which is generally higher compared to DUV patterning. Further innovation in this area is needed to successfully deploy EUV lithography in high volume manufacturing of semiconductor ICs. Summary of the Invention

[0004] 1. A method for manufacturing a semiconductor device, the method comprising: forming a base layer on a top layer of a substrate, the base layer comprising a silicon-based dielectric having a thickness of 5 nm or less and 0.5 nm or more; forming a photoresist layer on the base layer, the photoresist having a first side and an opposite second side; exposing a first portion of the photoresist layer to a pattern of extreme ultraviolet (EUV) radiation from the first side; and exposing a second portion of the photoresist layer to a pattern of electron flux from the second side, the electron flux being directed from the base layer into the photoresist layer in response to the EUV radiation; developing the exposed photoresist layer to form a patterned photoresist layer; and transferring a pattern of the patterned photoresist layer to the base layer and the top layer.

[0005] 1. A method of forming an etch mask over a substrate, the method comprising: forming an electron booster layer adhering to a major surface of the substrate; exposing the major surface of the electron booster layer to a hydrogen-containing gas to convert the major surface to hydrophobicity; forming a photoresist layer adhering to the hydrophobic major surface of the electron booster layer; exposing a first portion of the photoresist layer to a pattern of extreme ultraviolet (EUV) radiation; exposing a second portion of the photoresist layer to an electron flux from the electron booster layer, where a portion of the EUV radiation is absorbed beneath the photoresist layer to generate an electron flux; developing the exposed photoresist layer to form a patterned photoresist layer; and patterning the electron booster layer with the patterned photoresist layer to form a patterned electron booster layer, the etch mask being a combination of the patterned electron booster layer and the patterned photoresist layer remaining after patterning the electron booster layer.

[0006] 1. A method of patterning a substrate, the method comprising: providing a plurality of test substrates, each test substrate having substantially the same top layer; forming a lithography stack on the top layer of each of the plurality of test substrates, the lithography stack including a base layer and a photoresist layer disposed on the base layer, the base layer of each of the plurality of test substrates having a different combination of thickness and composition; patterning each photoresist layer with an extreme ultraviolet (EUV) lithography process by exposing the photoresist layer to a pattern of EUV radiation in a focus-dose matrix; measuring the patterned photoresist layer of each of the plurality of test substrates to obtain patterning metrics; and selecting a first type of base layer based on the patterning metrics, the first type of base layer having a specific combination of a first thickness and a first composition for a first base layer of the lithography stack for the EUV lithography process. [Brief description of the drawings]

[0007] For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

[0008] [Figure 1] FIG. 2 illustrates a perspective view of a lithography stack above a substrate, according to one embodiment. [Diagram 2] FIG. 1 is a flow diagram illustrating a method for manufacturing a semiconductor device, according to one embodiment. [Figure 3A] 1A-1D illustrate cross-sectional views of a substrate at various intermediate stages of a process flow for manufacturing a semiconductor device, according to one embodiment. [Figure 3B] 1A-1D illustrate cross-sectional views of a substrate at various intermediate stages of a process flow for manufacturing a semiconductor device, according to one embodiment. [Figure 3C] 1A-1D illustrate cross-sectional views of a substrate at various intermediate stages of a process flow for manufacturing a semiconductor device, according to one embodiment. [Figure 3D]1A-1D illustrate cross-sectional views of a substrate at various intermediate stages of a process flow for manufacturing a semiconductor device, according to one embodiment. [Figure 4] FIG. 1 is a flow diagram illustrating a method for patterning a substrate, according to one embodiment. [Diagram 5] 1 shows a schematic diagram of a plot of patterning data for use in a method of patterning a substrate, according to an embodiment; [Figure 6] 1 is a flow diagram illustrating a method of forming an etch mask over a substrate, according to one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] This disclosure describes a method for patterning a substrate using extreme ultraviolet (EUV) lithography in a process flow for manufacturing semiconductor integrated circuits (ICs). Exemplary embodiments utilize a method for selecting a lithography stack that helps reduce exposure dose and increase throughput, thereby lowering manufacturing costs.

[0010] Photolithography processes involve exposing a photoresist to a pattern of actinic radiation to form a patterned photoresist etch mask. In EUV lithography processes, the actinic radiation typically has a wavelength of about 13.5 nm. EUV's short wavelength of 13.5 nm holds promise for printing high resolution patterns without the added cost of multiple patterning techniques used to extend the resolution capabilities of 193 nm deep ultraviolet (DUV) lithography and immersion deep UV (iDUV) lithography, which use much longer wavelengths. For iDUV and multiple patterning, the number of masks and associated processing steps can be prohibitively expensive for process flows for manufacturing advanced IC designs, for example, at the 5 nm technology node. However, as known to those skilled in the art, the promise of EUV lithography's single patterning capability to print fine patterns (e.g., arrays of lines and spaces with 30 nm pitch) at one masking level has its own costs. Commercial EUV scanners remain several times more expensive than advanced 193 nm iDUV scanners, despite advances in the development of various components of EUV lithography technology, such as radiation sources, optics, photoresists, and optical mask technology.

[0011] Another factor that offsets the cost savings that can be realized through single patterning is the cost of the relatively high exposure dose of EUV lithography. A higher radiation dose to expose the photoresist can result in longer exposure times, thereby reducing throughput and increasing manufacturing costs. EUV radiation at 13.5 nm, which has 14.3 times more photon energy (92 eV) compared to the 6.4 eV photon energy of 193 nm DUV radiation, is partially responsible for the relatively high dose of EUV radiation used to expose the photoresist. For example, the 20 mJ / cm used to expose photoresist in a 193 nm iDUV lithography process 2 Consider a typical dose of 1000 photons per nm. The photon energy is 6.4 eV, which corresponds to approximately 200 photons / nm 2However, the high photon energy of 13.5 nm EUV radiation corresponds to 20 mJ / cm 2 is only 14 photons / nm 2 , which may not be sufficient to adequately expose the photoresist. Furthermore, the probability that a 92 eV photon will penetrate a photoresist film thickness of about 200 nm is higher than that for a 6.4 eV photon.

[0012] Photons chemically absorbed in the photoresist layer convert some of the unexposed photoresist molecules into exposed photoresist through a photochemical reaction. The photoresist may also be exposed with energetic electrons. Some of the energetic electrons are generated by photons that penetrate the photoresist and are absorbed in the underlying layer. The EUV photon absorption process generates energetic photoelectrons in the underlying layer, which then generate secondary electrons. EUV photons absorbed in the photoresist also generate secondary electrons, but a large amount of secondary electrons may be generated by photon absorption in the underlying layer. Some of the emitted electrons may enter the photoresist layer from the underlying layer and interact with unreacted photoresist molecules, which effectively exposes the unreacted photoresist. The photoresist used in EUV lithography is typically a positive photoresist, and the exposed photoresist is removed when developed during a subsequent process step to form a patterned photoresist mask layer. The embodiments described in this disclosure provide examples of methods for reducing the EUV radiation dose required to pattern a photoresist layer by facilitating exposure of the EUV photoresist with energetic electrons.

[0013] FIG. 1 shows a perspective view of a semiconductor device on a substrate 100. This figure shows the substrate 100 at an intermediate stage of processing in an EUV lithography process 200, which will be described in more detail below with reference to FIG. 2 and FIGS. 3A-3D. An incoming substrate 100 having a top layer 130 is patterned using the EUV lithography process 200. The top layer 130 may be, for example, a hardmask layer used as a mask layer in a subsequent etch step. In some embodiments, the hardmask material for the top layer 130 may include an organic layer, such as spin-on carbon (SOC), an amorphous carbon layer (ACL), an organic dielectric layer (ODL), and an organic planarization layer (OPL). In other embodiments, other hardmask layer materials may be used. For example, the hardmask layer material may include a dielectric, such as silicon nitride, silicon oxide, and metal oxides (e.g., aluminum oxide and hafnium oxide), or a metal, such as titanium and titanium nitride, etc.

[0014] A two-layer EUV lithography stack 102, including a base layer 120 and a photoresist layer 110, is shown formed on a top layer 130. Lithography stack refers to sacrificial laminated layers formed on the surface of an incoming substrate that participate in the process used to transfer a pattern of actinic radiation to an adjacent layer below in the lithography stack, such as the top layer 130 in FIG. 1. It should be noted that while the top layer 130 may be a hard mask layer used to etch a target layer further below, in an exemplary embodiment, we have chosen not to refer to the top layer 130 as a layer of the lithography stack 102, since the combination of the photoresist layer 110 and the base layer 120 is used as an etch mask in transferring the EUV radiation pattern to the incoming substrate 100 of the EUV lithography process 200.

[0015] In the perspective view shown in FIG. 1, the photoresist layer 110 is exposed and developed to form a dense pattern of parallel lines. The photoresist layer 110 is sensitive to 13.5 nm EUV radiation, and a pattern of EUV radiation (e.g., a pattern of dense lines) can be transferred to the photoresist layer 110. The base layer 120 serves multiple purposes. Typically, the base layer 120 has a higher resistance than the photoresist layer 110 to etchants used in a pattern transfer etch that transfers the EUV radiation pattern from the photoresist layer 110 to the top layer 130 of the substrate 100. Thus, the base layer 120 can be utilized as a hard mask in patterning the top layer 130. Additionally, the composition and thickness of the base layer 120 can be selected to help facilitate exposing the photoresist layer 110 to energetic electrons using the methods described in this disclosure.

[0016] The layers below the top layer 130 are collectively illustrated by the semiconductor substrate layer 150. The semiconductor substrate layer 150 comprises various dielectric, metal, and semiconductor layers formed on a starting substrate which may comprise a single crystal semiconductor. The starting substrate may comprise bulk silicon, epitaxial silicon on bulk silicon, gallium arsenide, silicon carbide, germanium, silicon-on-insulator (SOI), or heterostructures such as gallium nitride on silicon, silicon on sapphire, etc., and may further comprise an epitaxially grown buried semiconductor region, such as buried silicon germanium.

[0017] The EUV lithography process 200 used to pattern the top layer 130 is described below with reference to the flow diagram of FIG. 2 and several cross-sectional views of the substrate 100 at various intermediate stages of processing shown in FIGS. 3A-3D.

[0018] The method of patterning the top layer 130 of the substrate 100 includes performing a design of experiments (DOE) designed to select a first type of base layer. In this specification, a type of base layer refers to a specific combination of a material composition and a layer thickness of the base layer. Thus, a first type of base layer is a combination of a first composition and a first thickness. The selected first type of base layer may be used as the base layer 120 of the lithography stack 102 of FIG. 1 in an EUV lithography process 200. A method 400 of selecting a first type of base layer by performing DOE on multiple types of base layers is further described below with reference to a flow diagram shown in FIG. 4 and an exemplary data plot 500 shown generally in FIG. 5. The method 400 selects the first type of base layer according to its ability to facilitate irradiating the photoresist with a pattern of electron flux from below. When the base layer 120 is selected using the method 400 and used in the lithography stack 102 in the lithography process 200, it can strengthen the portion of the photoresist that is exposed to an influx of energetic electrons from layers below the photoresist layer 110. Increasing the portion of the photoresist that is exposed to energetic electrons from below means that the amount of photoresist that must be exposed by the flux of EUV photons from above is reduced, which allows the radiation dose for the EUV lithography process 200 to be reduced, for example, by about 10% to about 50%.

[0019] FIG. 6 illustrates a method 600 for forming an etch mask for use in transferring an EUV radiation pattern to an incoming substrate comprising a top layer 130 and a semiconductor substrate layer 150. The etch mask can be a combination of a patterned base layer 120 and a remaining photoresist layer 110, shown as lithographic stack 102 in FIG. 3C. A cross-sectional view of the patterned structure after the pattern has been transferred to the top layer 130 is shown in FIG. 3D. The base layer 120 can be selected, for example, using the selection method 400, to promote exposure of the photoresist by electrons from below the photoresist layer 110. Thus, the base layer 120 is described as an electron booster layer in the flow diagram for the method 600 shown in FIG. 6.

[0020] 2 and 3A-3D, as shown in box 210 in the flow diagram of FIG. 2 and in cross-sectional view in FIG. 3A, a base layer 120 of the lithography stack 102 is formed on a top layer 130 of an incoming substrate 100. The base layer 120 may be formed using a suitable deposition technique, such as atomic layer deposition (ALD), plasma enhanced ALD (PEALD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), physical vapor deposition (PVD), and the like. In some embodiments, forming the base layer 120 includes performing an ALD process that includes exposing the top layer of the substrate to a gas mixture that includes water vapor. In some other embodiments, forming the base layer 120 includes performing a cyclic chemical vapor deposition (CVD) process that includes exposing the substrate to a low temperature oxide precursor for SiOC(N).

[0021] In various embodiments, the base layer 120 may include a variety of materials that broadly fall into two categories: (i) materials that contain metal atoms, and (ii) silicon-based dielectrics that are substantially free of metals. Metal-containing materials may be metal conductors or metal oxide insulators. Examples of metal conductors include titanium, titanium nitride, tantalum nitride, aluminum nitride, tungsten, molybdenum, and ruthenium. Examples of metal oxide insulators include aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, tantalum oxide, manganese oxide, tin oxide, and indium oxide. Silicon-based dielectrics mean that the mole fraction of Si and at least one of O, C, and N is greater than 10 atomic %. Examples include silicon carbide, silicon carbonitride, carbon-doped silicon oxide, silicon oxycarbonitride, and silicon nitride.

[0022] Many of the materials for the base layer 120 are formed with a hydrophilic surface. Because photoresist is hydrophobic and has poor adhesion to hydrophilic surfaces, a surface modification step is typically performed to enhance the adhesion of the photoresist to the main surface of the base layer 120, as described above. After forming the base layer 120, a surface modification process step may be performed to enhance the adhesion of the photoresist to the main surface of the base layer 120. Because photoresist generally has poor adhesion to hydrophilic surfaces, the surface modification step can make the main surface of the base layer 120 hydrophobic. In some embodiments, modifying the main surface of the base layer 120 includes exposing the main surface to hydrogen radicals (H*), forming a hydrocarbon (CH xIn some other embodiments, modifying the major surface of the base layer 120 includes depositing a hydrogen gas-containing coating or annealing the substrate in an atmosphere containing hydrogen gas. In some other embodiments, modifying the major surface of the base layer 120 includes coating the surface with a self-assembled monolayer (SAM). Examples of SAMs include n-octadecyltrimethoxysilane (ODS: H3C(CH2)17Si(OCH3)3), heptadecafluoro-1,1,2,2-tetrahydro-decyl-1-trimethoxysilane (FAS: F3C(CF2)7(CH2)2Si(OCH3)3), n-(6-aminohexyl)aminopropyltrimethoxysilane (AHAPS: H2N(CH2)6NH(CH2)3Si(OCH3)3, and 4-(chloromethyl)phenyltrimethoxysilane (CMPhS: H2ClC(C6H4)Si(OCH3)3).

[0023] As shown in box 220 of the flow diagram for EUV lithography process 200 and in FIG. 3B, after the surface modification process steps (described above) are completed, the substrate 100 is coated with a photoresist layer 110 over a major surface of the base layer 120. The combination of the base layer 120 and the photoresist layer 110 forms the bilayer lithography stack 102. In FIG. 3B (and box 230 in FIG. 2), the photoresist layer 110 is exposed to EUV radiation 300 projected in a pattern that includes alternating light and dark lines. The dashed lines in FIG. 3B delineate the boundaries between the light and dark regions. The areas where EUV radiation 300 is present are indicated by three parallel arrows pointing downwards, and the dark areas are indicated by the absence of arrows. In the embodiment shown in FIG. 3B, a positive photoresist is used. Thus, the photoresist is removed from the areas irradiated with EUV radiation 300 while leaving the photoresist in the dark areas, such that the light and dark pattern of the EUV radiation 300 is transferred to the photoresist pattern of lines and spaces in photoresist layer 110, with the photoresist lines located in the dark areas of the pattern of EUV radiation 300.

[0024] As described below, the EUV radiation 300 generally exposes only a portion, i.e., a first portion, of the photoresist layer 110 due to photon absorption in the photoresist. The EUV radiation 300 enters the photoresist layer 110 from one side (top side), referred to as the first side 302. The remaining portion, i.e., the second portion, includes photoresist molecules that did not participate in photon absorption or interact with electrons generated from photon absorption in the photoresist. The photoresist in the second portion of the photoresist layer 110 is exposed due to the presence of the base layer 120 and the top layer 130. The energetic electrons 310 generated in the base layer 120 and the top layer 130 enter the photoresist layer 110 from the opposite side (bottom side), referred to as the second side 304. In one or more embodiments, the second portion is smaller than the first portion but is greater than 10% of the total volume of the photoresist layer 110.

[0025] As mentioned above, due to the high photon energy, some of the EUV radiation 300 may generate energetic electrons 310, as shown in FIG. 3B, which penetrate the photoresist layer 110 and are absorbed by the underlying layers, such as the base layer 120 and the top layer 130. Some of the energetic electrons 310 may enter the photoresist layer, as shown diagrammatically by the arrows attached to the energetic electrons 310 in FIG. 3B. Since the emission of the energetic electrons 310 is the result of photon absorption, the electron flux mimics the pattern of the EUV radiation 300. By irradiating the photoresist layer 110 with a pattern of electron flux including the energetic electrons 310 (as shown in box 240 of the flow diagram in FIG. 2), it is possible to expose some of the photoresist molecules that were not exposed by the photochemical reaction induced by the EUV photons. The result of exposing the photoresist to energetic electrons is very similar to exposing the photoresist to photons. Indeed, when an EUV photon is absorbed by a photoresist, the energy released from the photon generates a series of secondary electrons, which then interact with the photoresist via an electrochemical reaction. Exposing a positive photoresist to either photons or energetic electrons breaks the covalent bonds, converting the relatively insoluble unexposed positive photoresist polymer into a form that can be dissolved by a chemical developer.

[0026] As also explained above, enhancing the electron flux to expose more of the photoresist layer 110 with the energetic electrons 310 from the second side helps to reduce the EUV radiation dose used in the photoresist exposure step (box 230 in FIG. 2 ) of the EUV lithography process 200. A method described further below with reference to FIGS. 4-6 includes enhancing the electron flux by adjusting the composition and thickness of the base layer 120 to affect the generation rate of the energetic electrons 310 and the transport of the energetic electrons 310 from the top layer 130 to the photoresist layer 110.

[0027] As shown in box 250 of the flow diagram of the EUV lithography process 200, the photoresist layer 110 is developed, for example using a chemical solvent that removes the exposed photoresist. As shown in box 260 of FIG. 2, the patterned photoresist layer 110 may be a mask layer for transferring the EUV radiation pattern to the base layer 120. FIG. 3C depicts a cross-sectional view of the substrate 100 showing the resulting patterned photoresist layer 110 and the patterned base layer 120. In FIG. 3C, a space 320 is shown formed in the area in FIG. 3B, which is irradiated with EUV radiation 300 and an electron flux formed by photo-generation and secondary electron emission of energetic electrons 310. The space 320 in the patterned photoresist layer 110 exposes the surface of the base layer 120, and a subsequent etch step extends the space 320 through the base layer 120 to expose a portion of the top layer 130 of the substrate 100. As shown in Figure 3C, the dark areas are protected by the photoresist lines of the patterned photoresist layer 110 that remain after the patterned base layer 120 is formed. The combination of the patterned base layer 120 and the remaining patterned photoresist layer 110 forms the lithography stack 102 in Figure 3C. As shown in box 270 of the flow diagram of the EUV lithography process 200 and in cross-sectional view in Figure 3D, the lithography stack 102 in Figure 3C may be an etch mask used in a subsequent anisotropic etch step to transfer the EUV radiation pattern into the top layer 130 of the substrate 100.

[0028] In some embodiments, the pattern transfer etch process shown in boxes 260 and 270 of the flow diagram of Figure 2 and represented in cross section in Figure 3D may be performed using a two-step anisotropic plasma etch, such as, for example, a two-step reactive ion etching (RIE) process. A first step may remove exposed portions of the base layer 120 to form a patterned base layer 120, and a second step may transfer the pattern to the top layer 130.

[0029] During the anisotropic etch step used to etch the top layer 130 (box 270 in FIG. 2), the patterned base layer 120 can be used as a hard mask layer in combination with the remaining patterned photoresist layer 110 (shown in FIG. 3C) to extend the depth of the space 320 in FIG. 3C to form a higher aspect ratio space 330 with near vertical sidewalls, as depicted in FIG. 3D. FIG. 3D shows a cross-sectional view of the state of the substrate 100 after the pattern transfer etch indicated by box 270 is completed and the surface of the semiconductor substrate layer 150 is exposed. In some embodiments, the etch chemistry used to remove the exposed areas of the top layer 130 may not be highly selective to photoresist, as indicated by the significantly reduced thickness of the photoresist layer 110 in FIG. 3D, especially if the top layer 130 comprises an organic material. Some areas of the substrate 100 may erode away all of the photoresist, and the integrity of the pattern relies on the pattern transfer etch being highly selective to the base layer material of the base layer 120 .

[0030] FIG. 4 shows a flow diagram of a method 400 for selecting a type of base layer to be used as the base layer 120 in the lithographic stack 102 described above. The selection method 400 may be used to select a first type of base layer to form the base layer 120 shown in FIG. 1 and FIGS. 3A-3D. The method 400 selects the first type of base layer to have a particular combination of a first composition and a first thickness that facilitates a secondary exposure of the photoresist layer 110 by an influx of energetic electrons 310 from a layer below the photoresist layer 110 (see FIG. 3B). The secondary exposure complements the direct exposure by photon absorption in the photoresist layer 110.

[0031] The factors that are varied in the DOE to select a first type of base layer from the multiple types of base layers may be material composition (e.g., atomic concentration of constituent atoms) and film thickness. In some embodiments, the factors may include various surface treatments. As shown in box 410 of the flow diagram of Figure 4, the method 400 begins with preparing a number of test substrates, each having a top layer similar to the top layer 130 of the incoming substrate for the EUV lithography process 200 described above.

[0032] As shown in box 420 of the flow diagram of method 400, a bilayer lithography stack may be formed on a top layer of each of a plurality of test substrates, similar to lithography stack 102 (see FIGS. 3B-3D). The bilayer lithography stack includes a base layer and a photoresist layer coated on the base layer. Although the same photoresist layer is used in each test substrate, the base layer in each test substrate may be formed to have a different combination of thickness and composition according to the DOE to perform the experiment.

[0033] Next, as shown in box 430 of the flow diagram of FIG. 4, each of the photoresist layers is patterned by exposing the test substrate with a pattern of EUV radiation using an EUV projection stepper and then developing the exposed photoresist layers. The photolithography process is similar to the process shown in FIG. 1 and FIG. 3C used to form the patterned photoresist layer 110, except that each photoresist layer is exposed in a focus-exposure dose matrix. When exposing the photoresist layers of the test substrate in a focus-exposure dose matrix, the same EUV radiation pattern is projected onto each die of the matrix of dies, but using different combinations of exposure dose and focal plane height as the stepper steps from one die location to the next. For example, all dies along a row may be illuminated with a constant exposure dose, but the focal plane height may be increased between adjacent dies in the row, or all dies along a column may be projected onto the same focal plane, but the exposure dose may be increased between adjacent dies in the column. Using the technique of exposing the test substrate in a focus-exposure dose matrix, the depth of focus (DOF) for a given exposure dose can be estimated.

[0034] After exposing a number of test substrates to EUV radiation, the photoresist layer is patterned using a suitable process to remove the exposed areas of the photoresist. As shown in box 440 of the flow diagram of method 400, measurements were performed on the patterned photoresist layer to obtain various patterning metrics. Examples of patterning metrics include DOF, critical dimensions (CD) such as photoresist linewidth of critical patterns, edge placement error (EPE), linewidth roughness and line edge roughness (LWR and LER), photoresist profile metrics such as sidewall slope and photoresist foot, defect density for various patterning defects such as bridging, voids, photoresist collapse, photoresist peeling and scumming. Some of the patterning metrics can be measured using destructive techniques.

[0035] In box 450 of the flow diagram for method 400, a first type of base layer is selected based on patterning metrics obtained from experimental test substrates, as described above. The first type of base layer designates the first base layer, which is base layer 120 in the EUV lithography process used to fabricate semiconductor devices. The objective of the selection process is to select a particular combination of composition and thickness for base layer 120 such that a relatively low EUV exposure dose can be used by electrochemically exposing about 10% to about 50% of the photoresist to influx electrons from layers below photoresist layer 110, with negligible adverse effect on the quality of the photoresist pattern. As described above, reducing the exposure dose can provide the advantage of achieving higher throughput in manufacturing.

[0036] One exemplary selection process is outlined in box 450 of the flow diagram of Figure 4. The selection process includes defining an acceptable range for each patterning metric of interest and obtaining a relationship between exposure dose and the patterning metric measured for each base layer of multiple types of base layers of the DOE. If all patterning metrics for the photoresist pattern formed on the base layer are found to be within their corresponding acceptable ranges, then the base layer and corresponding EUV lithography process will be acceptable for manufacturing semiconductor devices.

[0037] Now consider an exemplary patterning metric, e.g., CD. FIG. 5 shows three plots 510, 520, and 530 of measured CD versus exposure dose for each of three types of base layers. Plot 510 may show CD measurements measured from a photoresist pattern formed on a reference base layer with a reference composition (e.g., carbon-doped silicon oxide with 10 atomic % carbon) and a reference thickness (e.g., 2.5 nm). Plot 520 may be measurements taken from a test substrate using, for example, a carbon-doped silicon oxide base layer with the same 2.5 nm thickness but with 30 atomic % carbon, and plot 530 may be CD data from a test substrate with the reference composition (carbon-doped silicon oxide with 10 atomic % carbon) but with a thickness of 1.5 nm. The acceptable range of CD is the CD measured from a target CD centered on the target CD indicated by the horizontal arrow. MIN and CDs MAX 5. The range of exposures for which the measured CD is acceptable is indicated by a pair of vertical dashed lines centered on the mid-exposure indicated by the vertical arrows. Based on plots 510, 520, and 530, any of the three base layers may be rejected. However, if the plot of LWR versus exposure shows that, for example, in the exposure range E1 identified from plot 510 of FIG. 5, the LWR data from the reference base layer is unacceptably high, then the reference base layer must be rejected.

[0038] For example, further assuming that a 2.5 nm thick carbon-doped silicon oxide base layer with 30 atomic % carbon and a 1.5 nm thick carbon-doped silicon oxide base layer with 10 atomic % carbon have all patterning metrics of interest within their corresponding acceptable ranges for a common exposure dose range (e.g., E2 for the base layer of plot 520 and E3 for the base layer of plot 530), both types of base layers are candidates to be considered for selection as the first type of base layer. Since E3 has a lower exposure dose compared to E2, the base layer of plot 530 of FIG. 5 can be selected as the first base layer, and a thickness of 1.5 nm combined with a composition of carbon-doped silicon oxide with 10 atomic % carbon, 45 atomic % silicon, and 45 atomic % oxygen can be the corresponding first type of base layer. It should be understood that this example is for illustrative purposes only to illustrate the method 400 of FIG. 4.

[0039] Several DOEs using silicon-based dielectrics as base layer materials have been performed using the methods described above. The composition of each of the base layers includes a composition of silicon (Si), oxygen (O), carbon (C), and nitrogen (N) atoms, with the mole fraction of Si and at least one of O, C, and N exceeding 10 atomic %. The experiments can be described as falling into five broad groups. The types of base layers within a group are similar in composition. The first group consists of silicon carbide (Si x C 1-x The second group includes base layer materials similar to silicon nitride (Si x N 1-x The third group includes base layer materials similar to silicon carbonitride (Si x C y N 1-y The fourth group includes base layer materials similar to carbon-doped silicon oxide (Si x O y C 1-x-y The fifth group includes base layer materials similar to silicon oxycarbonitride (Si x OyC zN 1-x-y-z ) includes a base layer material of a type similar to that of the

[0040] Using patterning data measured from the test wafers in these experiments and the patterned photoresist layers formed using the bilayer lithography stack 102 of the EUV lithography process 200 described above, the inventors have identified several types of base layers (specific combinations of composition and thickness) that can be selected as the first type of base layer to form the first base layer. These first base layers can enhance the exposure of the photoresist with an electron flux of energetic electrons 310 (see FIG. 3B) to achieve a reduction in the exposure dose of EUV radiation 300 (see FIG. 3B) by about 10% to about 50%. For example, the carbon content was identified to be about 40 atomic % to 50 atomic % for embodiments similar to silicon carbide, and about 10 atomic % to 30 atomic % for embodiments similar to silicon carbonitride or silicon oxycarbonitride.

[0041] When the thickness of the first base layer is reduced, the energetic electrons 310 generated in the top layer 130 below the first base layer are more likely to reach the photoresist above the first base layer. In some embodiments, for example in embodiments using silicon-based dielectrics, the photon absorption and secondary electron generation in the top layer 130 may far exceed the photon absorption and secondary electron generation in the first base layer including the silicon-based dielectric. Therefore, it may be advantageous to select a thin first base layer to promote electron flux from below into the photoresist layer 110. Reducing the thickness promotes the transport of the energetic electrons 310 through the dielectric material, lowering the impedance of the first base layer (often by a quantum tunneling mechanism). If the layer is too thick, a small portion of the energetic electrons 310 generated in the top layer 130 may reach the photoresist layer 110. In various embodiments, the thickness of the low impedance first base layer may be 5 nm or less, and in one embodiment, the thickness of the low impedance first base layer is less than 2 nm.

[0042] Note that in this example, the materials used for the DOE are limited to silicon-based dielectrics that cannot efficiently absorb EUV photons. Thus, the top layer 130 may be the main source of energetic electrons 310 for electron flux from below into the photoresist layer 110. Thus, promotion of electron influx through the second side of the photoresist layer 110 is provided by selecting a small thickness for the low impedance first base layer. As will be further described below, the thickness selected for the metal-containing material may not be as thin as the thickness selected for the silicon-based dielectric material.

[0043] In addition to functioning as an electron booster layer, the base layer 120 can function as a hard mask layer during the etching process used to extend the depth space 320 of FIG. 3B to the higher aspect ratio space 330 of FIG. 3D. As discussed above with reference to FIGS. 3C and 3D, in some embodiments, the etch chemistry used to etch the top layer 130 may have a relatively low selectivity to photoresist, for example in embodiments where the top layer 130 includes an organic material such as SOC. Thus, there may be a minimum thickness to be used in selecting the first thickness of the low impedance first base layer. Otherwise, the base layer 120 may fail to function properly as an etch mask when used as part of the lithography stack 102. In various embodiments, the thickness of the low impedance first base layer may be about 0.5 nm to about 5 nm. In some embodiments, the thickness may be greater than or equal to 0.5 nm and less than or equal to 2 nm.

[0044] The flow diagram of FIG. 6 illustrates a method 600 of forming an etch mask on a substrate. The method 600 includes forming a base layer 120 (box 610 and FIG. 3A). The base layer 120 may be referred to as an electron booster layer as described above. The electron booster layer may be formed on a major surface of the substrate 100, and a photoresist layer 110 may be formed on a major surface of the electron booster layer (box 620 and FIG. 3B). As shown in box 614, adhesion of the photoresist to the major surface of the electron booster layer may be improved by a surface treatment that exposes the major surface of the electron booster layer to a hydrogen-containing gas to convert the major surface of the electron booster to hydrophobicity prior to coating the photoresist on the surface. As described above, exemplary surface treatment processes include plasma treatment with hydrogen radicals, hydrogen gas annealing, and coating with a hydrocarbon. Another surface modification method is to form a thin coating of a hydrophobic material, such as a self-assembled monolayer (SAM), on the major surface of base layer 120, where SAM includes ODS, FAS, AHAPS, or CMPhS, as described above.

[0045] The photoresist layer 110 attached to the electron booster layer may be exposed to a pattern of EUV radiation 300 (see FIG. 3B). A portion of the EUV photon flux may penetrate the photoresist layer 110 and be absorbed by the layers below (e.g., the base layer 120 and the top layer 130). The photon absorption process generates an electron flux having the same pattern as the EUV radiation 300. A portion of the energetic electrons 310 (see FIG. 3B) emitted below the photoresist may enter the photoresist layer 110 and induce an electrochemical reaction that may expose some of the unreacted photoresist molecules. Thus, a first portion of the photoresist in the photoresist layer 110 is directly exposed by the absorption of the EUV radiation in the photoresist (shown in box 630), while a second portion of the photoresist in the photoresist layer 110 is exposed by the electron flux entering the photoresist from below, as shown in box 634 of the flow diagram of the method 600 for forming an etch mask.

[0046] After exposing the photoresist to a pattern of EUV radiation 300 and a flux of electrons from below the photoresist layer 110, the photoresist may be developed using a suitable developer to form a patterned photoresist etch mask 110, as shown in box 640 of the flow diagram of method 600 shown in FIG.

[0047] The patterned photoresist layer 110 can then be used as a mask layer to transfer the pattern of EUV radiation 300 to the electron booster layer, as illustrated in Figure 3C and indicated in box 650 of Figure 6. As further indicated in box 650, the combined layers of the lithography stack 102 of Figure 3C (the combination of the patterned electron booster layer and the patterned photoresist layer 110 remaining after patterning the electron booster layer) is an exemplary etch mask formed using the method 600 of forming an etch mask on a substrate. An example of a lithography stack 102 used as an etch mask for a subsequent etch step used to transfer the EUV pattern to the top layer 130 of the substrate 100 is described above with reference to the cross-sectional view shown in Figure 3D.

[0048] The electron flux through the second side 304 of the photoresist layer 110 (see FIG. 3B) can be promoted by the electron booster layer (base layer 120) in two ways: promoting the generation rate of energetic electrons 310 in the electron booster layer, and promoting the transport of electrons through the booster layer for energetic electrons 310 generated in the substrate below the electron booster layer, for example in the top layer 130 of the substrate 100, as shown diagrammatically by the arrows in FIG. 3B. Depending on which of the two ways of enhancing electron flux is emphasized, different materials and thicknesses may be used for the base layer 120. As described above with reference to FIGS. 4 and 5, a method 400 can be used to select the appropriate material and thickness for the base layer 120.

[0049] The electron generation rate in the electron booster layer (base layer 120) can be increased by introducing atoms with low ionization energy, such as atoms of many metals. In general, metal atoms and / or atoms with a high atomic number (high Z) efficiently absorb EUV photons. Thus, in some embodiments, the electron booster layer may be a high Z / metal-containing layer. The high Z / metal-containing electron booster layer may be a metal layer, including, for example, titanium, titanium nitride, tantalum nitride, aluminum nitride, tungsten, molybdenum, or ruthenium metal layers. In some other embodiments, the high Z / metal-containing electron booster layer may include a metal oxide, such as aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, tantalum oxide, manganese oxide, tin oxide, or indium oxide. Since the high Z / metal-containing electron booster layer is used to facilitate the supply of energetic electrons 310 from within the base layer 120, a thickness of about 3 nm or more may be used where EUV photons can be efficiently absorbed. However, it is noted that the base layer 120 is a sacrificial layer and excessive thickness is undesirable for subsequent process steps used to release the layer. In various embodiments, the thickness of the metal or metal oxide base layer 120 may be from about 3 nm to about 10 nm. It is further noted that the choice of material for the base layer 120 may be limited by the patterning level at which EUV lithography is being performed. For example, in some applications, concerns about metal contamination may preclude the use of metal-containing materials as the base layer 120 and a large Z / metal-containing electron booster layer may not be an option for the first base layer. However, silicon-based dielectrics may be used. A low impedance first base layer may then be selected to facilitate electron flux entering the photoresist layer 110 from the second side 304, as described above. As described above, in this case, electron flux is facilitated by facilitating the transport of energetic electrons 310 coming from the top layer 130 and passing through the base layer 120 to the photoresist layer 110. The transport of electrons through base layer 120 can be enhanced by reducing the thickness, thereby lowering the impedance of the layer to electron flow.In some embodiments, the low impedance base layer 120 may be thin enough so that the quantum tunneling probability for electrons is high. In the direct tunneling regime, the electron flux through the dielectric film may increase exponentially with decreasing film thickness. In general, when the thickness of the dielectric film is reduced to about 2 nm or less, direct tunneling becomes the dominant transport mechanism through the dielectric film.

[0050] When the thickness of the base layer 120 is reduced, energetic electrons 310 generated in the top layer 130 below the base layer 120 are more likely to reach the photoresist layer 110 through the second side 304. However, as previously described with reference to FIGS. 3C and 3D, in some embodiments, the patterned base layer 120 may be used as a hard mask to etch the top layer 130 of the substrate 100. Insufficient thickness of the electron booster layer may impair its ability to be an effective etch mask. Furthermore, if the layer is too thin, it may be difficult to form the layer in manufacturing and reliably control the deposition process. In some embodiments, a low impedance first base layer may be used as the base layer 120. In some embodiments, the low impedance base layer 120 may be a silicon-based dielectric layer including silicon carbide, silicon carbonitride, carbon-doped silicon oxide, silicon oxycarbonitride, or silicon nitride, and the thickness of the low impedance base layer 120 may be 0.5 nm or more and 5 nm or less, and in one embodiment, 2 nm or less.

[0051] As mentioned above, the embodiments described in this disclosure provide the advantage of lowering the cost of patterning a substrate using EUV lithography. The cost reduction is realized by a method of forming a lithography stack for patterning a top layer of an incoming substrate with a pattern of EUV radiation. Using the method described in this disclosure, the lithography stack may be a two-layer lithography stack including a base layer formed on a surface of the incoming substrate and a photoresist layer formed on the base layer. As described herein, the method of selecting the combination of thickness and composition of the base layer helps to reduce the EUV radiation dose with negligible adverse effect on pattern quality, thereby increasing throughput and reducing manufacturing costs.

[0052] Exemplary embodiments of the present invention are summarized here. Other embodiments can be seen throughout the specification and claims appended hereto. EXAMPLES

[0053] Example 1. A method of manufacturing a semiconductor device, the method including: forming a base layer on a top layer of a substrate, the base layer comprising a silicon-based dielectric having a thickness of 5 nm or less and 0.5 nm or more; forming a photoresist layer on the base layer, the photoresist having a first side and an opposite second side; exposing a first portion of the photoresist layer to a pattern of extreme ultraviolet (EUV) radiation from the first side; exposing a second portion of the photoresist layer to a pattern of electron flux from the second side, the electron flux being directed from the base layer into the photoresist layer in response to the EUV radiation; developing the exposed photoresist layer to form a patterned photoresist layer; and transferring the pattern of the patterned photoresist layer to the base layer and the top layer.

[0054] Example 2. The method of example 1, wherein the volume of the second portion is smaller than the volume of the first portion and is greater than 10% of the total volume of the photoresist.

[0055] Example 3. The method of any one of Examples 1 or 2, wherein the silicon-based dielectric is silicon carbide, the silicon carbide having a carbon content of greater than or equal to 40 atomic % and less than or equal to 50 atomic %.

[0056] Example 4. The method of any one of Examples 1-3, wherein the silicon-based dielectric is a silicon carbonitride, the silicon carbonitride having a carbon content of ≧10 atomic % and ≦30 atomic %.

[0057] Example 5. The method of any one of Examples 1-4, wherein the silicon-based dielectric is a silicon oxycarbonitride, the silicon oxycarbonitride having a carbon content of 10 atomic % or more and 30 atomic % or less.

[0058] Example 6. The method of any one of Examples 1-5, wherein forming the base layer further includes modifying a major surface of the base layer prior to forming the photoresist layer, such that the major surface is hydrophobic.

[0059] Example 7. The method of any one of Examples 1-6, wherein modifying the major surface of the base layer comprises exposing the major surface to hydrogen radicals (H*), depositing a hydrocarbon (CHx) coating on the major surface, or annealing the substrate in an atmosphere comprising hydrogen gas.

[0060] Example 8. The method of any one of Examples 1-7, wherein modifying the major surface of the base layer includes forming a coating of a self-assembled monolayer (SAM) on the major surface, the SAM including n-octadecyltrimethoxysilane (ODS: H3C(CH2)17Si(OCH3)3), heptadecafluoro-1,1,2,2-tetrahydro-decyl-1-trimethoxysilane (FAS: F3C(CF2)7(CH2)2Si(OCH3)3), n-(6-aminohexyl)aminopropyltrimethoxysilane (AHAPS: H2N(CH2)6NH(CH2)3Si(OCH3)3, and 4-(chloromethyl)phenyltrimethoxysilane (CMPhS: H2ClC(C6H4)Si(OCH3)3).

[0061] Example 9. The method of any one of Examples 1-8, wherein forming the base layer comprises performing an atomic layer deposition (ALD) process comprising exposing a top layer of the substrate to a gas mixture including water vapor.

[0062] Example 10. The method of any one of Examples 1-9, wherein forming the base layer comprises performing a cyclic chemical vapor deposition (CVD) process comprising exposing the substrate to a low temperature oxide precursor for SiOC(N).

[0063] Example 11. The method of any one of Examples 1-10, wherein the top layer comprises a spin-on carbon (SOC) layer, an organic dielectric layer (ODL), an amorphous carbon (aC) layer, or an organic planarization layer (OPL).

[0064] Example 12. A method of forming an etch mask over a substrate, the method including: forming an electron booster layer adhering to a major surface of the substrate; exposing the major surface of the electron booster layer to a hydrogen-containing gas to convert the major surface to hydrophobicity; forming a photoresist layer adhering to the hydrophobic major surface of the electron booster layer; exposing a first portion of the photoresist layer to a pattern of extreme ultraviolet (EUV) radiation; exposing a second portion of the photoresist layer to an electron flux from the electron booster layer, where a portion of the EUV radiation is absorbed beneath the photoresist layer to generate an electron flux; developing the exposed photoresist layer to form a patterned photoresist layer; and patterning the electron booster layer with the patterned photoresist layer to form a patterned electron booster layer, the etch mask being a combination of the patterned electron booster layer and the patterned photoresist layer remaining after patterning the electron booster layer.

[0065] Example 13. The method of example 12, wherein forming the electron booster layer includes forming a metal layer, the metal layer including titanium, titanium nitride, tantalum nitride, aluminum nitride, tungsten, molybdenum, or ruthenium.

[0066] Example 14. The method of example 12 or 13, wherein forming the electron booster layer includes forming a layer including a metal oxide, the metal oxide including aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, tantalum oxide, manganese oxide, tin oxide, or indium oxide.

[0067] Example 15. The method of any one of Examples 12-14, wherein forming the electron booster layer includes forming a silicon-based dielectric layer including silicon carbide, silicon carbonitride, carbon-doped silicon oxide, silicon oxycarbonitride, or silicon nitride, and the thickness of the silicon-based dielectric layer is greater than or equal to 0.5 nm and less than or equal to 5 nm.

[0068] Example 16. A method for patterning a substrate, the method including: preparing a plurality of test substrates, each test substrate having substantially the same top layer; forming a lithography stack on the top layer of each of the plurality of test substrates, the lithography stack including a base layer and a photoresist layer disposed on the base layer, the base layer of each of the plurality of test substrates having a different combination of thickness and composition; patterning each photoresist layer with an extreme ultraviolet (EUV) lithography process by exposing the photoresist layer to a pattern of EUV radiation in a focus-dose matrix; measuring the patterned photoresist layer of each of the plurality of test substrates to obtain a patterning metric; and selecting a first type of base layer based on the patterning metric, the first type of base layer having a specific combination of a first thickness and a first composition for a first base layer of the lithography stack for the EUV lithography process.

[0069] Example 17. The method of example 16, wherein the patterning metric comprises depth of focus, critical dimension, edge placement error, line edge roughness, line width roughness, photoresist sidewall angle, or defect density in the photoresist pattern, or a combination thereof.

[0070] Example 18. The method of Example 16 or 17, wherein selecting a first type of base layer includes: for each patterning metric, determining a range within which the metric is acceptable; for each patterning metric, obtaining a relationship between the exposure dose and the patterning metric for each base layer; based on the relationship, identifying base layers for which there is an exposure dose within which each of the patterning metric falls within a respective range; and selecting a first type of base layer from the identified base layers.

[0071] Example 19. The method of any one of Examples 16-18, wherein the composition of each of the base layers comprises a composition of silicon (Si), oxygen (O), carbon (C), and nitrogen (N) atoms, and the mole fraction of Si and the mole fraction of at least one of O, C, and N is 10 atomic % or more.

[0072] Example 20. The method according to any one of Examples 16 to 19, wherein the mole fraction of carbon is equal to or greater than 10 atomic % and equal to or less than 50 atomic %.

[0073] Although the present invention has been described with reference to exemplary embodiments, this specification is not intended to be construed in a limiting sense. Various modifications and combinations of those exemplary embodiments, as well as other embodiments of the present invention, will become apparent to those skilled in the art upon reference to this specification. Therefore, it is intended that the appended claims cover any such modifications or embodiments.

Claims

1. A method of manufacturing a semiconductor device, comprising: forming a base layer on the topmost layer of a substrate, the base layer including a silicon-based dielectric having a thickness of 5 nm or less and 0.5 nm or more; forming a photoresist layer on the base layer, the photoresist having a first side portion and a second side portion opposite thereto; exposing a first portion of the photoresist layer with a pattern of extreme ultraviolet (EUV) radiation from the first side portion; exposing a second portion of the photoresist layer with a pattern of an electron beam flux from the second side portion, the electron beam flux being directed from the base layer into the photoresist layer in response to the EUV radiation; developing the exposed photoresist layer to form a patterned photoresist layer; transferring the pattern of the patterned photoresist layer to the base layer and the topmost layer.

2. The method according to claim 1, wherein the volume of the second portion is smaller than the volume of the first portion and larger than 10% of the total volume of the photoresist.

3. The method according to claim 1, wherein the silicon-based dielectric is silicon carbide, and the silicon carbide has a carbon content of 40 atomic % or more and 50 atomic % or less.

4. The method according to claim 1, wherein the silicon-based dielectric is silicon carbonitride, and the silicon carbonitride has a carbon content of 10 atomic % or more and 30 atomic % or less.

5. The method according to claim 1, wherein the silicon-based dielectric is silicon oxycarbonitride, and the silicon oxycarbonitride has a carbon content of 10 atomic % or more and 30 atomic % or less.

6. Forming the base layer further includes: modifying a main surface of the base layer before forming the photoresist layer, so that the main surface is hydrophobic.

7. Modifying the main surface of the base layer includes exposing the main surface to hydrogen radicals (H*), depositing a hydrocarbon (CH ｘ ) coating thereon, or annealing the substrate in an atmosphere containing hydrogen gas, the method according to claim 6.

8. Modifying the main surface of the base layer includes forming a self-assembled monolayer (SAM) coating on the main surface, and the SAM is n-octadecyltrimethoxysilane (ODS: H ３ C(CH ２ )17Si(OCH ３ ) ３ ), heptadecafluoro-1,1,2,2-tetrahydro-decyl-1-trimethoxysilane (FAS: F ３ C(CF ２ ) ７ (CH ２ )2Si(OCH ３ ) ３ ), n-(6-aminohexyl)aminopropyltrimethoxysilane (AHAPS: H ２ N(CH ２ )6NH(CH ２ )3Si(OCH ３ ) ３ , and 4-(chloromethyl)phenyltrimethoxysilane (CMPPhS: H ２ ClC(C ６ H ４ )Si(OCH ３ ) ３ ), the method according to claim 6.

9. The method according to claim 1, wherein forming the base layer includes performing an atomic layer deposition (ALD) process including exposing the topmost layer of the substrate to a gas mixture containing water vapor.

10. The method according to claim 1, wherein forming the base layer includes performing a cyclic chemical vapor deposition (CVD) process including exposing the substrate to a low-temperature oxide precursor for SiO C(N).

11. The method according to claim 1, wherein the uppermost layer includes a spin-on carbon (SOC) layer, an organic dielectric layer (ODL), an amorphous carbon (a-C) layer, or an organic planarization layer (OPL).

12. A method of forming an etch mask on a substrate, the method comprising: forming an electron booster layer adhering to a main surface of the substrate; exposing a main surface of the electron booster layer to a hydrogen-containing gas to convert the main surface into a hydrophobic surface; forming a photoresist layer adhering to the hydrophobic main surface of the electron booster layer; exposing a first portion of the photoresist layer with a pattern of extreme ultraviolet (EUV) radiation; exposing a second portion of the photoresist layer with an electron flux from the electron booster layer, wherein a part of the EUV radiation is absorbed below the photoresist layer to generate the electron flux; developing the exposed photoresist layer to form a patterned photoresist layer; patterning the electron booster layer with the patterned photoresist layer to form a patterned electron booster layer, wherein the etch mask is a combination of the patterned electron booster layer and the patterned photoresist layer remaining after patterning the electron booster layer.

13. Forming the electron booster layer includes forming a metal layer, and the metal layer includes titanium, titanium nitride, tantalum nitride, aluminum nitride, tungsten, molybdenum, or ruthenium. The method according to claim 12.

14. Forming the electron booster layer includes forming a layer containing a metal oxide, and the metal oxide includes aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, tantalum oxide, manganese oxide, tin oxide, or indium oxide. The method according to claim 12.

15. Forming the electron booster layer includes forming a silicon-based dielectric layer including silicon carbide, silicon carbonitride, carbon-doped silicon oxide, silicon oxycarbonitride, or silicon nitride, and a thickness of the silicon-based dielectric layer is 0.5 nm or more and 5 nm or less. The method according to claim 12.

16. A method of patterning a substrate, the method comprising: Preparing a plurality of test substrates, each test substrate having substantially the same top layer, Forming a lithography stack on the top layer of each of the plurality of test substrates, the lithography stack including a base layer and a photoresist layer disposed on the base layer, wherein the base layer of each of the plurality of test substrates has a different combination of thickness and composition, Patterning each photoresist layer by EUV lithography process by exposing the photoresist layer with a pattern of extreme ultraviolet (EUV) radiation in a focus-exposure matrix, Obtaining a patterning measurement criterion by measuring the patterned photoresist layer of each of the plurality of test substrates, Selecting a first type of base layer based on the patterning measurement criterion, the first type of base layer having a specific combination of a first thickness and a first composition for creating a first base layer of a lithography stack for EUV lithography process, including,

17. The method according to claim 16, wherein the patterning measurement criterion includes depth of focus, critical dimension, edge placement error, line edge roughness, line width roughness, photoresist sidewall angle, or defect density in the photoresist pattern, or a combination thereof.

18. Selecting the first type of base layer includes, For each of the patterning measurement criteria, determining a range within which the measurement criterion is acceptable, For each of the patterning measurement criteria, obtaining a relationship between the exposure amount and the patterning measurement criterion for each base layer, Based on the relationship, identifying the base layer for which there exists an exposure amount such that each of the patterning measurement criteria is within its respective range, Selecting the first type of base layer from the identified base layers, the method according to claim 16.

19. The method according to claim 16, wherein the composition of each of the base layers includes a composition of silicon (Si), oxygen (O), carbon (C), and nitrogen (N) atoms, and the mole fraction of Si and the mole fraction of at least one of O, C, and N are each 10 atomic % or more.

20. The method according to claim 19, wherein the mole fraction of carbon is 10 atomic % or more and 50 atomic % or less. A method of manufacturing a device, the method comprising: forming a mask layer on a substrate; forming an electron booster layer on the mask layer, the electron booster layer being configured to generate secondary electrons when irradiated with extreme ultraviolet (EUV) radiation; forming a photoresist layer disposed on the electron booster layer, the photoresist layer including a first thickness; exposing the photoresist layer to the EUV radiation via a lithography mask; developing the photoresist layer to form a pattern extending through all of the first thickness of the photoresist layer; transferring the pattern to the mask layer. The method of claim 21, wherein the exposing is performed under first process conditions, the first process conditions being configured to underexpose a portion of the photoresist layer proximate the electron booster layer in the absence of the electron booster layer. The method of claim 22, wherein the underexposed portion of the photoresist layer is exposed by the secondary electrons generated in the electron booster layer in response to the EUV radiation. The method of claim 21, wherein forming the electron booster layer includes forming a metal layer, the metal layer including titanium, titanium nitride, tantalum nitride, aluminum nitride, tungsten, molybdenum, or ruthenium, or forming the electron booster layer includes forming a layer including a metal oxide, the metal oxide including aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, tantalum oxide, manganese oxide, tin oxide, or indium oxide. The method of claim 21, wherein forming the electron booster layer includes forming a silicon-based dielectric layer. The method of claim 25, wherein the silicon-based dielectric layer includes silicon carbide, silicon carbonitride, carbon-doped silicon oxide, silicon oxycarbonitride, or silicon nitride, and the thickness of the silicon-based dielectric layer is 0.5 nm or more and 5 nm or less.

27. The method according to claim 21, wherein forming the electron booster layer includes converting a main surface of the electron booster layer from hydrophilic to hydrophobic before forming the photoresist layer.

28. The method according to claim 21, wherein forming the electron booster layer includes exposing a main surface of the electron booster layer to hydrogen plasma, depositing a hydrocarbon (CHx) coating on the main surface, or annealing the substrate in an atmosphere containing hydrogen gas.

29. The method according to claim 27, wherein forming the electron booster layer includes forming a self-assembled monolayer (SAM) coating on the main surface, and the SAM includes n-octadecyltrimethoxysilane (ODS: H3C(CH2)17Si(OCH3)3), heptadecafluoro-1,1,2,2-tetrahydro-decyl-1-trimethoxysilane (FAS: F3C(CF2)7(CH2)2Si(OCH3)3), n-(6-aminohexyl)aminopropyltrimethoxysilane (AHAPS: H2N(CH2)6NH(CH2)3Si(OCH3)3), and 4-(chloromethyl)phenyltrimethoxysilane (CMPPhS: H2ClC(C6H4)Si(OCH3)3).

30. A method of manufacturing a device, the method comprising: forming a mask layer on a substrate; forming a base layer on the mask layer; forming a photoresist layer disposed on the base layer; exposing the photoresist layer to extreme ultraviolet (EUV) radiation through a lithography mask, wherein the exposing forms regions of the photoresist layer having different solubilities in a developer, the regions having an upper portion and a lower portion, the upper portion of the regions being formed by being exposed to direct energy of the EUV radiation, and the lower portion of the regions being formed by being exposed to indirect energy generated in the base layer in response to the EUV radiation; after the exposing, developing the photoresist layer using the developer to form a patterned photoresist layer. A method comprising transferring the patterned photoresist layer onto the mask layer.

31. The method according to claim 30, wherein the base layer comprises at least one of a metal layer, a metal oxide layer, or a silicon-based dielectric layer.

32. The method according to claim 31, wherein the silicon-based dielectric layer comprises silicon carbide, silicon carbonitride, or silicon oxycarbonitride.

33. The method according to claim 30, wherein forming the base layer includes converting the main surface of the base layer from hydrophilic to hydrophobic before forming the photoresist layer.

34. The method according to claim 30, wherein forming the base layer includes exposing the main surface of the base layer to hydrogen plasma, depositing a hydrocarbon (CHx) coating on the main surface, or annealing the substrate in an atmosphere containing hydrogen gas.

35. The method according to claim 34, wherein forming the base layer includes forming a coating of a self-assembled monolayer (SAM) on the main surface, and the SAM includes n-octadecyltrimethoxysilane (ODS: H3C(CH2)17Si(OCH3)3), heptadecafluoro-1,1,2,2-tetrahydro-decyl-1-trimethoxysilane (FAS: F3C(CF2)7(CH2)2Si(OCH3)3), n-(6-aminohexyl)aminopropyltrimethoxysilane (AHAPS: H2N(CH2)6NH(CH2)3Si(OCH3)3), and 4-(chloromethyl)phenyltrimethoxysilane (CMPPhS: H2ClC(C6H4)Si(OCH3)3).

36. A lithography stack comprising: a mask layer; an electron booster layer disposed on the mask layer; a photoresist layer disposed on the electron booster layer, wherein the electron booster layer is configured to generate secondary electrons that develop a part of the photoresist layer.

37. The lithography stack according to claim 36, wherein the electron booster layer comprises at least one of a metal layer or a metal oxide layer.

38. The lithography stack according to claim 36, wherein the electronic booster layer comprises a silicon-based dielectric having a thickness of 5 nm or less and 0.5 nm or more.

39. The lithography stack according to claim 38, wherein the silicon-based dielectric comprises silicon carbide, silicon carbonitride, carbon-doped silicon oxide, silicon oxycarbonitride, or silicon nitride.

40. The lithography stack according to claim 36, wherein the mask layer comprises a spin-on carbon (SOC) layer, an organic dielectric layer (ODL), an amorphous carbon (a-C) layer, or an organic planarization layer (OPL).

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