Semiconductor integrated circuit, layout design system, layout designing method, and program

Abstract

To provide a semiconductor integrated circuit efficiently with high logic density by using two types of standard cells with different numbers of layers.SOLUTION: A semiconductor integrated circuit according to an embodiment includes a first semiconductor layer, a second semiconductor layer, and a first CMOS circuit and a second CMOS circuit. The first semiconductor layer is stacked as a (2n-1)th layer, and the second semiconductor layer is stacked as a (2n)th layer (where 1≤n≤N, N≥2, and n and N are integers). For a certain i (where 1≤i≤N, N≥2, and i and N are integers), it includes a first standard cell in which the second conductivity type MOS as a (4i-1)th layer and the first conductivity type MOS as a (4i)th layer share a gate terminal, a second standard cell in which the second conductivity type MOS of a (4i-3)th layer and the first conductivity type MOS as a (4i-2)th layer share a gate terminal, and a third standard cell in which the second conductivity type MOSs as the (4i-3)th layer and as the (4i-1)th layer and the first conductivity type MOSs as the (4i)th layer and as the (4i-2)th layer share a gate terminal.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] An embodiment of the present invention relates to a semiconductor integrated circuit, a layout design system, a layout design method, and a program. [Background technology]

[0002] Previously, miniaturization efforts have been known to stack NMOS and PMOS transistors to create 3D circuits, but stacking NMOS and PMOS transistors one layer at a time can result in low element density per unit area of ​​the substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2021 / 0249401 [Patent Document 2] US Patent Application Publication No. 2021 / 0343715 [Patent Document 3] US Patent Application Publication No. 2022 / 0181322 [Non-patent literature]

[0004] [Non-Patent Document 1] S.Subramanian, M.Hosseini, T.Chiarella, S.Sarakar, P. Schuddinck, BT Chan, D. Radisic, G. Mannaert, A. Hikavyy, E. Rosseel, F. Sebaai, A. Peter, T. Hopf, P. Morin, S. Wang, K. Devriendt, D. Batuk, E.G Martinez, E. Veloz. Dentoni Litta, S. Baudot, YK Siew, X. Zhou, B. Briggs, E. Capogreco, J. Hung, R. Koret, A. Spessot, J. Ryckaert, S. Demuynck, N. Horiguchi, and J. Boemmels, “First Monolithic Implementation of 3D Cointegration FET(s) on 30mm Wafers”, 2020 IEEE Symposium on VLSI Technology, VLSI Technology Digest of Technical Papers, TH3.1.

Wood 2

Table 3

[0005] The problem to be solved by the embodiments is to provide a semiconductor integrated circuit, a layout design system, a layout design method, and a program that efficiently achieve high logic density by using two types of standard cells having different numbers of layers. [Means for solving the problem]

[0006] A semiconductor integrated circuit according to an embodiment includes a first semiconductor layer having a first source region, a first drain region, and a first channel region, a second semiconductor layer having a second source region, a second drain region, and a second channel region, a gate electrode formed to cover the first channel region and the second channel region via a gate insulating film, and a first CMOS circuit and a second CMOS circuit configured by combining a first conductivity type MOS having the first semiconductor layer and a second conductivity type MOS having the second semiconductor layer, wherein the first semiconductor layer is stacked in a (2n-1)th layer, and the second semiconductor layer is stacked in a 2nth layer (1≦n≦N, N≧2, a gate electrode of the first CMOS circuit electrically connects at least the first conductive type MOS of the first semiconductor layer in the (2i-1)th layer and the second conductive type MOS of the second semiconductor layer in the (2i-1)th layer in common to the first conductive type MOS of the second semiconductor layer in the (2i+1)th layer, for some i (1≦i≦N), where n and N are integers; and In the circuit, for a certain i (1≦i≦N), there is provided a first standard cell in which a second conductivity type MOS in the (4i-1)th layer and a first conductivity type MOS in the (4i)th layer share a gate terminal, a second standard cell in which a second conductivity type MOS in the (4i-3)th layer and a first conductivity type MOS in the (4i-2)th layer share a gate terminal, and a third standard cell in which a second conductivity type MOS in the (4i-3)th layer and a (4i-1)th layer and a first conductivity type MOS in the 4ith layer and a (4i-2)th layer share a gate terminal. [Brief description of the drawings]

[0007] [Figure 1] 1 is a planar pattern configuration diagram of a semiconductor integrated circuit according to an embodiment; [Diagram 2] FIG. 2 is a cross-sectional view taken along line A1-A1 in FIG. [Figure 3A] FIG. 2 is a planar pattern configuration diagram of a first semiconductor layer. [Figure 3B] FIG. 2 is a planar pattern configuration diagram of a first semiconductor layer. [Figure 3C]FIG. 4 is a plan view of a second semiconductor layer; [Figure 3D] FIG. 4 is a plan view of a second semiconductor layer; [Figure 4] 1 is an equivalent circuit diagram of a semiconductor integrated circuit according to an embodiment. [Diagram 5] FIG. 2 is a detailed planar pattern configuration diagram of the semiconductor integrated circuit according to the embodiment. [Figure 6] FIG. 6 is a cross-sectional view taken along line A2-A2 in FIG. 5 . [Figure 7] 6 is a cross-sectional view taken along line A3-A3 in FIG. 5 . [Figure 8] 6 is a cross-sectional view taken along line A4-A4 in FIG. 5 . [Figure 9] Cross-sectional view taken along line A5-A5 in Figure 5. [Figure 10] 6 is a cross-sectional view taken along line A6-A6 in FIG. 5 . [Figure 11] FIG. 2 is a planar pattern configuration diagram in which VDD and VSS lines are omitted in the semiconductor integrated circuit according to the embodiment. [Figure 12] 12 is a side view taken along lines A5-A5 and A6-A6 in FIG. 11. [Figure 13] 1 is a schematic diagram of a layout design system using a semiconductor integrated circuit according to an embodiment. [Figure 14] FIG. 14 is a block diagram of the layout design system of FIG. 13. [Figure 15] FIG. 14 is a block diagram showing a first modified example of the layout design system of FIG. 13. [Figure 16] FIG. 14 is a block diagram showing a second modified example of the layout design system of FIG. 13. [Figure 17] FIG. 2 is a flow diagram of a layout design method using a semiconductor integrated circuit according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, the embodiments will be described with reference to the drawings. The relationship between the thickness and planar dimensions of each component, the ratio of thicknesses of each component, and the like shown in the drawings may differ from the actual product. The up-down direction may differ from the up-down direction according to the gravitational acceleration. In addition, in the embodiments, substantially the same components are given the same reference numerals, and the description will be omitted as appropriate. In this specification, the term "connection" includes not only a physical connection but also an electrical connection, and unless otherwise specified, includes not only a direct connection but also an indirect connection.

[0009] In the following description, an XYZ coordinate system, which is an example of a Cartesian coordinate system, is used. That is, a plane parallel to the surface of a substrate constituting a semiconductor integrated circuit is defined as an XY plane, and a direction perpendicular to the XY plane is defined as a Z direction. The X-axis and the Y-axis are defined as two perpendicular directions in the XY plane. These directions are merely examples. Depending on the arrangement of the pattern, they can be appropriately changed. The substrate may also include an insulating substrate, a semiconductor substrate, or a substrate in which an electrode layer is embedded in an insulating substrate. Furthermore, the substrate may be a substrate in which semiconductor elements consisting of an N-channel MOS (Metal Oxide Gate Semiconductor) field effect transistor, a P-channel MOS field effect transistor, or a complementary MOS field effect transistor (CMOS: Complementary MOS) are embedded. (Configuration of Semiconductor Integrated Circuit)

[0010] FIG. 1 is a planar pattern configuration diagram of a semiconductor integrated circuit 100 according to an embodiment. FIG. 2 is a cross-sectional view taken along the line A1-A1 in FIG. 1. In FIG. 1, the illustration of the interlayer insulating film 2 is omitted. The semiconductor integrated circuit 100 according to the embodiment may include a substrate 1 and an interlayer insulating film 2. In FIG. 1 and FIG. 2, the arrangement direction of the gate electrodes 11A, 11B, 21A, and 21B is the X direction. The arrangement direction of the gate electrodes 11C, 11D, 21C, and 21B is also the X direction. In FIG. 1 and FIG. 2, the extension direction of the first semiconductor layers 12 and 22 is the Y direction. The extension direction of the second semiconductor layers 13 and 23 is also the Y direction. The plane parallel to the substrate 1 defined by the X direction and the Y direction is the XY plane, and the direction perpendicular to the XY plane is the Z direction.

[0011] 1 and 2, the semiconductor integrated circuit 100 according to the embodiment includes a first semiconductor layer (12, 22), a second semiconductor layer (13, 23), and gate electrodes (11A, 11B, 11C, 11D, 21A, 21B, 21C). The semiconductor integrated circuit 100 according to the embodiment also includes a first CMOS circuit (CMOS: Complementary CMOS) 10 (10A, 10B, 10C, 10D) and a second CMOS circuit 20 (20A, 20B, 20C) configured by a combination of a first conductivity type MOS (MOS: Metal Oxide Semiconductor) and a second conductivity type MOS.

[0012] As shown in Fig. 2, the first CMOS circuit (10C, 10D) constitutes a first standard cell SC1 (SC Type A), and the first CMOS circuit (10A, 10B) constitutes a second standard cell SC2 (SC Type A). The second CMOS circuit 20 (20A, 20B, 20C) constitutes a third standard cell SC3 (SC Type B). The first standard cell SC1 is stacked in the Z direction above the second standard cell SC2.

[0013] The third standard cell SC3 (SC Type B) includes a second CMOS circuit 20A, a second CMOS circuit 20C stacked in the Z direction above the second CMOS circuit 20A, a second CMOS circuit 20B, and a second CMOS circuit 20D stacked in the Z direction above the second CMOS circuit 20B. Here, the second CMOS circuit 20B and the second CMOS circuit 20D share a gate electrode 21B.

[0014] The first standard cell SC1 can drive a small-capacitance capacitor C1. The second standard cell SC2 can drive a small-capacitance capacitor C2. The third standard cell SC3 can drive a large-capacitance capacitor C3. Here, the capacitances of the capacitors C1 and C2 are smaller than that of the capacitor C3.

[0015] In the following description, the first semiconductor layers (12A, 12B, 22A, 22B) and the third semiconductor layers (12C, 12D, 22C, 22D) shown in Fig. 2 are also collectively referred to as the first semiconductor layers (12, 22). The second semiconductor layers (13A, 13B, 23A, 23B) and the fourth semiconductor layers (13C, 13D, 23C, 23D) shown in Fig. 2 are also collectively referred to as the second semiconductor layers (13, 23).

[0016] 2, the interlayer insulating film 2 is disposed on the substrate 1. The interlayer insulating film 2 is disposed so as to cover the gate electrodes (11A, 11B, 11C, 11D, 21A, 21B, 21C), the first semiconductor layers (12, 22), and the second semiconductor layers (13, 23).

[0017] FIG. 3A is a planar pattern configuration diagram of the first semiconductor layer 12 (12A, 12B, 12C, 12D). FIG. 3B is a planar pattern configuration diagram of the first semiconductor layer 22 (22A, 22B, 22C, 22D). FIG. 3C is a planar pattern configuration diagram of the second semiconductor layer 13 (13A, 13B, 13C, 13D). FIG. 3D is a planar pattern configuration diagram of the second semiconductor layer 23 (23A, 23B, 23C, 23D).

[0018] As shown in FIGS. 3A and 3B, the first semiconductor layer 12 and the first semiconductor layer 22 have a source region (14, 24), a drain region (15, 25), and a channel region (16, 26).

[0019] As shown in FIGS. 3C and 3D, the second semiconductor layer 13 and the second semiconductor layer 23 have a source region (17, 27), a drain region (18, 28), and a channel region (19, 29).

[0020] 2, the first semiconductor layers (12A, 12B, 22A, 22B) are disposed, for example, in the first layer stacked in the Z direction perpendicular to the surface of the substrate 1. The first semiconductor layers (12C, 12D, 22C, 22D) are disposed, for example, in the third layer stacked in the Z direction perpendicular to the surface of the substrate 1. That is, the first semiconductor layers (12, 22) are stacked in the (2n-1)th layer (1≦n≦N, N≧2, n and N are integers).

[0021] As shown in FIG. 2, the second semiconductor layer (13A, 13B, 23A, 23B) is disposed, for example, in the second layer stacked in the Z direction perpendicular to the surface of the substrate 1. The second semiconductor layer (13C, 13D, 23C, 23D) is disposed, for example, in the fourth layer stacked in the Z direction perpendicular to the surface of the substrate 1. That is, the second semiconductor layer (13, 23) is stacked in the 2nth layer (1≦n≦N, N≧2, n and N are integers). Note that, although the first semiconductor layer (12, 22) and the second semiconductor layer (13, 23) are stacked in four layers in FIG. 2, they may be stacked in four or more layers.

[0022] The first conductivity type MOS has a first semiconductor layer (12, 22). Specifically, the first conductivity type MOS may be, for example, a PMOS (P-channel MOS).

[0023] The second conductive type MOS has a second semiconductor layer (13, 23). Specifically, the second conductive type MOS may be, for example, an NMOS (N-channel MOS).

[0024] As shown in FIG. 2, gate electrodes (11A, 11B, 11C, 11D, 21A, 21B, 21C) are disposed on a substrate 1. The gate electrodes (11A, 11B, 11C, 11D, 21A, 21B, 21C) are formed so as to cover the channel regions (16, 26) and the channel regions (19, 29) via a gate insulating film 3. In this manner, a structure in which the gate electrodes cover the periphery of the channel region via a gate insulating film is provided with a so-called Surrounding Gate Transistor (SGT) structure. The SGT structure is also called a Gate-all-around structure.

[0025] Specifically, the gate electrode 11A is formed so as to cover the channel region 16 of the first semiconductor layer 12A and the channel region 19 of the second semiconductor layer 13A. The gate electrode 11B is formed so as to cover the channel region 16 of the first semiconductor layer 12B and the channel region 19 of the second semiconductor layer 13B.

[0026] The gate electrode 11C is formed so as to cover the channel region 16 of the first semiconductor layer 12C and the channel region 19 of the second semiconductor layer 13C. The gate electrode 11D is formed so as to cover the channel region 16 of the first semiconductor layer 12D and the channel region 19 of the second semiconductor layer 13D.

[0027] The gate electrode 21A is formed so as to cover the channel region 16 of the first semiconductor layer 22A and the channel region 19 of the second semiconductor layer 23A. The gate electrode 21C is formed so as to cover the channel region 26 of the first semiconductor layer 22C and the channel region 29 of the second semiconductor layer 23C. The gate electrode 21B is formed so as to cover the channel region 26 of the first semiconductor layer (22B, 22D) and the channel region 29 of the second semiconductor layer (23B, 23D). In the first standard cell SC1, the gate electrode 11C and the gate electrode 11D are arranged to be spaced apart from each other. In the second standard cell SC2, the gate electrode 11A and the gate electrode 11B are arranged to be spaced apart from each other. In the third standard cell SC3, the gate electrode 21A, the gate electrode 21B and the gate electrode 21C are arranged to be spaced apart from each other.

[0028] The first CMOS circuit 10 (10A, 10B, 10C, 10D) and the second CMOS circuit 20 (20A, 20B, 20C, 20D) are configured by a combination of a first conductivity type MOS and a second conductivity type MOS.

[0029] The first CMOS circuit 10 has gate electrodes 11A, 11B, 11C, and 11D. For a certain i (1≦i≦N), the first CMOS circuit 10 electrically connects at least a first conductivity type MOS in the (2i-1)th layer (i.e., the 1st, 3rd, 5th,..., (2i-1)th layers) of the first semiconductor layer 12 in common with a second conductivity type MOS in the 2ith layer (i.e., the 2nd, 4th, 6th,..., 2ith layers) of the second semiconductor layer 13 in common.

[0030] Specifically, in the first CMOS circuit 10, for example, a gate electrode 11A electrically connects a PMOS, which is a first conductivity type MOS, of a first semiconductor layer 12A in the first layer, and an NMOS, which is a second conductivity type MOS, of a second semiconductor layer 13A in the second layer. For example, the gate electrode 11B electrically connects a PMOS, which is a first conductive type MOS, in the first semiconductor layer 12B in the first layer, and an NMOS, which is a second conductive type MOS, in the second semiconductor layer 13B in the second layer. For example, the gate electrode 11C electrically connects a PMOS, which is a first conductivity type MOS, in the third first semiconductor layer 12C, and an NMOS, which is a second conductivity type MOS, in the fourth second semiconductor layer 13C. For example, in the first CMOS circuit 10, a gate electrode 11D electrically connects a PMOS, which is a first conductivity type MOS, in a first semiconductor layer 12D in the third layer, and an NMOS, which is a second conductivity type MOS, in a second semiconductor layer 13D in the fourth layer.

[0031] The second CMOS circuit 20 has a gate electrode 21A, a gate electrode 21B, and a gate electrode 21C. In the second CMOS circuit 20, for example, the gate electrode 21A electrically connects a PMOS, which is a first conductive type MOS of a first semiconductor layer 22A in the first layer, and an NMOS, which is a second conductive type MOS of a second semiconductor layer 23A in the second layer. For example, the gate electrode 21C electrically connects a PMOS, which is a first conductive type MOS, in the third first semiconductor layer 22C, and an NMOS, which is a second conductive type MOS, in the fourth second semiconductor layer 23C.

[0032] Furthermore, in the second CMOS circuit 20, for a certain i (1≦i≦N), the gate electrode 21B commonly electrically connects at least the second conductive type MOS in the second semiconductor layer 23 in the 2i-th layer and the first conductive type MOS in the first semiconductor layer 22 in the (2i+1)-th layer (i.e., the 3rd, 5th, 7th,...(2i+1)th layers). Specifically, in the second CMOS circuit 20, for example, the gate electrode 21B commonly electrically connects the NMOS, which is the second conductive type MOS in the second semiconductor layer 23B in the second layer, and the PMOS, which is the first conductive type MOS in the first semiconductor layer 22D in the third layer. Furthermore, for example, the gate electrode 21B may be electrically connected in common to a PMOS, which is a first conductivity type MOS, in the first semiconductor layer 22B in the first layer, and an NMOS, which is a second conductivity type MOS, in the second semiconductor layer 23D in the fourth layer.

[0033] The semiconductor integrated circuit 100 according to the embodiment includes, for a certain i (1≦i≦N), a first standard cell SC1 in which a first conductivity type MOS in the (4i-1)th layer and a second conductivity type MOS in the (4i)th layer share a gate terminal, a second standard cell SC2 in which a first conductivity type MOS in the (4i-3)th layer and a second conductivity type MOS in the (4i-2)th layer share a gate terminal, and a third standard cell SC3 in which a first conductivity type MOS in the (4i-3)th layer and the (4i-1)th layer and a second conductivity type MOS in the 4ith layer and the (4i-2)th layer share a gate terminal.

[0034] Also, the semiconductor device includes a plurality of first standard cells SC1 and second standard cells SC2, and at least some of the first standard cells SC1 are arranged so as to be stacked on at least some of the second standard cells SC2.

[0035] Furthermore, the capacitance of the signal line driven by the first standard cell SC1 and the second standard cell SC2 is lower than the capacitance of the signal line driven by the third standard cell SC3. Next, an equivalent circuit of the semiconductor integrated circuit 100 will be described with reference to FIG.

[0036] 4, an equivalent circuit of the semiconductor integrated circuit 100 is represented by a first CMOS circuit 10 (10A, 10B, 10C, 10D) and a second CMOS circuit 20 (20A, 20B, 20C). The connection relationship between the first CMOS circuit 10 (10A, 10B, 10C, 10D) and the second CMOS circuit 20 (20A, 20B, 20C) will be described later.

[0037] In the following description, the circuit structure including the first semiconductor layer 12A and the second semiconductor layer 13A is also referred to as the first circuit structure. The circuit structure including the first semiconductor layer 12B and the second semiconductor layer 13B is also referred to as the second circuit structure. The circuit structure including the first semiconductor layer 12C and the second semiconductor layer 13C is also referred to as the third circuit structure. The circuit structure including the first semiconductor layer 12D and the second semiconductor layer 13D is also referred to as the fourth circuit structure. The circuit structure including the first semiconductor layer 22A and the second semiconductor layer 23A is also referred to as the fifth circuit structure. The circuit structure including the first semiconductor layer 22B and the second semiconductor layer 23B is also referred to as the sixth circuit structure. The circuit structure including the first semiconductor layer 22C and the second semiconductor layer 23C is also referred to as the seventh circuit structure. The circuit structure including the first semiconductor layer 22D and the second semiconductor layer 23D is also referred to as the eighth circuit structure.

[0038] The first CMOS circuit 10A can represent, for example, a first circuit structure in which a gate electrode 11A is commonly connected between a PMOS, which is a first conductive type MOS having a first semiconductor layer 12A in the first layer, and an NMOS, which is a second conductive type MOS having a second semiconductor layer 13A in the second layer. Also, the first CMOS circuit 10B can represent, for example, a second circuit structure in which a gate electrode 11B is commonly connected between a PMOS, which is a first conductive type MOS having a first semiconductor layer 12B in the first layer, and an NMOS, which is a second conductive type MOS having a second semiconductor layer 13B in the second layer.

[0039] Similarly, the first CMOS circuit 10C can be represented by a third circuit structure in which a gate electrode 11C is commonly connected between a PMOS, which is a first conductivity type MOS having a first semiconductor layer 12C in the third layer, and an NMOS, which is a second conductivity type MOS having a second semiconductor layer 13C in the fourth layer. Also, the first CMOS circuit 10D can be represented by a fourth circuit structure in which a gate electrode 11D is commonly electrically connected between a PMOS, which is a first conductivity type MOS having a first semiconductor layer 12D in the third layer, and an NMOS, which is a second conductivity type MOS having a second semiconductor layer 13D in the fourth layer.

[0040] The second CMOS circuit 20A can be represented by a fifth circuit structure in which a gate electrode 21A is commonly and electrically connected between a PMOS, which is a first conductive type MOS having a first semiconductor layer 22A in the first layer, and an NMOS, which is a second conductive type MOS having a second semiconductor layer 23A in the second layer. The second CMOS circuit 20B can be represented by a sixth circuit structure in which a gate electrode 21B is commonly and electrically connected between a PMOS, which is a first conductive type MOS having a first semiconductor layer 22B in the first layer, and an NMOS, which is a second conductive type MOS having a second semiconductor layer 23B in the second layer.

[0041] Furthermore, the second CMOS circuit 20C can be represented by a seventh circuit structure in which a gate electrode 21C is commonly and electrically connected to a PMOS, which is a first conductivity type MOS having a first semiconductor layer 22C in the first layer, and an NMOS, which is a second conductivity type MOS having a second semiconductor layer 23C in the second layer.

[0042] The second CMOS circuit 20D can be represented by an eighth circuit structure in which a gate electrode 21C is electrically connected in common to a PMOS, which is a first conductivity type MOS having a first semiconductor layer 22D in the first layer, and an NMOS, which is a second conductivity type MOS having a second semiconductor layer 23D in the second layer. Furthermore, the sixth and eighth circuit structures can be represented by a circuit structure in which a gate electrode 21B is electrically connected in common.

[0043] 4, the semiconductor integrated circuit 100 according to the embodiment can be configured with standard cells SC1 (SC Type A), SC2 (SC Type A), and SC3 (SC Type B) as basic units. In the semiconductor integrated circuit 100, a plurality of CMOS circuits each having standard cells SC1, SC2, and SC3 as basic units are arranged in the XY directions, and further arranged across a plurality of layers in the Z direction. The semiconductor integrated circuit 100 according to the embodiment can efficiently provide a semiconductor integrated circuit with high logic density by using two types of standard cells with different numbers of layers. (Detailed planar pattern configuration)

[0044] Fig. 5 is a detailed planar pattern configuration diagram of the semiconductor integrated circuit 100 according to the embodiment. The interlayer insulating film 2 is omitted in Fig. 5. As shown in Fig. 5, the semiconductor integrated circuit 100 includes a power supply wiring layer (31, 32, 33, 34), gate electrodes (11C, 11A), gate electrodes (11D, 11B), gate electrodes (21C, 21D), gate electrode 21B, and signal wiring layers (401, 402, 403, 404). (Cross-sectional structure: A2-A2)

[0045] Fig. 6 is a cross-sectional view taken along line A2-A2 in Fig. 5. As shown in Fig. 6, standard cell SC1 (SC Type A) is disposed above standard cell SC2 (SC Type A). Second semiconductor layers (13A, 13C) in the second layer are disposed above first semiconductor layers (12A, 12C) in the first layer. The first semiconductor layer 12A and the second semiconductor layer 13A penetrate the gate electrode 11A. The first semiconductor layer 12C and the second semiconductor layer 13C penetrate the gate electrode 11C.

[0046] The first power supply wiring layer 31 is disposed, for example, below the source region 14A of the first semiconductor layer 12A (in the negative Z direction). The first power supply wiring layer 33 is disposed, for example, below the source region 14C of the first semiconductor layer 12C (in the negative Z direction). The first power supply wiring layers (31, 33) may be, for example, VDD wiring.

[0047] The second power supply wiring layer 32 is disposed, for example, above the source region 17A of the second semiconductor layer 13A (in the Z direction). The second power supply wiring layer 34 is disposed, for example, above the source region 17C of the second semiconductor layer 13C (in the Z direction). The second power supply wiring layers (32, 34) may be, for example, VSS wiring.

[0048] The drain region 15A of the first semiconductor layer 12A is connected to the drain region 18A of the second semiconductor layer 13A. The drain region 18A of the second semiconductor layer 13A is connected to the signal wiring layer 401A. The drain region 15C of the first semiconductor layer 12C is connected to the drain region 18C of the second semiconductor layer 13C. The drain region 18C of the second semiconductor layer 13C is connected to the signal wiring layer 401C. (Cross-sectional structure: A3-A3)

[0049] Fig. 7 is a cross-sectional view taken along line A3-A3 in Fig. 5. As shown in Fig. 7, a standard cell SC3 (SC Type B) is arranged. A second semiconductor layer (23B, 23D) is arranged above (in the Z direction) the first semiconductor layer (22B, 22D). The first semiconductor layer (22B, 22D) and the second semiconductor layer (23B, 23D) penetrate the gate electrode 21B.

[0050] The first power supply wiring layer 31 is disposed, for example, below the source region 24B of the first semiconductor layer 22B (in the negative Z direction). The first power supply wiring layer 33 is disposed, for example, below the source region 24D of the first semiconductor layer 22D (in the negative Z direction). The first power supply wiring layers (31, 33) may be, for example, VDD wiring.

[0051] The second power supply wiring layer 32 is disposed, for example, above the source region 27B of the second semiconductor layer 23B (in the Z direction). The second power supply wiring layer 34 is disposed, for example, above the source region 27D of the second semiconductor layer 23D (in the Z direction). The second power supply wiring layers (32, 34) may be, for example, VSS wiring.

[0052] The drain region 25B of the first semiconductor layer 22B is connected to the drain region 28B of the second semiconductor layer 23B. The drain region 28B of the second semiconductor layer 23B is connected to the signal wiring layer 404B. The drain region 25D of the first semiconductor layer 22D is connected to the drain region 28D of the second semiconductor layer 23D. The drain region 28D of the second semiconductor layer 23D is connected to the signal wiring layer 404.

[0053] Therefore, the drain region 25B of the first semiconductor layer 22B, the signal wiring layer 404B, the drain region 28B of the second semiconductor layer 23B, the drain region 25D of the first semiconductor layer 22D, the signal wiring layer 404, and the drain region 28D of the second semiconductor layer 23D are electrically connected in common. An output OUT is obtained from the signal wiring layer 404. (Cross-sectional structure: A4-A4)

[0054] FIG. 8 is a cross-sectional view taken along line A4-A4 in FIG. 5. As shown in FIG. 8, the standard cell SC1 is disposed above the standard cell SC2 (positive Z direction). The standard cell SC3 is disposed adjacent to the standard cell SC1 and the standard cell SC2 in the X direction. As shown in FIG. 8, the power supply wiring layer (31, 33) is disposed, for example, below the first semiconductor layer (12, 22) (negative Z direction). The first semiconductor layer (12, 22) extends in the Y direction, and the power supply wiring layer (31, 33) extends in the X direction. Specifically, the power supply wiring layer 31 is disposed, for example, below the source region (14, 24) of the first semiconductor layer (12A, 12B, 22A, 22B) (negative Z direction). The power supply wiring layer 33 is disposed, for example, below the source region (14, 24) of the first semiconductor layer (12C, 12D, 22C, 22D) (negative Z direction). The power supply wiring layers (31, 33) may be, for example, VDD wiring.

[0055] The power supply wiring layer (32, 34) is disposed, for example, above the second semiconductor layer (13, 23) (positive Z direction). The second semiconductor layer (13, 23) extends in the Y direction, and the power supply wiring layer (32, 34) extends in the X direction. Specifically, the power supply wiring layer 32 is disposed, for example, above the drain regions (18, 28) of the second semiconductor layers (13A, 13B, 23A, 23B) (positive Z direction). The power supply wiring layer 34 is disposed, for example, above the drain regions (18, 28) of the second semiconductor layers (13C, 13D, 23C, 23D) (positive Z direction). The power supply wiring layer (32, 34) may be, for example, a VSS wiring. (Cross-sectional structure: A5-A5)

[0056] FIG. 9 is a cross-sectional view taken along the line A5-A5 in FIG. 5. Note that the gate insulating film 3 shown in FIG. 3 is omitted in FIG. 9. As shown in FIG. 9, the standard cell SC1 is disposed on the standard cell SC2 in the Z direction. The standard cell SC3 is disposed adjacent to the standard cell SC1 and the standard cell SC2 in the X direction. The standard cell SC1 includes gate electrodes 11C and 11D, and the standard cell SC2 includes gate electrodes 11A and 11B. The standard cell SC3 includes gate electrodes 21A, 21B, and 21C. The second semiconductor layers (13A, 13B, 23A, and 23B) are disposed above (in the positive Z direction) the first semiconductor layers (12A, 12B, 22A, and 22B). The second semiconductor layers (13C, 13D, 23C, and 23D) are disposed above (in the positive Z direction) the first semiconductor layers (12C, 12D, 22C, and 22D).

[0057] The first semiconductor layer (12A, 12B, 22A, 22B) and the second semiconductor layer (13A, 13B, 23A, 23B) penetrate the gate electrode (11A, 11B, 21A, 21B). Similarly, the first semiconductor layer (12C, 12D, 22C, 22D) and the second semiconductor layer (13C, 13D, 23C, 23D) penetrate the gate electrode (11C, 11D, 21C, 21B). The input IN is connected to the gate electrode 11C. (Cross-sectional structure: A6-A6)

[0058] Fig. 10 is a cross-sectional view taken along line A6-A6 in Fig. 5. As shown in Fig. 10, in the standard cell SC1, the output of the first CMOS circuit 10C is connected to a signal wiring layer 401C, and the output of the first CMOS circuit 10D is connected to a signal wiring layer 402D. The signal wiring layer 402D is connected to a signal wiring layer 405, and the signal wiring layer 405 is connected to the gate electrode 11A of the first CMOS circuit 10A.

[0059] In the standard cell SC2, the output of the first CMOS circuit 10A is connected to a signal wiring layer 401A, and the output of the first CMOS circuit 10B is connected to a signal wiring layer 402B.

[0060] In the standard cell SC3, the output of the second CMOS circuit 20A is connected to the signal wiring layer 403A, the output of the second CMOS circuit 20B is connected to the signal wiring layer 404B, the output of the second CMOS circuit 20C is connected to the signal wiring layer 403C, and the output of the second CMOS circuit 20D is connected to the signal wiring layer 404. The output OUT is obtained from the signal wiring layer 404. (Side structure: A5+A6―A5+A6)

[0061] Fig. 11 is a diagram in which the power wiring layers 31, 32, 33, and 34 are omitted from Fig. 5. Fig. 12 is a side view of the cross sections along the lines A5-A5 and A6-A6 in Fig. 11 as viewed from the direction of the arrows. Fig. 12 is a diagram in which the cross sections along the lines A5-A5 and A6-A6 are superimposed. By referring to Fig. 12, the connection relationship of the equivalent circuit shown in Fig. 4 can be clarified.

[0062] 11, in the standard cell SC1, the input IN is connected to the gate electrode 11C. The signal wiring layer 401C is connected to the gate electrode 11D. The signal wiring layer 401C is connected to the signal wiring layer 402D. The signal wiring layer 402D is connected to the signal wiring layer 405. The signal wiring layer 405 is connected to the gate electrode 11A. In the standard cell SC2, the signal wiring layer 401A is connected to the gate electrode 11B.

[0063] In the standard cell SC3, the signal wiring layer 402B is connected to the gate electrode 21C. The signal wiring layer 403C is connected to the gate electrode 21A. The signal wiring layer 403A is connected to the gate electrode 21B. The signal wiring layer 403B is connected to the signal wiring layer 404. The output OUT is obtained from the signal wiring layer 404. (Layout design system)

[0064] Next, a description will be given of a layout design system for designing the layout of the semiconductor integrated circuit 100 according to the embodiment. The semiconductor integrated circuit used in the layout design system corresponds to the semiconductor integrated circuit 100 according to the embodiment.

[0065] Fig. 13 is a schematic diagram of a layout design system 200 for designing the layout of a semiconductor integrated circuit according to the embodiment, and Fig. 14 is a block diagram of the layout design system 200 of Fig. 13.

[0066] 13, the layout design system 200 includes a central processing unit (CPU) server 41, a storage medium 42, a computer device 43, and a network 44. In the following description, the central processing unit server 41 is also referred to as a CPU server 41. The CPU server 41 operates as a layout design device.

[0067] In the layout design system 200, a CPU server 41, a storage medium 42, and a computer device 43 operated by a user are connected via a network 44. The CPU server 41 stores a computer program used in the layout design system 200. The storage medium 42 stores information and data such as input information and output information required to execute the computer program used in the layout design system 200. The computer device 43 is operated by a user, and causes the CPU server 41 to execute a layout design process in accordance with the user's operation.

[0068] The CPU server 41 may be, for example, an engineering workstation, a mainframe, or a supercomputer. The storage medium 42 may be, for example, an external storage device such as a hard disk, a semiconductor storage device such as a memory, a storage medium (media), or may be a file server or a data server. The computer device 43 may be, for example, a personal computer (PC), a thin client terminal, a mobile terminal, or a personal digital assistant (PDA). The network 44 may be, for example, the Internet, an intranet, a LAN, a telephone communication network, or a dedicated line. However, in practice, it is not limited to these examples.

[0069] As shown in FIG. 14, the storage medium 42 includes a circuit description section 51, a cell library 52, cell connection information 53 (also called a gate netlist), and chip layout information 54.

[0070] The circuit description section 51 is, for example, a circuit design data file described in register transfer level (RTL). The circuit description section 51 is an example of input information required to execute a computer program used in the layout design system 200.

[0071] The cell connection information 53 is, for example, a circuit design data file written at the gate level that is output after logic synthesis. The cell connection information 53 is an example of input information required to execute a computer program used in the layout design system 200.

[0072] The cell library 52 stores information on various standard cells, including information on standard cells SC1, SC2, and SC3 constituting the semiconductor integrated circuit 100 according to the embodiment. The cell library 52 is an example of input information required to execute a computer program used in the layout design system 200.

[0073] The chip layout information 54 is, for example, a circuit pattern data file for arranging a circuit on the substrate 1. The chip layout information 54 is an example of output information required for executing a computer program used in the layout design system 200.

[0074] As shown in FIG. 14, the CPU server 41 includes a logic synthesis unit 61 and a layout design unit 62 that execute a computer program used in the layout design system 200. The logic synthesis unit 61 and the layout design unit 62 execute a computer program used in the layout design system 200.

[0075] The logic synthesis unit 61 and the layout design unit 62 may be processing devices such as a CPU or a microprocessor, but are not limited to these examples.

[0076] The logic synthesis unit 61 inputs information from the circuit description unit 51 and information from the cell library 52, and performs logic synthesis on the connection information based on the input information. The logic synthesis unit 61 also outputs the logic-synthesized cell connection information to the cell connection information 53 in the storage medium 42. In this embodiment, the information that the logic synthesis unit 61 has performed logic synthesis on and stored in the cell connection information 53 is also referred to as "tentative cell connection information."

[0077] Furthermore, for each cell in the tentative cell connection information stored in the cell connection information 53, the logic synthesis unit 61 calculates a signal delay time of a signal path including the cell, and judges whether or not the cell can be replaced with another cell (any of the first, second, or third standard cells) having a buffer size that reduces the calculated signal delay time. If the result of the judgment indicates that the cell can be replaced with another cell, the logic synthesis unit 61 replaces the cell with the other replaceable cell (any of the first, second, or third standard cells).

[0078] As a result, a cell that drives a signal line with a relatively large capacitance is replaced with a standard cell with a relatively large capacitance, and a cell that drives a signal line with a relatively small capacitance is replaced with a standard cell with a relatively small capacitance. For example, a cell that drives a signal line with a relatively large capacitance is replaced with a third standard cell SC3 that can drive a capacitor C3 with a relatively large capacitance. Also, a cell that drives a signal line with a relatively small capacitance is replaced with a first standard cell SC1 or a second standard cell SC2 that can drive a capacitor C1 or a capacitor C2 with a relatively small capacitance.

[0079] When the verification process for checking whether or not the cells can be replaced is completed for all the cells included in the tentative cell connection information, the logic synthesis unit 61 stores the final cell connection information in the cell connection information 53 in the storage medium 42 .

[0080] Let us explain in more detail. For example, the tentative cell connection information is composed of cells including the first, second, and third standard cells. Alternatively, the tentative cell connection information may be composed of cells including only the first and second standard cells. The logic synthesis unit 61 determines whether a part having a large wiring capacity and a long signal delay time, but composed of the first or second standard cell, can be replaced with the third standard cell. If the signal delay time is shortened by replacing the part with the third standard cell and the allowable range of the circuit operation is satisfied, the first and / or second standard cell in the part is replaced with the third standard cell. Alternatively, the portion configured with the third standard cell may be replaced with the first or second standard cell even though the wiring capacitance is relatively small. In this case, the signal delay time becomes longer. Therefore, the length of the delay time must be within the allowable range for the circuit operation. Furthermore, the circuit area may be added to the criteria for judgment. If the circuit area exceeds a predetermined size, the first and second standard cells do not need to be replaced with the third standard cell.

[0081] The layout design unit 62 executes automatic cell placement and automatic wiring (routing) connection based on the cell connection information 53 and the information of the cell library 52 , generates chip layout information, and stores the chip layout information 54 in the storage medium 42 .

[0082] As described above, the layout design system 200 according to the embodiment is a layout design system for performing layout design of the semiconductor integrated circuit 100, and includes a CPU server (layout design device) 41 and a storage medium 42 for storing data of the CPU server 41. The CPU server 41 includes a logic synthesis unit 61 that performs logic synthesis based on information stored in a circuit description unit 51 and a cell library 52 of the storage medium 42 and outputs the logic synthesis to cell connection information 53 of the storage medium 42 as tentative cell connection information, and a layout design unit 62 that performs automatic placement and automatic wiring connection based on information stored in the cell connection information 53 and the cell library 52 to generate chip layout information. The logic synthesis unit 61 calculates, for each cell in the tentative cell connection information stored in the cell connection information 53, the signal delay time of the signal path in which the cell is included, and determines whether the cell can be replaced with any of the first, second, or third standard cells SC1, SC2, or SC3 having a buffer size that reduces the calculated signal delay time. If the determination results in a determination that the cell can be replaced, the logic synthesis unit 61 replaces the cell with any of the first, second, or third standard cells SC1, SC2, or SC3 that can be replaced.

[0083] Here, the capacitance C1 of the signal line driven by the first standard cell SC1 and the capacitance C2 of the signal line driven by the second standard cell SC2 are lower than the capacitance C3 of the signal line driven by the third standard cell SC3.

[0084] Furthermore, when a plurality of first standard cells SC1 and second standard cells SC2 are arranged, at least some of the first standard cells SC1 may be arranged so as to be stacked on at least some of the second standard cells SC2. (Layout design system variation 1) FIG. 15 is a block diagram showing a first modification of the layout design system 200 shown in FIG. In the layout design system 200 shown in FIG. 13, a configuration in which the logic synthesis unit 61 and the layout design unit 62 are provided within the CPU server 41 is shown.

[0085] In contrast, in the layout design system 200 according to the first modification, the logic synthesis unit 61 and the layout design unit 62 are provided in a computer device 43 that is directly operated by a user, without using a CPU server 41. That is, in the layout design system 200 according to the first modification, the computer device 43 operates as a layout design device.

[0086] The functions and configurations of the logic synthesis unit 61 and layout design unit 62 provided in the computer device 43 are similar to the functions and configurations of the logic synthesis unit 61 and layout design unit 62 provided in the CPU server 41 in the layout design system 200 shown in FIG. 13. Moreover, the function and configuration of the storage medium 42 in the first modification are similar to those of the storage medium 42 in the layout design system 200 shown in FIG. For example, in the case of a layout design system 200 with a relatively low load, the layout design system 200 according to the first modification can be used. (Layout design system variation 2) FIG. 16 is a block diagram showing a second modification of the layout design system 200 shown in FIG.

[0087] 15, the layout design system 200 according to the second modification does not use a CPU server 41, but includes a logic synthesis unit 61 and a layout design unit 62 in a computer device 43. That is, in the layout design system 200 according to the second modification, the computer device 43 also operates as a layout design device. Furthermore, in the layout design system 200 according to the second modification, the storage medium 42 is also configured to be provided within the computer device 43.

[0088] The functions and configurations of the logic synthesis unit 61 and layout design unit 62 provided in the computer device 43 are similar to those of the logic synthesis unit 61 and layout design unit 62 provided in the CPU server 41 in the layout design system 200 shown in Fig. 13, and are similar to those of the logic synthesis unit 61 and layout design unit 62 provided in the computer device 43 shown in Fig. 14. In addition, the functions and configurations of the storage medium 42 provided in the computer device 43 are also similar to those of the storage medium 42 shown in Figs. 13 and 14.

[0089] For example, in the case of a layout design system 200 with a relatively low load, it is possible to use the layout design system 200 according to Modification 2. According to the layout design system 200 according to Modification 2, the network 44 is not necessarily required. (Effects of the layout design system)

[0090] As described above, according to the layout design using the layout design system 200 according to the embodiment and the layout design systems 200 according to the first and second modifications, it is possible to provide a layout design system that efficiently designs circuits by utilizing multi-layer stacked PMOS / NMOS channels by selectively replacing each cell constituting the semiconductor integrated circuit 100 according to the embodiment with the standard cells SC1, SC2, and SC3 depending on the capacitance of the signal line driven by the cell. (Layout design method)

[0091] A layout design method to which the semiconductor integrated circuit 100 according to the embodiment is applied will be described with reference to the flowchart shown in Fig. 17. The layout design method described below can be executed by the layout design system 200 according to the embodiment shown in Figs. 13 to 16 or the layout design system 200 according to the first and second modifications.

[0092] Also, a part or all of the layout design method described below can be written in a computer-executable program (computer program) as instructions to cause a computer to execute the method. The computer program is, for example, stored in a non-transitory computer-readable medium and executed by the layout design system 200 according to the embodiment or the layout design system 200 according to the first and second modifications.

[0093] (A) In step S 101 , the logic synthesis unit 61 of the layout design system 200 inputs the information stored in the circuit description unit 51 and the cell library 52 .

[0094] (B) In step S102, the logic synthesis unit 61 performs logic synthesis based on information input from the circuit description unit 51 and the cell library 52 of the storage medium 42. Specifically, a gate netlist of a desired circuit is generated from an RTL description expressed in a hardware description language. The generated gate netlist of the desired circuit is used as provisional cell connection information for performing a layout design of the semiconductor integrated circuit 100 according to the embodiment. (C) In step S103, the logic synthesis unit 61 outputs the logic-synthesized gate netlist to the cell connection information 53 in the storage medium .

[0095] (D) In ​​step S104, the logic synthesis unit 61 calculates, for each cell in the tentative cell connection information stored in the cell connection information 53, the signal delay time of the signal path including the cell, and determines whether the cell can be replaced with any of the first, second, or third standard cells having a buffer size that reduces the calculated signal delay time.

[0096] (E) If the result of the determination is that replacement is possible (if the result of the determination in step S104 is YES), in step S105, the logic synthesis unit 61 replaces the cell with any one of the first, second, and third standard cells that are replaceable.

[0097] Through the processing of steps S104 to S105, a cell having a relatively large capacitance of a driving signal line is replaced with a standard cell having a relatively large capacitance, and a cell having a relatively small capacitance of a driving signal line is replaced with a standard cell having a relatively small capacitance. For example, a cell having a relatively large capacitance of a driving signal line is replaced with a third standard cell SC3 capable of driving a relatively large capacitance capacitor C3. Also, a cell having a relatively small capacitance of a driving signal line is replaced with a first standard cell SC1 or a second standard cell SC2 capable of driving a relatively small capacitance capacitor C1 or capacitor C2.

[0098] As in the example shown in FIGS. 1 to 4, for a certain i (1≦i≦N), the layout design unit 62 selectively arranges a first standard cell SC1 in which a second conductivity type MOS in the (4i-3)th layer and a first conductivity type MOS in the (4i-2)th layer share a gate terminal, a second standard cell SC2 in which a second conductivity type MOS in the (4i-1)th layer and a first conductivity type MOS in the (4i)th layer share a gate terminal, and a third standard cell SC3 in which a second conductivity type MOS in the (4i-3)th layer and the (4i-1)th layer and a first conductivity type MOS in the 4ith layer and the (4i-2)th layer share a gate terminal.

[0099] Here, the capacitance C1 of the signal line driven by the first standard cell SC1 and the capacitance C2 of the signal line driven by the second standard cell SC2 are lower than the capacitance C3 of the signal line driven by the third standard cell SC3.

[0100] In addition, when the layout design unit 62 arranges a plurality of first standard cells SC1 and second standard cells SC2, the layout design unit 62 may arrange the first standard cells SC1 so that at least a portion of the first standard cells SC1 are stacked on at least a portion of the second standard cells SC2.

[0101] (F) In step S106, the logic synthesis unit 61 judges whether or not the verification process of whether or not the cells can be replaced has been completed for all the cells included in the tentative cell connection information stored in the cell connection information 53. If the result of the judgment shows that the verification process of whether or not the cells can be replaced has not been completed for all the cells (if the judgment result of step S106 is NO), the process returns to step S104 and processes the next cell.

[0102] (G) As a result of the judgment in step S106, if the verification process for whether or not the cells can be replaced is all complete (if the judgment result in step S106 is YES), that is, if the final cell connection information is completed, proceed to step S107. In step S107, the logic synthesis unit 61 outputs the final cell connection information to the cell connection information 53 in the storage medium 42. The layout design unit 62 executes automatic cell placement and automatic wiring connection based on the final cell connection information 53 and the information of the cell library 52, to generate chip layout information. Then, after the chip layout information is output, the process ends. (Effect of layout design method)

[0103] As described above, according to the layout design method and computer program to which the semiconductor integrated circuit 100 of the embodiment is applied, it is possible to provide a layout design system that efficiently designs circuits by utilizing multi-layer stacked PMOS / NMOS channels by selectively replacing each cell constituting the semiconductor integrated circuit 100 of the embodiment with the standard cells SC1, SC2, and SC3 in accordance with the capacitance of the signal line driven by the cell. (Effects of the embodiment)

[0104] As described above, according to the embodiments, by using two types of standard cells SC Type A and SC Type B having different numbers of layers, it is possible to efficiently provide a layout design system, a layout design method, and a program for a semiconductor integrated circuit having high logic density.

[0105] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0106] 1...Substrate 2...Interlayer insulating film 3...Gate insulating film 10, 10A, 10B, 10C, 10D...First CMOS circuit 11A, 11B, 11C, 11D, 21A, 21B, 21C...gate electrodes 12, 12A, 12B, 12C, 12D, 22, 22A, 22B, 22C, 22D...first semiconductor layer 13, 13A, 13B, 13C, 13D, 23, 23A, 23B, 23C, 23D...Second semiconductor layer 14, 24, 17, 27…Source region 15, 25, 18, 28…Drain region 16, 26, 19, 29…Channel regions 20, 20A, 20B, 20C, 20D...Second CMOS circuit 31, 32, 33, 34…power wiring layer 41…Server 42…Storage medium 43...Computer equipment 44…Network 51...Circuit description section 52…Cell library 53…Cell connection information 54…Chip layout information 61...Logic synthesis section 62…Layout Design Department 100...Semiconductor integrated circuit 200...Layout design system 401, 401A, 401C, 402, 402B, 402D, 403, 403A, 403C, 404, 404B, 405... signal wiring layer

Claims

1. a first semiconductor layer having a first source region, a first drain region, and a first channel region; a second semiconductor layer having a second source region, a second drain region, and a second channel region; a gate electrode formed to cover the first channel region and the second channel region via a gate insulating film; a first CMOS circuit and a second CMOS circuit each configured by combining a first conductivity type MOS having the first semiconductor layer and a second conductivity type MOS having the second semiconductor layer; Equipped with The first semiconductor layer is laminated on a (2n-1)th layer, and the second semiconductor layer is laminated on a 2nth layer (1≦n≦N, N≧2, n and N are integers), For a given i (1≦i≦N), the first CMOS circuit has a gate electrode electrically connected in common to at least the first conductive type MOS in the first semiconductor layer in a (2i−1)-th layer and the second conductive type MOS in the second semiconductor layer in a 2i-th layer; In the second CMOS circuit, the gate electrode is electrically connected in common to at least the second conductive type MOS in the second semiconductor layer in a 2i-th layer and the first conductive type MOS in the first semiconductor layer in a (2i+1)-th layer; For a certain i (1≦i≦N), a first standard cell in which a second conductive type MOS in the (4i-1)th layer and a first conductive type MOS in the (4i)th layer share a gate terminal, a second standard cell in which a second conductive type MOS in the (4i-3)th layer and a first conductive type MOS in the (4i-2)th layer share a gate terminal, and a third standard cell in which a second conductive type MOS in the (4i-3)th layer and a (4i-1)th layer and a first conductive type MOS in the 4ith layer and a (4i-2)th layer share a gate terminal. A semiconductor integrated circuit comprising:

2. 2. The semiconductor integrated circuit according to claim 1, comprising a plurality of said first standard cells and said second standard cells, at least a portion of said first standard cells being arranged in a stacked manner on at least a portion of said second standard cells.

3. 3. The semiconductor integrated circuit according to claim 1, wherein a capacitance of a signal line driven by said first standard cell and said second standard cell is lower than a capacitance of a signal line driven by said third standard cell.

4. 2. A layout design system for performing layout design of a semiconductor integrated circuit according to claim 1, The layout design system includes a layout design device and a storage medium for storing data of the layout design device; The layout design device includes: a logic synthesis unit that performs logic synthesis based on information stored in the circuit description unit and the cell library of the storage medium, and outputs the result as tentative cell connection information to the cell connection information of the storage medium; a layout design unit that performs automatic placement and automatic wiring connection based on the cell connection information and the information stored in the cell library to generate chip layout information; Equipped with the logic synthesis unit calculates, for each cell in the tentative cell connection information stored in the cell connection information, a signal delay time of a signal path including the cell, and determines whether or not the cell can be replaced with any one of the first, second, and third standard cells having a buffer size that reduces the calculated signal delay time; When the result of the determination indicates that replacement is possible, the logic synthesis unit replaces the cell with any one of the first, second, and third standard cells that are possible to be replaced.

5. 5. The layout design system according to claim 4, wherein the replacement by the layout design unit replaces a cell which drives a signal line with a relatively large capacity with the third standard cell, and replaces a cell which drives a signal line with a relatively small capacity with the first or second standard cell.

6. 5. The layout design system according to claim 4, wherein when the first standard cells and the second standard cells are arranged in a plurality of locations, the layout design unit arranges and wires the first standard cells in a manner that at least some of the first standard cells are stacked on at least some of the second standard cells.

7. 6. The layout design system according to claim 5, wherein a capacitance of the signal line driven by the first standard cell and the second standard cell is lower than a capacitance of the signal line driven by the third standard cell.

8. 2. A layout design method executed by a layout design system for performing layout design of a semiconductor integrated circuit according to claim 1, comprising: The layout design system includes a layout design device and a storage medium for storing data of the layout design device; The layout design device includes: a logic synthesis unit that performs logic synthesis based on information stored in the circuit description unit and the cell library of the storage medium, and outputs the result as tentative cell connection information to the cell connection information of the storage medium; a layout design unit that performs automatic placement and automatic wiring connection based on the cell connection information and the information stored in the cell library to generate chip layout information; Equipped with The logic synthesis unit calculates, for each cell in the tentative cell connection information stored in the cell connection information, a signal delay time of a signal path including the cell, and determines whether or not the cell can be replaced with any one of the first, second, and third standard cells having a buffer size that reduces the calculated signal delay time; the layout design method further comprising: if the determination result indicates that replacement is possible, replacing the cell with any one of the first, second, and third standard cells that are possible to be replaced by the logic synthesis unit.

9. 9. The layout design method according to claim 8, wherein, by the replacement by the logical synthesis unit, a cell which drives a signal line with a relatively large capacity is replaced with the third standard cell, and a cell which drives a signal line with a relatively small capacity is replaced with the first or second standard cell.

10. 9. The layout design method according to claim 8, wherein when the layout design unit places a plurality of the first standard cells and the second standard cells, the first standard cells are placed and wired in such a manner that at least a portion of the first standard cells are stacked on at least a portion of the second standard cells.

11. 10. The layout design method according to claim 9, wherein capacitances of the signal lines driven by the first standard cell and the second standard cell are lower than capacitance of the signal line driven by the third standard cell.

12. A computer-executable program for use in a layout design system for performing layout design of a semiconductor integrated circuit according to claim 1, The layout design system includes a layout design device and a storage medium for storing data of the layout design device; The layout design device includes: a logic synthesis unit that performs logic synthesis based on information stored in the circuit description unit and the cell library of the storage medium, and outputs the result as tentative cell connection information to the cell connection information of the storage medium; a layout design unit that performs automatic placement and automatic wiring connection based on the cell connection information and the information stored in the cell library to generate chip layout information; Equipped with calculating, by the logic synthesis unit, for each cell in the tentative cell connection information stored in the cell connection information, a signal delay time of a signal path including the cell, and determining whether or not the cell can be replaced with any one of the first, second, and third standard cells having a buffer size that reduces the calculated signal delay time; and if the determination result indicates that replacement is possible, replacing the cell with any one of the first, second, or third standard cells that are possible to be replaced, by the logic synthesis unit.

13. 13. The program according to claim 12, wherein the replacement by the logic synthesis unit replaces a cell that drives a signal line with a relatively large capacitance with the third standard cell, and replaces a cell that drives a signal line with a relatively small capacitance with the first or second standard cell.

14. 13. The program according to claim 12, wherein when the layout design unit places a plurality of the first standard cells and the second standard cells, the layout design unit places and wires the first standard cells in a manner that at least a portion of the first standard cells are stacked on at least a portion of the second standard cells.

15. 14. The program according to claim 13, wherein a capacitance of the signal line driven by the first standard cell and the second standard cell is lower than a capacitance of the signal line driven by the third standard cell.

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