Manufacturing method of semiconductor device

Abstract

To provide a manufacturing method of a semiconductor device which can further reduce a contact resistance.SOLUTION: A manufacturing method of a semiconductor device includes the steps of: forming a first nitride semiconductor layer containing gallium on a substrate; forming a mask layer on the first nitride semiconductor layer; forming an opening in the mask layer, a part of the first nitride semiconductor layer being exposed from the opening; performing a reduction treatment on the first surface exposed from the opening of the first nitride semiconductor layer in a chamber by using a first mixed gas containing hydrogen and ammonia; forming a second nitride semiconductor layer of a first conductivity type on the first surface by means of organic metal chemical vapor deposition method in the chamber by using a second gas mixture containing hydrogen, nitrogen, ammonia, and a raw material of a group III element; and forming an electrode on the second nitride semiconductor layer.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present disclosure relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art In order to reduce the contact resistance in a semiconductor device using a nitride semiconductor, a structure has been proposed in which a nitride semiconductor layer containing a high concentration of impurities is regrown. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2007-538402 [Patent Document 2] JP 2019-033155 A Summary of the Invention [Problem to be solved by the invention]

[0004] In recent years, there has been a demand for a further reduction in contact resistance in order to further increase the operating speed, but it is difficult to achieve a further reduction in contact resistance using conventional manufacturing methods.

[0005] An object of the present disclosure is to provide a method for manufacturing a semiconductor device that can further reduce contact resistance. [Means for solving the problem]

[0006] A method for manufacturing a semiconductor device according to the present disclosure includes the steps of forming a first nitride semiconductor layer containing gallium on a substrate, forming a mask layer on the first nitride semiconductor layer, forming an opening in the mask layer through which a portion of the first nitride semiconductor layer is exposed, performing a reduction treatment on a first surface of the first nitride semiconductor layer exposed from the opening in a chamber using a first mixed gas containing hydrogen and ammonia, forming a second nitride semiconductor layer of a first conductivity type on the first surface by metalorganic chemical vapor deposition in the chamber using a second mixed gas containing hydrogen, nitrogen, ammonia and a Group III element source, and forming an electrode on the second nitride semiconductor layer. Effect of the Invention

[0007] According to the present disclosure, the contact resistance can be further reduced. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a cross-sectional view (part 1) illustrating the method for manufacturing a semiconductor device according to the first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view (part 2) showing the method for manufacturing the semiconductor device according to the first embodiment. [Diagram 3] FIG. 3 is a cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Diagram 5] FIG. 5 is a cross-sectional view (part 5) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] FIG. 6 is a cross-sectional view (part 6) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] FIG. 7 is a cross-sectional view (part 7) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] FIG. 8 is a cross-sectional view (part 8) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 9]FIG. 9 is a cross-sectional view (part 1) showing the method for manufacturing the semiconductor device according to the second embodiment. [Figure 10] FIG. 10 is a cross-sectional view (part 2) showing the method for manufacturing the semiconductor device according to the second embodiment. [Figure 11] FIG. 11 is a cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the second embodiment. [Figure 12] FIG. 12 is a cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the second embodiment. [Figure 13] FIG. 13 is a cross-sectional view (part 1) showing the method for manufacturing the semiconductor device according to the third embodiment. [Figure 14] FIG. 14 is a cross-sectional view (part 2) showing the method for manufacturing the semiconductor device according to the third embodiment. [Figure 15] FIG. 15 is a cross-sectional view (part 3) showing the method for manufacturing the semiconductor device according to the third embodiment. [Figure 16] FIG. 16 is a cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the third embodiment. [Figure 17] FIG. 17 is a cross-sectional view (part 5) showing the method for manufacturing the semiconductor device according to the third embodiment. [Figure 18] FIG. 18 is a cross-sectional view (part 6) illustrating the method for manufacturing the semiconductor device according to the third embodiment. [Figure 19] FIG. 19 is a cross-sectional view (part 7) illustrating the method for manufacturing the semiconductor device according to the third embodiment. [Figure 20] FIG. 20 is a cross-sectional view (part 8) illustrating the method for manufacturing the semiconductor device according to the third embodiment. [Figure 21] FIG. 21 is a ninth cross-sectional view illustrating the method for manufacturing the semiconductor device according to the third embodiment. [Figure 22] FIG. 22 is a diagram showing an example of the relationship between the ratio of the flow rate of nitrogen to the total flow rate of hydrogen and nitrogen in the second mixed gas and the second nitride semiconductor layer. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] [Description of the embodiments of the present disclosure] First, the embodiments of the present disclosure will be listed and described.

[0010] [1] A method for manufacturing a semiconductor device according to one embodiment of the present disclosure includes the steps of forming a first nitride semiconductor layer containing gallium on a substrate, forming a mask layer on the first nitride semiconductor layer, forming an opening in the mask layer through which a portion of the first nitride semiconductor layer is exposed, performing a reduction treatment on a first surface of the first nitride semiconductor layer exposed through the opening in a chamber using a first mixed gas containing hydrogen and ammonia, forming a second nitride semiconductor layer of a first conductivity type on the first surface by metalorganic chemical vapor deposition in the chamber using a second mixed gas containing hydrogen, nitrogen, ammonia and a Group III element source, and forming an electrode on the second nitride semiconductor layer.

[0011] A reduction process is performed in the chamber used for forming the second nitride semiconductor layer, and the second nitride semiconductor layer is formed in this chamber. Therefore, even if a native oxide film is formed on the first surface of the first nitride semiconductor layer before the reduction process, the second nitride semiconductor layer is formed in a state where the native oxide film has been removed. This makes it possible to reduce the contact resistance between the electrode and the first nitride semiconductor layer.

[0012] [2] In the method of [1], the mask layer may be a silicon nitride layer. In this case, the mask layer can be used as a gate insulating film.

[0013] [3] In [1] or [2], the second nitride semiconductor layer may be an n-type gallium nitride layer. In this case, the resistance of the n-type gallium nitride layer is low, so that the contact resistance between the electrode and the first nitride semiconductor layer can be easily reduced.

[0014] [4] In any one of [1] to [3], the first mixed gas may contain nitrogen. In this case, nitrogen can suppress etching of the first nitride semiconductor layer by hydrogen.

[0015] [5] In any one of [1] to [4], the first face may be a nitrogen-polar face. In this case, it is easy to reduce the resistance of the current path in the first nitride semiconductor layer while suppressing the contact resistance.

[0016] [6] In the method of [5], the step of forming the first nitride semiconductor layer may include a step of forming a barrier layer and a step of forming a channel layer on the barrier layer. In this case, a high electron mobility transistor having low contact resistance between an electrode and the first nitride semiconductor layer can be configured.

[0017] [7] In any one of [6], a step of forming a recess in a portion of the channel layer exposed from the opening may be included between the step of forming the opening and the step of performing the reduction treatment, and the first surface may be an inner surface of the recess. In this case, the distance between the second nitride semiconductor layer and the channel region of the high electron mobility transistor can be reduced. Therefore, the contact resistance can be further reduced.

[0018] [8] In any one of [1] to [7], the second mixed gas may contain triethylgallium as a source of the Group III element. In this case, it is easy to lower the growth rate of the second nitride semiconductor layer and easy to suppress the formation of the second nitride semiconductor layer on the mask layer.

[0019] [9] In any one of [1] to [8], a ratio of a flow rate of nitrogen to a total flow rate of hydrogen and nitrogen in the second mixed gas may be 30% or more and 95% or less. In this case, the sheet resistance of the second nitride semiconductor layer is easily reduced.

[0020] [Details of the embodiment of the present disclosure] Hereinafter, the embodiments of the present disclosure will be described in detail, but the present disclosure is not limited thereto. In this specification and drawings, components having substantially the same functional configurations may be denoted by the same reference numerals to avoid redundant description.

[0021] (First embodiment) A first embodiment will be described. The first embodiment relates to a method for manufacturing a semiconductor device including a GaN-based high electron mobility transistor (HEMT). Figures 1 to 8 are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment.

[0022] 1, a nitride semiconductor layer 110 containing gallium (Ga) is formed on a substrate 101 by, for example, metal organic chemical vapor deposition (MOCVD). In forming the nitride semiconductor layer 110, a buffer layer 111, a barrier layer 112, and a channel layer 113 are formed in this order. The nitride semiconductor layer 110 is an example of a first nitride semiconductor layer.

[0023] The substrate 101 is, for example, a substrate for growing a gallium nitride (GaN)-based semiconductor, and is, for example, a semi-insulating silicon carbide (SiC) substrate. When the substrate 101 is a SiC substrate, the surface of the substrate 101 is a carbon (C) polarity surface. When the surface of the substrate 101 is a C polarity surface, the buffer layer 111, the barrier layer 112, and the channel layer 113 can grow as crystals with the nitrogen (N) polarity surface as the growth surface. A sapphire substrate may be used as the substrate for growing a GaN-based semiconductor. The substrate 101 may not be a substrate for crystal growth. In that case, the substrate 101 may be removed from the buffer layer 111, the barrier layer 112, and the channel layer 113 grown on another substrate, and the substrate 101 may be bonded to the buffer layer 111, the barrier layer 112, and the channel layer 113. In this case, various semi-insulating substrates made of various materials can be used as the substrate 101, such as a sapphire substrate, a silicon (Si) substrate, a SiC substrate, an aluminum nitride (AlN) substrate, a sintered body substrate, or the like.

[0024] The buffer layer 111 is, for example, an AlN layer. The thickness of the AlN layer is, for example, 5 nm or more and 100 nm or less. The buffer layer 111 may have an AlN layer and a GaN layer or an aluminum gallium nitride (AlGaN) layer on the AlN layer. The thickness of the GaN layer or the AlGaN layer is, for example, 300 nm or more and 2000 nm or less.

[0025] The barrier layer 112 is, for example, an AlGaN layer. The band gap of the barrier layer 112 is larger than the band gap of the channel layer 113. The thickness of the barrier layer 112 is, for example, 5 nm to 50 nm, and may be, for example, 30 nm. x Ga 1-x In the case of an N-layer, the Al composition x is, for example, 0.15 to 0.55, for example, 0.35. The conductivity type of the barrier layer 112 is, for example, n-type or undoped (i-type). Instead of the AlGaN layer, an indium aluminum nitride (InAlN) layer or an indium aluminum gallium nitride (InAlGaN) layer may be used.

[0026] The channel layer 113 is, for example, a GaN layer. The band gap of the channel layer 113 is smaller than the band gap of the barrier layer 112. The thickness of the channel layer 113 is, for example, 5 nm to 30 nm, and may be, for example, 9 nm. A strain occurs between the channel layer 113 and the barrier layer 112 due to the difference in their lattice constants, and this strain induces a piezoelectric charge at the interface between the two layers. As a result, a two dimensional electron gas (2DEG) is generated in the vicinity of the interface between the channel layer 113 and the barrier layer 112, and a channel region 113c is formed. The conductivity type of the channel layer 113 is, for example, n-type or undoped (i-type). The surface of the channel layer 113 constitutes the surface 110A of the nitride semiconductor layer 110. A spacer layer may be formed between the barrier layer 112 and the channel layer 113. The spacer layer is, for example, an AlN layer. The thickness of the spacer layer is, for example, not less than 0.5 nm and not more than 3.0 nm, and may be, for example, 1.0 nm.

[0027] On the C-polarity surface of the SiC substrate, the buffer layer 111, the barrier layer 112, and the channel layer 113 undergo crystal growth with the N-polarity surface as the growth surface. Therefore, in each of the buffer layer 111, the barrier layer 112, and the channel layer 113, the main surface farther from the substrate 101 (upper surface) is an N-polarity surface, and the main surface closer to the substrate 101 (lower surface) is a Ga-polarity surface.

[0028] 2, a silicon nitride (SiN) layer 121 is formed in contact with the surface 110A of the nitride semiconductor layer 110. The SiN layer 121 can be formed by, for example, a low pressure CVD (LPCVD) method. Next, a resist pattern 151 is formed on the SiN layer 121. The resist pattern 151 has an opening 151S for a source and an opening 151D for a drain. The SiN layer 121 is an example of a mask layer.

[0029] 3, the SiN layer 121 is etched using the resist pattern 151 as a mask. This etching is, for example, reactive ion etching (RIE) using a fluorine-based gas. As a result, an opening 121S is formed in the SiN layer 121 below the opening 151S, and an opening 121D is formed in the SiN layer 121 below the opening 151D. A part of the nitride semiconductor layer 110 is exposed from the opening 121S, and another part of the nitride semiconductor layer 110 is exposed from the opening 121D.

[0030] Next, as shown in FIG. 4, the resist pattern 151 is removed using a chemical solution. Next, in the MOCVD chamber, a first mixed gas containing nitrogen (N2), hydrogen (H2) and ammonia (NH3) is used to perform a reduction treatment on the surface 110S exposed from the opening 121S of the nitride semiconductor layer 110 and the surface 110D exposed from the opening 121D. In this reduction treatment, for example, the temperature of the substrate 101 is set to 700° C. or more and 900° C. or less, and may be set to 750° C. or more and 850° C. or less. A natural oxide film may be formed on the surface 110S and the surface 110D between the formation of the opening 121S and the opening 121D and the removal of the resist pattern 151, but the natural oxide film is removed by this reduction treatment. For example, the surface 110S and the surface 110D are part of the surface 110A. The surface 110S and the surface 110D are an example of the first surface.

[0031] Next, as shown in FIG. 5, an n-type GaN layer 131S is formed on the surface 110S, and an n-type GaN layer 131D is formed on the surface 110D. The n-type GaN layer 131S and the n-type GaN layer 131D are formed in the same MOCVD chamber without opening the MOCVD chamber to the atmosphere, using a second mixed gas containing N2, H2, NH3 and a gallium source. For example, triethylgallium (TEG) is used as the gallium source. For example, the n-type dopant is silicon (Si) or germanium (Ge), and the concentration of the n-type dopant is 1×10 17 cm -3 In this film formation, for example, the temperature of substrate 101 may be set to 700° C. or more and 900° C. or less, and may be set to 750° C. or more and 850° C. or less. In this film formation, for example, the pressure in the MOCVD chamber may be set to 13.3 kPa (100 Torr) or more and 101.3 kPa (760 Torr) or less, and may be set to 40.0 kPa (300 Torr) or more and 101.3 kPa (760 Torr) or less. N-type GaN layer 131S and n-type GaN layer 131D are examples of a second nitride semiconductor layer.

[0032] Next, as shown in FIG. 6, a source electrode 132S is formed on the n-type GaN layer 131S, and a drain electrode 132D is formed on the n-type GaN layer 131D. In forming the source electrode 132S and the drain electrode 132D, first, a laminated structure is formed by depositing a plurality of metal layers constituting the source electrode 132S and the drain electrode 132D. Then, this laminated structure is heat-treated to perform alloying. In forming the laminated structure, for example, a tantalum (Ta) layer, an aluminum (Al) layer, and a Ta layer may be formed in this order, or a titanium (Ti) layer, an Al layer, and a Ti layer may be formed in this order. The source electrode 132S and the drain electrode 132D are examples of electrodes.

[0033] Next, as shown in FIG. 7, a SiN layer 122 is formed on the SiN layer 121. The SiN layer 122 covers the n-type GaN layer 131S, the source electrode 132S, the n-type GaN layer 131D, and the drain electrode 132D. Next, an opening 122G is formed in the SiN layer 122 between the source electrode 132S and the drain electrode 132D. A part of the SiN layer 121 is exposed from the opening 122G. Next, a gate electrode 132G is formed in contact with the SiN layer 121 through the opening 122G. In forming the gate electrode 132G, a laminated structure is formed by depositing a plurality of metal layers constituting the gate electrode 132G. In forming the laminated structure, for example, a nickel (Ni) layer, a palladium (Pd) layer, and an Au layer may be formed in this order.

[0034] 8, a SiN layer 123 is formed on the SiN layer 121. The SiN layer 123 covers the gate electrode 132G.

[0035] In this manner, the semiconductor device 1 can be manufactured.

[0036] In the first embodiment, a reduction process is performed in the MOCVD chamber used for forming the n-type GaN layer 131S and the n-type GaN layer 131D, and the n-type GaN layer 131S and the n-type GaN layer 131D are formed in this MOCVD chamber. Therefore, the n-type GaN layer 131S and the n-type GaN layer 131D are formed in a state in which the natural oxide film has been removed. This makes it possible to reduce the contact resistance between the source electrode 132S and the drain electrode 132D and the nitride semiconductor layer 110. In addition, the SiN layer 121 is used as a gate insulating film.

[0037] H2 contained in the first mixed gas contributes to reduction, NH3 suppresses the desorption of Ga from the nitride semiconductor layer 110, and N2 suppresses the etching of the nitride semiconductor layer 110 by H2.

[0038] The NH3 and gallium raw materials contained in the second mixed gas are used as raw materials for the n-type GaN layer 131S and the n-type GaN layer 131D. The inclusion of H2 in the second mixed gas makes it easy to lower the growth rate of the n-type GaN layer when forming the n-type GaN layer 131S and the n-type GaN layer 131D. Therefore, it is easy to make the n-type GaN layer 131S and the n-type GaN layer 131D contain a high concentration of n-type dopant. Furthermore, the inclusion of H2 in the second mixed gas makes it easy to suppress the formation of the n-type GaN layer on the SiN layer 121. The use of TEG as a gallium raw material also makes it easy to lower the growth rate of the n-type GaN layer when forming the n-type GaN layer 131S and the n-type GaN layer 131D, making it easy to make the n-type GaN layer 131S and the n-type GaN layer 131D contain a high concentration of n-type dopant. For example, the growth rate of n-type GaN layer 131S and n-type GaN layer 131D may be 0.04 nm / sec or more and 0.08 nm / sec or less, or 0.05 nm / sec or more and 0.07 nm / sec or less.

[0039] Since the nitride semiconductor layers formed between the nitride semiconductor layer 110 and the source electrode 132S and between the nitride semiconductor layer 110 and the drain electrode 132D are the n-type GaN layers 131S and 131D, the contact resistance is easily reduced.

[0040] Since the surface 110A of the nitride semiconductor layer 110 is an N-polar surface, an increase in contact resistance can be avoided even if the Al composition of the barrier layer 112 is increased. This makes it easy to increase the concentration of the 2DEG and reduce the resistance of the channel region 113c. In particular, since the channel layer 113 is formed on the barrier layer 112, the resistance of the channel region 113c can be easily reduced.

[0041] Second embodiment Next, a second embodiment will be described. The second embodiment relates to a method for manufacturing a semiconductor device including a GaN-based HEMT. Figures 9 to 12 are cross-sectional views showing the method for manufacturing the semiconductor device according to the second embodiment.

[0042] In the second embodiment, first, similarly to the first embodiment, the process up to the formation of the opening 121S and the opening 121D is performed (see FIG. 3). Next, as shown in FIG. 9, the channel layer 113 is etched using the resist pattern 151 as a mask, thereby forming the recess 113S connected to the opening 121S and the recess 113D connected to the opening 121D in the channel layer 113. This etching is, for example, RIE using a chlorine-based gas. For example, the recess 113S and the recess 113D are formed to a depth that does not reach the channel region 113c. That is, the depth of the recess 113S and the recess 113D is smaller than the depth of the channel region 113c with respect to the surface 110A of the nitride semiconductor layer 110.

[0043] Next, as shown in FIG. 10, the resist pattern 151 is removed using a chemical solution. Next, in the MOCVD chamber, a first mixed gas containing N2, H2, and NH3 is used to perform a reduction treatment on the surface 210S exposed from the opening 121S of the nitride semiconductor layer 110 and the surface 210D exposed from the opening 121D. A natural oxide film may be formed on the surface 210S and the surface 210D between the formation of the opening 121S and the opening 121D and the removal of the resist pattern 151, but the natural oxide film is removed by this reduction treatment. For example, the surface 210S is the inner surface (bottom surface and side wall surface) of the recess 113S, and the surface 210D is the inner surface (bottom surface and side wall surface) of the recess 113D. The surface 210S and the surface 210D are examples of the first surface.

[0044] Next, as shown in Fig. 11, an n-type GaN layer 131S is formed on the surface 210S, and an n-type GaN layer 131D is formed on the surface 210D. The n-type GaN layer 131S and the n-type GaN layer 131D are formed in the same MOCVD chamber without opening the MOCVD chamber to the atmosphere, using a second mixed gas containing N2, H2, NH3, and a gallium source. For example, TEG is used as the gallium source.

[0045] Next, as shown in FIG. 12, similarly to the first embodiment, the processes subsequent to the formation of the source electrode 132S and the drain electrode 132D are carried out.

[0046] In this manner, the semiconductor device 2 can be manufactured.

[0047] The second embodiment also provides the same effect as the first embodiment. In the second embodiment, the recesses 113S and 113D are formed, the n-type GaN layer 131S is formed on the surface 210S, and the n-type GaN layer 131D is formed on the surface 210D, so that the distance between the n-type GaN layer 131S and the n-type GaN layer 131D and the channel region 113c can be reduced. Therefore, the contact resistance can be further reduced.

[0048] Third embodiment Next, a third embodiment will be described. The third embodiment relates to a method for manufacturing a semiconductor device including a GaN-based HEMT. Figures 13 to 24 are cross-sectional views showing the method for manufacturing the semiconductor device according to the third embodiment.

[0049] In the third embodiment, first, as shown in Fig. 13, a nitride semiconductor layer 310 containing Ga is formed on a substrate 301 by, for example, an MOCVD method. In forming the nitride semiconductor layer 310, a channel layer 311, a barrier layer 312, and a cap layer 313 are formed in this order. The nitride semiconductor layer 310 is an example of a first nitride semiconductor layer.

[0050] The substrate 301 is, for example, a substrate for growing a GaN-based semiconductor, and is, for example, a semi-insulating SiC substrate. When the substrate 301 is a SiC substrate, the surface of the substrate 301 is a Si polar surface. When the surface of the substrate 301 is a Si polar surface, the channel layer 311, the barrier layer 312, and the cap layer 313 can grow as crystals with the Ga polar surface as the growth surface.

[0051] The channel layer 311 is, for example, a GaN layer. The thickness of the channel layer 311 is, for example, 200 nm to 2000 nm, and may be, for example, 1000 nm. A buffer layer may be formed between the channel layer 311 and the substrate 301.

[0052] The barrier layer 312 is, for example, an AlGaN layer. The band gap of the barrier layer 312 is larger than the band gap of the channel layer 311. The thickness of the barrier layer 312 is, for example, 5 nm to 30 nm, and may be 15 nm, for example. x Ga 1-x In the case of an N layer, the Al composition x is, for example, 0.15 to 0.35, and may be 0.25. Between the channel layer 311 and the barrier layer 312, a strain occurs due to the difference in their lattice constants, and this strain induces a piezoelectric charge at the interface between them. As a result, a 2DEG occurs near the interface between the channel layer 311 and the barrier layer 312, and a channel region 311c is formed. Instead of the AlGaN layer, an InAlN layer or an InAlGaN layer may be used. Also, a spacer layer may be formed between the channel layer 311 and the barrier layer 312. The spacer layer is, for example, an AlN layer. The thickness of the spacer layer is, for example, 0.5 nm to 3.0 nm, and may be 1.0 nm.

[0053] The cap layer 313 is, for example, a GaN layer. The thickness of the cap layer 313 is, for example, 1 nm or more and 5 nm or less, and may be, for example, 2 nm. The surface of the cap layer 313 constitutes the surface 310A of the nitride semiconductor layer 310.

[0054] On the Si polarity surface of the SiC substrate, the channel layer 311, the barrier layer 312, and the cap layer 313 grow as crystals with the Ga polarity surface as the growth surface. Therefore, in each of the channel layer 311, the barrier layer 312, and the cap layer 313, the main surface farther from the substrate 301 (upper surface) is a Ga polarity surface, and the main surface closer to the substrate 301 (lower surface) is an N polarity surface.

[0055] 14, a SiN layer 121 is formed in contact with a surface 310A of the nitride semiconductor layer 310. A resist pattern 151 is then formed on the SiN layer 121. The resist pattern 151 has an opening 151S for a source and an opening 151D for a drain.

[0056] 15, the SiN layer 121 is etched using the resist pattern 151 as a mask. This etching is, for example, RIE using a fluorine-based gas. As a result, an opening 121S is formed in the SiN layer 121 below the opening 151S, and an opening 121D is formed in the SiN layer 121 below the opening 151D. A part of the nitride semiconductor layer 310 is exposed from the opening 121S, and another part of the nitride semiconductor layer 310 is exposed from the opening 121D.

[0057] Next, as shown in FIG. 16, the nitride semiconductor layer 310 is etched using the resist pattern 151 as a mask to form a recess 315S connected to the opening 121S and a recess 315D connected to the opening 121D in the nitride semiconductor layer 310. This etching is, for example, RIE using a chlorine-based gas. For example, the recess 315S and the recess 315D are formed to a depth penetrating the channel region 311c. That is, the depth of the recess 315S and the recess 315D is greater than the depth of the channel region 311c with respect to the surface 310A of the nitride semiconductor layer 310. The formation of the recess 315S and the recess 315D may be stopped midway through the barrier layer 312. That is, the recess 315S and the recess 315D may be formed so that the bottom surfaces of the recess 315S and the recess 315D are located within the barrier layer 312.

[0058] Next, as shown in FIG. 17, the resist pattern 151 is removed using a chemical solution. Next, in the MOCVD chamber, a first mixed gas containing N2, H2, and NH3 is used to perform a reduction treatment on the surface 310S exposed from the opening 121S of the nitride semiconductor layer 310 and the surface 310D exposed from the opening 121D. In this reduction treatment, for example, the temperature of the substrate 301 is set to 700°C or more and 900°C or less, and may be set to 750°C or more and 850°C or less. A natural oxide film may be formed on the surface 310S and the surface 310D between the formation of the opening 121S and the opening 121D and the removal of the resist pattern 151, but the natural oxide film is removed by this reduction treatment. For example, the surface 310S is the inner surface (bottom surface and side wall surface) of the recess 315S, and the surface 310D is the inner surface (bottom surface and side wall surface) of the recess 315D. The surface 310S and the surface 310D are examples of the first surface.

[0059] Next, as shown in FIG. 18, an n-type GaN layer 331 is formed so as to fill the recesses 315S and 315D. In forming the n-type GaN layer 331, a film is formed using a second mixed gas containing N2, H2, NH3 and gallium raw materials in the same MOCVD chamber without opening the MOCVD chamber to the atmosphere. Trimethylgallium (TMG) or TEG is used as the gallium raw material, for example. The n-type GaN layer 331 is deposited not only on the nitride semiconductor layer 310 but also on the SiN layer 121. The n-type GaN layer 331 may also be formed in the openings 121S and 121D. On the Ga polarity surface of the nitride semiconductor layer 310, the n-type GaN layer 331 is crystal-grown with the N polarity surface as the growth surface. Therefore, on the Ga polarity plane of the nitride semiconductor layer 310, of the two principal surfaces of the n-type GaN layer 331, the principal surface farther from the substrate 301 (upper surface) is a Ga polarity plane, and the principal surface closer to the substrate 301 (lower surface) is an N polarity plane.

[0060] 19, the n-type GaN layer 331 of the SiN layer 121 is removed using an alkaline solution such as an aqueous sodium hydroxide solution. Since the upper surface of the n-type GaN layer 331 on the Ga polarity surface of the nitride semiconductor layer 310 is a Ga polarity surface, the n-type GaN layer 331 in the recess 315S and the n-type GaN layer 331 in the recess 315D are not etched. As a result, the n-type GaN layer 331S is formed in the recess 315S, and the n-type GaN layer 331D is formed in the recess 315D. The n-type GaN layer 331S and the n-type GaN layer 331D are examples of a second nitride semiconductor layer.

[0061] 20, a source electrode 132S is formed on the n-type GaN layer 331S, and a drain electrode 132D is formed on the n-type GaN layer 331D. Next, an opening 121G is formed in the SiN layer 121 between the source electrode 132S and the drain electrode 132D. A part of the nitride semiconductor layer 310 is exposed from the opening 121G. Next, a gate electrode 132G is formed in contact with the nitride semiconductor layer 310 through the opening 121G.

[0062] 21, a SiN layer 123 is formed on the SiN layer 121. The SiN layer 123 covers the n-type GaN layer 331S, the source electrode 132S, the n-type GaN layer 331D, the drain electrode 132D, and the gate electrode 132G.

[0063] In this manner, the semiconductor device 3 can be manufactured.

[0064] In the third embodiment, a reduction process is performed in the MOCVD chamber used for forming the n-type GaN layer 331, and the n-type GaN layer 331 is formed in this MOCVD chamber. Therefore, the n-type GaN layer 331 is formed in a state in which the native oxide film has been removed. This makes it possible to reduce the contact resistance between the source electrode 132S and the drain electrode 132D and the nitride semiconductor layer 310.

[0065] In the present disclosure, the relative proportions of hydrogen and nitrogen in the second mixed gas are not limited, but when the proportion R of the flow rate of nitrogen to the total flow rate of hydrogen and nitrogen is 30% or more and 95% or less, a low sheet resistance is easily obtained in the second nitride semiconductor layer. When the proportion R is 60% or more and 90% or less, a lower sheet resistance is easily obtained in the second nitride semiconductor layer, and when the proportion R is 75% or more and 85% or less, a particularly low sheet resistance is easily obtained in the second nitride semiconductor layer. When the proportion R is less than 30%, the proportion of hydrogen is excessively high, the growth rate increases excessively, and the surface morphology is deteriorated, so that the sheet resistance is likely to be high. On the other hand, when the proportion R is more than 95%, the crystallinity of the second nitride semiconductor layer may be deteriorated, and the sheet resistance may be high. FIG. 22 is a diagram showing an example of the relationship between the proportion R of the flow rate of nitrogen to the total flow rate of hydrogen and nitrogen in the second mixed gas and the second nitride semiconductor layer.

[0066] Although the embodiments have been described in detail above, the present disclosure is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0067] 1, 2, 3: Semiconductor device 101, 301: Substrate 110, 310: nitride semiconductor layer 110A, 310A: Surface 110D, 110S, 210D, 210S, 310D, 310S: Surface 111: Buffer layer 112, 312: Barrier layer 113, 311: Channel layer 113c, 311c: Channel region 113D, 113S, 315D, 315S: Concave 121, 122, 123: SiN layer 121D, 121G, 121S, 122G: Aperture 131D, 131S, 331, 331D, 331S: n-type GaN layer 132D: Drain electrode 132G: Gate electrode 132S: Source electrode 151: Resist pattern 151D, 151S: Opening 313: Cap layer

Claims

1. forming a first nitride semiconductor layer containing gallium on a substrate; forming a mask layer on the first nitride semiconductor layer; forming an opening in the mask layer through which a portion of the first nitride semiconductor layer is exposed; performing a reduction treatment on a first surface of the first nitride semiconductor layer exposed through the opening in a chamber using a first mixed gas containing hydrogen and ammonia; forming a second nitride semiconductor layer of a first conductivity type on the first surface by metalorganic chemical vapor deposition in the chamber using a second mixed gas containing hydrogen, nitrogen, ammonia and a source of a Group III element; forming an electrode on the second nitride semiconductor layer; The method for manufacturing a semiconductor device comprising the steps of:

2. 2. The method of claim 1, wherein the mask layer is a silicon nitride layer.

3. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the second nitride semiconductor layer is an n-type gallium nitride layer.

4. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the first mixed gas contains nitrogen.

5. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the first surface is a nitrogen polarity surface.

6. The step of forming the first nitride semiconductor layer includes: forming a barrier layer; forming a channel layer on the barrier layer; The method for manufacturing a semiconductor device according to claim 5 , comprising:

7. a step of forming a recess in a portion of the channel layer exposed through the opening between the step of forming the opening and the step of performing the reduction treatment, The method for manufacturing a semiconductor device according to claim 6 , wherein the first surface is an inner surface of the recess.

8. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the second mixed gas contains triethylgallium as a source of the Group III element.

9. 3. The method for manufacturing a semiconductor device according to claim 1, wherein a ratio of a flow rate of nitrogen to a total flow rate of hydrogen and nitrogen in said second mixed gas is 30% or more and 95% or less.

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