Diamond FET, electrical device, and method for manufacturing diamond fet

Abstract

To provide a diamond FET, an electrical device, and a method for manufacturing diamond FET, which can contribute to ensuring contact of a gate electrode even when the gate length is miniaturized to less than 100 nm.SOLUTION: A diamond FET includes a diamond semiconductor layer, a gate electrode disposed on the diamond semiconductor layer and having a gate length of less than 100 nm, and a passivation film covering at least an element region of the diamond semiconductor layer including the gate electrode.SELECTED DRAWING: Figure 9

Description

[Technical field]

[0001] The present invention relates to a diamond FET, an electrical device, and a method for manufacturing a diamond FET. [Background technology]

[0002] Recent developments in diamond CVD (Chemical Vapor Deposition) technology have led to the production of increasingly higher purity CVD diamonds, making it possible to obtain single crystal diamonds with high carrier (electron, hole) mobility. This is expected to be used in diamond field effect transistors (FETs), which have excellent device performance, including electrical properties and high-frequency characteristics.

[0003] As one of the methods for manufacturing diamond FETs, there is a self-alignment method as described below (see, for example, Non-Patent Documents 1 and 2). First, a diamond semiconductor layer (for example, a hydrogen-terminated diamond layer) is formed on the (001) of a diamond single crystal, gold is evaporated on the surface of the diamond semiconductor layer, a first resist is formed in the element region on the gold, and the gold is wet-etched using the first resist as a mask until the diamond semiconductor layer is exposed, and the first resist is removed. Next, a second resist having an opening for forming a gate electrode and a source electrode / drain electrode is formed, and the gold exposed from the opening of the second resist is wet-etched to form a source electrode / drain electrode made of gold that is widely separated from the opening. Next, the second resist is used as a mask as it is to form a gate electrode by evaporation of metal on the diamond semiconductor layer exposed from the opening of the second resist, and then the second resist and the metal layer thereon are lifted off. This completes a MESFET (Metal Semiconductor Field Effect Transistor) type diamond FET.

[0004] According to the above-mentioned self-aligned method, compared to a non-self-aligned method (see, for example, Patent Document 1) in which the gate electrode and the source electrode / drain electrode are formed using separate resists, the gate electrode can be positioned accurately relative to the positions of the source electrode / drain electrode, and this is advantageous for forming a gate electrode with a fine gate length in order to improve high-frequency characteristics. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent Publication No. 2020-161587 [Non-patent literature]

[0006] [Non-Patent Document 1] Carrier transport properties in diamond and its application to high frequency FETs, Kawaharada et al., Applied Physics, 73, 339-345, 2004-03-10, The Japan Society of Applied Physics [Non-Patent Document 2] Gate metal interface of hydrogen-terminated diamond FET, Kakazu et al., Surface Science Vol. 29, No. 3, pp. 159-163, 2008 Special feature "The forefront of diamond surface and interface research" (https: / / www.jstage.jst.go.jp / article / jsssj / 29 / 3 / 29_3_159 / _pdf / -char / ja) [Non-Patent Document 3] "High performance diamond MISFETs using CaF2 gate insulator", S. Miyamoto et al, Diamond and Related Materials, Volume 12, Issues 3-7, 2003(https: / / doi.org / 10.1016 / S0925-9635(03)00034-7) Summary of the Invention [Problem to be solved by the invention]

[0007] The following analysis is provided by the present inventors.

[0008] As the gate electrode is miniaturized, the contact of the gate electrode is reduced due to the influence of the surface morphology (shape, damage, poisoning, etc.) of the diamond semiconductor layer, making it difficult to obtain the desired electrical characteristics. The same can be said when forming a gate electrode miniaturized by the self-alignment method described in Non-Patent Documents 1 and 2. In order to ensure the contact of the gate electrode, it is possible to cover the entire diamond semiconductor layer including the gate electrode, source electrode, and drain electrode with a passivation film as in Non-Patent Document 3, but when the gate length is miniaturized to less than 100 nm, the contact of the gate electrode is significantly reduced, so it is not clear whether the contact of the gate electrode can be ensured even when covered with a passivation film. In Non-Patent Document 3, the gate length is 0.4 to 0.5 μm, and the reduction in contact between the gate electrode and the diamond semiconductor layer is not a problem in terms of scale.

[0009] The main object of the present invention is to provide a diamond FET, an electrical machine and an apparatus, and a method for manufacturing a diamond FET, which can contribute to ensuring contact of a gate electrode even when the gate length is miniaturized to less than 100 nm. [Means for solving the problem]

[0010] The diamond FET according to the first aspect comprises a diamond semiconductor layer, a gate electrode disposed on the diamond semiconductor layer and having a gate length of less than 100 nm, and a passivation film covering at least the element region of the diamond semiconductor layer including the gate electrode.

[0011] An electrical device according to a second aspect includes the diamond FET according to the first aspect.

[0012] The manufacturing method of the diamond FET according to the third aspect includes the steps of forming a gate electrode having a gate length of less than 100 nm on a diamond semiconductor layer, and forming a passivation film on the diamond semiconductor layer including the gate electrode. Effect of the Invention

[0013] The first to third aspects can contribute to ensuring contact between the gate electrode and the diamond semiconductor layer even when the gate length is miniaturized to less than 100 nm. [Brief description of the drawings]

[0014] [Figure 1] FIG. 1 is a partial cross-sectional view showing a schematic example of the configuration of a diamond FET according to embodiment 1. [Diagram 2] FIG. 2 is a partial cross-sectional view showing a schematic diagram of a modified example of the configuration of the diamond FET according to the first embodiment. [Diagram 3] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing a diamond FET according to a first embodiment of the present invention. [Figure 4] 4A to 4C are cross-sectional process diagrams following FIG. 3, which are schematic diagrams illustrating an example of a method for producing a diamond FET according to embodiment 1. [Diagram 5] 5A to 5C are cross-sectional process views following FIG. 4, which are schematic diagrams illustrating an example of a method for producing a diamond FET according to embodiment 1. [Figure 6] 6A to 6C are cross-sectional process views following FIG. 5, which are schematic diagrams illustrating an example of a method for producing a diamond FET according to embodiment 1. [Figure 7] 1 is a graph showing a schematic relationship between the drain voltage and the drain current for each predetermined gate voltage of the diamond FET according to embodiment 1. [Figure 8] 1 is a graph showing a schematic relationship between the gate voltage and the drain current when the drain voltage of the diamond FET according to embodiment 1 is −6 V. [Figure 9] FIG. 11 is a cross-sectional view showing a schematic example of the configuration of a diamond FET according to embodiment 2. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Hereinafter, the embodiments will be described with reference to the drawings. Note that when reference symbols are used in this application, they are intended to aid understanding only and are not intended to limit the present invention to the illustrated embodiments. In addition, the following embodiments are merely examples and do not limit the present invention.

[0016] [Form 1] The diamond FET according to the embodiment 1 will be described with reference to the drawings. Fig. 1 is a partial cross-sectional view showing a schematic example of the configuration of the diamond FET according to the embodiment 1. Fig. 2 is a partial cross-sectional view showing a schematic modification of the configuration of the diamond FET according to the embodiment 1.

[0017] The diamond FET 1 is a FET (field effect transistor) having a source electrode 12a, a drain electrode 12b, and a gate electrode 14a in an element region 2 on a diamond semiconductor layer 11 (hydrogen termination portion 11a in FIG. 1) (see FIG. 1). In the diamond FET 1, the diamond semiconductor layer 11 including the source electrode 12a, the drain electrode 12b, and the gate electrode 14a is covered with a passivation film 15. The diamond FET 1 can be incorporated into electrical machinery and equipment such as semiconductor devices, power electronics devices, high frequency devices, communication devices, sensing devices, automobiles, power transmission and distribution equipment, devices for harsh environments, devices for high temperature environments, devices for radiation environments, space equipment, and nuclear reactor equipment.

[0018] When the diamond FET 1 is applied to a MESFET (Metal Semiconductor Field Effect Transistor) without a gate insulating film as shown in FIG. 1, it can be configured as follows.

[0019] In the diamond FET 1 of FIG. 1, a diamond semiconductor layer 11 having a hydrogen-terminated portion 11a on its upper surface ((001) surface) is formed on a diamond substrate 10. In FIG. 1, the hydrogen-terminated portion 11a is configured to be present in the element region 2 and not present outside the element region 2. A gate electrode 14a is disposed near the center of the hydrogen-terminated portion 11a so as to be in Schottky contact with the hydrogen-terminated portion 11a. On both sides of the gate electrode 14a on the hydrogen-terminated portion 11a, a source electrode 12a and a drain electrode 12b are disposed so as to be in ohmic contact with the hydrogen-terminated portion 11a. The source electrode 12a and the drain electrode 12b are disposed at a distance from the gate electrode 14a. The diamond semiconductor layer 11 including the source electrode 12a, the drain electrode 12b, and the gate electrode 14a is covered with a passivation film 15. The passivation film 15 has contact holes 15a and 15b that lead to the source electrode 12a and the drain electrode 12b. Plugs 16a and 16b (may be contact pads) are embedded in the contact holes 15a and 15b. The plugs 16a and 16b may not be included. A contact hole (not shown) leading to the gate electrode 14a is formed in the passivation film 15 at a position different from the cross-sectional position of FIG. 1, and a plug (not shown) is embedded in the contact hole. A multilayer wiring structure (not shown) may be formed on the passivation film 15 including the plugs 16a and 16b, or pads (not shown, may be integrated with the plug) for the source electrode 12a, the drain electrode 12b, and the gate electrode 14a may be formed depending on the size of the diamond FET 1. The diamond FET 1 can be applied to a MISFET (Metal Insulator Semiconductor Field Effect Transistor) having a gate insulating film 13a between the gate electrode 14a and the hydrogen termination portion 11a as shown in FIG. 2, in addition to the MESFET as shown in FIG. 1, and may be applied to a MIMSFET (Metal Insulator Metal Semiconductor Field Effect Transistor; not shown).

[0020] The diamond substrate 10 is a substrate made of a diamond single crystal (see FIG. 1). For example, a high-temperature, high-pressure synthetic diamond single crystal substrate can be used as the diamond substrate 10. It is preferable to use a diamond substrate 10 having a surface roughness (in accordance with ISO4287) of 10 nm or less. If the surface roughness of the diamond substrate 10 exceeds 10 nm, it is preferable to polish the diamond substrate 10 so that the surface roughness is 10 nm or less. This has the advantage of reducing the surface roughness of the diamond semiconductor layer 11 synthesized on the diamond substrate 10 and improving the contact between the diamond semiconductor layer 11 and metals or insulating films.

[0021] The diamond semiconductor layer 11 is a layer that includes diamond and has a portion that functions as a semiconductor (see FIG. 1). The thickness of the diamond semiconductor layer 11 can be, for example, several μm or several tens of μm, but is not limited thereto. The diamond semiconductor layer 11 can be formed by chemical vapor deposition of diamond crystals (epitaxial diamond crystals) on the diamond substrate 10 using hydrogen and methane gas as raw materials, for example, using a microwave plasma CVD (Chemical Vapor Deposition) device. The diamond semiconductor layer 11 thus formed has a hydrogen termination portion 11a on the (001) plane (upper surface). The hydrogen termination portion 11a has a hole channel formed therein and exhibits p-type conduction. By subjecting the region of the hydrogen termination portion 11a other than the element region 2 to ozone treatment to remove hydrogen, the hydrogen termination portion 11a can be configured to be present in the element region 2 and not to be present in the region other than the element region 2. The diamond semiconductor layer 11 is not limited to having the hydrogen termination portion 11a, and may have a portion containing (doped or implanted with) impurities (e.g., boron, phosphorus, etc.) in diamond. Also, instead of having the diamond semiconductor layer 11 on the diamond substrate 10, for example, a free-standing diamond film may be obtained by chemical vapor deposition of diamond crystals on a seed substrate using hydrogen and methane gas as raw materials using a microwave plasma CVD device, and then removing the seed substrate.

[0022] The source electrode 12a and the drain electrode 12b are electrodes made of a predetermined metal (see FIG. 1). For example, Au can be used for the source electrode 12a and the drain electrode 12b. The source electrode 12a and the drain electrode 12b are formed on the diamond semiconductor layer 11. In order to ensure adhesion to the diamond semiconductor layer 11, it is preferable that the source electrode 12a and the drain electrode 12b are formed on the diamond semiconductor layer 11 in a state that the source electrode 12a and the drain electrode 12b have not been exposed to an etching agent, a resist remover, or oxygen plasma for resist ashing. The source electrode 12a and the drain electrode 12b are disposed so as to be in direct contact (ohmic contact) with the hydrogen termination portion 11a of the diamond semiconductor layer 11. The source electrode 12a and the drain electrode 12b can be formed, for example, by forming a metal layer (for example, by vapor deposition or sputtering) on ​​the diamond semiconductor layer 11, forming a resist for forming the source electrode / drain electrode on the metal layer, etching using the resist as a mask, and removing the resist. The source-drain distance L between the source electrode 12a and the drain electrode 12b is a distance between the source electrode 12a and the drain electrode 12b. SD Considering that the device is operated in a high frequency band (for example, a cutoff frequency of 50 to 100 GHz), the source-drain distance L is preferably less than 100 nm. SD The lower limit of the thickness of the source electrode 12a and the drain electrode 12b is the critical distance at which the electrode functions as a FET. The thickness of the source electrode 12a and the drain electrode 12b is preferably less than 100 nm in consideration of operation in a high frequency band, preferably less than 50 nm in consideration of obtaining desired RF (Radio Frequency) characteristics, and preferably less than 25 nm in consideration of operation in an even higher frequency band (for example, a cutoff frequency of more than 100 GHz). The lower limit of the thickness of the source electrode 12a and the drain electrode 12b is the critical film thickness (the same applies to other thicknesses for which no lower limit is specified).

[0023] The gate electrode 14a can be made of a metal film having a single layer structure or a laminate structure of any combination of Al, Au, Ti, Mo, Cr, Ru, Cu, Pb, Zn, or Pt. The gate electrode 14a can be made, for example, by forming a resist for gate electrode formation on the diamond semiconductor layer 11, forming (for example, by vapor deposition or sputtering) a metal film for the gate electrode 14a on the diamond semiconductor layer 11 by a self-alignment method using the resist as a mask, and then lifting off the resist and the metal film thereon. 2, when the gate insulating film 13a is formed between the gate electrode 14a and the hydrogen termination portion 11a, for example, an insulating film having a single layer structure of any of Al2O3, SiO2, HfO2, AlN, BN, Si3N4, SiON, Ta2O5, TiO2, WO3, CaF2, LaF3, and MgF2 or a laminated structure of any combination can be used for the gate insulating film 13a. In consideration of the combination with the passivation film 15 and the improvement of carrier mobility (60 to 3800 cm / Vs), an insulating film having a single layer structure of any of CaF2, LaF3, and MgF2 or a laminated structure of any combination can be used. In addition, in consideration of the improvement of carrier mobility (60 to 3800 cm / Vs), it is also useful to use an insulating film having a single layer structure of any of CaF2, LaF3, and MgF2 or a laminated structure of any combination depending on the application of the device utilizing the present invention. The gate insulating film 13a can be formed, for example, by forming an insulating film for the gate insulating film 13a by a CVD method using a predetermined source gas before forming a metal film for the gate electrode 14a, and lifting off the insulating film between the resist and the metal film during lift-off in the above-mentioned method for forming the gate electrode 14a. The thickness of the gate electrode 14a is desirably less than 100 nm, taking into account the size of the gate length.

[0024] The gate length, which is the width of the gate electrode 14a, is preferably less than 100 nm in order to improve frequency characteristics (shorten the travel time of carriers traveling through the channel), and is preferably less than 60 nm in consideration of operating at a higher frequency band (for example, a cutoff frequency of over 100 GHz), and is preferably less than 50 nm in consideration of obtaining desired RF (Radio Frequency) characteristics. The lower limit of the gate length is the limit length at which the gate electrode 14a functions as a FET. As the gate length becomes finer, the contact between the gate electrode 14a and the diamond semiconductor layer 11 decreases, and resistance components are generated or the element is easily broken and destroyed. Therefore, when the gate length is made less than 100 nm, it is preferable to cover the gate electrode 14a with a passivation film 15 as described below.

[0025] For the passivation film 15, an insulating film having a single layer structure or a laminate structure of any combination of Al2O3, SiO2, HfO2, AlN, BN, Si3N4, SiON, Ta2O5, TiO2, WO3, CaF2, LaF3, and MgF2 can be used, and in consideration of improving carrier mobility and processability, an insulating material containing F (fluorine), such as CaF2, LaF3, and MgF2, or any combination thereof, can be used. In order to prevent deterioration of electrical characteristics due to components such as ions, electrons, and radicals in the atmosphere, it is desirable for the passivation film 15 to cover and protect at least the entire element region 2. The thickness of the passivation film 15 is preferably 100 nm or more in consideration of ensuring contact between the gate electrode 14a and the diamond semiconductor layer 11, and between the source electrode 12a and the drain electrode 12b and the diamond semiconductor layer 11, and is preferably 300 nm or more in consideration of the flatness or flat processability of the upper surface of the passivation film 15.

[0026] The plugs 16a, 16b may be made of a metal, for example, Au, Ru, Al, Ti, Mo, Cu, Cr, Pb, Zn, Pt, or W, having a single layer structure or a layered structure of any combination thereof. It is preferable to use a metal different from the metal of the source electrode 12a and the drain electrode 12b in the layer in contact with the source electrode 12a and the drain electrode 12b.

[0027] The source electrode 12a and the drain electrode 12b have extensions 17a and 17b that extend (protrude) toward the gate electrode 14a beyond the end faces of the plugs 16a and 16b on the gate electrode 14a side. ext The length (from the end face of plugs 16a, 16b on the gate electrode 14a side to the tip face of extensions 17a, 17b) is preferably less than 200 nm in consideration of operation in the high frequency band, is preferably less than 100 nm in consideration of the balance with the thicknesses of source electrode 12a and drain electrode 12b when operating in the high frequency band, and is preferably less than 50 nm (or may be 0 nm) in consideration of obtaining desired RF characteristics.

[0028] Next, a method for producing a diamond FET according to embodiment 1 will be described with reference to the drawings. Fig. 3 to Fig. 6 are cross-sectional views illustrating steps of a method for producing a diamond FET according to embodiment 1.

[0029] First, a diamond semiconductor layer 11 is formed on a diamond substrate 10 (see FIG. 3(A)). The diamond semiconductor layer 11 can be formed by chemical vapor deposition of diamond crystals on the diamond substrate 10 using, for example, a microwave plasma CVD device with hydrogen and methane gas without added impurities as raw materials (volume ratio of methane to hydrogen is 0.5%). The diamond semiconductor layer 11 thus formed is hydrogen-terminated diamond having a hydrogen termination portion 11a on the (001) plane (upper surface).

[0030] Next, the metal layer 12 is formed on the diamond semiconductor layer 11 (see FIG. 3(B)). The metal layer 12 can be formed by depositing a predetermined metal (e.g., gold) on the diamond semiconductor layer 11 by, for example, RF sputtering.

[0031] Next, a resist 20 is formed to cover the element region 2 on the metal layer 12, and the metal layer 12 is etched using the resist 20 as a mask until the diamond semiconductor layer 11 is exposed (see FIG. 3(C)). The resist 20 can be formed by, for example, a lithography method. The etching of the metal layer 12 can be performed by, for example, using a wet etching agent.

[0032] Next, using the resist 20 as a mask, ozone treatment is performed to selectively eliminate the hydrogen termination 11a in the region other than the element region 2 in the diamond semiconductor layer 11 (see FIG. 3(D)). As a result, the region other than the element region 2 in the diamond semiconductor layer 11 (the region that has become the oxygen termination) becomes highly resistive, and the elements can be electrically insulated from each other.

[0033] Next, the resist (20 in FIG. 3(D)) on the metal layer 12 is removed (see FIG. 4(A)). The resist 20 can be removed, for example, with a resist remover or by ashing. After removing the resist 20, cleaning is performed.

[0034] Next, a resist 21 having openings 21a for forming a gate electrode and a source electrode / drain electrode is formed on the diamond semiconductor layer 11 including the metal layer 12 (see FIG. 4(B)). The resist 21 can be formed by, for example, a lithography method.

[0035] Next, the metal layer (12 in FIG. 4(B)) exposed from the opening 21a is etched using the resist 21 as a mask, and the metal layer 12 is separated into the source electrode 12a and the drain electrode 12b by under-etching, and then the distance between the end faces of the source electrode 12a and the drain electrode 12b is made wider than the width of the opening 21a by side-etching (see FIG. 4(C)). The metal layer 12 can be etched using, for example, a wet etching agent.

[0036] Next, the metal layer 14 and the gate electrode 14a are formed on the diamond semiconductor layer 11 including the resist 21 (see FIG. 5(A)). In other words, the gate electrode 14a is formed on the diamond semiconductor layer 11 in the region of the opening 21a of the resist 21 by the self-alignment process using the resist 21 as it is. The metal layer 14 and the gate electrode 14a can be formed by, for example, a sputtering method.

[0037] Next, the resist (21 in FIG. 5(A)) and the metal layer thereon (14 in FIG. 5(A)) are removed (see FIG. 5(B)). The resist 21 and the metal layer thereon 14 can be removed by lifting off using, for example, a resist remover. After removing the resist 21, cleaning is performed.

[0038] Next, a passivation film 15 is formed on the diamond semiconductor layer 11 including the source electrode 12a, the drain electrode 12b, and the gate electrode 14a by a CVD method using a predetermined raw material gas, and the upper surface of the passivation film 15 is planarized by a CMP (Chemical Mechanical Polishing) method. After that, a resist 22 having openings 22a and 22b for forming plugs (openings for the gate electrode are not shown) is formed on the planarized passivation film 15 (see FIG. 5(C)). The resist 21 can be formed by, for example, a lithography method. It is not essential to planarize the passivation film 15, and the planarization method is not limited to the CMP method.

[0039] Next, using the resist 22 as a mask, the passivation film 15 exposed from the openings 22a and 22b (openings for the gate electrodes are not shown) is etched until the source electrode 12a, the drain electrode 12b, and the gate electrode 14a appear, thereby forming contact holes 15a and 15b (contact holes on the gate electrodes are not shown) (see FIG. 6(A)). The etching of the passivation film 15 can be performed by, for example, a dry etching method.

[0040] Next, the resist (22 in FIG. 6(A)) on the passivation film 15 is removed (see FIG. 6(B)). The resist 22 can be removed using, for example, a resist remover. After removing the resist 22, cleaning is performed.

[0041] Next, a metal layer 16 (e.g., a metal layer having Au laminated on Ti) is formed on the passivation film 15 including the source electrode 12a, the drain electrode 12b, and the gate electrode 14a so as to fill the contact holes 15a and 15b (the contact holes on the gate electrode are not shown) (see FIG. 6(C)). The metal layer 16 can be formed by, for example, RF sputtering or vapor deposition.

[0042] Next, the metal layer 16 is polished and removed by CMP until the entire upper surface of the passivation film 15 appears, and the metal layer 16 is planarized to form plugs 16a and 16b (the plugs on the gate electrodes are not shown) (see FIG. 1). Then, depending on the size of the diamond FET 1, a multilayer wiring structure (not shown) may be formed on the passivation film 15 including the plugs 16a and 16b. When the plugs 16a and 16b having pads (not shown) on the upper portions are formed, the plugs 16a and 16b (contact pads) with pads can be formed by using lithography and etching. Also, the plugs 16a and 16b may not be present.

[0043] Next, the characteristics and state of the sample of the diamond FET according to the embodiment 1 will be described. Fig. 7 is a graph that shows the relationship between the drain voltage and the drain current for each predetermined gate voltage of the diamond FET according to the embodiment 1. Fig. 8 is a graph that shows the relationship between the gate voltage and the drain current of the diamond FET according to the embodiment 1 when the drain voltage is -6V.

[0044] A sample of the diamond FET according to the first embodiment (see FIG. 1) was obtained as follows. First, a diamond semiconductor layer 11 (100 nm thick) having a hydrogen termination 11a was formed (CVD method) on a diamond substrate 10 (4 mm×4 mm×0.5 mm). Next, a metal layer (Au, 90 nm thick; corresponding to 12 in FIG. 3(B)) for source / drain electrodes was formed on the hydrogen termination 11a (electron beam vacuum deposition apparatus: NPF023 manufactured by Eiko Engineering Co., Ltd. was used, deposition temperature was 100° C. or less), a resist (20 in FIG. 3(C); 200 μm square) was formed on the metal layer 12, and the metal layer 12 was etched using the resist 20 as a mask. Next, the resist (20 in FIG. 3(D)) was used as it was and ozone treatment was performed to selectively eliminate the hydrogen termination 11a in the diamond semiconductor layer 11 in the region other than the element region 2, and the resist was removed and washed. Next, a resist (corresponding to 21 in FIG. 4(B)) having an opening (width 80 nm) for forming a gate electrode and for forming a source electrode / drain electrode was formed on the diamond semiconductor layer 11 including the Au electrode (corresponding to 12 in FIG. 4(B)) for the source electrode / drain electrode, and the metal layer (corresponding to 12 in FIG. 4(B)) exposed from the opening was etched using the resist 21 as a mask to form the source electrode 12a and the drain electrode 12b. Next, a metal layer (14 in FIG. 5(A)) and a gate electrode 14a were formed (sputtered) on the diamond semiconductor layer 11 including the resist (corresponding to 21 in FIG. 5(A)) for forming a gate electrode and for forming a source electrode / drain electrode, and the resist 21 and the metal layer 14 thereon were lifted off and washed. Next, a passivation film 15 (thickness: 100 to 1000 nm) was formed on the diamond semiconductor layer 11 including the source electrode 12a, the drain electrode 12b, and the gate electrode 14a by a CVD method using a predetermined raw material gas, and the upper surface of the passivation film 15 was planarized by a CMP method. After that, a resist (corresponding to 22 in FIG. 5(C)) having an opening for forming a plug was formed on the planarized passivation film 15.Next, the passivation film 15 exposed from the openings was etched using a resist (corresponding to 22 in FIG. 6(A)) as a mask until the source electrode 12a, the drain electrode 12b, and the gate electrode 14a appeared, forming contact holes 15a and 15b (contact holes on the gate electrodes are not shown), and then the resist (corresponding to 22 in FIG. 6(A)) on the passivation film 15 was removed and washed. Next, a metal layer (corresponding to 16 in FIG. 6(C)) was formed (sputtered) on the passivation film 15 including the source electrode 12a, the drain electrode 12b, and the gate electrode 14a so as to fill the contact holes 15a and 15b (contact holes on the gate electrodes are not shown), and then the metal layer 16 was polished and removed by the CMP method until the entire top surface of the passivation film 15 appeared, thereby forming plugs 16a and 16b (plugs on the gate electrodes are not shown), and a sample was obtained. The thickness and length were measured using a scanning electron microscope (Hitachi High-Technologies: S-4800) and a stylus step gauge (KLA-Tencor: Alpha-Step IQ) as a supplementary measurement. Electrical properties were measured using a prober (Hybridge: ultra-high vacuum microprober: HUMP-100) and a semiconductor parameter analyzer (Agilent: B1505A).

[0045] The contact of the gate electrode of the above sample was measured once a day (re-contacting the measurement needle each time) for one month, and no peeling of the source electrode 12a, the drain electrode 12b, or the gate electrode 14a occurred. It was also confirmed that the contact stabilization effect of the gate electrode was high when the CaF2 thickness was 100 nm or more. It was also effective in the gate length range of less than 100 nm, which is essential for high-frequency operation in the millimeter wave band or higher (30 GHz or higher). Furthermore, the stabilization of the contact of the gate electrode was particularly remarkable in the gate length range of 50 to 60 nm, which is aimed at even higher frequency operation.

[0046] Regarding the mobility of the above sample, it was confirmed that the mobility of the above sample calculated from the current-voltage characteristics was more than twice as high as that of a diamond FET with an Al2O3 passivation film of the same design.

[0047] The electrical characteristics of the above sample were less affected by atmospheric components than those of a diamond FET with the same design but without a passivation film. In addition, when the sample was left for one month and then remeasured, the maximum current value, transconductance, threshold voltage, and leakage current all showed less than 40% change.

[0048] Drain current I for each given gate voltage (-2 to +3 V) D -Drain voltage V D The characteristics are shown in Figure 7. The drain current I D - Gate voltage V G The characteristics are shown in Figure 8. Note that the current values ​​in Figures 7 and 8 have been converted to absolute values.

[0049] According to the first embodiment, by covering the gate electrode 14a with the passivation film 15, it is possible to contribute to ensuring the contact between the gate electrode 14a and the diamond semiconductor layer 11 (the contact between the gate electrode 14a and the gate insulating film 13a when the gate insulating film 13a is present, and the contact between the gate insulating film 13a and the diamond semiconductor layer 11) even when the gate length is miniaturized to less than 100 nm. As a result, it is possible to improve the yield during manufacturing and to manufacture stably. In addition, it is possible to stabilize the electrical characteristics of the diamond FET 1 even after long-term use.

[0050] In addition, according to the embodiment 1, by covering the source electrode 12a and the drain electrode 12b with the passivation film 15, even if the thickness of the source electrode 12a and the drain electrode 12b is set to less than 100 nm in order to suppress the variation in the source-drain distance, the contact between the source electrode 12a and the drain electrode 12b and the diamond semiconductor layer 11 can be ensured, and the element destruction and the deterioration of the electrical characteristics can be prevented.

[0051] In addition, according to embodiment 1, the channel of the diamond semiconductor layer 11 is protected by the passivation film 15, so that the influence of components such as ions, electrons, and radicals in the air on the surface of the element region 2 (such as changes in structure and adsorbed substances) is reduced, the electrical characteristics can be stabilized, and durability can be improved.

[0052] In addition, according to the embodiment 1, the channel of the diamond semiconductor layer 11 is protected by a passivation film 15 made of a fluorine-based insulating material, thereby suppressing the effect of increased resistance in the channel portion, and improving reliability and electrical characteristics.

[0053] According to the first embodiment, in the MISFET structure, by covering the channel portion with the passivation film 15 and the gate insulating film 13a using a fluorine-based insulating material, it is possible to improve the mobility, transconductance, and high-frequency characteristics, as compared with the case where the channel portion is covered with a passivation film and a gate insulating film using an oxide film such as Al2O3. Note that, although it is possible to manufacture a highly reliable MISFET by using an oxide film such as Al2O3 for the gate insulating film and the passivation film, in the MISFET using an oxide film such as Al2O3, since the charge is close to the interface and thus the carrier mobility is low due to Coulomb scattering, it is difficult to improve the transconductance and the high-frequency characteristics.

[0054] In addition, according to the first embodiment, by using a fluorine-based insulating material for the passivation film 15, it is possible to improve electrical characteristics and safety compared to a process using an insulating material of an oxide film. In other words, in the case of an insulating material of an oxide film such as Al2O3, the surface of the channel part is significantly deteriorated by the ALD (Atomic Layer Deposition) process, but in the case of a fluorine-based insulating material, the film can be formed by resistance heating deposition, and the deterioration of the surface of the channel part can be suppressed. In addition, cleaning and wet etching by hydrofluoric acid treatment are very useful in the semiconductor device process, but such cleaning and processing are impossible for oxide films such as Al2O3, because they dissolve in hydrofluoric acid. On the other hand, in the case of an element using a fluorine-based passivation film, such cleaning and processing are possible, which expands the process options and enables more efficient element fabrication.

[0055] Furthermore, according to embodiment 1, the gate electrode 14a is formed using a self-alignment method in which the resist 21 used in forming the source electrode 12a and the drain electrode 12b is also used in forming the gate electrode 14a. This eliminates the need to align the gate electrode 14a with the source electrode 12a and the drain electrode 12b, and allows for the stable formation of a fine diamond FET 1 having a gate length of less than 100 nm.

[0056] Furthermore, according to embodiment 1, even if the diamond substrate 10 is small and difficult to handle, the self-alignment process can ensure yield, reliability, and adhesion between the gold and the diamond semiconductor layer, while providing a high-performance element that operates stably even in harsh environments such as a high-temperature environment of 400°C, a high-voltage environment of 500V, and a radiation environment.

[0057] [Form 2] The diamond FET according to the second embodiment will be described with reference to the drawings. Fig. 9 is a cross-sectional view showing a schematic example of the configuration of the diamond FET according to the second embodiment.

[0058] The diamond FET 1 includes a diamond semiconductor layer 11, a gate electrode 14a, and a passivation film 15. The gate electrode 14a is disposed on the diamond semiconductor layer 11 and has a gate length of less than 100 nm. The passivation film 15 covers at least the element region of the diamond semiconductor layer 11 including the gate electrode 14a.

[0059] According to the second embodiment, by covering the gate electrode 14a with the passivation film 15, it is possible to contribute to ensuring contact between the gate electrode 14a and the diamond semiconductor layer 11 even when the gate length is miniaturized to less than 100 nm.

[0060] Some or all of the above aspects may be described as follows, but are not limited to the following:

[0061] [Appendix 1] a diamond semiconductor layer; a gate electrode disposed on the diamond semiconductor layer and having a gate length of less than 100 nm; A passivation film covering at least an element region of the diamond semiconductor layer including the gate electrode; Diamond FET. [Appendix 2] 2. The diamond FET of claim 1, wherein the gate length is less than 60 nm. [Appendix 3] 3. The diamond FET of claim 1 or 2, wherein the gate length is less than 50 nm. [Appendix 4] 4. The diamond FET according to claim 1, wherein the passivation film is made of an insulating material containing fluorine. [Appendix 5] 5. A diamond FET according to any one of claims 1 to 4, wherein the passivation film is made of a single layer structure of any one of CaF2, LaF3, and MgF2, or a laminated structure of any combination thereof. [Appendix 6] 6. The diamond FET according to any one of claims 1 to 5, wherein the passivation film has a thickness of 100 nm or more. [Appendix 7] 7. The diamond FET according to any one of claims 1 to 6, wherein the gate electrode is in Schottky contact with the diamond semiconductor layer. [Appendix 8] 7. The diamond FET according to any one of claims 1 to 6, comprising a gate insulating film interposed between the gate electrode and the diamond semiconductor layer. [Appendix 9] 9. A diamond FET according to claim 8, wherein the gate insulating film has a single layer structure of any one of CaF2, LaF3, and MgF2, or a laminate structure of any combination thereof. [Appendix 10] The diamond FET according to any one of claims 1 to 9, comprising a source electrode and a drain electrode that are spaced apart on both sides of the gate electrode on the diamond semiconductor layer, have a thickness of less than 100 nm, and are covered with the passivation film. [Appendix 11] 11. The diamond FET according to any one of claims 1 to 10, having a carrier mobility of 60 cm / Vs or more and 3800 cm / Vs or less. [Appendix 12] An electrical device comprising the diamond FET according to any one of appendix 1 to 11. [Appendix 13] forming a gate electrode having a gate length of less than 100 nm on the diamond semiconductor layer; forming a passivation film on the diamond semiconductor layer including the gate electrode; A method for producing a diamond FET, comprising:

[0062] The disclosures of the above patent documents and non-patent documents are incorporated herein by reference and may be used as the basis or part of the present invention as necessary. Within the framework of the entire disclosure of the present invention (including the claims and drawings), modifications and adjustments of the forms and embodiments are possible based on the basic technical ideas. Furthermore, within the framework of the entire disclosure of the present invention, various combinations or selections (or non-selection as necessary) of various disclosed elements (including each element of each claim, each element of each form or embodiment, each element of each drawing, etc.) are possible. In other words, the present invention naturally includes various modifications and corrections that a person skilled in the art would be able to make in accordance with the entire disclosure, including the claims and drawings, and the technical ideas. Furthermore, with regard to the numerical values ​​and numerical ranges described in this application, any intermediate value, lower numerical value, and small range are considered to be described even if not specified. Furthermore, the disclosures of the above cited documents may be used in part or in whole in combination with the descriptions in this document as part of the disclosure of the present invention in accordance with the spirit of the present invention as necessary, and are considered to be included (belong) to the disclosures of this application. [Explanation of symbols]

[0063] 1. Diamond FET 2. Element Area 10 Diamond Substrate 11 Diamond semiconductor layer 11a Hydrogen termination 12 metal layer 12a Source electrode 12b Drain electrode 13 Insulating layer 13a Gate insulating film 14 Metal layer 14a Gate electrode 15 Passivation film 15a, 15b contact holes 16 metal layer 16a, 16b plug 17a, 17b extension part 20, 21, 22 Resist 21a, 22a, 22b opening

Claims

1. a diamond semiconductor layer; a gate electrode and a source electrode and a drain electrode disposed on both sides of the gate electrode at a predetermined interval on the diamond semiconductor layer via a hydrogen termination portion; the gate electrode has a gate length of less than 100 nm and a thickness of less than 100 nm; the source electrode and the drain electrode have a thickness of less than 100 nm; A diamond FET comprising a passivation film that covers the gate electrode (excluding a contact metal layer), openings on both sides of the gate electrode, and contact holes for the gate electrode, and also covers extensions of the source electrode and the drain electrode that extend from ends of the contact metal layer, The passivation film has a single layer structure of any one of CaF 2 , LaF 3 and MgF 2 or a laminated structure of any combination thereof, and has a thickness of 100 nm or more.

2. A diamond FET as described in claim 1, wherein the thickness of the source electrode and the drain electrode is less than 50 nm or less than 25 nm.

3. 2. The diamond FET according to claim 1, wherein the gate length is 50 to 60 nm.

4. The diamond FET of claim 1 , wherein the gate length is less than 50 nm.

5. A diamond FET as described in claim 1, wherein the distance between the source electrode and the drain electrode is less than 100 nm.

6. The diamond FET according to claim 1 , wherein the passivation film has a thickness of 300 nm or more.

7. A diamond FET as described in claim 1, wherein the contact metal layer is configured as a metal plug and the length of the extension portion is less than 50 nm.

8. A gate insulating film is provided between the gate electrode and the diamond semiconductor layer via a hydrogen termination portion, wherein the gate insulating film is made of CaF ２ , LaF ３ , MgF ２ 2. The diamond FET according to claim 1, which has a single layer structure of any one of the above or a laminated structure in which any combination thereof is used.

9. 2. The diamond FET according to claim 1, wherein the carrier mobility is 60 cm / Vs or more and 3800 cm / Vs or less.

10. The diamond FET according to claim 1, which operates stably even in a high temperature environment of 400° C., a high voltage environment of 500 V, or a radiation environment.

11. An electrical device comprising the diamond FET according to any one of claims 1 to 10.

12. forming a gate electrode having a gate length of less than 100 nm and a thickness of less than 100 nm on the diamond semiconductor layer via a hydrogen termination; forming a source electrode and a drain electrode each having a thickness of less than 100 nm on the hydrogen termination portion at both sides of the gate electrode with a predetermined distance therebetween; forming a passivation film on the diamond semiconductor layer so as to cover the gate electrode, the source electrode, the drain electrode, and an opening including the top and both sides of the gate electrode, and excluding the contact holes of each electrode; forming a metal layer so as to fill each of the contact holes; removing the metal layer so that the upper surfaces of the buried metal layer in each of the contact holes and the passivation film are flat; Including, The passivation film has a single layer structure of any one of CaF 2 , LaF 3 and MgF 2 or a laminated structure of any combination thereof, and is formed to a thickness of 100 nm or more. A method for manufacturing a diamond FET.

13. The method further comprises, before the step of forming the gate electrode, a step of forming a gate insulating film on the hydrogen termination portion of the diamond semiconductor layer, wherein the gate insulating film has a single layer structure of any of CaF 2 , LaF 3 and MgF 2 or a laminated structure of any combination thereof. The method for manufacturing a diamond FET according to claim 12.

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