Wiring board

Abstract

To provide a wiring board in which generation of a cracking is suppressed.SOLUTION: A wiring board 1 of an embodiment contains: an insulation layer 113; a conductor layer 123 containing a conductive pad P1; and a solder resist layer 114. The solder resist layer 114 includes an opening 114a that exposes a front surface directed to the side opposite to the insulation layer 113 in the conductive pad P1 and all of side surfaces of the conductive pad P1. An inner side surface of the opening 114a contains: a first part 114a1 containing a boundary a1 with the insulation layer 113; and a second part 114a2 on the side opposite to the insulation layer 113 of the first part 114a1. The second part 114a2 contains a part positioned at the innermost side of the opening 114a. The boundary a1 with the insulation layer 113 of the first part 114a1 is separated by a distance of 5 μm or more and 25 μm or less in a direction separating from the conductive pad P1 in a direction along the front surface of the insulation layer 113 from the part positioned at the innermost side of the opening 114a.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a wiring board. [Background technology]

[0002] Patent Document 1 discloses a wiring board in which a solder resist layer has an opening that exposes the entire surface and side of a conductor pad formed on an insulating layer, and the inner side of the opening is formed so as to expand toward the opposite side to the insulating layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2004-22713 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the wiring board disclosed in Patent Document 1, stress applied to the wiring board may be concentrated near the contact portion of the insulating layer that contacts the inner surface of the solder resist. This concentrated stress may cause cracks to occur in the insulating layer near the contact portion. [Means for solving the problem]

[0005] The wiring board of the present invention includes an insulating layer, a conductor layer formed on the surface of the insulating layer and including a conductor pad, and a solder resist layer formed on the surface of the insulating layer, the solder resist layer has an opening that exposes the entire surface of the conductor pad facing away from the insulating layer and the side surface of the conductor pad, the inner surface of the opening includes a first portion including a boundary with the insulating layer and a second portion of the first portion opposite the insulating layer, the second portion includes a portion located on the innermost side of the opening, and the boundary of the first portion with the insulating layer is spaced from the portion located on the innermost side of the opening by a distance of 5 μm or more and 25 μm or less in a direction along the surface of the insulating layer away from the conductor pad.

[0006] According to the embodiment of the present invention, it is possible to reduce stress concentration on the solder resist layer and stress applied to the insulating layer, and it is possible to suppress the occurrence of cracks in the solder resist layer and the insulating layer. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a cross-sectional view showing an example of a wiring board according to an embodiment of the present invention. [Diagram 2] An enlarged view of part II in FIG. [Diagram 3] FIG. 4 is an enlarged cross-sectional view showing another example of the wiring board according to an embodiment of the present invention. [Figure 4A] 5A to 5C are cross-sectional views showing an example of a manufacturing process of the wiring board according to the embodiment of the present invention. [Figure 4B] 5A to 5C are cross-sectional views showing an example of a manufacturing process of the wiring board according to the embodiment of the present invention. [Figure 4C] 5A to 5C are cross-sectional views showing an example of a manufacturing process of the wiring board according to the embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] A wiring board according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a cross-sectional view of a wiring board 1, which is an example of a wiring board according to an embodiment, and FIG. 2 shows an enlarged view of a part II of the wiring board 1 shown in FIG. 1, which is enclosed by a dashed line, turned upside down. Note that the drawings referred to below are not intended to show the exact ratio of each component, but are drawn so that the features of the embodiment can be easily understood. The wiring board 1 shown in the drawings is merely an example of the wiring board according to the present embodiment. The laminated structure of the wiring board according to the embodiment, and the number of each of the conductor layers and the insulating layers included in the wiring board 1 are not limited to the laminated structure of the wiring board 1 shown in the drawings, and the number of each of the conductor layers and the insulating layers included in the wiring board 1.

[0009] As shown in FIG. 1, the wiring board 1 has a first main surface 1F and a second main surface 1S, and includes a conductor layer 123 having a first conductor pad P1 (also simply referred to as a "conductor pad P1") and a solder resist layer 114 having an opening 114a on at least one side of the first main surface 1F and the second main surface 1S (the first main surface 1F side in the example of FIG. 1). In the wiring board 1 of this embodiment, the opening 114a of the solder resist layer 114 has a predetermined shape, and exposes the entire surface (upper surface) and side surface of the first conductor pad P1. In the example of FIG. 1, the wiring board 1 is a so-called multi-layer wiring board. However, the wiring board of the embodiment may be a so-called double-sided wiring board.

[0010] In the example of Figure 1, the wiring board 1 includes a core substrate 100, a first wiring structure 10 formed on one main surface (first surface 100F) of the core substrate 100, and a second wiring structure 20 formed on the other main surface (second surface 100S) of the core substrate 100.

[0011] In the description of the wiring board of this embodiment, the side farther from core substrate 100 is referred to as "top", "upper side", "outer side", or "outside", and the side closer to core substrate 100 is referred to as "bottom", "lower side", "inner side", or "inside". In addition, in each component, the surface facing the side opposite core substrate 100 is also referred to as the "top surface", and the surface facing core substrate 100 is also referred to as the "bottom surface".

[0012] In the example of Fig. 1, the core substrate 100 includes an insulating layer (core insulating layer) 101 and a conductor layer (core conductor layer) 102 formed on both sides of the core insulating layer 101. The core conductor layer 102 is patterned to have a predetermined conductor pattern. The core insulating layer 101 of the core substrate 100 is formed with a through-hole conductor 103 that connects the conductor pattern of the conductor layer 102 constituting the first surface 100F of the core substrate 100 with the conductor pattern of the conductor layer 102 constituting the second surface 100S. The inside of the cylindrical through-hole conductor 103 is filled with a resin body 104 containing any resin such as an epoxy resin.

[0013] In the example of FIG. 1, the first wiring structure 10 includes insulating layers and conductor layers alternately stacked on the first surface 100F of the core substrate 100. Specifically, the first wiring structure 10 has a multilayer wiring structure in which an insulating layer 111, a conductor layer 121, an insulating layer 112, a conductor layer 122, an insulating layer 113, a conductor layer 123, and a solder resist layer 114 are stacked in this order from the first surface 100F side of the core substrate 100. The insulating layers 111, 112, and 113 each include a via conductor 13. The conductor layers 121, 122, and 123 of the first wiring structure 10 are connected to each other by the via conductor 13. The first main surface 1F of the wiring substrate 1 is configured by the exposed surfaces of the outermost conductor layer 123, the insulating layer 113, and the solder resist layer 114 of the first wiring structure 10.

[0014] In the example of FIG. 1, the second wiring structure 20 includes insulating layers and conductor layers alternately stacked on the second surface 100S of the core substrate 100. Specifically, the second wiring structure 20 has a multilayer wiring structure in which an insulating layer 211, a conductor layer 221, an insulating layer 212, a conductor layer 222, an insulating layer 213, a conductor layer 223, and a solder resist layer 214 are stacked in this order from the second surface 100S side of the core substrate 100. The insulating layers 211, 212, and 213 each include a via conductor 23. The conductor layers 221, 222, and 223 of the second wiring structure 20 are each connected by the via conductor 23. The second main surface 1S of the wiring substrate 1 is configured by the exposed surfaces of the outermost conductor layer 223 and the solder resist layer 214 of the second wiring structure 20.

[0015] The conductor layers 121, 122, 123, 221, 222, 223, 102, the via conductors 13, 23, and the through-hole conductors 103 are formed using any metal such as copper or nickel, and may be composed of, for example, a metal foil such as copper foil, and / or a metal film formed by plating, sputtering, or the like. The conductor layers 121, 122, 123, 221, 222, 223, 102, the via conductors 13, 23, and the through-hole conductors 103 are shown as single-layer structures in FIG. 1, but may have a multi-layer structure having two or more metal layers. For example, the conductor layer 102 formed on the surface of the insulating layer 101 may include a metal foil (preferably copper foil), an electroless plating film (preferably electroless copper plating film), and an electrolytic plating film (preferably electrolytic copper plating film). Furthermore, the conductor layers 121, 122, 123, 221, 222, 223, the via conductors 13, 23, and the through-hole conductor 103 may include, for example, an electroless plated film and an electrolytic plated film.

[0016] Each of the conductor layers 121, 122, and 123 of the first wiring structure 10 is patterned to have a predetermined conductor pattern. In particular, the outermost conductor layer 123 of the first wiring structure 10 has a first conductor pad P1. The first conductor pad P1 can be electrically connected to a connection pad E1p of an external element (external element) E1 that can be connected to the wiring board 1 when the wiring board 1 is used. Also, in the example of FIG. 1, the outermost conductor layer 223 of the second wiring structure 20 has a second conductor pad P2. The second conductor pad P2 can be connected to a connection pad E2p of the external element E2.

[0017] The first conductor pad P1 may be electrically and mechanically connected to the connection pad E1p of the external element E1 by a bonding material such as solder. The external element E1 is not particularly limited, but may be, for example, a motherboard or any electronic component having a size larger than the wiring board 1. That is, in this case, the first surface 1F is a connection surface connected to the external element E1. The second conductor pad P2 may also be electrically and mechanically connected to the connection pad E2p of the external element E2 by a bonding material such as solder. The external element E2 is not particularly limited, but may be, for example, a semiconductor element or any electronic component having a size smaller than the wiring board 1. That is, in this case, the second surface 1S is a component mounting surface on which components are mounted. In the example of FIG. 1, the first conductor pad P1 is larger than either of the second conductor pads P2. There are cases where the external element E1 larger than the external element E2 and the wiring board 1 are firmly connected over a larger area.

[0018] In the example of FIG. 1, the first conductor pad P1 is connected to the conductor pattern of the core conductor layer 102 through a plurality of via conductors 13 arranged at overlapping positions in a plan view. Here, "plan view" means viewing an object with a line of sight parallel to a direction perpendicular to the first main surface 1F or the second main surface 1S of the wiring board 1. In other words, in the example of FIG. 1, the plurality of via conductors 13 arranged at overlapping positions in a plan view have a form of a so-called stacked via conductor. In this case, the conductor patterns of the conductor layers 102, 121, 122, and 123 can be connected to each other through a relatively short path. However, the first conductor pad P1 may be connected to the conductor pattern of the core conductor layer 102 through a plurality of via conductors 13 arranged at different positions in a plan view. Also, in the example of FIG. 1, the second conductor pad P2 is connected to the conductor pattern of the core conductor layer 102 through a via conductor 23.

[0019] Although not shown in FIG. 1, the first conductive pad P1 and the second conductive pad P2 may include a surface treatment layer on their surfaces. The surface treatment layer that may be formed on the surfaces of the first conductive pad P1 and the second conductive pad P2 is, for example, a coating formed by anticorrosion treatment and / or antirust treatment of the exposed parts of the first conductive pad P1 and the second conductive pad P2, respectively. The surface treatment layer may prevent corrosion or oxidation of the core parts of the conductive pads P1 and P2. The surface treatment layer may be, for example, a metal coating containing a metal different from that of the core parts of the conductive pads P1 and P2, or an organic coating containing an organic substance such as an imidazole compound. When the core parts of the conductive pads P1 and P2 are formed of copper, the surface treatment layer may be formed of nickel, palladium, silver, gold, or an alloy thereof, or solder. As shown in FIG. 2, a surface treatment layer P11 may be formed on the surface of the first conductive pad P1.

[0020] The insulating layers 101, 111, 112, 113, 211, 212, and 213 constituting the wiring board 1 may each be formed using an insulating resin such as an epoxy resin, a bismaleimide triazine resin (BT resin), or a phenol resin. Each of the insulating layers 101, 111, 112, 113, 211, 212, and 213 may contain a reinforcing material (core material) such as glass fiber and / or an inorganic filler such as silica or alumina. The solder resist layers 114 and 214 may each be formed using a photosensitive epoxy resin or polyimide resin, for example.

[0021] In the wiring board 1 of the embodiment, the solder resist layer 114 in the first wiring structure 10 has an opening 114a that exposes the first conductor pad P1. Specifically, the opening 114a exposes the surface (upper surface) of the first conductor pad P1 facing the opposite side to the insulating layer 113 and the entire side surface of the first conductor pad P1. That is, the entire upper surface and side surface of the first conductor pad P1 are exposed in the opening 114a. On the other hand, in the example of FIG. 1, the solder resist layer 214 in the second wiring structure 20 covers the peripheral portion of the second conductor pad P2, and the opening 214a exposes only the portion of the second conductor pad P2 other than the peripheral portion (part of the upper surface). However, the opening 214a of the solder resist layer 214 in the second wiring structure 20, like the opening 114a of the solder resist layer 114 in the first wiring structure 10, may also expose the surface (upper surface) of the second conductor pad P2 facing away from the insulating layer 213 and the entire side surface of the second conductor pad P2.

[0022] 2, in the wiring board 1 of the embodiment, the inner side surface of the opening 114a has a portion that extends in a direction expanding the opening 114a from the inside to the outside of the opening 114a near the insulating layer 113. Specifically, the boundary a1 between the inner side surface of the opening 114a and the insulating layer 113 is separated by a separation distance D1 from the innermost portion of the opening 114a on the inner side surface of the opening 114a in a direction away from the conductor pad P1 in a direction along the surface (upper surface) of the insulating layer 113. The separation distance D1 is 5 μm or more and 25 μm or less.

[0023] A portion of the inner surface of the opening 114a including the boundary a1 with the insulating layer 113 (e.g., portion 114a1 on the side closer to the insulating layer 113 on the inner surface as shown) is referred to as the first portion 114a1. The first portion 114a1 is, for example, a portion extending in a direction expanding the opening 114a from the inside to the outside of the above-mentioned opening 114a. A portion of the inner surface of the opening 114a that is farther from the insulating layer 113 than the first portion 114a1 (a portion of the first portion 114a1 opposite the insulating layer 113) and includes a portion located at the innermost side of the opening 114a (e.g., portion 114a2 on the side farther from the insulating layer 113 on the inner surface as shown) is referred to as the second portion 114a2.

[0024] When the solder resist layer 114 has an opening 114a that exposes the upper surface and side surface of the first conductive pad P1, the insulating layer 113 may be subjected to stress due to, for example, a difference in thermal expansion coefficient between the insulating layer 113 and the solder resist layer 114, or an external force applied to the first conductive pad P1 and the solder resist layer 114. In such a case, the stress may be concentrated at a contact point between the surface of the insulating layer 113 and the inner side surface of the opening 114a of the solder resist layer 114. The insulating layer 113 may not be able to withstand the concentrated stress and may crack at the contact point with the inner side surface of the opening 114a. In the wiring board of the embodiment, as described above, the boundary a1 with the insulating layer 113 is spaced a predetermined distance from the part of the second portion 114a2 located at the innermost position of the opening 114a in the direction away from the first conductive pad P1. In other words, the inner surface of opening 114a expands in the direction in which the opening widens in first portion 114a1 near insulating layer 113. This configuration may reduce stress that may be concentrated at the contact portion between the surface of insulating layer 113 and the inner surface of opening 114a of solder resist layer 114. Therefore, the occurrence of cracks in insulating layer 113 may be suppressed.

[0025] Furthermore, by setting the distance D1 from the innermost portion of the opening 114a in the second portion 114a2 of the boundary a1 with the insulating layer 113 in the direction along the upper surface of the insulating layer 113 to 5 μm or more and 25 μm or less, it is possible to reduce stress concentration on the solder resist layer 114. That is, in the wiring board of the present embodiment, the occurrence of cracks in the insulating layer 113 and the solder resist layer 114 on the insulating layer 113 can be suppressed.

[0026] A first portion 114a1 of the inner side including a boundary a1 with the insulating layer 113 is in contact with a surface (bottom surface of the opening 114a) of the insulating layer 113 exposed in the opening 114a at a first angle θ1. Specifically, the first angle θ1 is an angle between the upper surface of the insulating layer 113 and the inner side inside the opening 114a. The second portion 114a2 of the inner side includes the innermost portion of the opening 114a, which forms an angle with the upper surface of the insulating layer 113 at a second angle θ2. Specifically, in the illustrated example, it is the innermost portion of the opening 114a among the inner side of the opening 114a that has the second angle θ2 with the upper surface of the insulating layer 113. This innermost portion of the opening 114a extends linearly in the thickness direction of the solder resist layer 114 in the vicinity of the upper surface of the solder resist layer 114. The first angle θ1 is smaller than the second angle θ2. With this configuration, the stress on the insulating layer 113 and the solder resist layer 114 can be effectively relaxed, and the occurrence of cracks in the insulating layer 113 and the solder resist layer 114 can be effectively suppressed.

[0027] The first angle θ1 may have a value of, for example, 30° or more and 75° or less. For example, the first angle θ1 is more preferably 35° or more and 70° or less, and further preferably 45° or more and 70° or less. The second angle θ2 is, for example, approximately 90°. When the second angle θ2 is approximately 90°, it is considered that the connection between the first conductor pad P1 of the wiring board 1 and the connection pad E1p of the external element E1 (see FIG. 1) may be facilitated. The separation distance D1, the first angle θ1, and the second angle θ2 on the inner side surface of the opening 114a can be adjusted by, for example, exposure and development conditions in a photolithography process for forming the opening 114a in the solder resist layer 114, as described later.

[0028] 2, the first conductor pad P1 is connected to a via conductor 13 that connects the conductor layer 123 to the conductor layer 122 (see FIG. 1). In other words, in the example of FIG. 2, the first conductor pad P1 is a so-called via pad. By using the first conductor pad P1 as a via pad, an external force that may be applied to the first conductor pad P1 is distributed to the via conductor 13, which may further suppress the occurrence of cracks in the insulating layer 113. However, the first conductor pad P1 does not have to be connected to the conductor layer 122 via the via conductor 13, and the first conductor pad P1 may be a so-called independent pad.

[0029] As in the example shown in FIG. 3, the second angle θ2 that the innermost portion of the opening 114a, which is included in the second portion 114a2, has with the upper surface of the insulating layer 113 may be smaller than 90°.

[0030] Furthermore, first portion 114a, which contacts insulating layer 113 at first angle θ1, and the innermost portion of opening 114a in second portion 114a2 can be connected via a curved surface, as shown in Figures 2 and 3. With this configuration, the inner surface of opening 114a has a structure that is relatively unlikely to develop cracks due to stress concentration, and therefore, a wiring board with even higher reliability may be provided.

[0031] The wiring board of the embodiment can be manufactured by any general method for manufacturing a wiring board. With reference to Fig. 1 and Fig. 4A to Fig. 4C, the method for manufacturing the wiring board of the embodiment will be described by taking as an example the case where the wiring board 1 shown in Fig. 1 and Fig. 2 is manufactured. In Fig. 4A to Fig. 4C, a portion corresponding to the range of part II in Fig. 1 is shown upside down in an enlarged view, similar to Fig. 2.

[0032] First, a core substrate 100 as shown in Fig. 1 is prepared. In preparing the core substrate 100, for example, a double-sided copper-clad laminate having a metal foil provided on the surface of a core insulating layer 101 is prepared. A through hole 101h is formed in the double-sided copper-clad laminate by, for example, drilling, and an electroless plating film is formed on the inner wall of the through hole 101h and the upper surface of the metal foil, and an electrolytic plating film is formed on the electroless plating film using the electroless plating film as a power supply layer. A through-hole conductor 103 is formed on the inner wall of the through hole 101h.

[0033] The inside of the through-hole conductor 103 formed on the inner wall of the through hole 101h is filled with a resin body 104 by injecting, for example, an epoxy resin. After the filled resin body 104 is solidified, an electroless plating film and an electrolytic plating film are further formed on the upper surfaces of the resin body 104 and the electrolytic plating film. As a result, a conductor layer 102 having a five-layer structure of a metal foil, an electroless plating film, an electrolytic plating film, an electroless plating film, and an electrolytic plating film is formed on both sides of the insulating layer 101. Then, the conductor layer 102 is patterned by a subtractive method to obtain a core substrate 100 having a predetermined conductor pattern.

[0034] 1, a plurality of insulating layers 111, conductor layers 121, insulating layers 112, conductor layers 122, insulating layers 113, and conductor layers 123 are alternately laminated on the first surface 100F of the core substrate 100. A plurality of insulating layers 211, conductor layers 221, insulating layers 212, conductor layers 222, insulating layers 213, and conductor layers 223 are alternately laminated on the second surface 100S. For example, the insulating layer 111 can be formed by thermocompression bonding a film-like insulating resin onto the first surface 100F of the core substrate 100. For example, the insulating layer 211 can be formed by thermocompression bonding a film-like insulating resin onto the second surface 100S of the core substrate 100.

[0035] The conductor layers 121 and 221 may be formed by any conductor pattern forming method such as a semi-additive method. At the same time as the formation of the conductor layers 121 and 221, via conductors 13 and 23 are formed to fill the openings that may be formed in the insulating layers 111 and 211 by, for example, laser light. On the first surface 100F side of the core substrate 100, an insulating layer 112, a conductor layer 122, and an insulating layer 113 are further formed on the conductor layer 121 by the same method as the insulating layer 111 and the conductor layer 121. On the second surface 100S side of the core substrate 100, an insulating layer 212, a conductor layer 222, and an insulating layer 213 are further formed on the conductor layer 221 by the same method as the insulating layer 211 and the conductor layer 221. The outermost insulating layer 113 on the first surface 100F side and the outermost insulating layer 213 on the second surface 100S side are laminated.

[0036] Next, on the first surface 100F side of the core substrate 100, a conductor layer (outermost conductor layer) 123 including a first conductor pad P1 is formed on the surface of the outermost insulating layer 113. Also, on the second surface 100S side of the core substrate 100, a conductor layer (outermost conductor layer) 223 including a second conductor pad P2 is formed on the surface of the outermost insulating layer 213.

[0037] Next, a solder resist layer 114 is formed of a photosensitive film on the surfaces of the insulating layer 113 and the conductor layer 123. A solder resist layer 214 is formed of a photosensitive film on the surfaces of the insulating layer 213 and the conductor layer 223. The solder resist layers 114, 214 are made of, for example, a photosensitive epoxy resin, and may be formed by spray coating, curtain coating, lamination, or the like. As shown in FIG. 4B, the upper surface and side surfaces of the first conductor pad P1 are covered by the solder resist layer 114 formed on the insulating layer 113 and the conductor layer 123.

[0038] Next, openings 114a exposing the first conductor pads P1 are formed in the solder resist layer 114. Openings 214a exposing the second conductor pads P2 are formed in the solder resist layer 214. As shown in Fig. 4C, on the first surface 100F side of the core substrate 100, a film-like mask M having a predetermined pattern corresponding to the shape of the openings 114a (see Fig. 2) is disposed above the solder resist layer 114, and exposure light L is irradiated onto the solder resist layer 114 through the mask M.

[0039] In the exposure of the solder resist layer 114, the portion 114B far from the exposure light source (the portion of the solder resist layer 114 close to the insulating layer 113) may be hard to cure by exposure, compared to the portion 114U closer to the exposure light source (the portion of the solder resist layer 114 opposite the insulating layer 113). Due to this difference in the progress of cure by exposure depending on the part of the solder resist layer 114, in the subsequent development process, the portion 114B on the insulating layer 113 side may be removed more by the developer than the portion 114U on the opposite side to the insulating layer 113. By appropriately selecting the exposure conditions (e.g., the intensity of the exposure light L, the exposure time) and the development process conditions (e.g., the concentration of the developer, the development process temperature), the portion 114B on the insulating layer 113 side may be removed relatively more. As a result, the solder resist layer 114 having the opening 114a having the shape shown in FIG. 2 or FIG. 3 may be formed.

[0040] Although not shown, the openings 214a in the solder resist layer 214 on the second surface 100S side of the core substrate 100 are also formed by any general forming method such as exposure and development of a photosensitive film. When the solder resist layer 214 on the second surface 100S side of the core substrate 100 has a shape similar to that of the solder resist layer 114 on the first surface 100F side of the core substrate 100, the solder resist layer 214 can be formed by a method similar to the forming method of the solder resist layer 114 described above.

[0041] A surface treatment layer (surface treatment layer P11, see FIG. 4A) may be formed on the surface and side of the first conductor pad P1. For example, an organic coating containing an organic substance such as an imidazole compound may be formed by applying a heat-resistant organic substance by spraying. Alternatively, a metal coating may be formed by depositing a metal such as nickel, palladium, or gold by electroless plating. Similarly, a surface treatment layer may be formed on the surface and side of the second conductor pad P2.

[0042] 1 can be manufactured through the above manufacturing steps. In forming the openings 114a, 214a in the solder resist layers 114, 214, there may be cases where the exposure light L is directly irradiated onto the solder resist layers 114, 214 without using a mask.

[0043] The wiring board of the embodiment is not limited to the structure illustrated in each drawing, and the structure, shape, and material illustrated in this specification. For example, the first wiring structure and the second wiring structure constituting the wiring board may have any number of insulating layers and conductor layers. In addition, the wiring board is not limited to the embodiment having a core substrate, and may be a coreless substrate. [Explanation of symbols]

[0044] 1. Wiring board 100 core board 101 Core insulation layer 102 Core conductor layer 103 Through-hole conductor 111~113 Insulating layer 114 Solder resist layer 114a aperture 114a1 Part 1 114a2 2nd part 121~123 Conductor layer 13 Via conductor a1 boundary P1 Contact pad (first contact pad) θ1 1st angle θ2 2nd angle

Claims

1. An insulating layer; a conductor layer formed on a surface of the insulating layer and including a conductor pad; a solder resist layer formed on a surface of the insulating layer; A wiring board comprising: the solder resist layer has an opening that exposes a surface of the conductor pad facing away from the insulating layer and an entire side surface of the conductor pad; an inner surface of the opening includes a first portion including a boundary with the insulating layer and a second portion on an opposite side of the first portion from the insulating layer; the second portion includes an innermost portion of the opening, The boundary of the first portion with the insulating layer is spaced from the innermost portion of the opening by a distance of 5 μm or more and 25 μm or less in a direction along the surface of the insulating layer away from the conductor pad.

2. 2. The wiring board according to claim 1, wherein an angle at which the first portion contacts the surface of the insulating layer is smaller than an angle at which a portion of the second portion located at an innermost side of the opening contacts the surface of the insulating layer.

3. 3. The wiring board according to claim 2, wherein the angle at which the first portion contacts the surface of the insulating layer is not less than 30 degrees and not more than 75 degrees.

4. 3. The wiring board according to claim 2, wherein the second portion has an innermost portion of the opening that is inclined at an angle of approximately 90 degrees with respect to a surface of the insulating layer.

5. 2. The wiring board according to claim 1, wherein the first portion and the innermost portion of the opening in the second portion are connected via a curved surface.

6. 2. A wiring board as described in claim 1, wherein the wiring board has a first surface and a second surface which is the opposite surface to the first surface, the second surface being a component mounting surface on which components are mounted, and the conductor layer is formed on the first surface side.

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