Semiconductor device

Abstract

To provide a semiconductor device (RC-IGBT) having an IGBT region and a diode region that prevents an element from being destroyed due to current concentration during avalanche breakdown when high voltage is applied.SOLUTION: A p-type high concentration region (129) (second conductivity type high concentration region) having a higher concentration than a p-type (second conductivity type) anode layer (117) is formed in a part of the region of the p-type (second conductivity type) anode layer (117) in a diode region (103) that contacts an n-type (first conductivity type) drift layer (101), and an n-type high concentration region (130) (first conductivity type high concentration region) having a higher concentration than the n-type (first conductivity type) drift layer (101) is formed in a part of the n-type (first conductivity type) drift layer (101) that contacts the p-type high concentration region (129) (second conductivity type high concentration region).SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Electrification of various systems is being promoted in order to realize a low-carbon society as soon as possible. Electric vehicles are one representative example, and by replacing the propulsion system that was previously driven by an internal combustion engine with an electric motor and inverter, the environmental impact can be reduced. IGBT modules are generally used in inverters for driving motors, and it is important to improve their performance and reduce their cost.

[0003] An IGBT module is usually composed of an electric circuit including multiple semiconductor switching elements, and conventionally, one unit of circuit element is composed of an IGBT (Insulated Gate Bipolar Transistor) and an anti-parallel diode as a set. In addition, since the IGBT and the diode have different structures, they are formed as separate semiconductor substrates, i.e., separate semiconductor devices (semiconductor chips), and are electrically connected to each other and combined in the IGBT module.

[0004] However, in recent years, attention has been drawn to RC-IGBT (Reverse Conducting Insulated Gate Bipolar Transistor), which configures an IGBT and a diode on the same semiconductor substrate, i.e., the same semiconductor device (semiconductor chip). RC-IGBTs perform the functions of an IGBT, which is a switching element, and a diode, which is a freewheeling element, in a single semiconductor device (semiconductor chip), resulting in high area utilization efficiency and being an advantageous technology for reducing the cost of IGBT modules. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent Publication No. 2022-79281 [Patent Document 2] Patent Publication No. 2021-73714 Summary of the Invention [Problem to be solved by the invention]

[0006] Patent Documents 1 and 2 disclose RC-IGBTs in which an IGBT region and a diode region are formed in the same semiconductor device (semiconductor chip). According to the studies of the present inventors, the conventional RC-IGBTs disclosed in these patent documents have a problem in that the avalanche resistance of the element is low, and the element is destroyed when a high voltage is applied. [Means for solving the problem]

[0007] A semiconductor device (RC-IGBT) having an IGBT region and a diode region, which is one embodiment of the present invention, is characterized in that a p-type high-concentration region (second conductivity type high-concentration region) having a higher concentration than the p-type (second conductivity type) anode layer is formed in a part of the region of the p-type (second conductivity type) anode layer in contact with the n-type (first conductivity type) drift layer, and an n-type high-concentration region (first conductivity type high-concentration region) having a higher concentration than the n-type (first conductivity type) drift layer is formed in a part of the n-type (first conductivity type) drift layer in contact with the p-type high-concentration region (second conductivity type high-concentration region). Effect of the Invention

[0008] According to the present invention, in an RC-IGBT, it is possible to prevent the element from being destroyed due to current concentration during avalanche breakdown when a high voltage is applied. [Brief description of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. [Diagram 2] FIG. 1 is a cross-sectional view of a semiconductor device serving as a comparative example for explaining the effects of the present invention. [Diagram 3] FIG. 11 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention. [Figure 4] FIG. 11 is a cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same components are designated by the same reference numerals, and detailed description of overlapping parts will be omitted. EXAMPLES

[0011] FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention.

[0012] The semiconductor device shown in Fig. 1 is an RC-IGBT in which an IGBT region (102) and a diode region (103) are formed on a single semiconductor chip in which an n-type drift layer (101) is continuously formed in a semiconductor substrate. Although Fig. 1 shows only one of each of the above regions, an actual semiconductor device (RC-IGBT) has multiple of each of the above regions. Also, multiple IGBTs are formed in the IGBT region (102), and multiple diodes are formed in the diode region (103).

[0013] Impurity concentration: 1.5×10 14 cm -3 On the upper surface side of a semiconductor substrate constituted by an n-type drift layer (101), the surface between the multiple IGBTs in the IGBT region (102) is removed by etching to form first trench grooves (106), and the surface between the multiple diodes in the diode region (103) is removed by etching to form second trench grooves (118).

[0014] The surfaces (bottom and side surfaces) of the first trench (106) and the second trench (118) are covered with a first gate oxide film (107) and a second gate oxide film (119) formed by thermal oxidation of the upper surface of the semiconductor substrate.

[0015] In addition, after the thermal oxidation treatment of the upper surface side of the semiconductor substrate, a conductive film such as polysilicon is deposited over the entire upper surface side of the semiconductor substrate, and this conductive film is anisotropically etched using a mask covering the field plate formation portion, thereby forming a gate electrode (108) and a first field plate electrode (109) facing the semiconductor substrate with a first gate oxide film (107) interposed therebetween in the IGBT region (102), and forming a buried anode electrode (120) and a second field plate electrode (121) facing the semiconductor substrate with a second gate oxide film (119) interposed therebetween in the diode region (103).

[0016] Furthermore, by ion-implanting p-type impurities into the upper surface of the semiconductor substrate using a mask covering the first and second trench grooves (106, 118), an impurity concentration of 2.1×10 is implanted into the upper surface of the semiconductor substrate in each of the IGBT region (102) and the diode region (103). 17 cm -3 A p-type channel layer (104) and an anode layer (117) are formed. In addition, an n-type impurity is ion-implanted into the upper surface of the semiconductor substrate using a mask that covers the first trench groove (106) and the diode region (103), thereby driving the upper surface of the p-type channel layer (104) back and implanting an impurity concentration of 6.3×10 19 cm -3 In this embodiment, the impurity concentration of the p-type channel layer (104) and the anode layer (117) is the same, but the impurity concentration of each layer may be made different by separately implanting p-type impurity ions into the IGBT region (102) and the diode region (103).

[0017] After forming the channel layer (104), source layer (105), and anode layer (117), an insulating film is deposited over the entire upper surface of the semiconductor substrate to form a first insulating film (110) in the IGBT region (102) and a second insulating film (122) in the diode region (103).

[0018] Furthermore, by performing etching using a mask having openings above the channel layer (104) and first field plate electrode (109) in the IGBT region (102) and the anode layer (117) and second field plate electrode (121) in the diode region (103), a first emitter contact (111) that penetrates the first insulating film (110) and source layer (105) to reach the channel layer (104) and a second emitter contact (112) that penetrates the first insulating film (110) to reach the first field plate electrode (109) are formed in the IGBT region (102), and a first anode contact (123) that penetrates the second insulating film (122) to reach the anode layer (117) and a second anode contact (124) that penetrates the second insulating film (122) to reach the second field plate electrode (121) are formed in the diode region (103).

[0019] After forming the contacts (111, 112, 123, 124), a conductive film such as aluminum is deposited on the entire upper surface of the semiconductor substrate, and an emitter electrode (113) connected to the channel layer (104), source layer (105), and first field plate electrode (109) is formed in the IGBT region (102), and an anode electrode (125) connected to the anode layer (117) and second field plate electrode (121) is formed in the diode region (103). The emitter electrode (113) and anode electrode (125) are integrally formed from the same conductive film and are electrically connected, and a plurality of embedded anode electrodes (120) are connected to an emitter terminal (E). A plurality of gate electrodes (108) are connected to a gate terminal (G).

[0020] On the other hand, impurity concentration: 1.5×10 14 cm -3 The n-type drift layer (101) is formed on the lower surface of the semiconductor substrate. By ion-implanting n-type impurities from the lower surface of the entire surface of the semiconductor substrate, an impurity concentration of 1.9×10 is implanted on the lower surface of each of the IGBT region (102) and the diode region (103). 16 cm -3An n-type first buffer layer (114) and an n-type second buffer layer (126) are formed.

[0021] Furthermore, by ion-implanting p-type impurities into the lower surface of the semiconductor substrate using a mask covering the diode region (103), the lower surface of the n-type first buffer layer (114) in the IGBT region (102) is implanted back to the lower surface of the n-type first buffer layer (114) to obtain an impurity concentration of 1.4×10 17 cm -3 A p-type collector layer (115) is formed.

[0022] In addition, by ion-implanting n-type impurities into the lower surface of the semiconductor substrate using a mask covering the IGBT region (102), an n-type second buffer layer (126) in the diode region (103) is implanted at an impurity concentration of 3.0×10 19 cm -3 An n-type cathode layer (127) is formed on the semiconductor substrate.

[0023] After forming the above layers on the underside of the semiconductor substrate, a conductive film such as aluminum is deposited over the entire underside of the semiconductor substrate, and a collector electrode (116) connected to the collector layer (115) is formed in the IGBT region (102), and a cathode electrode (128) connected to the cathode layer (127) is formed in the diode region (103). The collector electrode (116) and the cathode electrode (128) are integrally formed from the same conductive film and are electrically connected to the collector terminal (C).

[0024] A feature of the present invention is that a p-type high concentration region (129) having a higher concentration than the anode layer (117) is formed in a part of the region of the anode layer (117) in the diode region (103) that contacts the drift layer (101), and an n-type high concentration region (130) having a higher concentration than the drift layer (101) is formed in a part of the diode region (103) that contacts the p-type high concentration region (129) of the drift layer (101).

[0025] The p-type high concentration region (129) and n-type high concentration region (130), which are characteristic features of the present invention, can be formed by implanting ions through the first anode contact (123) that penetrates the second insulating film (122) in the diode region (103) and reaches the anode layer (117).

[0026] In this embodiment, after forming the contacts (111, 112, 123, 124), a mask having an opening above the first anode contact (123) is used to first ion-implant a p-type impurity to obtain an impurity concentration of 2.1×10 17 cm -3 Impurity concentration higher than that of the anode layer (117): 7.4×10 18 cm -3 The p-type high concentration region (129) is formed in a part of the region where the anode layer (117) and the drift layer (101) contact each other below the first anode contact (123), and then n-type impurities are ion-implanted to form an impurity concentration of 1.5×10 14 cm -3 Impurity concentration higher than that of the n-type drift layer (101): 1.6×10 17 cm -3 The n-type high concentration region (130) is formed in a portion that contacts the p-type high concentration region (129) of the drift layer (101) below the first anode contact (123).

[0027] In this embodiment, the p-type high concentration region (129) and the n-type high concentration region (130) are formed by ion implantation through the first anode contact (123), so that each of the high concentration regions (129, 130) is formed only in a portion below the first anode contact (123), and the anode layer (117) and drift layer (101) that are not highly concentrated are left around the p-type high concentration region (129) and the n-type high concentration region (130).

[0028] FIG. 2 is a cross-sectional view of a semiconductor device serving as a comparative example for explaining the effects of the present invention.

[0029] In explaining the effects of the semiconductor device (RC-IGBT) according to the first embodiment of the present invention, the problems in the conventional technology will be explained using the RC-IGBT shown in FIG. 2 as a comparative example.

[0030] The configuration of the semiconductor device (RC-IGBT) of the comparative example shown in FIG. 2 is generally similar to that of the semiconductor device (RC-IGBT) of Example 1, but differs in that it does not have the p-type high concentration region (129) and n-type high concentration region (130) of the diode region (103) which are the characteristic configuration of the present invention that is included in FIG. 1.

[0031] In the comparative example shown in FIG. 2, consider the case where a voltage smaller than the threshold voltage is applied to the gate terminal (G) with the emitter terminal (E) as the reference, and a positive voltage is applied to the collector terminal (C) with the emitter terminal (E) as the reference.

[0032] In the IGBT region (102), the voltage of the gate terminal (G) is lower than the threshold voltage, so the IGBT is in the off state (voltage-retaining state). When a voltage is applied to the collector terminal (C), the pn junction formed by the p-type channel layer (104) and the n-type drift layer (101) is reverse-biased, and an electric field is applied to this pn junction. Since the n-type drift layer (101) has a lower impurity concentration than the p-type channel layer (104), the depletion layer mainly spreads from the pn junction to the n-type drift layer (101).

[0033] When the voltage applied to the collector terminal (C) increases and the electric field strength across the pn junction reaches a critical value, the element undergoes avalanche breakdown. However, in the comparative example shown in FIG. 2, the pn junction in the IGBT region (102) breaks down before the pn junction in the diode region (103) breaks down.

[0034] This is because the IGBT in the IGBT region (102) has a pnp transistor structure consisting of a p-type channel layer (104), an n-type drift layer (101), a buffer layer (114), and a p-type collector layer (115), and the avalanche voltage is reduced by the amplification of the leakage current. In other words, a small collector leakage current becomes a base current, which causes a positive feedback that further increases the collector leakage current, lowering the avalanche voltage.

[0035] On the other hand, the diode in the diode region (103) does not have a pnp structure since the cathode layer (127) on the back surface is n-type, resulting in a high avalanche voltage.

[0036] In the comparative example shown in FIG. 2, when an avalanche breakdown occurs in an IGBT in the IGBT region (102) described above, there is a problem that the element is often destroyed. This is because the leakage current-withstand voltage characteristics of the pnp transistor structure have a negative resistance region. In the negative resistance region, the holding withstand voltage decreases as the leakage current increases. Therefore, when an avalanche breakdown occurs in any IGBT in the IGBT region (102) and a leakage current flows, a positive feedback is generated in which the holding voltage of the current path decreases and the leakage current flows more and more. As a result, the leakage current flows in a concentrated manner in a local area in the IGBT region (102), leading to the destruction of the element.

[0037] As described above, the comparative example shown in FIG. 2 has a problem in that current concentrates in a part of the IGBT region (102) during avalanche breakdown of the element, causing destruction.

[0038] Returning to the semiconductor device (RC-IGBT) according to the first embodiment of the present invention shown in Fig. 1, the operation and effects of the present invention will be described. Unlike the comparative example shown in Fig. 2, the first embodiment shown in Fig. 1 has a p-type high concentration region (129) selectively formed under the anode layer (117) of the diode region (103), and an n-type high concentration region (130) selectively formed in the drift layer (101) so as to face the p-type high concentration region (129).

[0039] In Example 1 shown in FIG. 1, consider the case where a voltage smaller than the threshold voltage is applied to the gate terminal (G) with the emitter terminal (E) as the reference, and a positive voltage is applied to the collector terminal (C) with the emitter terminal (E) as the reference.

[0040] In the IGBT region (102), the voltage of the gate terminal (G) is lower than the threshold voltage, so the IGBT is in the off state (voltage-retaining state). When a voltage is applied to the collector terminal (C), the pn junction formed by the p-type channel layer (104) and the n-type drift layer (101) is reverse-biased, and an electric field is applied to this pn junction. Since the n-type drift layer (101) has a lower impurity concentration than the p-type channel layer (104), the depletion layer mainly spreads from the pn junction to the n-type drift layer (101).

[0041] At this time, in the diode region (103), a positive voltage is applied to the cathode electrode (128) with respect to the anode electrode (125), so that the pn junction formed by the p-type high concentration region (129) and the n-type high concentration region (130) is similarly reverse biased, and an electric field is applied to the pn junction, which maintains a withstand voltage. The depletion layer spreads from the pn junction to the n-type drift layer, but the impurity concentrations of the p-type high concentration region (129) and the n-type high concentration region (130) are high near the pn junction, so the gradient of the electric field becomes large. Therefore, the pn junction of the diode region (103) is in a state where a higher electric field is applied compared to the pn junction of the IGBT region (102). As a result, in the embodiment 1 shown in FIG. 1, the diode region (103) can be made to undergo avalanche breakdown before the IGBT region (102) undergoes avalanche breakdown.

[0042] In this way, even if avalanche breakdown occurs in the diode region (103), the element is unlikely to be destroyed. This is because the diode region (103) does not have a pnp structure because the cathode layer (127) on the back surface is n-type, and the leakage current-withstand voltage characteristics do not have a negative resistance region. Since there is no negative resistance region, the leakage current flows uniformly and is not locally concentrated in the diode region (103), so the element is unlikely to be destroyed.

[0043] In the semiconductor device (RC-IGBT) according to the first embodiment of the present invention shown in FIG. 1 , a p-type high concentration region (129) is formed only in a portion of the region of the anode layer (117) that contacts the drift layer (101) in the diode region (103), and an n-type high concentration region (130) is formed only in a portion of the drift layer (101) that contacts the p-type high concentration region (129). As a result, the anode layer (117) and the drift layer (101) that are not highly concentrated are left around the p-type high concentration region (129) and the n-type high concentration region (130), which has the effect of enabling the avalanche breakdown voltage of the diode region (103) to be adjusted without affecting the static operation of the diode in the diode region (103). EXAMPLES

[0044] Second Embodiment FIG. 3 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention.

[0045] The difference from the semiconductor device (RC-IGBT) according to the first embodiment of the present invention shown in FIG. 1 is that the opening width (W2) of the first anode contact (123) that penetrates the second insulating film (122) of the diode region (103) to reach the anode layer (117) is formed to be larger than the opening width (W1) of the first emitter contact (111) that penetrates the first insulating film (110) and source layer (105) of the IGBT region (102) to reach the channel layer (104).

[0046] As described above, the p-type high concentration region (129) and n-type high concentration region (130), which are characteristic features of the present invention, can be formed by ion implantation through the first anode contact (123) that penetrates the second insulating film (122) of the diode region (103) and reaches the anode layer (117). In this case, if the opening width (W2) of the first anode contact (123) is increased, the amount of impurities that form the p-type high concentration region (129) and n-type high concentration region (130) implanted into the anode layer (117) and drift layer (101) of the diode region (103) increases. As a result, the avalanche voltage of the diode region (103) decreases, thereby further enhancing the effects of the present invention. EXAMPLES

[0047] In the semiconductor device (RC-IGBT) according to the third embodiment of the present invention, the depth of the first anode contact (123) penetrating the second insulating film (122) of the diode region (103) to reach the anode layer (117) is made deeper than the depth of the first emitter contact (111) penetrating the first insulating film (110) and source layer (105) of the IGBT region (102) to reach the channel layer (104).

[0048] This also makes it possible to increase the amount of impurities forming the p-type high concentration region (129) and the n-type high concentration region (130) in the same manner as in the second embodiment of the present invention, thereby making it possible to further enhance the effects of the present invention. EXAMPLES

[0049] Fourth Embodiment FIG. 4 is a cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention.

[0050] The important aspect of the effect of the present invention is to lower the avalanche breakdown voltage in the diode region, where avalanche breakdown is less likely to occur, than in the IGBT region (102), where avalanche breakdown is more likely to occur. Therefore, measures other than the introduction of the p-type high concentration region (129) and n-type high concentration region (130) can be used.

[0051] In FIG. 4, the thickness of the second gate oxide film (119) sandwiched between the second field plate electrode (121) and the drift layer (101) in the diode region (103) is formed to be thicker than the thickness of the first gate oxide film (107) sandwiched between the first field plate electrode (109) and the drift layer (101) in the IGBT region (102).

[0052] The second gate oxide film (119) which is thicker than the first gate oxide film (107) shown in FIG. 4 can be formed, for example, by forming a first trench groove (106) and a second trench groove (118) in a semiconductor substrate, subjecting the upper surface side of the semiconductor substrate to a thermal oxidation treatment to form an oxide film on the surface of the semiconductor substrate, removing the oxide film except for the bottom surface of the second trench groove (118) by etching using a mask covering the bottom surface of the second trench groove (118), and again subjecting the upper surface side of the semiconductor substrate to a thermal oxidation treatment to make the oxide film at the bottom of the second trench groove (118) thicker than the oxide film at the bottom of the first trench groove (106).

[0053] The first field plate electrode (109) and the second field plate electrode (121) have the effect of relaxing the electric field in the drift layer (101) region that faces them via the first gate oxide film (107) and the second gate oxide film (119), thereby increasing the avalanche breakdown voltage. Since the effect of relaxing the electric field is greater when the gate oxide film is thinner, the configuration according to the fourth embodiment of the present invention can weaken the effect of the second field plate electrode (121) in the diode region (103), thereby reducing the avalanche breakdown voltage of the diode region (103).

[0054] In addition, in FIG. 4, the effects of the present invention can be achieved even without forming the p-type high concentration region (129) and the n-type high concentration region (130). However, by combining the two as shown in FIG. 4, the effects of the present invention can be further enhanced. [Explanation of symbols]

[0055] 101...Drift layer 102…IGBT area 103...Diode region 104…Channel layer 105…Sauce layer 106…First trench 107...First gate oxide film 108...Gate electrode 109...First field plate electrode 110...first insulating film 111…First emitter contact 112…Second emitter contact 113...Emitter electrode 24…First buffer layer 115…Collector layer 116…Collector electrode 117...Anode layer 118…Second trench 119...Second gate oxide 120...Buried anode electrode 121...Second field plate electrode 122...Second insulating film 1…First anode contact 124…Second anode contact 125...Anode electrode 126…Second buffer layer 127…Cathode layer 128…Cathode electrode 129...p-type high concentration region 130…n-type high concentration region

Claims

1. In a semiconductor device having an IGBT region and a diode region, a drift layer of a first conductivity type provided on a semiconductor substrate; a first conductivity type source layer provided on an upper surface side of the semiconductor substrate in the IGBT region; a second conductivity type channel layer provided between the source layer and the drift layer of the semiconductor substrate in the IGBT region; an emitter electrode in contact with the source layer and the channel layer; a gate electrode provided opposite the channel layer via a first gate oxide film; a collector layer of a second conductivity type provided on a lower surface side of the semiconductor substrate in the IGBT region; a collector electrode in contact with the collector layer; an anode layer of a second conductivity type provided on an upper surface side of the semiconductor substrate in the diode region; an anode electrode in contact with the anode layer; a cathode layer of a first conductivity type provided on a lower surface side of the semiconductor substrate in the diode region; a cathode electrode in contact with the cathode layer; a second conductivity type high concentration region having a higher concentration than the anode layer is formed in a part of a region of the anode layer in contact with the drift layer, a first conductivity type high concentration region having a higher concentration than the drift layer is formed in a portion of the drift layer in contact with the second conductivity type high concentration region.

2. the emitter electrode and the anode electrode are formed of the same first conductor film, the source layer, the channel layer and the anode layer are electrically connected to each other, 2. The semiconductor device according to claim 1, wherein the collector electrode and the cathode electrode are formed from a same second conductor film, and the collector layer and the cathode layer are electrically connected to each other.

3. 2. The semiconductor device according to claim 1, further comprising a buffer layer of the first conductivity type between the collector layer and the drift layer and between the drift layers.

4. an insulating film covering an upper surface side of the semiconductor substrate; an emitter contact provided on the insulating film in the IGBT region; an anode contact provided on the insulating film in the diode region; 4. The semiconductor device according to claim 1, wherein an opening width of the anode contact is larger than an opening width of the emitter contact.

5. 5. The semiconductor device according to claim 4, wherein the second conductivity type high concentration region and the first conductivity type high concentration region are formed below the anode contact.

6. an insulating film covering an upper surface side of the semiconductor substrate; an emitter contact provided on the insulating film in the IGBT region; an anode contact provided on the insulating film in the diode region; 4. The semiconductor device according to claim 1, wherein the anode contact has a depth greater than the emitter contact.

7. 7. The semiconductor device according to claim 6, wherein the second conductivity type high concentration region and the first conductivity type high concentration region are formed below the anode contact.

8. A plurality of IGBTs are formed in the IGBT region; A plurality of diodes are formed in the diode region; a first field plate electrode provided between the first gate oxide film and facing the drift layer between the IGBTs in the IGBT region; a second field plate electrode provided between the plurality of diodes in the diode region and facing the drift layer via a second gate oxide film; 4. The semiconductor device according to claim 1, wherein the thickness of the second gate oxide film is made thicker than the thickness of the first gate oxide film.

9. In a semiconductor device having an IGBT region in which a plurality of IGBTs are formed and a diode region in which a plurality of diodes are formed, a drift layer of a first conductivity type provided on a semiconductor substrate; a first field plate electrode provided between the drift layers between the IGBTs in the IGBT region and with a first gate oxide film interposed therebetween; a second field plate electrode provided between the plurality of diodes in the diode region and facing the drift layer via a second gate oxide film; 1. A semiconductor device comprising: a first gate oxide film and a second gate oxide film, the second gate oxide film being thicker than the first gate oxide film.

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