Power factor improvement circuit

Abstract

To provide a power factor improvement circuit in which a circuit component is miniaturized to reduce a circuit area, and which reduces a noise.SOLUTION: A power factor improvement circuit 1 of the present invention, provides external capacitors Cgc1 and Cgc2, which are different from a gate corrector inter parasitic capacitance of a transistor to between a gate and a corrector (or a drain) of a transistor constructing a totem pole circuit in a low-frequency switch element 11 having a high-frequency switch element 10 and the low-frequency switch element 11.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to power factor correction circuits. [Background technology]

[0002] In switching power supplies, power factor correction circuits are used to improve the power factor. Many power factor correction circuits handle large amounts of power, and so there is a need to suppress noise generation. For example, the bridgeless power factor correction converter described in Patent Document 1 shows a noise countermeasure for the power factor correction circuit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2015-192546 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the bridgeless power factor correction converter described in Patent Document 1, a separate parallel capacitor connected in parallel to the series diode is provided to suppress noise generation. However, when an external capacitor is connected between the collector-emitter (drain-source) of a transistor, a surge current flows through the external capacitor during switching, requiring a parallel capacitor with a high allowable current value, which increases the size of the circuit components and the circuit area, leaving room for improvement. Therefore, the present disclosure has an object to provide a power factor correction circuit that enables the miniaturization of circuit components and the reduction of circuit area. [Means for solving the problem]

[0005] One aspect of the power factor correction circuit according to the present disclosure includes a positive input line through which a positive signal of an AC signal is transmitted, a negative input line through which a negative signal of the AC signal is transmitted, a reactor provided on the positive input line, a first capacitor and a second capacitor connected in series between the positive input line and the negative input line at a position between an input end of the AC signal and the reactor, a positive output line through which one of the output signals is transmitted, a negative output line through which the other of the output signals is transmitted, a first transistor having a first terminal connected to the positive output line and a second terminal connected to the positive input line, a second transistor having a first terminal connected to the positive input line and a second terminal connected to the negative output line, and a first terminal the third transistor connected to the positive output line and having a second terminal connected to the negative input line; a fourth transistor having a first terminal connected to the negative input line and a second terminal connected to the negative output line; diodes connected in parallel to the first to fourth transistors, respectively, with cathodes connected to the first terminal and anodes connected to the second terminal; a drive signal generating unit that provides a drive signal from the first transistor to a gate of the fourth transistor, the drive signal controlling on-off switching of the transistor based on the AC signal; a third capacitor connected between the first terminal and gate of the third transistor; and a fourth capacitor connected between the first terminal and gate of the fourth transistor.

[0006] According to the power factor correction circuit of the above aspect, it is possible to reduce the size of the external capacitor, thereby reducing the circuit area, and also to reduce noise. Effect of the Invention

[0007] According to the present disclosure, a power factor correction circuit is provided that enables miniaturization of circuit components and reduction in circuit area. [Brief description of the drawings]

[0008] [Figure 1]1 is a circuit diagram of a power factor correction circuit according to a first embodiment. [Diagram 2] 4 is a timing chart for explaining the operation of an example (comparative example) in which an external capacitor is not provided in the power factor correction circuit according to the first embodiment; [Diagram 3] 4 is a timing chart illustrating an operation of the power factor correction circuit according to the first embodiment. [Figure 4] 4 is a circuit diagram for explaining a noise current that flows due to a voltage change in a third transistor of the power factor correction circuit according to the first embodiment. FIG. [Diagram 5] 4 is an equivalent circuit illustrating a path of a noise current that flows due to a voltage change of a third transistor in the power factor correction circuit according to the first embodiment. [Figure 6] 4 is a circuit diagram for explaining a noise current that flows due to a voltage change of a fourth transistor in the power factor correction circuit according to the first embodiment. FIG. [Figure 7] 4 is an equivalent circuit illustrating a path of a noise current that flows due to a voltage change of a fourth transistor in the power factor correction circuit according to the first embodiment. [Figure 8] 4 is a graph for explaining the relationship between the equivalent series resistance ESR of an external capacitor in the power factor correction circuit according to the first embodiment and loss. [Figure 9] FIG. 11 is a circuit diagram of a power factor correction circuit according to a second embodiment. [Figure 10] FIG. 11 is a circuit diagram of a first example of a power factor correction circuit according to a third embodiment. [Figure 11] FIG. 11 is a circuit diagram of a second example of a power factor correction circuit according to the third embodiment. [Figure 12] FIG. 11 is a circuit diagram of a power factor correction circuit according to a fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. In the following description, the same or corresponding elements are denoted by the same reference numerals, and redundant description will not be repeated.

[0010] <Embodiment 1> FIG. 1 shows a circuit diagram of a power factor correction circuit 1 according to the first embodiment. The power factor correction circuit 1 according to the first embodiment includes a high-frequency switch element 10, a low-frequency switch element 11, and a drive signal generating unit 12. The power factor correction circuit 1 according to the first embodiment converts power supplied by a power source 13 as an AC signal into a DC voltage and outputs the DC voltage by controlling transistors constituting a totem pole circuit in the high-frequency switch element 10 and the low-frequency switch element 11 by the drive signal generating unit 12. The power factor correction circuit 1 according to the first embodiment has a positive output line NLP and a negative output line NLN as output lines, and the voltage difference between the positive output line NLP and the negative output line NLN becomes the output voltage. In addition, in the first embodiment, a reactor Ld, a first capacitor (for example, a capacitor Cy1), and a second capacitor (for example, a capacitor Cy2) are provided in an input line that transmits an AC signal from the power source 13 to the high-frequency switch element 10 and the low-frequency switch element 11.

[0011] 1 also shows a frame ground FG, which is a reference potential provided around an electronic circuit board on which the power factor correction circuit 1 is configured. Furthermore, FIG 1 also shows a chassis parasitic capacitance Cpe formed between the frame ground FG and the positive output line NLP, and a chassis parasitic capacitance Cne formed between the frame ground FG and the negative output line NLN.

[0012] The configuration of the power factor correction circuit 1 according to the first embodiment will be described in more detail with reference to Fig. 1. The power source 13 outputs an AC signal, which is a power signal, to the high-frequency switch element 10 and the low-frequency switch element 11 via the positive input line ILP and the negative input line ILN. The positive input line ILP transmits the positive signal of the AC signal, and the negative input line ILN transmits the negative signal of the AC signal. The reactor Ld is inserted in series in the positive input line ILP. The capacitors Cy1 and Cy2 are connected in series between the positive input line ILP and the negative input line ILN at a position between the power source 13 connected to the input end of the AC signal and the reactor Ld.

[0013] The high-frequency switch element 10 includes a first transistor (for example, a transistor Q1), a second transistor (for example, a transistor Q2), and diodes D1 and D2. The transistors Q1 and Q2 are, for example, field effect transistors (FETs).

[0014] The transistor Q1 has a first terminal (e.g., drain) connected to the positive output line NLP and a second terminal (e.g., source) connected to the positive input line ILP. The transistor Q2 has a first terminal (e.g., drain) connected to the positive input line ILP and a second terminal (e.g., source) connected to the negative output line NLN. A drive signal generating unit 12 provides a drive signal for controlling the on / off switching of the transistors Q1 and Q2 to the control terminals (e.g., gates) of the transistors Q1 and Q2.

[0015] The diode D1 is connected in parallel with the transistor Q1. More specifically, the anode of the diode D1 is connected to the source of the transistor Q1, and the cathode of the diode D1 is connected to the drain of the transistor Q1. The diode D2 is connected in parallel with the transistor Q2. More specifically, the anode of the diode D2 is connected to the source of the transistor Q2, and the cathode of the diode D2 is connected to the drain of the transistor Q2.

[0016] The low-frequency switch element 11 includes a third transistor (e.g., transistor Q3), a fourth transistor (e.g., transistor Q4), diodes D3 and D4, a third capacitor (e.g., external capacitor Cgc1), and a fourth capacitor (e.g., external capacitor Cgc2). In the power factor correction circuit 1 according to the first embodiment, the transistors Q3 and Q4 are both bipolar transistors, and more preferably, IGBTs (insulated gate bipolar transistors).

[0017] The transistor Q3 has a first terminal (e.g., collector) connected to the positive output line NLP and a second terminal (e.g., emitter) connected to the negative input line ILN. The transistor Q4 has a first terminal (e.g., collector) connected to the negative input line ILN and a second terminal (e.g., emitter) connected to the negative output line NLN. A drive signal for controlling the on / off switching of the transistors Q3 and Q4 is provided from the drive signal generating unit 12 to the control terminals (e.g., gates) of the transistors Q3 and Q4.

[0018] The diode D3 is connected in parallel with the transistor Q3. More specifically, the anode of the diode D3 is connected to the emitter of the transistor Q3, and the cathode of the diode D3 is connected to the collector of the transistor Q3. The diode D4 is connected in parallel with the transistor Q4. More specifically, the anode of the diode D4 is connected to the emitter of the transistor Q4, and the cathode of the diode D4 is connected to the collector of the transistor Q4.

[0019] An external capacitor Cgc1 is connected between the collector and gate of the transistor Q3, and an external capacitor Cgc2 is connected between the collector and gate of the transistor Q4.

[0020] Here, in the power factor correction circuit 1 according to the first embodiment, the transistors Q3 and Q4 have parasitic capacitances, and noise occurs due to these parasitic capacitances, so these parasitic capacitances will also be described. As shown in FIG. 1, the transistor Q3 has a gate-collector parasitic capacitance Cp1 and a collector-emitter parasitic capacitance Cp2. The gate-collector parasitic capacitance Cp1 is a capacitance formed between the collector and gate of the transistor Q3. The collector-emitter parasitic capacitance Cp2 is a capacitance formed between the collector and emitter of the transistor Q3. In addition, the transistor Q4 has a gate-collector parasitic capacitance Cp3 and a collector-emitter parasitic capacitance Cp4. The gate-collector parasitic capacitance Cp3 is a capacitance formed between the collector and gate of the transistor Q4. The collector-emitter parasitic capacitance Cp4 is a capacitance formed between the collector and emitter of the transistor Q4. In the power factor correction circuit 1 according to the first embodiment, the capacitance values ​​of the external capacitors Cgc1 and Cgc2 are set to values ​​that are greater than 1 time and less than 40 times the gate-collector parasitic capacitances Cp1 and Cp3. It has been verified that setting the capacitance values ​​of the external capacitors Cgc1 and Cgc2 in this way provides a sufficient noise reduction effect in actual use.

[0021] The drive signal generating unit 12 detects the AC signal output by the power source 13, and outputs a drive signal for driving the transistors Q1 to Q4 according to the detected phase. In the power factor correction circuit 1 according to the first embodiment, the drive signal generating unit 12 sets the frequency of the drive signal provided to the transistors Q3 and Q4 to be approximately the same as the frequency of the AC signal, and sets the frequency of the drive signal provided to the transistors Q1 and Q2 to be 100 times or more the frequency of the AC signal. More specifically, the drive signal generating unit 12 controls the high-frequency switch element 10 with a drive signal having a frequency of about several tens of kHz, and controls the low-frequency switch element 11 with a drive signal having a frequency of 50 to 60 Hz.

[0022] Next, the operation of the power factor correction circuit 1 according to the first embodiment will be described. In the power factor correction circuit 1 according to the first embodiment, noise is reduced by providing external capacitors Cgc1 and Cgc2, but in order to explain the effect of providing external capacitors, a power factor correction circuit 1 not provided with external capacitors Cgc1 and Cgc2 will be described as a power factor correction circuit according to a comparative example. Below, first, the operation of the power factor correction circuit according to the comparative example will be described, and then the operation of the power factor correction circuit 1 according to the first embodiment will be described.

[0023] (Power factor correction circuit without an external capacitor: Comparison example) FIG. 2 shows a timing chart for explaining the operation of an example of the power factor correction circuit 1 according to the first embodiment, which is a comparative example, in which the external capacitors Cgc1 and Cgc2 are not provided. In FIG. 2, only the operation of the transistors Q3 and Q4, which are highly related to noise generation, is explained, but in the power factor correction circuit 1, the transistors Q1 and Q2 are also repeatedly turned on and off during normal operation. As shown in FIG. 2, the operation of the power factor correction circuit 1 is explained by dividing it into a first period TM1 to an eighth period TM8. After the eighth period TM8 has elapsed, the operation returns to the first period TM1 and is repeated. In addition, in the power factor correction circuit 1 according to the first embodiment, the voltages of the gate-emitter voltage VgeQ3 of the transistor Q3 and the gate-emitter voltage VgeQ4 of the transistor Q4 change due to a change in the voltage level of the drive signal output by the drive signal generating unit 12.

[0024] The first period TM1 is a period during which the gate-emitter voltage VgeQ4 of the transistor Q4 falls below the threshold voltage VthQ4 of the transistor Q4 due to the voltage level of the drive signal output by the drive signal generating unit 12, turning the transistor Q4 off, and the gate-emitter voltage VgeQ3 of the transistor Q3 begins to rise to the threshold voltage VthQ3 of the transistor Q3. Also, the gate-collector parasitic capacitance Cp1 of the transistor Q3 is fully charged. Therefore, the collector-emitter voltage VceQ4 of the transistor Q4 is the voltage difference VE between the negative output line NLN and the positive output line NLP.

[0025] The second period TM2 is a period during which the voltage level of the drive signal output from the drive signal generating unit 12 to the gate-emitter voltage VgeQ3 of the transistor Q3 reaches the threshold VthQ3 of the transistor Q3, and the transistor Q3 is turned on, causing a current to be supplied from the drive signal generating unit 12 to the gate-collector parasitic capacitance Cp1 of the transistor Q3. During this period, the gate-collector parasitic capacitance Cp1 of the transistor Q3 is discharged.

[0026] The third period TM3 is a period during which the discharge from the gate-collector parasitic capacitance Cp1 is completed and the drive signal generating unit 12 further increases the gate-emitter voltage VgeQ3. The drive signal generating unit 12 increases the gate-emitter voltage VgeQ3 to Vgon, which is a voltage that the drive signal generating unit 12 can output. At this time, since the gate-collector parasitic capacitance Cp1 has already been discharged, the gate-collector current IgcQ3 of the transistor Q3 does not flow, but the gate-collector voltage VgcQ3 of the transistor Q3 changes in synchronization with the change in the gate-emitter voltage VgeQ3.

[0027] The fourth period TM4 is a period during which the gate-emitter voltage VgeQ3 of the transistor Q3 is reduced and reaches the threshold voltage VthQ3 due to the voltage level of the drive signal output by the drive signal generating unit 12. During this period, the drive signal generating unit 12 charges the gate-collector parasitic capacitance Cp1, causing a gate-collector current IgcQ3 to flow.

[0028] Note that, in FIG. 2, an example is shown in which the threshold voltage VthQ3 when the gate-emitter voltage VgeQ3 is increased and the threshold voltage VthQ3 when the gate-emitter voltage VgeQ3 is decreased are the same for the transistor Q3; however, the threshold voltages VthQ3 when the gate-emitter voltage VgeQ3 is increased and decreased may be different.

[0029] The fifth period TM5 is a period during which the gate-emitter voltage VgeQ3 of the transistor Q3 falls below the threshold voltage VthQ3 of the transistor Q3 due to the voltage level of the drive signal output by the drive signal generating unit 12, so that the transistor Q3 is turned off, and the gate-emitter voltage VgeQ4 of the transistor Q4 rises toward the threshold voltage VthQ4 of the transistor Q4. In addition, the gate-collector parasitic capacitance Cp3 of the transistor Q4 is fully charged. Therefore, the collector-emitter voltage VceQ3 of the transistor Q3 becomes VE.

[0030] The sixth period TM6 is a period during which the voltage level of the drive signal output from the drive signal generating unit 12 to the gate-emitter voltage VgeQ4 of the transistor Q4 reaches the threshold VthQ4 of the transistor Q4, and the transistor Q4 is turned on, causing a current to be supplied from the drive signal generating unit 12 to the gate-collector parasitic capacitance Cp3 of the transistor Q4. During this period, the gate-collector parasitic capacitance Cp3 of the transistor Q4 is discharged.

[0031] The seventh period TM7 is a period in which the discharge from the gate-collector parasitic capacitance Cp3 is completed and the drive signal generating unit 12 further increases the gate-emitter voltage VgeQ4. The drive signal generating unit 12 increases the gate-emitter voltage VgeQ4 to Vgon. At this time, since the gate-collector parasitic capacitance Cp3 has already been discharged, the gate-collector current IgcQ4 of the transistor Q4 does not flow, but the gate-collector voltage VgcQ4 of the transistor Q4 changes in synchronization with the change in the gate-emitter voltage VgeQ4.

[0032] The eighth period TM8 is a period during which the gate-emitter voltage VgeQ4 of the transistor Q4 is lowered and reaches the threshold voltage VthQ4 due to the voltage level of the drive signal output by the drive signal generating unit 12. During this period, the gate-collector parasitic capacitance Cp3 is charged by the drive signal generating unit 12, so that the gate-collector current IgcQ4 flows. After the eighth period TM8, the operation returns to the first period TM1, and the operations from the first period TM1 to the eighth period TM8 are repeated.

[0033] Note that, in FIG. 2, an example is shown in which the threshold voltage VthQ4 when the gate-emitter voltage VgeQ4 is increased and the threshold voltage VthQ4 when the gate-emitter voltage VgeQ4 is decreased are the same for the transistor Q4, but the threshold voltages VthQ4 when the gate-emitter voltage VgeQ4 is increased and decreased may be different.

[0034] Here, in the power factor correction circuit according to the comparative example, when charging and discharging the gate-collector parasitic capacitance Cp1 and the collector-emitter parasitic capacitance Cp2, if the gain of the transistor is A, a mirror effect occurs in which the capacitance value of each parasitic capacitance appears to be (1+A) times larger when viewed from the drive signal generating unit 12. In the power factor correction circuit 1 according to the first embodiment, by providing the external capacitors Cgc1 and Cgc2, this mirror effect is further increased, the rise and fall times of the collector-emitter voltages VceQ3 and VceQ4 are also extended, and the slope of the voltages can be made gentler, thereby reducing noise.

[0035] (Power factor correction circuit with external capacitor) Next, the operation of the power factor correction circuit 1 according to the first embodiment will be described. Fig. 3 shows a timing chart for explaining the operation of the power factor correction circuit 1 according to the first embodiment. As shown in Fig. 3, in the power factor correction circuit 1 according to the first embodiment, external capacitors Cgc1 and Cgc2 are additionally provided compared to the comparative example, so that the Miller effect becomes even larger, and the durations of the second period TM2, fourth period TM4, sixth period TM6, and eighth period TM8 during which charging and discharging of the gate-collector parasitic capacitance are performed become longer.

[0036] In the power factor correction circuit 1 according to the first embodiment, a noise current Icom is generated during the fourth period TM4 and the eighth period TM8 in which the collector-emitter voltages VceQ3 and VceQ4 of the transistors Q3 and Q4 change, causing noise. Here, the path through which this noise current flows will be described.

[0037] First, Fig. 4 shows a circuit diagram for explaining a noise current flowing due to a voltage change of the transistor Q3 of the power factor correction circuit 1 according to the first embodiment. As shown in Fig. 4, in the power factor correction circuit 1 according to the first embodiment, when the collector-emitter voltage VceQ3 of the transistor Q3 changes, a noise current Icom flows in a loop through the transistor Q3, the negative input line ILN, the capacitor Cy1, the chassis (for example, the frame ground FG), the chassis parasitic capacitance Cpe between the chassis and the positive output line NLP, the positive output line NLP, and the transistor Q3. Here, Fig. 5 shows an equivalent circuit for explaining the path of the noise current flowing due to a voltage change of the transistor Q3 of the power factor correction circuit 1 according to the first embodiment.

[0038] In the equivalent circuit shown in Fig. 5, one end of a voltage source showing a voltage change of the collector-emitter voltage VceQ3 of the transistor Q3 is connected to the positive output line NLP. In addition, in the equivalent circuit, the other end of the voltage source showing a voltage change of the collector-emitter voltage VceQ3 of the transistor Q3 is connected to the frame ground FG via the chassis parasitic capacitance Cpe. Furthermore, in the equivalent circuit, a capacitor Cy1 is connected between the positive output line NLP and the frame ground FG.

[0039] 5, when the collector-emitter voltage VceQ3 of the transistor Q3 changes, the voltage applied to the capacitor Cy1 and the chassis parasitic capacitance Cpe changes, causing a noise current Icom to flow. If C is the combined capacitance of the external capacitor Cgc1 and the chassis parasitic capacitance Cpe, this noise current Icom is expressed as Icom=Cdv / dt, so it can be seen that the peak value can be suppressed by reducing the rate of change of the collector-emitter voltage VceQ3 of the transistor Q3 with respect to time.

[0040] Next, Fig. 6 shows a circuit diagram for explaining a noise current flowing due to a voltage change VceQ4 of the transistor Q4 of the power factor correction circuit 1 according to the first embodiment. As shown in Fig. 6, in the power factor correction circuit 1 according to the first embodiment, when the collector-emitter voltage VceQ4 of the transistor Q4 changes, a noise current Icom flows in a loop through the transistor Q4, the negative input line ILN, the capacitor Cy1, the chassis (for example, the frame ground FG), the chassis parasitic capacitance Cne between the chassis and the negative output line NLN, the negative output line NLN, and the transistor Q4. Here, Fig. 7 shows an equivalent circuit for explaining the path of the noise current flowing due to the voltage change of the transistor Q4 of the power factor correction circuit 1 according to the first embodiment.

[0041] In the equivalent circuit shown in Fig. 7, one end of a voltage source showing a voltage change of the collector-emitter voltage VceQ4 of the transistor Q4 is connected to the negative output line NLN. In addition, in the equivalent circuit, the other end of the voltage source showing a voltage change of the collector-emitter voltage VceQ4 of the transistor Q4 is connected to the frame ground FG via the chassis parasitic capacitance Cne. Furthermore, in the equivalent circuit, a capacitor Cy1 is connected between the negative output line NLN and the frame ground FG.

[0042] As shown in Figure 7, when the collector-emitter voltage VceQ4 of transistor Q4 changes, the voltage applied to capacitor Cy1 and chassis parasitic capacitance Cne changes, causing a noise current Icom to flow. If C is the combined capacitance of external capacitor Cgc2 and chassis parasitic capacitance Cne, this noise current Icom is expressed as Icom = Cdv / dt, so it can be seen that the peak value can be suppressed by lowering the rate of change of the collector-emitter voltage VceQ4 of transistor Q4 with respect to time.

[0043] In order to extend the mirror period between the gates and collectors of the transistors Q3 and Q4, it is preferable to set the capacitance values ​​of the external capacitors Cgc1 and Cgc2 to be large. Specifically, it is preferable that the capacitance values ​​of the external capacitors Cgc1 and Cgc2 are greater than 1 time and less than 40 times the capacitance values ​​of the gate-collector parasitic capacitances Cp1 and Cp3. By setting the capacitance values ​​of the external capacitors Cgc1 and Cgc2 at such values, it is possible to use capacitors with a lower withstand voltage than when an external capacitor is connected between the collectors and emitters of the transistors, which makes it possible to miniaturize the circuit components and reduce the circuit area.

[0044] According to the inventor's study, in the bridgeless power factor correction converter described in Patent Document 1, when trying to suppress the noise level to the same extent as the power factor correction circuit 1 according to the first embodiment, a separate parallel capacitor having a capacitance value about 2000 times larger than that of the external capacitors Cgc1 and Cgc2 according to the first embodiment is required. Therefore, in the power factor correction circuit 1 according to the first embodiment, it is sufficient to set the capacitance values ​​of the external capacitors Cgc1 and Cgc2 to be larger than 1 time but not larger than about 40 times the capacitance values ​​of the gate-collector parasitic capacitances Cp1 and Cp3, so that it is possible to use chip components instead of large components such as lead components, and the circuit components can be made smaller and the circuit area can be reduced.

[0045] In addition, in the power factor correction circuit 1 according to the first embodiment, the period during which the Miller effect occurs is extended by providing the external capacitors Cgc1 and Cgc2. As a result, in the power factor correction circuit 1 according to the first embodiment, the rate of change of the collector-emitter voltage decreases, making it possible to suppress the peak value of the noise current. <Embodiment 2>

[0046] In the second embodiment, another form of the power factor correction circuit 1 according to the first embodiment will be described. In the power factor correction circuit 1 according to the first embodiment, by providing external capacitors Cgc1 and Cgc2, the loss occurring in the transistors Q3 and Q4 corresponding to the external capacitors is different. This loss varies depending on the magnitude of the equivalent series resistance ESR of the external capacitor. Therefore, FIG. 8 shows a graph for explaining the relationship between the equivalent series resistance ESR of the external capacitor of the power factor correction circuit 1 according to the first embodiment and the loss. It can be seen from FIG. 8 that the loss is minimized when the equivalent series resistance ESR of the external capacitor becomes a specific value, and the loss increases even if the equivalent series resistance ESR increases or decreases from the specific value.

[0047] Therefore, if the equivalent series resistance ESR of the external capacitors Cgc1 and Cgc2 used does not match the minimum loss, connect external capacitors in parallel or add external resistors to adjust the equivalent series resistance ESR of the external capacitors Cgc1 and Cgc2 so that the loss is minimized.

[0048] Fig. 9 shows a circuit diagram of the power factor correction circuit 2 according to the second embodiment. The power factor correction circuit 2 shown in Fig. 9 is an example having a low-frequency switch element 21 in which a resistor Rgc1 is added in series to the external capacitor Cgc1 and a resistor Rgc2 is added in series to the external capacitor Cgc2.

[0049] Here, if the capacitance value of the equivalent series resistance of the external capacitor is determined in accordance with the loss, a problem occurs in which the capacitor must be unnecessarily large. However, in the power factor correction circuit 2 according to the second embodiment, it is possible to determine the capacitance value of the external capacitor and the magnitude of the equivalent series resistance ESR as separate parameters. That is, in the power factor correction circuit 2 according to the second embodiment, the capacitance values ​​of the external capacitors Cgc1 and Cgc2 are determined based on the magnitude of the noise reduction effect and the size of the circuit area, while the loss can be minimized by the resistors Rgc1 and Rgc2. As a result, in the power factor correction circuit 2 according to the second embodiment, it is possible to further reduce the capacitor size and the circuit area.

[0050] <Embodiment 3> In the third embodiment, two examples of other configurations of the power factor correction circuit 1 according to the first embodiment will be described.

[0051] (Embodiment 3: First Example) 10 shows a circuit diagram of a first example of a power factor correction circuit according to the third embodiment. The power factor correction circuit 3a as the first example has a low-frequency switch element 31 instead of the low-frequency switch element 11. The low-frequency switch element 31 employs field effect transistors (FETs) as the transistors Q3 and Q4 of the high-frequency switch element 10. In this way, even if field effect transistors are employed instead of bipolar transistors, it is possible to obtain the effect of reducing noise by lowering the rate of change of the drain-source voltage due to the external capacitors Cgc1 and Cgc2.

[0052] (Embodiment 3: Second Example) Next, FIG. 11 shows a circuit diagram of a second example of the power factor correction circuit according to the third embodiment. The power factor correction circuit 3b of the second example has a high-frequency switch element 30 instead of the high-frequency switch element 10. The high-frequency switch element 30 has a totem pole circuit with a greater number of stages than the high-frequency switch element 10. Changing the configuration of the high-frequency switch element does not affect the low-frequency switch element 11, and the high-frequency switch element 10 may have the same configuration as the high-frequency switch element 30, or may have various modifications. Changing the configuration of the high-frequency switch element in this way does not affect the noise reduction effect of the low-frequency switch element 11. Note that, in the circuit diagram of the second example shown in FIG. 11, an example in which the totem pole circuit has two stages is shown, but the number of stages may be two or more. <Fourth embodiment>

[0053] In the fourth embodiment, another form of the power factor correction circuit 1 according to the first embodiment will be described. FIG. 12 shows a circuit diagram of the power factor correction circuit 4 according to the fourth embodiment. The power factor correction circuit 4 according to the fourth embodiment is obtained by adding an additional circuit 14 to the power factor correction circuit 1 according to the first embodiment. The additional circuit 14 is provided, for example, between an input terminal of an AC signal (for example, a power source 13) and the capacitors Cy1 and Cy2. The additional circuit 14 is, for example, at least one of a noise filter circuit and an impedance adjustment circuit. Furthermore, the capacitors Cy1 and Cy2 may be part of the noise filter circuit or the impedance adjustment circuit.

[0054] In the power factor correction circuit 4 according to the fourth embodiment, a noise filter circuit and an impedance adjustment circuit are employed as the additional circuit 14, so that the noise level can be further suppressed.

[0055] The present disclosure is not limited to the above-described embodiment, and can be modified as appropriate without departing from the spirit and scope of the present disclosure. [Explanation of symbols]

[0056] 1, 2, 3a, 3b, 4...power factor improvement circuit, 10, 30...high frequency switch element, 11, 21, 31...low frequency switch element, 12...drive signal generating unit, 13...power source, 14...additional circuit, Q1 to Q4...transistors, D1 to D4...diodes, Cgc1, Cgc2...external capacitor, Co...output capacitor, Ld...reactor

Claims

1. A positive input line through which a positive signal of an AC signal is transmitted; a negative input line through which a negative signal of the AC signal is transmitted; A reactor provided on the positive input line; a first capacitor and a second capacitor connected in series between the positive input line and the negative input line at a position between the input end of the AC signal and the reactor; a positive output line through which one of the output signals is transmitted; a negative output line to which the other of the output signals is transmitted; a first transistor having a first terminal connected to the positive output line and a second terminal connected to the positive input line; a second transistor having a first terminal connected to the positive input line and a second terminal connected to the negative output line; a third transistor having a first terminal connected to the positive output line and a second terminal connected to the negative input line; a fourth transistor having a first terminal connected to the negative input line and a second terminal connected to the negative output line; a diode connected in parallel to each of the first to fourth transistors, the diode having a cathode connected to the first terminal and an anode connected to the second terminal; a drive signal generating unit that provides drive signals to gates of the first transistor to the fourth transistor, the drive signals controlling on-off switching of the transistors based on the AC signal; a third capacitor connected between the first terminal and a control terminal of the third transistor; a fourth capacitor connected between the first terminal and a control terminal of the fourth transistor.

2. the third capacitor has a capacitance value greater than 1 and less than 40 times a parasitic capacitance between the first terminal and the gate of the third transistor; 2. The power factor correction circuit according to claim 1, wherein the fourth capacitor has a capacitance value greater than 1 time and less than 40 times a parasitic capacitance between the first terminal and the gate of the fourth transistor.

3. 2. The power factor correction circuit according to claim 1, further comprising: a first resistor connected in series with the third capacitor; and a second resistor connected in series with the fourth capacitor.

4. an additional circuit provided between the input terminal for the AC signal and the first and second capacitors; 2. The power factor correction circuit according to claim 1, wherein the additional circuit is at least one of a noise filter circuit and an impedance adjustment circuit.

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