Automatic testing device and interface device therefor

Abstract

To provide an interface device with which high-speed devices can be tested with high accuracy.SOLUTION: An interface device 200 is installed between a test head 130 and a DUT 1. A socket board 210 includes a socket 220 to which the DUT 1 is attached, and a socket PCB 230 to which the socket 220 is mounted. A plurality of surface electrodes 232a for high-speed signals are formed on a first side S1 of the socket PCB 230. A plurality of reverse-side electrodes 234a for high-speed signals are formed on a second side S2 of the socket PCB 230 at the same positions as the plurality of surface electrodes 232a in a plan view of the socket PCB 230. A via hole 236 penetrates the socket PCB 230 and electrically connects the corresponding surface electrode 232a and reverse-side electrode 234a.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to an interface device for automatic test equipment. [Background technology]

[0002] Automatic test equipment (ATE) is used to test various semiconductor devices such as memories and CPUs (Central Processing Units). The ATE supplies test signals to the semiconductor device to be tested (hereafter referred to as the device under test (DUT)), measures the response of the DUT to the test signals, and judges the quality of the DUT or identifies defective parts.

[0003] 1 is a block diagram of a conventional ATE 10. The ATE 10 includes a tester (also called a tester main body) 20, a test head 30, an interface device 40, and a handler 50.

[0004] The tester 20 comprehensively controls the ATE 10. Specifically, the tester 20 executes a test program, controls the test head 30 and the handler 50, and collects measurement results.

[0005] The test head 30 includes hardware that generates a test signal to be supplied to the DUT 1 and detects a signal (called a device signal) from the DUT. Specifically, the test head 30 includes pin electronics (PE) 32, a power supply circuit (not shown), and the like. The PE 32 is an ASIC (Application Specific IC) including a driver, a comparator, and the like. Conventionally, the PE 32 has been mounted on a printed circuit board called a PE board 34 and housed inside the test head 30.

[0006] The interface device 40 is also called a HIFIX, and relays an electrical connection between the test head 30 and the DUT 1. The interface device 40 includes a socket board 42. The socket board 42 is provided with a plurality of sockets 44, enabling simultaneous measurement of a plurality of DUTs 1. In the case of an ATE that performs wafer-level testing, a probe card is used instead of the socket board 42.

[0007] A plurality of DUTs 1 are loaded into the plurality of sockets 44 by the handler 50, and the DUTs 1 are pressed against the sockets 44. After the test is completed, the handler 50 unloads the DUTs 1, and separates non-defective products from defective products as necessary.

[0008] The interface device 40 includes a socket board 42 and a plurality of cables 46 that connect the test head 30. A test signal generated by the PE 32 is transmitted to the DUT 1 via the cable 46, and a device signal generated by the DUT 1 is transmitted to the PE 32 via the cable 46. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] JP 2008-76308 A [Patent Document 2] International Publication No. WO2009-034641 [Patent Document 3] JP 2009-036602 A [Patent Document 4] JP 2008-078408 A Summary of the Invention [Problem to be solved by the invention]

[0010] In recent years, the speed of DRAM (Dynamic Random Access Memory) has been increasing. The GDDR (Graphics Double Data Rate) memory installed in graphic boards has achieved a transmission speed of 21 Gbps in the GDDR6X standard by using the NRZ (Non Return to Zero) method.

[0011] The next generation GDDR7 will use PAM4 (Pulse Amplitude Modulation 4) and will increase the transmission speed to 40Gbps. The NRZ method is also becoming faster every year, and in the next generation, it will be increased to about 28Gbps.

[0012] When the transmission speed exceeds 20 Gbps, it becomes difficult to perform accurate measurements using memory testers that use conventional architectures. Currently, there are no commercially available ATEs that can accurately measure high-speed memories of 28 Gbps or 40 Gbps.

[0013] The present disclosure has been made in this context, and one of its exemplary purposes is to provide an interface apparatus and an automatic test apparatus capable of testing high-speed devices with high accuracy. [Means for solving the problem]

[0014] An interface device according to an embodiment of the present disclosure is provided between a test head and a device under test (DUT). The interface device includes a socket board having a socket on which the DUT is attached and a multilayer printed circuit board on which the socket is mounted. The multilayer printed circuit board includes a plurality of high-speed signal front electrodes formed on a first surface of the multilayer printed circuit board and electrically contacting a plurality of pins of the socket through which a high-speed signal passes, a plurality of high-speed signal back electrodes formed on a second surface of the multilayer printed circuit board at the same positions as the plurality of high-speed signal front electrodes when the multilayer printed circuit board is viewed in plan, and a plurality of high-speed signal via holes penetrating the multilayer printed circuit board, each of which electrically connects a corresponding high-speed signal front electrode and a corresponding high-speed signal back electrode.

[0015] Any combination of the above components, or mutual substitution of components or expressions between methods, devices, etc. are also valid aspects of the present invention. Effect of the Invention

[0016] Certain aspects of the present disclosure enable production testing of high speed devices. [Brief description of the drawings]

[0017] [Figure 1] FIG. 1 is a block diagram of a conventional ATE. [Diagram 2] FIG. 1 illustrates an ATE according to an embodiment. [Diagram 3] 1 is a cross-sectional view of an interface device according to one embodiment. [Figure 4] FIG. 2 is a perspective view of the socket PCB. [Diagram 5] FIG. 2 is a perspective view of a connection means for high speed signals; [Figure 6] 11 is a cross-sectional view of an interface device according to a first modified example. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] (Overview of the embodiment) A summary of some exemplary embodiments of the present disclosure will be described. This summary is intended to provide a simplified overview of some concepts of one or more embodiments for a basic understanding of the embodiments as a prelude to the detailed description that follows, and is not intended to limit the scope of the invention or disclosure. This summary is not intended to be an exhaustive overview of all possible embodiments, nor is it intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may be used to refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed in this specification.

[0019] In order to realize an ATE capable of testing ultra-high-speed memory devices, it is necessary to minimize the transmission distance between the signal source (driver) and the DUT. Conventionally, a motherboard (MB) using a coaxial cable was used to transmit signals between the pin electronics board (PE) and the DUT, but there were many signal degradation factors such as transmission loss of the coaxial cable of several tens of centimeters and the transmission loss of the connector required to connect the coaxial cable to the board, and signal reflection due to mode conversion at the connection point of the transmission medium such as the wiring lead from the pin electronics IC on the board to the connector, which was disadvantageous for accurate transmission of high-speed signals. This disclosure is based on such knowledge. In this disclosure, we propose a method that enables transmission of high-speed signals by reducing the loss in the transmission path.

[0020] An interface device according to one embodiment is provided between a test head and a device under test (DUT). The interface device includes a socket board having a socket on which the DUT is attached and a multilayer printed circuit board on which the socket is mounted. The multilayer printed circuit board includes a plurality of high-speed signal front electrodes formed on a first surface of the multilayer printed circuit board and electrically contacting a plurality of pins through which a high-speed signal passes among a plurality of pins of the socket, a plurality of high-speed signal rear electrodes formed on a second surface of the multilayer printed circuit board at the same positions as the plurality of high-speed signal front electrodes when the multilayer printed circuit board is viewed in a plan view, and a plurality of high-speed signal via holes penetrating the multilayer printed circuit board, each electrically connecting a corresponding high-speed signal front electrode and a corresponding high-speed signal rear electrode.

[0021] With this configuration, high-speed signals are not routed horizontally (in-plane) within the printed circuit board of the socket board, but are propagated in a straight line in the shortest distance vertically (out-of-plane) through the via holes. This makes it possible to shorten the electrical length of the transmission path for high-speed signals, enabling high-speed signal transmission with low loss.

[0022] In one embodiment, the interface device may further include a front-end module in which a pin electronics IC (Integrated Circuit) is modularized, and a plurality of coaxial cables connecting the front-end module and a plurality of back electrodes for high-speed signals. By providing the pin electronics IC in the interface device instead of the test head, the length of the coaxial cables connecting the pin electronics IC and the socket board can be reduced to half or less of the conventional length.

[0023] In one embodiment, the ends of the multiple coaxial cables may be provided with pogo pins. By using the pogo pins to make electrical contact with the back electrodes for high-speed signals, multiple paths can be arranged at a higher density than when using a contact point that uses a coaxial connector. In addition, loss can be reduced compared to when using a coaxial connector.

[0024] In one embodiment, the lengths of the multiple coaxial cables may be adjusted so that the electrical lengths between the input / output pins of the pin electronics IC and the multiple back electrodes for high-speed signals are equal. By using the coaxial cables to equalize the electrical lengths, the delay and attenuation of the multiple high-speed signals are equalized, enabling more accurate testing.

[0025] In one embodiment, the interface device may further include a connector for connecting the socket board and the front-end module. In the case of a DUT with a large number of pins, it is practically difficult to arrange multiple back electrodes for all signals within the range of the DUT. In this case, non-high-speed signals may be routed through the connector. Non-high-speed signals may include low-speed signals and DC signals such as power signals.

[0026] An automatic test apparatus according to an embodiment may include a tester body, a test head, and an interface device connected to the test head.

[0027] (Embodiment) Hereinafter, preferred embodiments will be described with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be given the same reference numerals, and duplicated descriptions will be omitted as appropriate. In addition, the embodiments are illustrative and do not limit the disclosure and invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the disclosure and invention.

[0028] In addition, the dimensions (thickness, length, width, etc.) of each component shown in the drawings may be enlarged or reduced as appropriate for ease of understanding. Furthermore, the dimensions of multiple components do not necessarily represent their relative sizes, and even if a component A is drawn thicker than another component B on the drawings, component A may actually be thinner than component B.

[0029] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their combination.

[0030] Similarly, "a state in which component C is connected (provided) between components A and B" includes not only the case in which components A and C, or components B and C, are directly connected to each other, but also the case in which they are indirectly connected to each other via other components that do not substantially affect the electrical connection between them or that do not impair the functions or effects achieved by their combination.

[0031] 2 is a diagram showing an ATE 100 according to an embodiment. The ATE 100 includes a tester 120, a test head 130, a handler 150, and an interface device 200.

[0032] The tester 120 comprehensively controls the ATE 100. Specifically, the tester 120 executes a test program, controls the test head 130 and the handler 150, and collects measurement results.

[0033] The handler 150 supplies (loads) the DUT1 to the interface device 200, and unloads the tested DUT1 from the interface device 200. The handler 150 also classifies the DUT1 into good and bad products.

[0034] The interface device 200 comprises a socket board 210 , a connection means 290 and a front-end module 300 .

[0035] In this embodiment, multiple pin electronics ICs (PE-ICs) 400 are provided in the interface device 200, not in the test head 130. The pin electronics IC 400 is an application specific integrated circuit (ASIC: Application Specific IC) that integrates a driver that generates a test signal and a comparator that receives a device signal. The test signal and the device signal are NRZ signals or PAM4 signals.

[0036] More specifically, a plurality of pin electronics ICs 400 are modularized. This module is called a front-end module 300.

[0037] The socket board 210 is provided with a plurality of sockets 220. The DUT 1 is attached to the socket 220. The front-end module 300 and the socket board 210 are electrically connected via a connection means 290.

[0038] The above is the configuration of ATE100.

[0039] According to this ATE 100, by incorporating a front-end module 300, which is formed by modularizing a plurality of pin electronics ICs 400, into the interface device 200, it becomes possible to place the pin electronics ICs 400 in close proximity to the DUT 1. This makes it possible to significantly shorten the transmission distance of the test signal and the device signal compared to the conventional case.

[0040] For example, in conventional ATE, the pin electronics IC and the socket board are connected by a coaxial cable with a length of about 500 mm to 600 mm, but in this embodiment, the length of the connection means 290 can be shortened to about 100 mm to 150 mm, or even to 100 mm or less. This makes it possible to significantly reduce the loss of high-frequency components and transmit high-speed test signals and device signals. The ATE 100 equipped with this interface device 200 is capable of testing high-speed memories exceeding 20 Gbps.

[0041] 3 is a cross-sectional view of an interface device 200A according to an embodiment. Only a configuration related to one DUT is shown in FIG. 3. In this embodiment, the interface device 200A includes a motherboard 280 and a socket board 210.

[0042] A front-end module 300A is housed in the motherboard 280. The front-end module 300A is supported and fixed by a frame (not shown) of the motherboard 280.

[0043] The front-end module 300A includes a plurality of pin electronics ICs 400 and a plurality of printed circuit boards (pin electronics PCBs) 310 on which the pin electronics ICs 400 are mounted. The pin electronics PCBs 310 are arranged in a direction perpendicular to the surfaces (front and back surfaces) of the DUT, in other words, the surface S1 of the socket board 210. In this embodiment, the socket board 210 is horizontal to the ground, and therefore the pin electronics PCBs 310 are arranged parallel to the direction of gravity. The front-end module 300A may include a cooling device (not shown). A relay connector 286 is provided on the bottom surface of the motherboard 280. The relay connector 286 is connected to the test head 130.

[0044] The socket board 210 is detachable from the motherboard 280. The socket board 210 includes a socket guide 212, a socket 220, and a printed circuit board (socket PCB) 230.

[0045] The socket 220 includes a plurality of pins 222 that are contact points with the socket PCB 230. The plurality of pins 222 include a pin 222a that transmits a high-speed signal and a pin 222b that transmits a non-high-speed signal. In the following description, the subscript a indicates high speed, and b indicates non-high speed. In this specification, the "high-speed signal" includes a signal with a frequency of 1 GHz or more, and the "non-high-speed signal" includes a signal other than a high-speed signal, that is, a low-speed signal with a frequency of less than 1 GHz, a power signal that is a direct current signal, and the like. The design limit of currently known technology is approximately 10 Gbps (5 GHz), and a new architecture is required for frequencies higher than this, specifically, for the 20 Gbps (10 GHz) band. The technology according to the present disclosure is particularly useful in bands higher than 10 Gbps, and the effect is more evident in the 20 Gbps band.

[0046] Taking the GDDR7 standard memory as an example, high-speed and non-high-speed signals can be classified as follows: High-speed signal DQ, CA, WCK / RCK, RESETN Non-high speed signals ZQ, VSS, VDDQ, VDD, VPP

[0047] The socket PCB 230 is a multi-layer printed circuit board and may be an IVH (Inner Via Hole) board (also called a build-up board). A plurality of surface electrodes 232 are formed on a first surface (upper surface) S1 of the socket PCB 230. The plurality of surface electrodes 232 are disposed to face the plurality of pins 222 of the socket 220.

[0048] The surface electrodes 232 include a surface electrode 232a and a surface electrode 232b. The surface electrode 232a is electrically connected to the pin 222a through which a high-speed signal propagates. The surface electrode 232b is electrically connected to the pin 222b through which a non-high-speed signal propagates.

[0049] A plurality of back electrodes 234a are formed on the second surface (lower surface) S2 of the socket PCB 230. The plurality of back electrodes 234a are formed at the same positions as the plurality of front electrodes 232a when the socket PCB 230 is viewed in a plan view.

[0050] A plurality of via holes 236a are formed in the socket PCB 230. Each via hole 236a penetrates the socket PCB 230 and electrically connects the corresponding front surface electrode 232a and the corresponding back surface electrode 234a. That is, high-speed signals are not routed in the lateral direction (in-plane direction) within the socket PCB 230, but move only in the vertical direction (out-of-plane direction). The via holes 236a may be through vias (through holes) that penetrate all layers. Alternatively, the via holes 236a may be formed by forming buried vias or blind vias (collectively referred to as IVH) at the same position in each of a plurality of layers and electrically connecting them.

[0051] The non-high speed surface electrode 232 b is routed laterally through a via hole 236 b and a wiring 238 b and is electrically connected to a connector 240 .

[0052] 4 is a perspective view of the socket PCB 230. The dashed line 2 indicates the range of the DUT 1. The wiring 238b extends from the range 2 of the DUT 1 to the mounting range of the connector 240. The wiring 238b is formed by combining wiring on a surface layer or an inner layer of the socket PCB 230 and a via hole 236b.

[0053] Returning to Fig. 3, the connection means 290 includes a connection means 290a for high-speed signals and a connection means 290b for non-high-speed signals. The connection means 290a includes a coaxial cable 292, a pogo pin (also called a spring probe or a spring-loaded probe) 294, and a pogo block 296. The pogo pin 294 is attached to the tip of the coaxial cable 292. The pogo pin 294 is fixed by the pogo block 296. The pogo pin 294 is electrically connected to the back electrode 234a.

[0054] The connection means 290b includes a connector 282. The connector 282 is connected to the connector 240 of the socket board 210.

[0055] 5 is a perspective view of a connection means 290a for high-speed signals. A plurality of through holes 298 are formed in a pogo block 296 inside the range 2 of the DUT 1. Among the plurality of through holes 298, a pogo pin 294 is inserted into one provided at a position facing the back electrode 234a through which the high-speed signal propagates.

[0056] The above is the configuration of the interface device 200A.

[0057] According to this interface device 200A, high-speed signals are propagated straight through the via holes 236a without being routed laterally within the socket PCB 230. This makes it possible to shorten the electrical length of the transmission path of the high-speed signal, enabling the transmission of the high-speed signal with low loss.

[0058] The lengths of the multiple coaxial cables 292 may be adjusted so that the electrical lengths between the input / output pins of the pin electronics IC 400 and the multiple back electrodes 234a are equal. By using the length of the coaxial cables, the delay amounts of multiple high-speed signals are equalized, enabling more accurate testing.

[0059] The above-described embodiment is merely an example, and it will be understood by those skilled in the art that various modifications are possible in the combination of each component and each processing step. Such modifications will be described below.

[0060] (Variation 1) Depending on the pin arrangement of the DUT 1, it may be difficult to form a transmission path for all high-speed signals using only the via holes 236a without routing the signals laterally within the socket PCB 230. In such a case, the configuration of the first modified example can be adopted.

[0061] 6 is a cross-sectional view of an interface device 200B according to the first modification. The pin 222c of the socket 220 is for high-speed signals, similar to the pin 222a. The back electrode 234c corresponding to the pin 222c is not provided at the same position as the front electrode 232c when the socket PCB 230B is viewed in plan, but is provided at an adjacent position by one pin. The front electrode 232c and the back electrode 234c are connected via a via hole 236b and a wiring 238c. According to this modification, the lateral wiring can be minimized.

[0062] (Variation 2) In the embodiment, the coaxial cable 292 is used as the connection means 290a, but the present disclosure is not limited thereto. Instead of the coaxial cable 292, a flexible printed circuit (FPC) may be used.

[0063] Although the embodiments according to the present disclosure have been described using specific terms, this description is merely an example for facilitating understanding and does not limit the scope of the present disclosure or the claims. The scope of the present invention is defined by the claims, and therefore, embodiments, examples, and modifications not described herein are also included in the scope of the present invention. [Explanation of symbols]

[0064] 1 DUT 100ATE 120 Tester 130 Test Head 200 Interface device 210 Socket Board 220 Socket 222 pin 230 Socket PCB 232 Surface electrode 234 Back electrode 236 Beer Hall 238 Wiring 240 Connector 280 Motherboard 290 Connection Methods 292 Coaxial Cable 294 Pogo pin 296 Pogo Block 300 Front-end Module 310 pin electronics PCB 400 pin electronics IC

Claims

1. An interface device provided between a test head and a device under test (DUT), comprising: a socket board including a socket on which the DUT is mounted and a multi-layer printed circuit board on which the socket is mounted; The multilayer printed circuit board comprises: a plurality of high-speed signal surface electrodes formed on a first surface of the multilayer printed circuit board and electrically contacting a plurality of pins of the socket through which high-speed signals pass; a plurality of high-speed signal back electrodes formed on a second surface of the multilayer printed circuit board at the same positions as the plurality of high-speed signal front surface electrodes when the multilayer printed circuit board is viewed in a plan view; a plurality of high-speed signal via holes penetrating the multilayer printed circuit board, each of which electrically connects a corresponding high-speed signal front surface electrode and a corresponding high-speed signal back surface electrode; An interface device comprising:

2. a front-end module in which a pin electronics IC (Integrated Circuit) is modularized; a plurality of coaxial cables connecting the front-end module and the plurality of high-speed signal back electrodes; The interface device of claim 1 further comprising:

3. 3. The interface device according to claim 2, wherein pogo pins are attached to the ends of the plurality of coaxial cables.

4. 4. The interface device according to claim 2, wherein the lengths of the coaxial cables are adjusted so that electrical lengths between the input / output pins of the pin electronics IC and the multiple high-speed signal back electrodes are equal.

5. a connector for connecting the socket board and the front-end module; 3. The interface device according to claim 2, wherein non-high-speed signals are routed through said connector.

6. The tester body, A test head; an interface device according to any one of claims 1 to 3, connected to the test head; An automatic test apparatus comprising:

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