Manufacturing method of light-emitting device

Abstract

To provide a manufacturing method of a light-emitting device capable of reducing an error between a designed shape of a light-emitting device region and an obtained shape of the light-emitting device region.SOLUTION: A manufacturing method of a light-emitting device includes the steps of: preparing a wafer comprising a substrate and a semiconductor structure disposed on the substrate; and forming a plurality of light-emitting device regions by dividing the semiconductor structure. The step of forming the light-emitting device regions includes the steps of: forming a plurality of first masks on the semiconductor structure; and exposing the substrate from the semiconductor structure by removing portions exposed from the first masks, of the semiconductor structure. In the step of forming the first masks, each of the plurality of first masks covers a first region predetermined to form one of the plurality of light-emitting device regions and has an area larger than the first region in a planar view.SELECTED DRAWING: Figure 10

Description

[Technical field]

[0001] The present disclosure relates to a method for manufacturing a light-emitting device. [Background technology]

[0002] Patent Document 1 proposes a light-emitting element in which a plurality of light-emitting cells are arranged on a substrate. In the manufacturing process of such a light-emitting element, a semiconductor structure arranged on a substrate is divided to form a plurality of light-emitting cells. When dividing the semiconductor structure, etching is performed using a resist mask that covers the portion of the semiconductor structure where the light-emitting cells are to be formed and exposes the other portions. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2017-195370 A Summary of the Invention [Problem to be solved by the invention]

[0004] When a relatively thick semiconductor structure is etched as in the conventional light emitting device manufacturing method, the error between the designed shape of the light emitting device region and the resulting shape of the light emitting device region is likely to become large.

[0005] An object of the present disclosure is to provide a method for manufacturing a light-emitting element that can reduce the error between the designed shape of a light-emitting element region and the obtained shape of the light-emitting element region. [Means for solving the problem]

[0006] According to one aspect of the disclosed technology, a method for manufacturing a light-emitting element includes a step of preparing a wafer having a substrate and a semiconductor structure disposed on the substrate, and a step of dividing the semiconductor structure to form a plurality of light-emitting element regions, the step of forming the light-emitting element regions includes a step of forming a plurality of first masks on the semiconductor structure, and a step of removing a portion of the semiconductor structure exposed from the first mask to expose the substrate from the semiconductor structure, and in the step of forming the first masks, each of the plurality of first masks covers a first region in which one of the plurality of light-emitting element regions is to be formed, and has an area larger than the first region in a planar view. Effect of the Invention

[0007] According to the present disclosure, it is possible to provide a method for manufacturing a light-emitting element that can reduce the error between the designed shape of the light-emitting element region and the obtained shape of the light-emitting element region. [Brief description of the drawings]

[0008] [Figure 1] 1A to 1C are top views (part 1) illustrating a method for manufacturing a light-emitting device according to an embodiment. [Diagram 2] 4A to 4C are top views (part 2) illustrating the method for manufacturing the light emitting device according to the embodiment. [Diagram 3] 6A to 6C are top views (part 3) illustrating the method for manufacturing the light emitting device according to the embodiment. [Figure 4] 4 is a top view (part 4) illustrating the method for manufacturing the light emitting device according to the embodiment. FIG. [Diagram 5] 5 is a top view (part 5) illustrating the method for manufacturing the light emitting device according to the embodiment. FIG. [Figure 6] 6 is a top view (part 6) illustrating the method for manufacturing the light emitting device according to the embodiment. FIG. [Figure 7] 7 is a top view (part 7) illustrating the method for manufacturing the light emitting device according to the embodiment. FIG. [Figure 8] 8 is a top view (part 8) illustrating the method for manufacturing the light emitting device according to the embodiment. FIG. [Figure 9]FIG. 2 is a top view showing a first region in which a light emitting element region is to be formed. [Figure 10] FIG. 2 is a top view showing a first mask. [Figure 11] 1A to 1C are cross-sectional views (part 1) illustrating a method for manufacturing a light-emitting element according to an embodiment. [Figure 12] 5A to 5C are cross-sectional views (part 2) illustrating the method for manufacturing the light-emitting element according to the embodiment. [Figure 13] 5A to 5C are cross-sectional views (part 3) illustrating the method for manufacturing the light-emitting element according to the embodiment. [Figure 14] 4A to 4C are cross-sectional views showing the method for manufacturing the light-emitting element according to the embodiment; [Figure 15] 5A to 5C are cross-sectional views showing the method for manufacturing the light-emitting element according to the embodiment; [Figure 16] 6 is a cross-sectional view (part 6) illustrating the method for manufacturing the light-emitting element according to the embodiment. [Figure 17] 7 is a cross-sectional view (part 7) showing the method for manufacturing the light-emitting element according to the embodiment. [Figure 18] 8 is a cross-sectional view showing the method for manufacturing the light-emitting element according to the embodiment; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment for carrying out the present disclosure will be described with reference to the drawings. The following description is for embodying the technical idea of ​​the present disclosure, and unless otherwise specified, the present disclosure is not limited to the following description.

[0010] In each drawing, the same reference numerals may be attached to components having the same function. In consideration of the explanation or ease of understanding of the main points, the embodiments may be shown separately for convenience, but partial replacement or combination of the configurations shown in different embodiments or examples is possible. In the embodiments shown later, differences from the embodiments shown earlier are mainly explained, and overlapping explanations of matters common to the embodiments shown earlier may be omitted. The size and positional relationship of the components shown in each drawing may be exaggerated to clarify the explanation. In order to avoid overly complicated drawings, some elements may be omitted, or an end view showing only the cut surface may be used as a cross-sectional view. In the following explanation, an XYZ Cartesian coordinate system is used, but this coordinate system is defined for the purpose of explanation and does not limit the attitude of the substrate, etc. In addition, the +Z side may be referred to as the upper side, upper side, or top, and the -Z side may be referred to as the lower side, lower side, or bottom, when viewed from an arbitrary point.

[0011] This embodiment relates to a method for manufacturing a light-emitting element. FIGS. 1 to 8 are top views showing a method for manufacturing a light-emitting element according to an embodiment. FIG. 9 is a top view showing a first region in which a light-emitting element region is to be formed. FIG. 10 is a top view showing a first mask. FIGS. 11 to 18 are cross-sectional views showing a method for manufacturing a light-emitting element according to an embodiment. FIGS. 11 to 18 correspond to cross-sectional views taken along lines XI-XI, XII-XII, XIII-XIII, XIV-XIV, XV-XV, XVI-XVI, XVII-XVII, and XVIII-XVIII in FIGS. 1 to 8, respectively. In this embodiment, a light-emitting element 1 shown in FIGS. 8 and 18 is manufactured. The light-emitting element 1 has two light-emitting element regions 40 arranged in the X direction.

[0012] In this embodiment, first, as shown in FIG. 1 and FIG. 11, a process of preparing a wafer 10 having a substrate 20 and a semiconductor structure 30 is performed. The substrate 20 is an insulating substrate such as a sapphire substrate. The semiconductor structure 30 is disposed on the substrate 20. The semiconductor structure 30 has an n-side semiconductor layer 31, an active layer 32, and a p-side semiconductor layer 33. The n-side semiconductor layer 31 is disposed on the substrate 20, the active layer 32 is disposed on the n-side semiconductor layer 31, and the p-side semiconductor layer 33 is disposed on the active layer 32. The thickness T1 of the n-side semiconductor layer 31 is greater than the total thickness T2 of the p-side semiconductor layer 33 and the active layer 32. For example, the thickness T1 of the n-side semiconductor layer 31 is 5.0 μm or more and 15.0 μm or less, and the total thickness T2 of the p-side semiconductor layer 33 and the active layer 32 is 0.5 μm or more and 1.0 μm or less. For example, a compound semiconductor such as a III-V group compound semiconductor or a II-VI group compound semiconductor is used as the material of the semiconductor structure 30. The semiconductor structure 30 may include, for example, a nitride semiconductor.

[0013] The wafer 10 has a plurality of chip regions 5 to be used as the light-emitting element 1. The shape of the chip region 5 in plan view is, for example, a rectangular shape with each side having a length of 100 μm to 2000 μm, preferably 500 μm to 2000 μm. The plurality of chip regions 5 are arranged at regular intervals in the X and Y directions. For example, the distance between two adjacent chip regions 5 is, for example, 5 μm to 30 μm. FIG. 1 shows two chip regions 5 aligned in the X direction. Each of the chip regions 5 has two first regions 41 to be used to form the light-emitting element region 40 shown in FIG. 6. The two first regions 41 are aligned in the X direction. The shape of the first region 41 in plan view is a rectangle having a short side parallel to the X direction and a long side parallel to the Y direction. The corners of the rectangular first region 41 may be rounded. As shown in FIG. 8, each of the light-emitting elements 1 has two light-emitting element regions 40.

[0014] 9, the first region 41 has two first sides 41S that are parallel to each other and two second sides 41L that are longer than the first sides 41S and parallel to each other. The first sides 41S are parallel to the X direction, and the second sides 41L are parallel to the Y direction. The first region 41 has a third region 43 where the p-side semiconductor layer 33 and the active layer 32 are to be removed to expose the n-side semiconductor layer 31, and a second region 42 where the p-side semiconductor layer 33 and the active layer 32 are to be left without being removed.

[0015] 2 and 12, a step of forming a plurality of second masks 60 on the semiconductor structure 30 is performed. The second mask 60 is formed on the second region 42 of the semiconductor structure 30, and other parts of the semiconductor structure 30 (including the third region 43) are exposed from the second mask 60. At this time, an outer edge 60E of each of the plurality of second masks 60 coincides with an outer edge 42E of the second region 42 in a plan view. The second mask 60 is, for example, a resist mask.

[0016] 3 and 13, a step is performed in which the portion of the semiconductor structure 30 exposed from the second mask 60 is removed to a thickness T3 that is greater than the total thickness T2 of the p-side semiconductor layer 33 and the active layer 32 and smaller than the thickness T1 of the n-side semiconductor layer 31, thereby exposing the n-side semiconductor layer 31 from the p-side semiconductor layer 33 and the active layer 32. As a result, a recess 70 is formed in the portion of the semiconductor structure 30 exposed from the second mask 60. The thickness T3, i.e., the depth of the recess 70, is, for example, 0.5 μm or more and 1.5 μm or less. The thickness of the n-side semiconductor layer 31 in the portion exposed from the p-side semiconductor layer 33 and the active layer 32 is, for example, 5.0 μm or more and 15.0 μm or less. The step of removing the semiconductor structure 30 is performed by, for example, reactive ion etching (RIE), and the temperature of the wafer 10 is about 100° C.

[0017] 4 and 14, the second mask 60 is removed, and a step of forming a plurality of first masks 50 on the semiconductor structure 30 is performed. The first mask 50 covers the first region 41 and has an area larger than that of the first region 41 in a plan view.

[0018] As shown in FIG. 10, the shape of the first mask 50 in plan view has a base 53, two first portions 51, and two second portions 52. The shape of the base 53 overlaps with the first region 41 in plan view and has two third sides 53S parallel to the first side 41S of the first region 41, and two fourth sides 53L longer than the third sides 53S and parallel to the second side 41L of the first region 41. The third sides 53S are parallel to the X direction, and the fourth sides 53L are parallel to the Y direction. The first portions 51 are located outside the second side 41L of the first region 41 in plan view, and the second portions 52 are located outside the first side 41S of the first region 41 in plan view.

[0019] The outer edge 51E of the first portion 51 has a curved shape that is more distant from the base 53 as it approaches the middle between the two second portions 52 in the Y direction. In a plan view, a part of the outer edge 51E of the first portion 51 is an arc shape that is convex outward from the fourth side 53L of the base 53 on a perpendicular bisector 55 that bisects the fourth side 53L of the base 53. In addition, the outer edge 52E of the second portion 52 has a curved shape that is more distant from the base 53 as it approaches the middle between the two first portions 51 in the Y direction. In a plan view, a part of the outer edge 52E of the second portion 52 has an arc shape that is convex outward from the third side 53S of the base 53 on a perpendicular bisector 56 that bisects the third side 53S of the base 53.

[0020] For example, in a plan view, the maximum distance L1 between the outer edge 51E of the first portion 51 and the fourth side 53L of the base 53 is greater than the maximum distance L2 between the outer edge 52E of the second portion 52 and the third side 53S of the base 53. The maximum distance L1 is preferably 1.2 to 2.0 times the maximum distance L2, more preferably 1.3 to 1.8 times, and even more preferably 1.4 to 1.6 times. For example, the maximum distance L1 is 1.0 μm to 2.0 μm, and the maximum distance L2 is 0.5 μm to 1.5 μm.

[0021] Next, as shown in FIG. 5 and FIG. 15, a step of removing the portion of the semiconductor structure 30 exposed from the first mask 50 to expose the substrate 20 from the semiconductor structure 30 is performed. The step of removing the semiconductor structure 30 is performed by, for example, RIE, as described above. During RIE, the temperature of the wafer 10 becomes about 100° C., and the heat of the wafer 10 is transferred to the first mask 50. Therefore, while performing RIE, the temperature of the first mask 50 increases, and the first mask 50 gradually shrinks. The amount of shrinkage is larger as the volume of the first mask 50 is larger. When a relatively thick semiconductor layer is to be removed, the thickness of the first mask 50 needs to be thickened according to the thickness of the semiconductor layer. As described above, the thickness of the n-side semiconductor layer 31 in the portion exposed from the first mask 50 is, for example, 10.0 μm or more and 15.0 μm or less, and the first mask 50 has a thickness T50 according to this thickness. For example, the thickness T50 is 10 μm or more and 20 μm or less. Therefore, the first mask 50 is more likely to shrink than a mask having a relatively thin thickness. At this time, in the shape of the first mask 50 in a plan view, the first portion 51 shrinks more than the second portion 52, and the first portion 51 shrinks more in the vicinity of the perpendicular bisector 55. As a result, even if the first mask 50 has the first portion 51 and the second portion 52 protruding from the first region 41 in a plan view before the step of removing the semiconductor structure 30 using the first mask 50, after the step of removing the semiconductor structure 30 using the first mask 50, the base 53, the first portion 51, and the second portion 52 of the first mask 50 each shrink, so that the entire first mask 50 generally overlaps with the first region 41. In addition, the thickness of the first mask 50 becomes slightly thinner by RIE.

[0022] Next, as shown in Figs. 6 and 16, the first mask 50 is removed. In this manner, a plurality of light-emitting element regions 40 are formed by dividing the semiconductor structure 30. The light-emitting element regions 40 are formed so as to overlap with the first region 41. In the light-emitting element region 40, a part of the n-side semiconductor layer 31 is exposed from the p-side semiconductor layer 33. In addition, the substrate 20 is exposed around the light-emitting element region 40. For example, the distance between two adjacent light-emitting element regions 40 in the chip region 5 is 5 µm or more and 20 µm or less.

[0023] Next, as shown in FIG. 7 and FIG. 17, an insulating film 81 is formed to cover the light-emitting element region 40 and the substrate 20. Next, an opening 81n exposing the n-side semiconductor layer 31 and an opening (not shown) exposing the p-side semiconductor layer 33 are formed in the insulating film 81. Next, an n-side electrode 82n electrically connected to the n-side semiconductor layer 31 through the opening 81n exposing the n-side semiconductor layer 31, and a p-side electrode 82p electrically connected to the p-side semiconductor layer 33 through the opening exposing the p-side semiconductor layer 33 are formed. For example, the insulating film 81 is a film of at least one oxide or nitride selected from the group consisting of Si, Ti, Zr, Nb, Ta, and Al. For example, metals such as Au, Pt, Pd, Rh, Ni, W, Mo, Cr, Ti, Al, and Cu, or alloys of these metals are used as materials for the n-side electrode 82n and the p-side electrode 82p. In addition, the n-side electrode 82n and the p-side electrode 82p may be composed of a single layer film or a laminated film.

[0024] 8 and 18, the substrate 20 is divided to separate the multiple chip regions 5. In this manner, multiple light-emitting elements 1 can be manufactured.

[0025] Thus, in this embodiment, the first mask 50 has a base 53, a first portion 51, and a second portion 52. Therefore, although the first mask 50 shrinks during RIE to remove the portion of the semiconductor structure 30 exposed from the first mask 50, at the end of the RIE, the first mask 50 is shrunk so that the entire first mask 50 is generally overlapped with the first region 41. Therefore, it is possible to reduce the error between the shape of the first region 41 in which the light-emitting element region 40 is to be formed and the shape of the light-emitting element region 40 obtained through RIE. Since the first region 41 corresponds to the light-emitting element region 40 in design, according to this embodiment, it is possible to reduce the error between the shape of the light-emitting element region 40 in design and the shape of the light-emitting element region 40 obtained.

[0026] In addition, even during RIE to remove the portion of the semiconductor structure 30 exposed from the second mask 60, the second mask 60 is shrunk by the heat of the wafer 10. However, the second mask 60 does not substantially shrink, and in this step, the second mask 60 is likely to maintain a state in which it covers the second region 42. This is because the thickness T3 of the portion to be removed in this step is, for example, 0.5 μm or more and 1.5 μm or less, the second mask 60 only needs to have a thickness T60 corresponding to this thickness T3, and the volume of the second mask 60 is small enough that the amount of shrinkage can be ignored. In other words, the thickness T60 of the second mask 60 may be smaller than the thickness T50 of the first mask 50.

[0027] Furthermore, the first mask 50 is likely to shrink significantly in portions away from the four corners of the first mask 50 in a plan view. In this embodiment, since the maximum distance L1 is greater than the maximum distance L2, the first portion 51 is likely to shrink significantly more than the second portion 52, and the first mask 50 is likely to entirely overlap with the first region 41 due to the shrinkage of the first mask 50. If the maximum distance L1 is 1.2 to 2.0 times the maximum distance L2, the first mask 50 is particularly likely to entirely overlap with the first region 41 due to the shrinkage of the first mask 50.

[0028] In addition, in a planar view, a portion of the outer edge 51E of the first portion 51 is arc-shaped and convex outward from the fourth side 53L of the base 53 on the perpendicular bisector 55, so that in a planar view, the outer edge 51E of the first portion 51 is likely to overlap the second side 41L of the first region 41 due to shrinkage of the first mask 50.

[0029] This specification includes the following embodiments. 1. Providing a wafer having a substrate and a semiconductor structure disposed on the substrate; dividing the semiconductor structure to form a plurality of light emitting device regions; having The step of forming the light emitting element region includes: forming a plurality of first masks over the semiconductor structure; removing a portion of the semiconductor structure exposed through the first mask to expose the substrate from the semiconductor structure; having A method for manufacturing a light-emitting element, wherein in the step of forming the first mask, each of the multiple first masks covers a first region in which one of the multiple light-emitting element regions is to be formed and has an area larger than the first region in a planar view. 2. a shape of the first region in a plan view has two first sides that are parallel to each other and two second sides that are longer than the first sides and parallel to each other; a shape of the first mask in a plan view includes a base portion that overlaps with the first region and has two third sides parallel to the first side and two fourth sides that are longer than the third sides and parallel to the second side, a first portion positioned outside the second side of the first region, and a second portion positioned outside the first side of the first region, The method for manufacturing a light-emitting element described in claim 1, wherein, in a planar view, the maximum distance between the outer edge of the first portion and the fourth side of the base is greater than the maximum distance between the outer edge of the second portion and the third side of the base. 3. the semiconductor structure includes an n-side semiconductor layer disposed on the substrate, an active layer disposed on the n-side semiconductor layer, and a p-side semiconductor layer disposed on the active layer; The step of forming the light emitting element region includes the steps of: forming a plurality of second masks over the semiconductor structure; removing a portion of the semiconductor structure exposed from the second mask by a thickness greater than a total thickness of the p-side semiconductor layer and the active layer and less than a thickness of the n-side semiconductor layer to expose the n-side semiconductor layer from the p-side semiconductor layer and the active layer; 3. The method for producing the light-emitting device according to 1 or 2 above, comprising: 4. in the step of forming the plurality of second masks, an outer edge of each of the plurality of second masks coincides with an outer edge of a second region in which the p-side semiconductor layer and the active layer are to be left, in a plan view; 4. The method for manufacturing a light-emitting element according to claim 3, wherein in the step of exposing the n-side semiconductor layer from the p-side semiconductor layer and the active layer, the second mask is maintained in a state of covering the second region. 5. 5. The method for manufacturing a light-emitting element according to 3 or 4 above, wherein a thickness of the first mask is greater than a thickness of the second mask. 6. 3. The method for manufacturing a light-emitting element described in claim 2, wherein, in a planar view, the maximum distance between the outer edge of the first portion and the fourth side of the base is 1.2 to 2.0 times the maximum distance between the outer edge of the second portion and the third side of the base. 7. The method for manufacturing a light-emitting element described in claim 2, wherein, in a planar view, a portion of the outer edge of the first portion is an arc-shaped portion that convex outward from the fourth side of the base on a perpendicular bisector that bisects the fourth side of the base. [Explanation of symbols]

[0030] 1: Light emitting element 10: Wafer 20: Substrate 30: Semiconductor structure 31: n-side semiconductor layer 32:Active layer 33: p-side semiconductor layer 40: Light emitting element area 41:First area 41S: First side 41L: Second side 42:Second area 42E: Outer edge 43:Third area 50: First Mask 51: Part 1 52:Second part 51E, 52E: Outer edge 53: Base 53S: Third side 53L: 4th side 55, 56: Perpendicular bisector 60: 2nd Mask 60E:Outer edge

Claims

1. Providing a wafer having a substrate and a semiconductor structure disposed on the substrate; dividing the semiconductor structure to form a plurality of light emitting device regions; having The step of forming the light emitting element region includes: forming a plurality of first masks over the semiconductor structure; removing a portion of the semiconductor structure exposed through the first mask to expose the substrate from the semiconductor structure; having A method for manufacturing a light-emitting element, wherein in the step of forming the first mask, each of the multiple first masks covers a first region in which one of the multiple light-emitting element regions is to be formed and has an area larger than the first region in a planar view.

2. a shape of the first region in a plan view has two first sides that are parallel to each other and two second sides that are longer than the first sides and parallel to each other, a shape of the first mask in a plan view includes a base portion that overlaps with the first region and has two third sides parallel to the first side and two fourth sides that are longer than the third sides and parallel to the second side, a first portion positioned outside the second side of the first region, and a second portion positioned outside the first side of the first region, The method for manufacturing a light-emitting element according to claim 1 , wherein, in a planar view, a maximum distance between an outer edge of the first portion and the fourth side of the base is greater than a maximum distance between an outer edge of the second portion and the third side of the base.

3. the semiconductor structure includes an n-side semiconductor layer disposed on the substrate, an active layer disposed on the n-side semiconductor layer, and a p-side semiconductor layer disposed on the active layer; The step of forming the light emitting element region includes the steps of: forming a plurality of second masks over the semiconductor structure; removing a portion of the semiconductor structure exposed from the second mask to a thickness greater than a total thickness of the p-side semiconductor layer and the active layer and less than a thickness of the n-side semiconductor layer to expose the n-side semiconductor layer from the p-side semiconductor layer and the active layer; The method for producing a light-emitting element according to claim 1 , comprising:

4. in the step of forming the plurality of second masks, an outer edge of each of the plurality of second masks coincides with an outer edge of a second region in which the p-side semiconductor layer and the active layer are to be left, in a plan view; The method for manufacturing a light-emitting element according to claim 3 , wherein in the step of exposing the n-side semiconductor layer from the p-side semiconductor layer and the active layer, the second mask is maintained in a state of covering the second region.

5. The method of claim 3 , wherein the first mask has a thickness greater than a thickness of the second mask.

6. 3. The method for manufacturing a light-emitting element according to claim 2, wherein, in a planar view, the maximum distance between an outer edge of the first portion and the fourth side of the base is 1.2 to 2.0 times the maximum distance between the outer edge of the second portion and the third side of the base.

7. 3. The method for manufacturing a light-emitting element according to claim 2, wherein, in a planar view, a portion of an outer edge of the first portion is an arc-shaped portion that convex outward from the fourth side of the base on a perpendicular bisector that bisects the fourth side of the base.

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