Printed circuit board and method of manufacturing the same

Abstract

To provide a printed circuit board in which bumps with a fine pitch may be implemented in a printed circuit board for mounting electronic components, semiconductor chips, and the like, in which protruding bumps may be implemented without etching an insulating layer, and in which reliability can be improved.SOLUTION: The present disclosure relates to: a printed circuit board which includes a first insulating layer, a first metal layer disposed on an upper side of the first insulating layer, a second metal layer disposed on a lower side of the first insulating layer, and a first via layer penetrating through at least a portion of the first insulating layer to connect the first metal layer to the second metal layer, the first via layer having a tapered shape becoming narrower toward the upper side of the first insulating layer, an upper surface of the first metal layer being substantially flat, a side surface of the first metal layer having a curved surface; and a method of manufacturing the printed circuit board.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to printed circuit boards and methods for manufacturing printed circuit boards. [Background technology]

[0002] Recently, with the development of artificial intelligence (AI) technology, multi-chip packages containing memory chips such as HBM (High Bandwidth Memory) and processor chips such as CPU (Central Processing Unit), GPU (Graphics Processing Unit), ASIC (Application Specific Integrated Circuit), and FPGA (Field Programmable Gate Array) are being used to process data that has increased exponentially. In particular, the number of CPU and GPU cores in server products is increasing rapidly, making it necessary to accommodate finer chip bump pitches. Therefore, research is ongoing to develop substrate and package structures that can reduce bump pitches in response to the demand for higher density, thereby improving connection reliability and increasing yields. Summary of the Invention [Problem to be solved by the invention]

[0003] One of several objectives of the present disclosure is to provide a printed circuit board capable of realizing bumps having fine pitch on the printed circuit board for mounting electronic components, semiconductor chips, and the like.

[0004] Another of several objects of the present disclosure is to provide a printed circuit board that can achieve protruding bumps without etching an insulating layer.

[0005] Another of several objects of the present disclosure is to provide a printed circuit board that can improve reliability. [Means for solving the problem]

[0006] One of several solutions proposed throughout the present disclosure is to provide a printed circuit board including a first insulating layer, a first metal layer disposed on an upper side of the first insulating layer, a second metal layer disposed on a lower side of the first insulating layer, and a first via layer penetrating at least a portion of the first insulating layer to connect the first metal layer and the second metal layer, wherein the first via layer has a tapered shape that becomes narrower toward the upper side of the first insulating layer, a top surface of the first metal layer being substantially flat, and a side surface of the first metal layer having a curved surface.

[0007] Another of several solutions proposed through the present disclosure is to provide a method for manufacturing a printed circuit board, including the steps of forming a first barrier layer on a carrier substrate, forming a second barrier layer on the first barrier layer, forming a first insulating layer on the second barrier layer, forming a first through hole and a second through hole penetrating the first insulating layer and the second barrier layer, respectively, forming a first metal layer to fill the second through hole, forming a first via layer to fill the first through hole, forming the second metal layer on the first insulating layer, and removing the carrier substrate, the first barrier layer, and the second barrier layer. Effect of the Invention

[0008] As one of the various effects of the present disclosure, it is possible to provide a printed circuit board capable of realizing fine-pitch bumps on a printed circuit board for mounting electronic components, semiconductor chips, and the like.

[0009] Another advantage of the present disclosure is that it provides a printed circuit board that can realize protruding bumps without etching an insulating layer.

[0010] Another advantage of the present disclosure is that it is possible to provide a printed circuit board that can improve reliability. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a block diagram illustrating a schematic example of an electronic device system. [Diagram 2] FIG. 1 is a perspective view illustrating an example of an electronic device. [Diagram 3] FIG. 1 is a cross-sectional view illustrating a schematic diagram of a printed circuit board according to an example. [Figure 4] 1A to 1C are cross-sectional views illustrating a method for manufacturing a printed circuit board according to an embodiment of the present invention. [Diagram 5] 1A to 1C are cross-sectional views illustrating a method for manufacturing a printed circuit board according to an embodiment of the present invention. [Figure 6] 1A to 1C are cross-sectional views illustrating a method for manufacturing a printed circuit board according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, the present disclosure will be described with reference to the accompanying drawings. The shapes and sizes of elements in the drawings may be scaled (or highlighted or simplified) for a clearer description.

[0013] electronic equipment FIG. 1 is a block diagram illustrating an example of an electronic device system.

[0014] Referring to the drawing, an electronic device 1000 houses a main board 1010. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected to the main board 1010. These are also coupled to other electronic components described below to form various signal lines 1090.

[0015] The chip-related components 1020 include, but are not limited to, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processors (e.g., CPU), graphic processors (e.g., GPU), digital signal processors, encryption processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). In addition, these chip-related components 1020 may be combined with each other. The chip-related components 1020 may be in the form of a package including the above-mentioned chips and electronic components.

[0016] The network-related components 1030 may include, but are not limited to, any other wireless and wired protocols designated as Wi-Fi (such as the IEEE 802.11 family), WiMAX (such as the IEEE 802.16 family), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G, and beyond, and may include any of numerous other wireless or wired standards and protocols. The network-related components 1030 may also be combined with the chip-related components 1020 together.

[0017] The other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (low temperature co-firing ceramics), EMI (electromagnetic interference) filters, MLCC (multi-layer ceramic capacitors), etc. However, the other components 1040 are not limited to these, and may include passive elements in the form of chip components used for various other applications. The other components 1040 may also be combined with the chip-related components 1020 and / or the network-related components 1030.

[0018] Depending on the type of electronic device 1000, the electronic device 1000 may include other electronic components that may or may not be physically and / or electrically connected to the main board 1010. Examples of other electronic components include, but are not limited to, a camera module 1050, an antenna module 1060, a display 1070, and a battery 1080. Other electronic components may include, but are not limited to, an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a compact disk (CD), a digital versatile disk (DVD), and the like. In addition, other electronic components used for various purposes may be included depending on the type of electronic device 1000.

[0019] The electronic device 1000 may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, etc. However, the electronic device 1000 is not limited to these, and may be any other electronic device that processes data.

[0020] FIG. 2 is a perspective view that illustrates an example of an electronic device.

[0021] Referring to the drawings, the electronic device may be, for example, a smartphone 1100. A motherboard 1110 is housed inside the smartphone 1100, and various components 1120 are physically and / or electrically connected to the motherboard 1110. In addition, other components, such as a camera module 1130 and / or a speaker 1140, which may or may not be physically and / or electrically connected to the motherboard 1110, are housed inside the smartphone 1100. Some of the components 1120 may be the above-mentioned chip-related components, for example, a component package 1121, but are not limited thereto. The component package 1121 may be in the form of a printed circuit board on which electronic components including active components and / or passive components are mounted on a surface. Alternatively, the component package 1121 may be in the form of a printed circuit board in which active components and / or passive components are built in. Meanwhile, the electronic device is not necessarily limited to the smartphone 1100, and may be other electronic devices as described above.

[0022] Printed Circuit Board FIG. 3 is a schematic cross-sectional view of a printed circuit board according to an example.

[0023] Referring to FIG. 3, an example printed circuit board may include a first insulating layer 111, a first metal layer 121 disposed on the upper side of the first insulating layer 111, a second metal layer 122 disposed on the lower side of the first insulating layer 111, and a first via layer 131 penetrating at least a portion of the first insulating layer 111 to connect the first metal layer 121 and the second metal layer 122, wherein the first via layer 131 has a tapered shape that becomes narrower toward the upper side of the first insulating layer 111, the upper surface of the first metal layer 121 is substantially flat, and the side of the first metal layer 121 may have a curved surface.

[0024] The first insulating layer 111 may include an insulating material. The insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material including such a resin together with an inorganic filler, an organic filler, and / or glass fiber (glass fiber, glass cloth, and / or glass fabric). The insulating material may be a photosensitive material and / or a non-photosensitive material. For example, the insulating material of the first insulating layer 111 may be an insulating material such as PPG (Prepreg) or RCC (Resin Coated Copper), but is not limited thereto, and may be ABF (Ajinomoto Build-up Film), PID (Photo Imageable Dielectric), FR-4, BT (Bismaleimide Triazine), etc. However, the insulating material is not limited thereto, and other polymeric materials having excellent rigidity may be used as necessary.

[0025] The first metal layer 121 may include a metal material. The metal material may include, but is not limited to, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), lead (Pb), titanium (Ti), or an alloy thereof. The metal material may preferably include, but is not limited to, copper (Cu). The first metal layer 121 may perform various functions according to the design. For example, the first metal layer 121 may be a pad on which electronic components and chips can be mounted, or may be a circuit pattern for connecting signals to other pads, and may perform various functions according to the design. When the first metal layer 121 requires a high density fine pitch for mounting a semiconductor chip or the like, the interval between the first metal layers 121 may be narrow, and when mounting an electronic component, the interval between the first metal layers 121 may be wider.

[0026] The first metal layer 121 may be formed by any one of SAP (Semi Additive Process), MSAP (Modified Semi Additive Process), TT (Tenting), or a subtractive process, but is not limited thereto. The first metal layer 121 is formed by filling the second through-holes 232 penetrating the second barrier layer 220 as described below, and therefore can function as a pad and / or post for reducing the pitch of the bumps in order to mount a semiconductor chip having a fine pitch. The first metal layer 121 may include, but is not limited to, an electroless plating layer (or chemical copper) as a seed layer and an electrolytic plating layer (or electrolytic copper) as a plating layer. A sputtering layer may be formed instead of chemical copper as the electroless plating layer. If necessary, a copper foil may be further included. The seed layer will be described later.

[0027] The first metal layer 121 may be disposed on the upper side of the first insulating layer 111. The first metal layer 121 may have a structure protruding from the upper surface of the first insulating layer 111. The first metal layer 121 may be composed of a plurality of first metal layers disposed in the same layer. Each of the plurality of first metal layers 121 may have substantially the same height as one another.

[0028] Here, being substantially the same is a concept that includes roughness, and means that it can be judged including process errors, position deviations, and measurement errors that occur in the manufacturing process. Since the first metal layer 121 is formed by filling the second through-holes 232 penetrating the second barrier layer 220 as described below, the first metal layers 121 can be uniformly formed. In addition, since the second barrier layer 220 uses a metal different from that of the first metal layer 121, the first metal layer 121 can be protected in the step of removing the second barrier layer 220, and therefore the heights of the first metal layers 121 can be substantially the same.

[0029] The height of the first metal layer 121 may be measured by photographing a cross section cut in the stacking direction of the printed circuit board using a scanning microscope or the like. The height of the first metal layer 121 may be interpreted in the same sense as the thickness of the first metal layer 121, and the thickness of a certain component may be interpreted as the vertical distance of a certain component, but may include measurement errors or errors in the manufacturing process. That is, the height of the first metal layer 121 may be an average value of the vertical distances between the bottom surface and the top surface of the first metal layer 121 measured at any five points for one first metal layer 121. The fact that the heights of the multiple first metal layers 121 may be substantially the same means that the measured heights of each first metal layer 121 may be substantially the same.

[0030] The upper surface of the first metal layer 121 may be substantially flat, and the side of the first metal layer 121 may have a curved surface. As described later in the manufacturing process of the printed circuit board, the first metal layer 121 may be formed to fill the second through-hole 232 penetrating the second barrier layer 220. Since the first barrier layer 210 is not removed even if the second barrier layer 220 is completely penetrated in the step of forming the second through-hole 232 so that the upper and lower surfaces of the second barrier layer 220 are connected, the first metal layer 121 may be formed to have a substantially flat upper surface. At this time, the second through-hole 232 penetrating the second barrier layer 220 may have a curved side, and therefore the side of the first metal layer 121 may have a curved shape. Specifically, if the step of removing the second barrier layer 220 involves chemical etching, the side of the second through-hole 232 penetrating the second barrier layer 220 may have a curved shape.

[0031] The first metal layer 121 may have a lower surface that is wider than the upper surface. If the step of removing the second barrier layer 220 is performed by etching, the second through-hole 232 penetrating the second barrier layer 220 may have different widths at the upper and lower sides, and the second through-hole 232 may be formed so that the width at the lower surface is wider than the width at the upper surface. In addition, the side surface of the first metal layer 121 may have a curved surface such that the width at the upper side is narrowest and the width at the lower side is widest.

[0032] The width of the first metal layer 121 can be measured by photographing a cross section of the printed circuit board in the lamination direction using a scanning microscope or the like. The width of a certain component can be interpreted as the horizontal distance across the component, but may include measurement errors or errors in the manufacturing process. That is, the width of the top surface of the first metal layer 121 can mean the horizontal distance between both ends of the top surface of one first metal layer 121. This can be similarly applied to measuring the width of the bottom surface of the first metal layer 121. In this case, the width of the bottom surface of the first metal layer 121 being wider than the width of the top surface of the first metal layer 121 can be understood to mean the same thing as the cross-sectional area of ​​the bottom surface of the first metal layer 121 being wider than the cross-sectional area of ​​the top surface of the first metal layer 121.

[0033] The second metal layer 122 may be disposed under the first insulating layer 111. The second metal layer 122 may include a metal material. The metal material may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), lead (Pb), titanium (Ti), or an alloy thereof. The metal material may preferably include, but is not limited to, copper (Cu). The second metal layer 122 may include the same metal material as the first metal layer 121.

[0034] The second metal layer 122 may perform various functions according to the design, such as being a circuit pattern for connecting signals between the first metal layer 121 and other metal layers, and may perform various functions according to the design of the corresponding configuration. For example, it may include a ground pattern, a power pattern, a signal pattern, etc. Here, the signal pattern may include various signals other than the ground pattern, the power pattern, etc., such as a data signal, etc. These patterns may include a line pattern, a plane pattern, and / or a pad pattern.

[0035] The second metal layer 122 may be formed by any one of SAP (Semi Additive Process), MSAP (Modified Semi Additive Process), TT (Tenting), and subtractive processes, but is not limited thereto. The second metal layer 122 may include, but is not limited to, an electroless plating layer (or chemical copper) as a seed layer and an electrolytic plating layer (or electrolytic copper) as a plating layer. A sputtering layer may be formed instead of chemical copper as the electroless plating layer. If necessary, a copper foil may be further included. The seed layer will be described later.

[0036] The second metal layer 122 may be composed of a plurality of second metal layers 122 arranged in the same layer. The fact that the second metal layer 122 may be composed of a plurality of second metal layers 122 may have the same meaning as the fact that the first metal layer 121 may be composed of a plurality of first metal layers 121. Meanwhile, in FIG. 3, in order to depict the area of ​​one first metal layer 121 and one second metal layer 122 in detail, it is expressed that one first metal layer 121 and one second metal layer 122 are respectively composed in one to one relationship, but the arrangement of the first metal layer 121 and the second metal layer 122 of the printed circuit board according to an example is not limited thereto, and a plurality of first metal layers 121 may be connected by the second metal layer 122, and there may be a portion where the first metal layer 121 and the second metal layer 122 are not connected.

[0037] The first via layer 131 may penetrate at least a portion of the first insulating layer 111 to connect the first metal layer 121 and the second metal layer 122 to each other. The first via layer 131 may have a tapered shape such that the width becomes narrower toward the upper side of the first insulating layer 111. The first via layer 131 may be composed of a plurality of first via layers 131, and the fact that the first via layer may be composed of a plurality of first via layers 131 may have the same meaning as the first metal layer 121 may be composed of a plurality of first metal layers 121.

[0038] The first via layer 131 may include microvias. The microvias may be field vias that fill a via hole, or conformal vias that are arranged along the wall surface of the via hole. The microvias may be arranged in a stacked type and / or staggered type with other via layers.

[0039] The first via layer 131 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The metal material may preferably include, but is not limited to, copper (Cu). The first via layer 131 may include a metal material such as the first metal layer 121 and the second metal layer 122.

[0040] The first via layer 131 may include, but is not limited to, an electroless plating layer (or chemical copper) as a seed layer and an electrolytic plating layer (or electrolytic copper) as a plating layer. A sputtering layer may be formed as the electroless plating layer instead of chemical copper. The first via layer 131 may perform various functions according to the design of the layer. For example, it may include a ground via, a power via, a signal via, etc. Here, the signal via may include a via for transmitting various signals, such as a data signal, other than a ground via, a power via, etc.

[0041] The first via layer 131 may be formed by any one of SAP (Semi Additive Process), MSAP (Modified Semi Additive Process), TT (Tenting), or subtractive methods, but is not limited thereto, and may be formed by any method capable of forming a circuit on a printed circuit board. The first via layer 131 may include, but is not limited to, an electroless plating layer (or chemical copper) as a seed layer and an electrolytic plating layer (or electrolytic copper) as a plating layer. A sputtering layer may be formed instead of chemical copper as the electroless plating layer. If necessary, a copper foil may be further included. The seed layer will be described later.

[0042] Each of the first metal layers 121, each of the first via layers 131, and each of the second metal layers 122 may be formed integrally with each other. Formed integrally may mean that they may be formed simultaneously by one process in one manufacturing stage, and may mean that the boundary between the components may not be clear. That is, the first metal layer 121, the first via layer 131, and the second metal layer 122 may be formed integrally, and the boundary between them may not appear. Each of the first metal layer 121, the first via layer 131, and the second metal layer 122 may be composed of the first metal 141 and the second metal 142, and the boundary between the first metal 141 and the second metal 142 may occur, but is not limited thereto, and the boundary may not be clear due to a post-process or the like.

[0043] The first metal 141 may be disposed at the boundary between the first metal layer 121 and the first insulating layer 111, may be disposed at the boundary between the first via layer 131 and the first insulating layer 111, and may be disposed at the boundary between the second metal layer 122 and the first insulating layer 111. Each of the first metals 141 may be integrally formed by extending along each boundary. This is because the first metal 141 may be formed on the inner walls of the first through hole 231 and the second through hole 232 during the manufacturing process and may be disposed to extend to the lower surface of the first insulating layer 111. The first metal 141 may function as a seed layer for the second metal 142. The first metal 141 may be formed by electroless plating (or chemical copper plating), but is not limited thereto, and may be formed by sputtering instead of chemical copper in an electroless plating layer, and may be used without limitation as long as it is a process of forming a seed for plating.

[0044] The second metal 142 may be formed to form the first metal layer 121, the first via layer 131, and the second metal layer 122, and each second metal 142 may be integrally configured. This is because the second metal 142 may be formed on the first metal 141 in the manufacturing stage to fill the first through hole 231 and the second through hole 232. The second metal 142 may be disposed so as to be in contact with the first metal 141. The second metal 142 may be formed by performing electrolytic plating (or electrolytic copper plating), but is not limited thereto, and may be formed by using any process capable of forming a metal layer without limitation.

[0045] As described above, the first metal layer 121, the first via layer 131, and the second metal layer 122 may be integrally formed, so that the central axes CA of the first metal layer 121, the first via layer 131, and the second metal layer 122 may be substantially aligned. The central axis of a certain configuration may refer to the center of a cross section of a certain configuration viewed from above, and may refer to a virtual line in the stacking direction passing through such a center. Alternatively, it may refer to a virtual line in the stacking direction passing through the center of the width of a certain configuration in a cross section cut in the stacking direction of a printed circuit board. As shown in FIG. 3, the central axis of the first metal layer 121, the central axis of the first via layer 131, and the central axis of the second metal layer 122 correspond to a virtual line passing through the center of the width of the corresponding configuration in a cross section cut in the stacking direction of a printed circuit board, and each central axis (Central Axis, CA) may be substantially aligned with each other. The central axes being substantially aligned with each other is a concept that includes a rough concept, and means that it can be determined including, for example, process errors, position deviations, and measurement errors that occur in a manufacturing process. The central axes of the first metal layer 121, the first via layer 131, and the second metal layer 122 substantially coincide with each other, which means that the first metal layer 121, the first via layer 131, and the second metal layer 122 can be formed simultaneously. That is, since the first metal layer 121, the first via layer 131, and the second metal layer 122 can be formed simultaneously, the central axes of each can substantially coincide with each other. In the case of a general printed circuit board, the via and the land part can be formed integrally, but the pad disposed under the via is not formed integrally, so that the central axis of the pad and the central axis of the via are not aligned, which is called eccentricity. The finer the pad and via are realized, the greater the effect of the eccentricity, and even defects in which the pad and the via are not connected may occur. However, in the printed circuit board according to an example, the first metal layer 121, the first via layer 131, and the second metal layer 122 are formed while simultaneously filling the first through hole 231 penetrating the first insulating layer 111 and the second through hole 232 penetrating the second barrier layer 220, so that eccentricity may not occur. Therefore, the printed circuit board according to an example can improve reliability while realizing a fine pattern.

[0046] The top surface of the first insulating layer 111 of the printed circuit board according to an example may be substantially flat. The fact that the top surface of the first insulating layer 111 is substantially flat may mean that the top surface of the first insulating layer 111 of the printed circuit board according to an example is not separately processed. Unlike a case where a method of partially removing the uppermost insulating layer to expose the metal post is used, the printed circuit board according to an example does not process the first insulating layer 111, which means that no steps are generated in the first insulating layer 111 and the top surface of the first insulating layer 111 is substantially flat.

[0047] In addition, the surface roughness of the lower surface of the first metal layer 121 can be substantially the same as the surface roughness of the upper surface of the second metal layer 122. When laminating an insulating layer on a circuit pattern, it may be common to perform a surface treatment on the upper surface of the circuit pattern to ensure adhesion with the insulating layer. However, in the printed circuit board according to the example, the first metal layer 121 and the second metal layer 122 are formed after laminating the first insulating layer 111 in the manufacturing stage, so that the adhesion can be sufficiently ensured without performing a surface treatment in the region where the first metal layer 121 and the second metal layer 122 contact the first insulating layer 111. In other words, since the surface treatment of the metal layer is not performed on the region where it contacts the first insulating layer 111, the lower surface of the first metal layer 121 and the upper surface of the second metal layer 122 can have substantially the same roughness.

[0048] The roughness of the lower surface of the first metal layer 121 can be measured by photographing a cut cross section in the lamination direction of the printed circuit board using a scanning microscope or the like. The roughness can be measured by a known method of measuring the roughness of the cut surface of the first metal layer 121 using a center line average calculation method (Ra) or a known method of measuring the roughness using a ten-point average calculation method (Rz), but is not limited thereto and can be used without limitation as long as it can measure the roughness. For example, as a non-limiting example, the average position of the lower surface of the first metal layer 121 can be displayed as a virtual line, and then the average of the absolute value of the height difference based on the average line can be measured, or the average of the height difference between the five points having the highest height and the five points having the lowest height based on the average line can be obtained. Note that the roughness measurement method is not limited thereto, but a more accurate comparison can be made only when the measurement method used to measure the roughness of the lower surface of the first metal layer 121 and the measurement method used to measure the roughness of the upper surface of the second metal layer 122 are the same.

[0049] In the printed circuit board according to an example, the first metal layer 121 and the second metal layer 122 are formed after the first insulating layer 111 is formed, so that the first metal layer 121 and the second metal layer 122 may not be embedded in the first insulating layer 111. That is, the first metal layer 121 and the second metal layer 122 may each have a structure protruding from the first insulating layer 111, and the first insulating layer 111 may not cover the side surfaces of the first metal layer 121 and the second metal layer.

[0050] In one example, the printed circuit board may further include a second insulating layer 112 disposed under the first insulating layer 111 and embedding the second metal layer 122, a third metal layer 123 disposed on or within the second insulating layer 112, and a second via layer 132 penetrating at least a portion of the second insulating layer 112 to connect the second metal layer 122 and the third metal layer 123, or between the third metal layer 123.

[0051] The second insulating layer 112, the third metal layer 123, and the second via layer 132 may correspond to the first insulating layer 111, the second metal layer 122, and the first via layer 131, respectively, and may correspond to configurations that may be included as general configurations of a printed circuit board. Descriptions of this will be omitted as they may overlap with the descriptions of the first insulating layer 111, the second metal layer 122, and the first via layer 131.

[0052] The solder resist layer 150 is disposed on the second insulating layer 112 and is disposed on the outermost side of the printed circuit board to protect the printed circuit board from the outside. The solder resist layer 150 may use a known solder resist, and the solder resist layer 150 may include a thermosetting resin and an inorganic filler dispersed in the thermosetting resin, but may not include glass fiber. The insulating resin may be a photosensitive insulating resin, and the filler may be an inorganic filler and / or an organic filler, but is not limited thereto, and other polymer materials may be used as necessary. The solder resist layer 150 may have an opening, and at least a portion of the third metal layer 123 may be exposed through the opening. The third metal layer 123 exposed through the opening may be connected to a main board or another printed circuit board, or may be connected to another element such as a semiconductor chip.

[0053] Meanwhile, the printed circuit board according to the embodiment is not limited to the configuration shown in Fig. 3 and may further include other general configurations of a printed circuit board, that is, may further include configurations that can be utilized by a person having ordinary skill in the art.

[0054] Printed circuit board manufacturing method 4 to 6 are cross-sectional views that briefly show a method for manufacturing a printed circuit board according to an example.

[0055] Referring to FIG. 4, one example of a method for manufacturing a printed circuit board may include forming a first barrier layer 210 on a carrier substrate 200, forming a second barrier layer 220 on the first barrier layer 210, and forming a first insulating layer 111 on the second barrier layer.

[0056] The carrier substrate 200 may include a core 201 and a copper foil 202 formed on one or both sides of the core 201. The core 201 is for supporting an insulating layer and / or a circuit layer when the insulating layer and / or the circuit layer are formed, and may be made of an insulating material or a metal material. The copper foil 202 may be made of copper, but is not limited thereto. The above-mentioned carrier substrate 200 is an example, and the carrier substrate may be used by anyone having ordinary skill in the art, and may be used without any particular limitation in the present disclosure as long as it is used as a support substrate and can be detached or removed thereafter.

[0057] The first barrier layer 210 can function as an etching stopper for the second barrier layer 220 in the process of processing the second barrier layer 220 described later. The first barrier layer 210 can include metal or metal oxide. The metal material can be silver (Ag), aluminum (Al), tin (Sn), gold (Au), lead (Pb), titanium (Ti), or an alloy thereof, and stainless steel (SUS) can be used. The metal oxide can be alumina (Al2O3), silica (SiO2), etc. In this case, when the metal oxide is included, it can be formed in the form of a thin film. The first barrier layer 210 can preferably include silver (Ag) or alumina (Al2O3), but is not limited thereto, and it is sufficient that the first barrier layer 210 is made of a material different from the copper foil 202 of the carrier substrate 200 and / or the second barrier layer 220 to be formed later, and can be used without any particular limitation as long as it can function as a stopper so that the first barrier layer 210 is not processed in the process of processing the second barrier layer 220.

[0058] The second barrier layer 220 is a region in which the second through-holes 232 are formed in a later step, and may correspond to a layer in which the first metal layer 121 is formed later. The second barrier layer 220 may include a metal material. As the metal material, nickel (Ni), aluminum (Al), tin (Sn), gold (Au), lead (Pb), titanium (Ti), or an alloy thereof may be used. The second barrier layer 220 may preferably include nickel (Ni), but is not limited thereto. Since it is necessary to separate the second barrier layer 220 from the first metal layer 121 later, it is sufficient that the second barrier layer 220 is made of a material different from the first metal layer 121, and any material that can be easily separated from the first metal layer 121 may be used without any particular limitation.

[0059] The description of the first insulating layer 111 overlaps with that of the printed circuit board, so a detailed description thereof will be omitted.

[0060] Referring to FIG. 5, a method for manufacturing a printed circuit board according to one example may include forming a first through hole 231 penetrating a first insulating layer 111, forming a second through hole 232 penetrating a second barrier layer 220, forming a first metal layer 121 to fill the second through hole 232, forming a first via layer 131 to fill the first through hole 231, and forming a second metal layer 122 on the first insulating layer 111.

[0061] The step of forming the first through hole 231 penetrating the first insulating layer 111 may be performed by laser drilling, mechanical drilling, etc., but is not limited thereto, and any method capable of penetrating the insulating layer may be used without limitation. Meanwhile, when performing the laser drilling, a CO2 laser or a YAG laser may be used, but is not limited thereto. The first through hole 231 may be formed by the thickness of the first insulating layer 111 so as to penetrate the upper and lower surfaces of the first insulating layer 111. When the first through hole 231 is formed by drilling, the first through hole 231 may have a tapered shape. Specifically, the first through hole 231 may have a tapered shape such that the width in the direction of the second barrier layer 220 is narrowest. As a result, in the printed circuit board according to an example, the first via layer 131 may have a tapered shape such that the width at the upper surface of the first insulating layer 111 is narrowest and the width at the lower surface of the first insulating layer 111 is widest.

[0062] The step of forming the second through-hole 232 penetrating the second barrier layer 220 may be performed by an etching process, but is not limited thereto, and any method that can remove and penetrate a portion of the metal material of the second barrier layer 220 may be used without limitation. As the etching process, wet etching or dry etching may be used. The second through-hole 232 may be formed by the thickness of the second barrier layer 220 so as to penetrate the upper and lower surfaces of the second barrier layer 220. In this case, when the second through-hole 232 is formed by wet etching, the side of the second through-hole 232 may have a curved shape, and the width of the upper surface may be narrower than the width of the lower surface. This may occur depending on the degree to which the etching solution penetrates in the wet etching process. Even if the second through-hole 232 penetrates the entire second barrier layer 220, the first barrier layer 210 exists, so that the first metal layer 121 formed thereafter may have a substantially flat upper surface. Since the first through hole 231 is formed first, and then the second through hole 232 is formed, and the second through hole 232 is subjected to wet etching to perform an isotropic process, the central axes of the first through hole 231 and the second through hole 232 can be substantially aligned, and the possibility of eccentricity errors occurring between the first metal layer 121, the first via layer, and the second metal layer 122 can be reduced.

[0063] The steps of forming the first metal layer 121, the first via layer 131, and the second metal layer 122 may include a step of forming a first metal 141 along the outer surfaces of the first through hole 231 and the second through hole 232 and the lower surface of the first insulating layer 111, a step of forming a second metal 142 on the first metal 141, and a step of removing a part of the first metal 141 and the second metal 142. Since the step of forming the first metal 141 and the step of forming the second metal 142 may each be performed in one step, the first metal layer 121, the first via layer 131, and the second metal layer 122 may be formed to be integral with each other.

[0064] The step of forming the first metal 141 may be performed by electroless plating, and the first metal 141 may function as a seed for forming the second metal 142. The step of forming the second metal 142 may be performed by electrolytic plating using the first metal 141 as a seed. Thereafter, the first metal 141 and the second metal 142 in the remaining portions except for the necessary regions may be removed to complete the step of forming the first metal 141 and the second metal 142.

[0065] 6, the method for manufacturing a printed circuit board according to an example may further include forming a second insulating layer 112 on a first insulating layer 111 to embed a second metal layer, forming a second via layer 132 penetrating at least a portion of the second insulating layer 112, forming a third metal layer 123 on the second insulating layer 112, and forming a solder resist layer 150. After forming the first metal layer 121, the first via layer 131, and the second metal layer 122, a structure may be formed to further include other structures of the printed circuit board, and the number of layers of the second insulating layer 112, the third metal layer 123, and the second via layer 132 may be designed without any restrictions.

[0066] An example method for manufacturing a printed circuit board may include removing the carrier substrate 200, the first barrier layer 210, and the second barrier layer 220.

[0067] In the step of removing the carrier substrate 200, the copper foil 202 may be removed after removing the core 201, or the core 201 and the copper foil 202 may be removed simultaneously. The step of removing the carrier substrate 200 may be performed using any known process used for carrier detachment without any limitation.

[0068] The step of removing the first barrier layer 210 may be performed by etching, but is not limited thereto. The step of removing the first barrier layer 210 may be performed by different processes depending on the constituent material of the first barrier layer 210, and any process capable of removing the constituent material of the first barrier layer 210 may be used without limitation. Different conditions may be realized depending on the material of the first barrier layer 210. Since the second through-holes 232 penetrating the second barrier layer 220 penetrate the upper and lower surfaces of the second barrier layer 220, and the first metal layer 121 is formed to fill the second through-holes 232, when the step of removing the first barrier layer 210 is performed, the upper surface of the first metal layer 121 may be exposed to the outside.

[0069] The step of removing the second barrier layer 220 may be performed by etching. Since the first barrier layer 210 and the second barrier layer 220 are made of different materials, the second barrier layer 220 may be removed under different conditions than the step of removing the first barrier layer 210. Since the second barrier layer 220 includes a different material from the first metal layer 121, the first metal layer 121 remains even after the step of removing the second barrier layer 220 is performed, so that a structure in which the first metal layer 121 protrudes from the first insulating layer 111 may be completed.

[0070] 4 to 6 show the configuration only on the lower surface of the carrier substrate 200, a similar process can be performed on the upper surface of the carrier substrate 200 to manufacture printed circuit boards having a symmetrical structure. In this case, two printed circuit boards having the same structure can be manufactured via one carrier substrate 200.

[0071] In addition, the general configuration of a printed circuit board may be further included, as detailed in the description of the printed circuit board according to an example, and may be freely added or omitted without changing the technical meaning of the present disclosure.

[0072] In this disclosure, a cross-sectional meaning can refer to the cross-sectional shape of an object cut vertically or the cross-sectional shape of an object when viewed from the side, and a planar meaning can refer to the shape of an object cut horizontally or the shape of an object when viewed from the top or bottom.

[0073] In this disclosure, for convenience, the terms upper side, top, top surface, etc. are used to mean a direction toward a surface on which electronic components can be mounted based on a cross section of a drawing, and the terms lower side, bottom, bottom surface, etc. are used to mean the opposite direction. However, this is a definition of directions for convenience of explanation, and the scope of the claims is not particularly limited by the description of such directions.

[0074] In the present disclosure, the term "connected" refers not only to a direct connection but also to an indirect connection via an adhesive layer or the like. The term "electrically connected" refers to both a physical connection and a non-connection. Furthermore, the terms "first" and "second" are used to distinguish one component from another, and do not limit the order and / or importance of the components. In some cases, the first component may be named the second component, and similarly the second component may be named the first component, without departing from the scope of the right.

[0075] The expression "one example" used in the present disclosure does not mean the same embodiment as the other, but is provided to emphasize and describe the unique features that are different from each other. However, the above-mentioned one example does not exclude being realized in combination with the features of another example. For example, even if the matter described in a particular example is not described in another example, it can be understood as being related to the other example, unless there is a description in the other example that is opposite or contradictory to the matter.

[0076] The terms used in the present disclosure are merely used to describe an example and are not intended to limit the present disclosure. In this case, the singular expression includes the plural expression unless the context clearly indicates otherwise. [Explanation of symbols]

[0077] 111 First insulating layer 112 Second insulating layer 121 1st metal layer 122 2nd metal layer 123 Third metal layer 131 First via layer 132 2nd via layer 141 First metal 142 Second metal 150 Solder resist layer 200 Carrier Board 201 Core 202 Copper foil 210 First Barrier Layer 220 Second Barrier Layer 231 First Through Hole 232 Second Through Hole 1000 electronic equipment 1010 Mainboard 1020 Chip related parts 1030 Network related parts 1040 Other parts 1050 Camera Module 1060 Antenna Module 1070 display 1080 Battery 1090 Signal Line 1100 Smartphone 1110 Smartphone internal main board 1120 Smartphone internal electronic components 1121 Smartphone Internal Antenna Module 1130 Smartphone internal camera module 1140 Smartphone internal speaker

Claims

1. A first insulating layer; a first metal layer disposed over the first insulating layer; a second metal layer disposed below the first insulating layer; a first via layer penetrating at least a portion of the first insulating layer to connect the first metal layer and the second metal layer; the first via layer has a tapered shape such that the width becomes narrower toward an upper side of the first insulating layer, A printed circuit board, wherein a top surface of the first metal layer is substantially flat and a side surface of the first metal layer has a curved surface.

2. The printed circuit board according to claim 1 , wherein the side surface of the first metal layer has a curved surface that is narrowest on an upper side and widest on a lower side.

3. 2. The printed circuit board of claim 1, wherein the first metal layer, the first via layer, and the second metal layer each include a first metal disposed at a respective boundary between the first insulating layer and the first metal layer, the first via layer, and the second metal layer.

4. The printed circuit board according to claim 3 , wherein the first metal extends along boundaries between the first insulating layer and the first metal layer, the first via layer, and the second metal layer, and is integrally formed with the first metal.

5. the first metal layer, the first via layer, and the second metal layer include a second metal disposed on the first metal; The printed circuit board according to claim 4 , wherein the second metal extends through the first metal layer, the first via layer, and the second metal layer and is integrally formed therewith.

6. The printed circuit board of claim 5 , wherein central axes of the first metal layer, the first via layer, and the second metal layer are substantially coincident.

7. the first metal layer includes a plurality of first metal layers; The printed circuit board of claim 1 , wherein the heights of the first metal layers are substantially the same as each other.

8. The printed circuit board of claim 1 , wherein a width of the bottom surface of the first metal layer is greater than a width of the top surface of the first via layer.

9. the top surface of the first insulating layer is substantially flat; 2. The printed circuit board of claim 1, wherein a roughness of the lower surface of the first metal layer is substantially the same as a roughness of the upper surface of the second metal layer.

10. a second insulating layer disposed on a lower surface of the first insulating layer and burying the second metal layer therein; a third metal layer disposed on or within the second insulating layer; The printed circuit board of claim 1 , further comprising: a second via layer extending through at least a portion of the second insulating layer.

11. forming a first barrier layer on a carrier substrate; forming a second barrier layer on the first barrier layer; forming a first insulating layer on the second barrier layer; forming a first through hole penetrating the first insulating layer; forming a second via hole through the second barrier layer; forming a first metal layer to fill the second via hole; forming a first via layer to fill the first through hole; forming a second metal layer on the first insulating layer; removing the carrier substrate, the first barrier layer, and the second barrier layer.

12. The step of forming a second through hole penetrating the second barrier layer includes: The method of claim 11 , further comprising penetrating the second barrier layer so that an upper surface and a lower surface of the second barrier layer are connected to each other.

13. The step of forming the first metal layer, the first via layer, and the second metal layer includes: The method of claim 11 , further comprising the steps of forming a first metal along outer surfaces of the first through hole and the second through hole, and forming a second metal on the first metal.

14. forming the first metal by electroless plating; The method of claim 13 , wherein the forming of the second metal is performed by electrolytic plating.

15. The method for manufacturing a printed circuit board according to claim 14 , wherein the first metal layer, the first via layer, and the second metal layer are integral.

16. The step of forming the first through hole is performed by a drilling process, The method of claim 11, wherein the forming of the second through hole is performed by an etching process.

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