Oxide semiconductor layer, semiconductor device, and method for manufacturing the semiconductor device

Abstract

To provide an oxide semiconductor layer that can be used for a semiconductor device with favorable electrical characteristics.SOLUTION: There is provided an oxide semiconductor layer which is formed over a substrate and includes indium. The oxide semiconductor layer is formed in parallel or substantially in parallel with a surface of the substrate. The oxide semiconductor layer includes a first region, a second region over the first region, and a third region over the second region. The first region is located in a range from a surface on which the oxide semiconductor layer is to be formed to greater than or equal to 0 nm to less than or equal to 3 nm in a direction substantially perpendicular to the surface. In cross-sectional observation of the oxide semiconductor layer using a transmission electron microscope, bright spots arranged in a layered manner in a direction parallel to the surface on which the oxide semiconductor layer is to be formed are observed in each of the first region, the second region, and the third region.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device each including an oxide semiconductor. Another embodiment of the present invention relates to a method for manufacturing the semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device (e.g., a touch sensor), an input / output device (e.g., a touch panel), a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices. [Background technology]

[0004] In recent years, the development of semiconductor devices has progressed, and LSIs (Large Scale Integration), CPUs (Central Processing Units), memories, etc. are mainly used in semiconductor devices. A CPU is a collection of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) that are chipped by processing a semiconductor wafer and on which electrodes that serve as connection terminals are formed.

[0005] Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and used as components in a variety of electronic devices.

[0006] In addition, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface is attracting attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, but oxide semiconductors are also attracting attention as other materials.

[0007] It is also known that a transistor using an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, Patent Document 1 discloses a low-power consumption CPU that utilizes the property of a transistor using an oxide semiconductor that the leakage current is small. For example, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the property of a transistor using an oxide semiconductor that the leakage current is small.

[0008] Furthermore, Patent Document 3 discloses a transistor with a fine structure in which a source electrode layer and a drain electrode layer are provided in contact with the upper surface of an oxide semiconductor.

[0009] Furthermore, Non-Patent Document 1 discloses CAAC-IGZO as a crystalline oxide semiconductor, and also discloses the growth mechanism of CAAC-IGZO. [Prior art documents] [Patent documents]

[0010] [Patent Document 1] JP 2012-257187 A [Patent Document 2] JP 2011-151383 A [Patent Document 3] International Publication No. 2016-125052 [Non-patent literature]

[0011] [Non-Patent Document 1] Noboru Kimizuka and Shunpei Yamazaki, “PHYSICS AND TECHNOLOGY OF CRYSTALLINE OXIDE SEMICONDUCTOR CAAC-IGZO:FUNDAMENTALS”, (USA), Wiley-SID Series in Display Technology, 2017, pp.50-150 Summary of the Invention [Problem to be solved by the invention]

[0012] An object of one embodiment of the present invention is to provide an oxide semiconductor layer that can be applied to a semiconductor device such as a transistor.An object of one embodiment of the present invention is to provide an oxide semiconductor layer that can be applied to a semiconductor device having favorable electrical characteristics.An object of one embodiment of the present invention is to provide an oxide semiconductor layer that can be applied to a highly reliable semiconductor device.An object of one embodiment of the present invention is to provide a novel oxide semiconductor layer.An object of one embodiment of the present invention is to provide a method for manufacturing a novel oxide semiconductor layer.

[0013] An object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device which can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device having a high operating speed. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another object of one embodiment of the present invention is to provide a semiconductor device in which variation in electrical characteristics of transistors is small. Another object of one embodiment of the present invention is to provide a novel semiconductor device. Another object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high productivity. Another object of one embodiment of the present invention is to provide a method for manufacturing a novel semiconductor device.

[0014] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description of the specification, drawings, and claims. [Means for solving the problem]

[0015] One embodiment of the present invention is an oxide semiconductor layer containing indium formed over a substrate, the oxide semiconductor layer being formed parallel or approximately parallel to a surface of the substrate, the oxide semiconductor layer having a first region, a second region on the first region, and a third region on the second region, the first region being positioned approximately perpendicularly to a surface on which the oxide semiconductor layer is to be formed and being located at a distance of 0 nm to 3 nm inclusive, and bright spots arranged in a layered manner in a direction parallel to the surface on which the oxide semiconductor layer is to be formed are observed in each of the first region, the second region, and the third region in cross-sectional observation of the oxide semiconductor layer using a transmission electron microscope.

[0016] In the oxide semiconductor layer, it is preferable that the second region contains zinc, the second region has crystals, and a c-axis of the crystals is approximately parallel to a normal direction to a surface on which the oxide semiconductor layer is formed.

[0017] In the oxide semiconductor layer, the c-axis orientation rate in the second region is preferably higher than the c-axis orientation rate in the first region.

[0018] In the oxide semiconductor layer, the c-axis orientation rate in the third region is preferably higher than the c-axis orientation rate in the first region.

[0019] In the oxide semiconductor layer, the indium content in the first region is preferably higher than the indium content in the second region, and the indium content in the third region is preferably higher than the indium content in the second region.

[0020] In the oxide semiconductor layer, it is preferable that the oxide semiconductor layer is formed on an insulator, and the insulator has an amorphous structure.

[0021] Another embodiment of the present invention is a semiconductor device including a first insulator over a substrate, an oxide semiconductor layer over the first insulator, a second insulator on the oxide semiconductor layer, and a conductor on the second insulator, the first insulator and the oxide semiconductor layer being formed parallel or approximately parallel to a surface of the substrate, the oxide semiconductor layer including indium, the oxide semiconductor layer including a first region, a second region over the first region, and a third region over the second region, the first region being positioned at a distance of 0 nm to 3 nm approximately perpendicularly from a surface on which the oxide semiconductor layer is to be formed, and bright spots arranged in a layered manner in a direction parallel to the surface on which the oxide semiconductor layer is to be formed are observed in each of the first region, the second region, and the third region in cross-sectional observation of the oxide semiconductor layer using a transmission electron microscope.

[0022] In the above semiconductor device, it is preferable that the second region contains zinc and has crystals whose c-axes are approximately parallel to a normal to a surface on which the oxide semiconductor layer is formed.

[0023] In the above semiconductor device, the c-axis orientation rate in the second region is preferably higher than the c-axis orientation rate in the first region.

[0024] In the above semiconductor device, the c-axis orientation rate in the third region is preferably higher than the c-axis orientation rate in the first region.

[0025] In addition, in the above semiconductor device, it is preferable that the indium content in the first region is higher than the indium content in the second region, and the indium content in the third region is higher than the indium content in the second region.

[0026] In the above semiconductor device, the first insulator preferably has an amorphous structure.

[0027] Furthermore, in the above semiconductor device, it is preferable that the semiconductor device has a third insulator covering the first insulator and the oxide semiconductor layer, an opening is formed in the third insulator reaching the oxide semiconductor layer, and the second insulator and the conductor are disposed in the opening.

[0028] In the above semiconductor device, the second insulator is preferably in contact with the third region.

[0029] Another embodiment of the present invention is a method for manufacturing a semiconductor device including an oxide semiconductor layer containing first to third metal oxides, first to third insulators, and a conductor, the method including: forming a first insulator over a substrate; forming an oxide semiconductor layer over the first insulator; performing heat treatment on the oxide semiconductor layer; processing the first insulator and the oxide semiconductor layer into an island shape; forming a third insulator to cover the first insulator and the oxide semiconductor layer; forming an opening in the third insulator that reaches the oxide semiconductor layer; forming a second insulator in the opening; a conductor is formed over a second insulator; and in a film formation step of an oxide semiconductor layer, a first metal oxide is formed over the first metal oxide, a second metal oxide is formed over the first metal oxide, and a third metal oxide is formed over the second metal oxide, each of the first metal oxide and the third metal oxide is formed by an ALD method using a precursor containing indium and an oxidizing agent, and the second metal oxide is formed by a sputtering method using a sputtering target containing indium.

[0030] In the above-described method for manufacturing a semiconductor device, it is preferable that the sputtering target contains zinc and the sputtering method is performed in an atmosphere containing oxygen.

[0031] In the above-described method for manufacturing a semiconductor device, the substrate is preferably heated to a temperature of 100° C. or higher and 350° C. or lower in the ALD method.

[0032] In the above-mentioned method for manufacturing a semiconductor device, it is preferable that, in cross-sectional observation of the oxide semiconductor layer using a transmission electron microscope, bright spots arranged in layers in a direction parallel to a surface on which the oxide semiconductor layer is formed are observed in each of the first metal oxide, the second metal oxide, and the third metal oxide.

[0033] In addition, in the above-mentioned method for manufacturing a semiconductor device, it is preferable that no clear boundary is observed between the first metal oxide and the second metal oxide, and no clear boundary is observed between the second metal oxide and the third metal oxide.

[0034] In the above-described method for manufacturing a semiconductor device, the heat treatment is preferably performed at a temperature in the range of 350° C. to 550° C. Effect of the Invention

[0035] According to one embodiment of the present invention, an oxide semiconductor layer applicable to a semiconductor device such as a transistor can be provided. Alternatively, according to one embodiment of the present invention, an oxide semiconductor layer applicable to a semiconductor device having favorable electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, an oxide semiconductor layer applicable to a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a novel oxide semiconductor layer can be provided. Alternatively, according to one embodiment of the present invention, a novel method for forming an oxide semiconductor layer can be provided.

[0036] According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with high operating speed can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to one embodiment of the present invention, a semiconductor device with less variation in electrical characteristics of transistors can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device with high productivity can be provided. According to one embodiment of the present invention, a method for manufacturing a novel semiconductor device can be provided. According to one embodiment of the present invention, a novel display device can be provided.

[0037] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims. [Brief description of the drawings]

[0038] [Figure 1] 1A to 1D are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. [Diagram 2] 2A to 2D are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. [Diagram 3] 3A to 3E are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. [Figure 4] 4A to 4D are cross-sectional views of metal oxides according to one embodiment of the present invention. [Diagram 5] 5A to 5D are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. [Figure 6] 6A to 6C are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. [Figure 7] Fig. 7A is a plan view showing an example of a semiconductor device, and Figs. 7B to 7D are cross-sectional views showing an example of the semiconductor device. [Figure 8] 8(A) and 8(B) are cross-sectional views showing an example of a semiconductor device. [Figure 9] Fig. 9A is a plan view showing an example of a semiconductor device, and Figs. 9B to 9D are cross-sectional views showing an example of the semiconductor device. [Figure 10] Fig. 10A is a plan view showing an example of a semiconductor device, and Figs. 10B to 10D are cross-sectional views showing an example of the semiconductor device. [Figure 11] 11(A) and 11(B) are cross-sectional views showing an example of a semiconductor device. [Figure 12] Fig. 12A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 12B to Fig. 12D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 13] Fig. 13A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 13B to Fig. 13D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 14] Fig. 14A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 14B to Fig. 14D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 15] Fig. 15A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 15B to Fig. 15D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 16] 16A1 to 16D2 are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 17] Fig. 17A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 17B to Fig. 17D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 18] Fig. 18A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 18B to Fig. 18D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 19] Fig. 19A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 19B to Fig. 19D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 20] FIG. 20 is a block diagram illustrating a configuration example of a semiconductor device. [Figure 21] 21A to 21H are diagrams illustrating examples of circuit configurations of memory cells. [Figure 22] FIG. 22 is a cross-sectional view showing an example of a semiconductor device. [Diagram 23] 23A and 23B are perspective views illustrating a configuration example of a semiconductor device. [Figure 24] FIG. 24 is a cross-sectional view showing an example of a semiconductor device. [Diagram 25] FIG. 25 is a block diagram illustrating the CPU. [Figure 26] 26(A) and 26(B) are perspective views of the semiconductor device. [Figure 27] 27(A) and 27(B) are perspective views of a semiconductor device. [Figure 28] 28(A) and 28(B) are diagrams showing various storage devices by hierarchical level. [Figure 29] 29(A) and 29(B) are diagrams showing an example of an electronic device, and FIGS. 29(C) to 29(E) are diagrams showing an example of a mainframe computer. [Diagram 30] FIG. 30 is a diagram showing an example of space equipment. [Diagram 31] FIG. 31 is a diagram illustrating an example of a storage system applicable to a data center. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0039] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the modes and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0040] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and the repeated explanations are omitted. In addition, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be used.

[0041] In addition, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0042] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (e.g., the order of processes or the order of stacking). In addition, an ordinal number attached to a component in one part of this specification may not match an ordinal number attached to the same component in another part of this specification or in the claims.

[0043] Note that the terms "film" and "layer" can be interchanged depending on the circumstances. For example, the term "conductive layer" can be interchanged with the term "conductive film". The term "insulating film" can be interchanged with the term "insulating layer". The term "oxide semiconductor film" can be interchanged with the term "oxide semiconductor layer". The term "conductor" can be interchanged with the term "conductive layer" or the term "conductive film" depending on the circumstances. The term "insulator" can be interchanged with the term "insulating layer" or the term "insulating film" depending on the circumstances. The term "oxide semiconductor" can be interchanged with the term "oxide semiconductor layer" or the term "oxide semiconductor film" depending on the circumstances.

[0044] In addition, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes the case of -5 degrees or more and 5 degrees or less. "Approximately parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. "Perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes the case of 85 degrees or more and 95 degrees or less. "Approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0045] The openings include, for example, grooves, slits, etc. Furthermore, a region in which an opening is formed may be referred to as an opening portion.

[0046] In addition, in the drawings used in this specification and the like, the sidewall of the insulator at the opening in the insulator is shown to be perpendicular or approximately perpendicular to the substrate surface or the surface on which the film is formed, but the sidewall may be tapered.

[0047] In this specification, the term "tapered shape" refers to a shape in which at least a part of the side of the structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle between the inclined side and the substrate surface or the surface to be formed (hereinafter, sometimes referred to as the taper angle) is less than 90°. The side of the structure and the substrate surface do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with fine irregularities.

[0048] (Embodiment 1) In this embodiment, an oxide semiconductor layer according to one embodiment of the present invention will be described. The oxide semiconductor layer according to one embodiment of the present invention is preferably used as a semiconductor layer of a transistor. When the oxide semiconductor layer according to one embodiment of the present invention is used as a semiconductor layer of a transistor, the oxide semiconductor layer preferably has a channel formation region. In addition, the oxide semiconductor layer preferably has a source region and a drain region.

[0049] [Oxide semiconductor layer] The oxide semiconductor layer of one embodiment of the present invention preferably contains a metal oxide having crystallinity. Examples of the structure of a metal oxide having crystallinity include a c-axis aligned crystal (CAAC) structure, a polycrystalline (polycrystal) structure, and a nanocrystalline (nc) structure. By using a metal oxide having crystallinity for the oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Thus, the reliability of a transistor including the oxide semiconductor layer of one embodiment of the present invention can be improved, and the reliability of a semiconductor device including the transistor can be improved.

[0050] The oxide semiconductor layer of one embodiment of the present invention particularly preferably contains a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have a c-axis orientation and are connected without being oriented in the ab-plane. When a cross section of an oxide semiconductor layer having a CAAC structure is observed using a high-resolution transmission electron microscope (TEM) image, it can be confirmed that metal atoms are arranged in a layered manner in the crystal parts. Thus, the oxide semiconductor layer having a CAAC structure can be said to have a structure having layered crystal parts.

[0051] The polycrystalline structure has crystal grain boundaries. When a heat treatment is performed after forming an oxide semiconductor layer having a polycrystalline structure, a minute gap (also referred to as a nanocrack or a microcrack) or a minute space (also referred to as a nanospace or a microspace) may be formed between the crystal parts. When a minute gap or a minute space is formed in the oxide semiconductor layer, the electric resistance of the oxide semiconductor layer increases. This is because the electric resistance of the minute gap or the minute space is very high, for example, infinite. When an oxide semiconductor layer having a minute gap or a minute space is used in a channel formation region of a transistor, the contact resistance between the oxide semiconductor layer and one or both of a source electrode and a drain electrode increases. This adversely affects the initial characteristics or reliability of the transistor. In the CAAC structure, a crystal grain boundary is not clearly observed in the ab plane, and therefore a highly reliable semiconductor device can be realized. In addition, since there are few crystal grain boundaries, an energy barrier against carrier conduction in the channel of the transistor is small, and an improvement in on-current is expected.

[0052] The crystallinity of the oxide semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED), or the analysis may be performed by combining a plurality of these techniques.

[0053] Note that the crystallinity of the semiconductor material included in the oxide semiconductor layer is not particularly limited. For example, the oxide semiconductor layer may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single crystal semiconductor (a semiconductor having a single crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). When the oxide semiconductor layer has crystallinity, deterioration of transistor characteristics may be suppressed.

[0054] Examples of the metal oxide contained in the oxide semiconductor layer of one embodiment of the present invention include indium oxide, gallium oxide, and zinc oxide. The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn). The metal oxide preferably contains two or three elements selected from indium, an element M, and zinc. Note that the element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a higher bond energy with oxygen than indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M of the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. When the element M of the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably has one or more selected from indium, gallium, and zinc. In this specification, etc., metal elements and metalloid elements may be collectively referred to as "metal elements", and the "metal element" described in this specification, etc. may include metalloid elements.

[0055] Examples of metal oxides according to an embodiment of the present invention include indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), and indium tin oxide (In-Zn oxide, also referred to as GZO). Indium aluminum zinc oxide (In-Al-Zn oxide, also written as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also written as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as IGAZO or IAGZO), etc. can be used. Alternatively, indium tin oxide containing silicon (also called ITSO), gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. can be used.

[0056] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the transistor can have a large on-current and high frequency characteristics.

[0057] The metal oxide may have one or more kinds of metal elements having a large period number in the periodic table instead of indium. Alternatively, the metal oxide may have one or more kinds of metal elements having a large period number in the periodic table in addition to indium. The greater the overlap of the orbits of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including a metal element having a large period number in the periodic table, the field effect mobility of a transistor may be increased. Examples of metal elements having a large period number in the periodic table include metal elements belonging to the fifth period and metal elements belonging to the sixth period. Specific examples of the metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0058] The metal oxide may contain one or more nonmetallic elements. When the metal oxide contains a nonmetallic element, the field-effect mobility of the transistor may be increased. Examples of the nonmetallic element include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0059] In addition, by increasing the ratio of the number of zinc atoms to the total number of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing the fluctuation of the electrical characteristics of the transistor and improving its reliability.

[0060] In addition, by increasing the ratio of the number of atoms of element M to the sum of the number of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-current can be obtained. In addition, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0061] In the present embodiment, an In-Ga-Zn oxide may be taken as an example of the metal oxide.

[0062] The oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide by using two kinds of film formation methods. For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide by using a first film formation method and a second film formation method. Note that an oxide semiconductor layer formed by using two kinds of film formation methods may be referred to as a hybrid OS.

[0063] The oxide semiconductor layer of one embodiment of the present invention has crystallinity and preferably has a CAAC structure.

[0064] In the formation of the oxide semiconductor layer of one embodiment of the present invention, a metal oxide having crystallinity is formed by the first film formation method. In particular, the metal oxide formed at this time preferably has a CAAC structure. For example, a metal oxide formed by a sputtering method is likely to have crystallinity.

[0065] When a metal oxide is formed by using the first film-forming method, a mixed layer may be formed at the interface between the metal oxide and a layer on which the metal oxide is to be formed. For example, when a sputtering method is used as the first film-forming method, the mixed layer may be formed by particles (also called sputtering particles) emitted from a target or the like, or by energy given to the substrate by the sputtering particles or the like. There is a concern that the mixed layer may hinder the crystallization of the metal oxide.

[0066] For example, when an insulating layer having silicon, for example silicon oxide, is used as a surface to be formed, there is a risk that silicon may be mixed into the metal oxide when a metal oxide is formed on the silicon oxide by using the first film formation method. There is a concern that the crystallization of the metal oxide may be hindered by the mixing of impurities such as silicon into the metal oxide.

[0067] In view of this, in one embodiment of the present invention, before forming a metal oxide by using the first film formation method, a metal oxide is formed by using the second film formation method. That is, after forming a metal oxide as a first layer by using the second film formation method, a metal oxide is formed as a second layer on the first layer by using the first film formation method. In this case, it is preferable to use a film formation method that causes less damage to a surface to be formed compared to the first film formation method as the second film formation method. By using a film formation method that causes less damage to a surface to be formed as the second film formation method, it is possible to suppress the formation of a mixed layer at the interface between the oxide semiconductor layer and a layer that is the surface to be formed of the oxide semiconductor layer. In addition, since the inclusion of impurities such as silicon in the second layer can be suppressed, the crystallinity can be possibly increased. For example, an atomic layer deposition (ALD) method and a chemical vapor deposition (CVD) method are suitable as the second film formation method because they can suppress damage to a surface to be formed compared to a sputtering method.

[0068] The first layer may be, for example, a metal oxide having a microcrystalline structure or an amorphous structure with lower crystallinity than the CAAC structure. By forming a second layer with high crystallinity on the first layer with low crystallinity, or by forming the second layer and then performing heat treatment, the crystallinity of the first layer may be increased with the second layer as a nucleus. This may increase the crystallinity of the entire oxide semiconductor layer, including the vicinity of the interface with the surface on which it is formed.

[0069] In the oxide semiconductor layer of one embodiment of the present invention, it is preferable that a metal oxide be first formed over a surface to be formed by the second film formation method, and then a metal oxide be formed above the metal oxide by the first film formation method.

[0070] Examples of the first film formation method include a sputtering method and a pulsed laser deposition (PLD) method.

[0071] Examples of the second film formation method include the ALD method, the plasma enhanced CVD (PECVD) method, the thermal CVD method, the photo-CVD method, the metal organic CVD (MOCVD) method, and the molecular beam epitaxy (MBE) method. The MBE method is a film formation method that grows a thin film having a crystal structure that reflects the crystal system of the substrate, and can be said to be one of the film formation methods that cause less damage to the surface on which the film is formed. In addition, a wet method can be used as the second film formation method. The wet method is one of the film formation methods that cause less damage to the surface on which the film is formed. For example, a spray coating method can be used as the wet method.

[0072] For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide as a first layer by using the second film formation method, and then forming a metal oxide as a second layer by using the first film formation method. Specifically, an ALD method can be used as the second film formation method, and a sputtering method can be used as the first film formation method. In addition, the metal oxide formed by the first film formation method preferably has a CAAC structure.

[0073] A third layer can also be formed on the second layer. Since the second layer has high crystallinity, the third layer can grow crystals using the crystals of the second layer as nuclei or seeds. Therefore, even if a film formation method that is likely to give crystallinity is not used as a film formation method for the third layer, the third layer can be crystallized. Here, for example, by using a film formation method that has higher coverage than the second layer as the third layer, the oxide semiconductor layer can have both high crystallinity and high coverage in the entire layer. Also, for example, by using a film formation method that causes less damage than the second layer as the third layer, damage to the second layer is reduced, and the oxide semiconductor layer can have high crystallinity in the entire layer.

[0074] In addition, the second layer has excellent crystallinity because the effect of the surface on which it is formed is reduced by providing the first layer, and therefore the third layer, which is crystallized using the second layer as a nucleus or seed, is also expected to have excellent crystallinity.

[0075] Note that the third layer is the uppermost layer of the oxide semiconductor layer, and is in contact with, for example, a gate insulating layer when the oxide semiconductor layer is used as a semiconductor layer of a transistor described later. By increasing the crystallinity of the layer in contact with the gate insulating layer, carrier mobility can be increased when the transistor is in an on state.

[0076] For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide as a first layer by using the second film formation method, forming a metal oxide as a second layer by using the first film formation method, and forming a metal oxide as a third layer by using the second film formation method. Specifically, an ALD method can be used as the second film formation method, and a sputtering method can be used as the first film formation method. In addition, the metal oxide formed by the first film formation method preferably has a CAAC structure. The ALD method is a film formation method with better coverage than the sputtering method, and the coverage of the oxide semiconductor layer can be improved by using the ALD method as the film formation method for the first layer and the third layer. Thus, the oxide semiconductor layer can be well covered over steps, openings, and the like with a high aspect ratio.

[0077] There are three types of sputtering: RF sputtering, which uses a high-frequency power source for the sputtering power supply, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used when depositing insulating films, while DC sputtering is mainly used when depositing metal conductive films. Pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, and carbides using the reactive sputtering method.

[0078] Examples of the ALD method include a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, and a plasma enhanced ALD (PEALD) method in which a plasma-excited reactant is used.

[0079] The ALD method can deposit atoms one layer at a time, and therefore has the following advantages: extremely thin films can be formed; films can be formed on structures with high aspect ratios or surfaces with large steps; films can be formed with few defects such as pinholes; films can be formed with excellent coverage; and films can be formed at low temperatures. The PEALD method may be preferable because it uses plasma, which allows films to be formed at lower temperatures. Note that some precursors used in the ALD method contain elements such as carbon or chlorine. For this reason, films formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods. The amounts of these elements can be quantified using X-ray photoelectron spectroscopy (XPS) or secondary ion mass spectrometry (SIMS). In one embodiment of the present invention, a metal oxide film formation method uses an ALD method. However, since the method employs a high substrate temperature condition during film formation and / or an impurity removal treatment, the amount of carbon and chlorine contained in the film may be smaller than that in the case of using an ALD method without employing these conditions.

[0080] The ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece, unlike a film formation method in which particles emitted from a target or the like are deposited. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio.

[0081] The plasma CVD method can produce high-quality films at relatively low temperatures. Thermal CVD is a film formation method that can reduce plasma damage to the workpiece because it does not use plasma. In addition, thermal CVD does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0082] In addition, in the CVD method, a film of any composition can be formed by changing the flow rate ratio of the raw material gases. For example, in the CVD method, a film with a continuously changing composition can be formed by changing the flow rate ratio of the raw material gases while forming a film. When forming a film while changing the flow rate ratio of the raw material gases, the time required for film formation can be shortened compared to the case of forming a film using multiple film formation chambers because no time is required for transportation or pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.

[0083] [Method for producing oxide semiconductor layer] The oxide semiconductor layer 30 can be fabricated, for example, by forming an oxide semiconductor 30a on a layer 29 that is a surface to be formed by an ALD method, forming an oxide semiconductor 30b on the oxide semiconductor 30a by a sputtering method, and forming an oxide semiconductor 30c on the oxide semiconductor 30b by an ALD method. Here, when the layer 29 is formed on a substrate, the layer 29 and the oxide semiconductor 30 can be formed parallel or approximately parallel to the surface of the substrate.

[0084] Furthermore, after the oxide semiconductor 30 is formed, it is preferable to perform heat treatment. By performing the heat treatment, the crystallinity of the oxide semiconductor 30 can be improved. The heat treatment here is not limited to heating treatment. For example, it may be heat applied during a manufacturing process.

[0085] The layer 29 is an insulating film, for example, an insulating film made of silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, etc. Also, as the layer 29, a film to be described later as an insulator of the semiconductor device can be used.

[0086] Alternatively, the layer 29 may be a conductive film. For example, the oxide semiconductor 30 may be formed on a conductive film that functions as an electrode of a semiconductor device.

[0087] The layer 29 does not need to have crystallinity. In other words, the layer 29 may have an amorphous structure. In addition, when the layer 29 has crystallinity, the layer 29 may have a crystal structure that has low lattice matching with the metal oxide of the oxide semiconductor 30.

[0088] An example of a method for manufacturing the oxide semiconductor 30 will be described with reference to FIGS.

[0089] First, an oxide semiconductor 30a is formed on the layer 29 (FIG. 1(A)). Then, an oxide semiconductor 30b is formed on the oxide semiconductor 30a (FIG. 1(B)).

[0090] The oxide semiconductor 30b is preferably formed by sputtering and has a composition suitable for forming a CAAC structure.

[0091] The oxide semiconductor 30a is preferably formed by a film formation method that causes less damage to the surface on which it is formed, as compared with the film formation method for the oxide semiconductor 30b. Here, the oxide semiconductor 30a is formed by the ALD method.

[0092] When a metal oxide film is formed by a sputtering method, the components contained in the metal oxide film may be alloyed with the components contained in the layer on which the film is formed due to damage to the surface on which the film is formed. When the alloying occurs, it is difficult to improve the crystallinity of the alloyed region even when a heat treatment described later is performed. In addition, there is a concern that the use of an oxide semiconductor layer having an alloyed region in a transistor may adversely affect the initial characteristics or reliability of the transistor. Therefore, it is preferable to suppress the alloying between the components contained in the metal oxide film and the components contained in the layer on which the film is formed.

[0093] In a method for forming an oxide semiconductor layer according to one embodiment of the present invention, after the oxide semiconductor 30a is formed over the layer 29, the oxide semiconductor 30b is formed by a sputtering method. At this time, the oxide semiconductor 30a is preferably formed by a deposition method that causes little damage to the surface on which the oxide semiconductor 30a is formed. By forming the oxide semiconductor 30a between the oxide semiconductor 30b and the layer 29 by a deposition method that causes little damage to the surface on which the oxide semiconductor 30a is formed, alloying between the components contained in the oxide semiconductor 30 and the components contained in the layer 29 can be suppressed, and the crystallinity of the oxide semiconductor 30 can be further improved.

[0094] With the above configuration, the thickness of the alloyed region can be made thin, or can be made thin enough that the alloyed region cannot be observed. For example, the thickness of the alloyed region can be set to 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and further preferably 0 nm or more and less than 0.3 nm. Note that Figs. 1(A) and 1(B) show an example in which no alloyed region is formed between the layer 29 and the oxide semiconductor 30a.

[0095] In addition, the thickness of the alloyed region may be calculated by performing a line analysis of the composition of the alloyed region and its surroundings using SIMS or energy dispersive X-ray spectroscopy (EDX).

[0096] For example, the EDX line analysis is performed on the above region and its periphery with the direction perpendicular to the surface of the oxide semiconductor 30a being the depth direction. Next, in the profile of the quantitative values ​​of each element in the depth direction obtained by the analysis, the depth at which the quantitative value of a metal (In when the oxide semiconductor 30a contains In) that is the main component of the oxide semiconductor 30a and is not the main component of the layer that becomes the surface to be formed (here, layer 29) becomes half-value is defined as the depth (position) of the interface between the above region and the oxide semiconductor 30a. Also, the depth at which the quantitative value of an element (e.g., Si) that is the main component of the layer that becomes the surface to be formed and is not the main component of the oxide semiconductor 30a becomes half-value is defined as the depth (position) of the interface between the above region and the layer that becomes the surface to be formed. From the above, the thickness of the alloyed region can be calculated.

[0097] In the oxide semiconductor layer of one embodiment of the present invention, when the thickness of the alloyed region is observed by EDX analysis, the thickness is, for example, 0 nm to 3 nm, preferably 0 nm to 2 nm, more preferably 0 nm to 1 nm, and even more preferably 0 nm to less than 0.3 nm.

[0098] For example, when a silicon oxide layer is used as the layer 29 and an oxide semiconductor 30 formed on the layer 29 is subjected to SIMS analysis, the depth at which the silicon concentration is 50% of the maximum concentration of the layer 29 is defined as the interface, and the silicon concentration is 1.0×10 21 atoms / cm 3 , preferably 5.0 x 10 20 atoms / cm 3 , more preferably 1.0×10 20 atoms / cm 3 The distance between the depth at which the thickness decreases to the interface and the depth is defined as thickness t_s2. The thickness t_s2 is preferably 3 nm or less, and more preferably 2 nm or less.

[0099] By reducing the thickness of the alloyed region, the thickness t_s2 can be set to a value within the above range.

[0100] By reducing the thickness of the alloyed region, it becomes possible to form the CAAC structure near the surface to be formed. Here, the vicinity of the surface to be formed refers to, for example, a region from more than 0 nm to 3 nm or less, preferably more than 0 nm to 2 nm or less, more preferably 1 nm to 2 nm or less, approximately perpendicularly from the surface to be formed of the oxide semiconductor 30.

[0101] The CAAC structure near the formation surface may be observed by TEM observation. For example, in a cross-sectional observation of the oxide semiconductor 30 by a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are observed near the formation surface.

[0102] Alternatively, the CAAC structure near the surface to be formed may be evaluated from a map showing the crystal orientation. The map showing the crystal orientation can be obtained, for example, by acquiring a cross-sectional TEM image, performing a fast Fourier transform (FFT) process on each region in the cross-sectional TEM image to create an FFT pattern, and calculating the direction of the crystal axis of each region. The FFT pattern reflects reciprocal lattice space information similar to an electron beam diffraction pattern. For example, a region in which the calculated crystal axis direction of each region is 70° or more and 100° or less with respect to the surface to be formed can be regarded as a CAAC structure.

[0103] When the oxide semiconductor 30a is formed by the ALD method, an oxide semiconductor layer having a microcrystalline structure or an amorphous structure, which has lower crystallinity than the CAAC structure, may be formed. That is, at the manufacturing stage shown in FIG. 1A, the oxide semiconductor 30a may have a region having lower crystallinity than the oxide semiconductor 30b.

[0104] Here, a method for forming an In-M-Zn oxide as the oxide semiconductor 30a by the ALD method will be described. The formation of a metal oxide by the ALD method will be described later in detail.

[0105] First, a source gas containing a precursor having indium is introduced into the chamber, and the precursor is adsorbed onto the surface of the layer 29. Here, the substrate is preferably heated to a temperature corresponding to the decomposition temperature of the precursor.

[0106] Next, the introduction of the raw material gas is stopped, the chamber is purged, and excess precursors and reaction products are discharged from the chamber. Next, an oxidizing agent is introduced into the chamber as a reactant, and reacted with the adsorbed precursor to form a layer of indium and oxygen (hereinafter, the first layer) by desorbing components other than indium while leaving indium adsorbed on the substrate. Ozone, oxygen, water, etc. can be used as the oxidizing agent. Next, the introduction of the oxidizing agent is stopped, the chamber is purged, and excess reactants and reaction products are discharged from the chamber.

[0107] Next, a source gas containing a precursor having element M is introduced into the chamber and adsorbed onto the first layer. Here, the substrate is preferably heated to a temperature corresponding to the decomposition temperature of the precursor.

[0108] Next, the introduction of the source gas is stopped, the chamber is purged, and excess precursors and reaction products are discharged from the chamber. Next, an oxidizing agent is introduced into the chamber as a reactant, and reacted with the adsorbed precursor to form a layer (hereinafter, a second layer) in which element M is combined with oxygen by desorbing components other than element M while leaving element M adsorbed on the substrate. Next, the introduction of the oxidizing agent is stopped, the chamber is purged, and excess reactants and reaction products are discharged from the chamber.

[0109] Next, a source gas containing a zinc-containing precursor is introduced into the chamber and adsorbed onto the second layer, where the substrate is heated to a temperature that preferably corresponds to the decomposition temperature of the precursor.

[0110] Here, in the case of a thermal ALD method using triethylindium as the indium-containing precursor, triethylgallium as the gallium-containing precursor, and diethylzinc as the zinc-containing precursor, for example, the substrate heating temperature is 100° C. or higher and 350° C. or lower, preferably 150° C. or higher and 300° C. or lower.

[0111] Next, the introduction of the raw material gas is stopped, the chamber is purged, and excess precursors and reaction products are discharged from the chamber. Next, an oxidizing agent is introduced into the chamber as a reactant, and reacted with the adsorbed precursor to form a layer of zinc and oxygen (hereinafter, the third layer) by desorbing components other than zinc while leaving zinc adsorbed on the substrate. Next, the introduction of the oxidizing agent is stopped, the chamber is purged, and excess reactants and reaction products are discharged from the chamber.

[0112] Next, the first layer is formed again on the third layer by the above-mentioned method. By repeating the above-mentioned method, an In-M-Zn oxide can be formed as the oxide semiconductor 30a on the layer 29 by the ALD method.

[0113] In the ALD method, the composition of the film obtained can be controlled by the amount of the raw material gas introduced. For example, in the ALD method, a film of any composition can be formed by adjusting the amount of the raw material gas introduced, the number of introductions (also called the number of pulses), the time required for one pulse (also called the pulse time), and the like. In addition, for example, in the ALD method, a film whose composition changes continuously can be formed by changing the raw material gas while forming the film. When forming a film while changing the raw material gas, the time required for film formation can be shortened by not requiring the time required for transport and pressure adjustment compared to the case of forming a film using multiple film formation chambers. Therefore, the productivity of semiconductor devices can be increased in some cases.

[0114] After the oxide semiconductor 30a is formed by the ALD method, an In-M-Zn oxide is formed as the oxide semiconductor 30b on the oxide semiconductor 30a by the sputtering method.

[0115] When the oxide semiconductor 30b is formed by sputtering, the mixed layer 31 is formed on or near the surface of the oxide semiconductor 30a. In addition, minute crystal regions may be formed in the mixed layer 31 due to sputtering particles or energy given to the substrate by the sputtering particles or the like during the formation of the oxide semiconductor 30b. In a subsequent heat treatment process, the mixed layer 31 or the minute crystal regions formed in the mixed layer 31 may become nuclei, and at least a part of the oxide semiconductor 30a may be crystallized.

[0116] In-M-Zn oxide can be used as a target for the sputtering method. When forming a metal oxide by the sputtering method, oxygen or a mixed gas of oxygen and a noble gas can be used as the sputtering gas. In addition, by increasing the ratio of oxygen contained in the sputtering gas, the amount of excess oxygen in the oxide film to be formed can be increased.

[0117] Furthermore, there are cases where a metal oxide having higher crystallinity can be formed as the ratio of the flow rate of oxygen gas to the total deposition gas used during deposition (hereinafter also referred to as oxygen flow rate ratio) is higher.

[0118] When a metal oxide is formed by a sputtering method, an oxygen-excess metal oxide may be formed when the ratio of oxygen contained in the sputtering gas is set to more than 30% and not more than 100%, preferably 70% to 100%. A transistor using an oxygen-excess metal oxide for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. An oxygen-deficient metal oxide is formed when the ratio of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%, when the transistor is formed. A transistor using an oxygen-deficient metal oxide for a channel formation region can have relatively high field-effect mobility.

[0119] When a metal oxide is formed by a sputtering method, the composition of the formed metal oxide may differ from that of the sputtering target. In particular, the zinc content in the formed metal oxide may decrease to about 50% compared to that of the sputtering target.

[0120] In forming the oxide semiconductor 30b by sputtering, it is preferable to heat the substrate. In forming the metal oxide, a metal oxide with high crystallinity may be formed by increasing the substrate temperature (stage temperature) during the formation of the metal oxide. In forming the oxide semiconductor 30b by sputtering, the substrate heating temperature is preferably 100°C or more and 400°C or less, and more preferably 200°C or more and 300°C or less.

[0121] Through the above steps, an oxide semiconductor 30a can be formed over the layer 29, and an oxide semiconductor 30b can be formed over the oxide semiconductor 30a, as shown in FIG.

[0122] Next, the oxide semiconductor 30c is formed on the oxide semiconductor 30b (FIG. 1C). Here, the oxide semiconductor 30c is formed by the ALD method. The formation of the oxide semiconductor 30c by the ALD method can be performed by referring to the method for forming the oxide semiconductor 30a.

[0123] When an oxide semiconductor 30c having a lower crystallinity than the CAAC structure is formed on an oxide semiconductor 30b having a CAAC structure by using an ALD method, the oxide semiconductor 30c may grow epitaxially around the oxide semiconductor 30b as a nucleus. Thus, when the oxide semiconductor 30c is formed, the oxide semiconductor 30c may have a region having the CAAC structure. In addition, the region having the CAAC structure is preferably formed over the entire oxide semiconductor 30c.

[0124] A heat treatment step may then be performed.

[0125] The temperature of the heat treatment can be, for example, 100° C. to 800° C., preferably 250° C. to 650° C., and more preferably 350° C. to 550° C. Typically, the temperature can be 400° C.±25° C. (375° C. to 425° C.). The treatment time can be 10 hours or less, or 1 minute to 5 hours, or 1 minute to 2 hours. When an RTA apparatus is used, the treatment time can be, for example, 1 second to 5 minutes. It is expected that the heat treatment can repair the gaps in the crystal parts at the atomic level of the CAAC structure of the oxide semiconductor 30b by the oxide semiconductor 30c (in other words, the crystal molecules formed by the ALD method).

[0126] There is no particular limitation on the heating device used for the heat treatment, and it may be a device that heats the workpiece by thermal conduction or thermal radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA (Rapid Thermal Anneal) device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. The LRTA device is a device that heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA device is a device that performs heat treatment using a high-temperature gas.

[0127] The heat treatment step may increase the crystallinity of the region having the CAAC structure in the oxide semiconductor 30c. If the region is formed only below the oxide semiconductor 30c after the ALD process, the heat treatment step may cause the region to expand upward (FIG. 1D). That is, the heat treatment may cause the region having the CAAC structure to be formed throughout the entire layer of the oxide semiconductor 30c.

[0128] In addition, the heat treatment process may further repair the oxide semiconductor 30b by the oxide semiconductor 30c (in other words, the crystal molecules formed by the ALD method) that fills gaps in the atomic-level crystal parts of the CAAC structure of the oxide semiconductor 30b.

[0129] It is also preferable that at least a part of the oxide semiconductor 30a is converted into a CAAC by the heat treatment process (FIG. 1(D)). It is expected that the CAAC is easily generated because the mixed layer 31 formed in the oxide semiconductor 30a during the deposition of the oxide semiconductor 30b serves as a nucleus or seed. It is preferable that the region in the oxide semiconductor 30a that is converted into a CAAC is large, and it is preferable that the CAAC is converted into a CAAC up to the vicinity of the layer 29.

[0130] Furthermore, because the CAAC process occurs from the top to the bottom of the oxide semiconductor 30a, the CAAC process can be performed up to the vicinity of the layer 29 without being limited by the material or crystallinity of the layer 29. For example, even when the layer 29 has an amorphous structure, the oxide semiconductor 30a can have high crystallinity. Thus, the method for forming an oxide semiconductor layer according to one embodiment of the present invention is particularly suitable for the case where a layer on which the oxide semiconductor layer is to be formed has an amorphous structure.

[0131] 1A to 1D are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. FIG. 1A to 1D can also be regarded as conceptual diagrams illustrating a model for forming a metal oxide film according to one embodiment of the present invention. As illustrated in FIG. 1A to 1D, the oxide semiconductor 30a and the oxide semiconductor 30c each have high crystallinity using the oxide semiconductor 30b having high crystallinity as a nucleus or seed. Specifically, the crystallinity of the oxide semiconductor 30a may be increased by heat treatment during the formation of the oxide semiconductor 30b or after the formation of the oxide semiconductor 30c. The crystallinity of the oxide semiconductor 30c may be increased by heat treatment during the formation of the oxide semiconductor 30c or after the formation of the oxide semiconductor 30c. The heat treatment has an assisting effect of increasing the crystallinity.

[0132] In this manner, in the metal oxide film formation method according to one embodiment of the present invention, the highly crystalline oxide semiconductor 30b (i.e., CAAC) can be used as a nucleus or seed to increase the crystallinity of the upper and lower oxide semiconductors (here, the oxide semiconductor 30a and the oxide semiconductor 30c). This can increase the crystallinity of the entire oxide semiconductor. In other words, the upper and lower oxide semiconductors can be grown in a solid phase using the oxide semiconductor 30b as a nucleus or seed to form an oxide semiconductor with high crystallinity. The oxide semiconductor formed using such a film formation method, here a CAAC film, can be referred to as an axial growth CAAC (AG CAAC).

[0133] In the entire oxide semiconductor 30 including the oxide semiconductor 30a and the oxide semiconductor 30c, it is preferable that a region having a CAAC structure is widely present throughout the entire layer. FIG. 2A shows the state in which the oxide semiconductor 30a, the oxide semiconductor 30b, and the oxide semiconductor 30c are crystallized. In the oxide semiconductor 30a, the region having a CAAC structure is connected to the region having a CAAC structure in the oxide semiconductor 30b through crystals. In the oxide semiconductor 30c, the region having a CAAC structure is connected to the region having a CAAC structure in the oxide semiconductor 30b through crystals. As a result, the boundary between the oxide semiconductor 30a and the oxide semiconductor 30b may not be observed. Also, the boundary between the oxide semiconductor 30b and the oxide semiconductor 30c may not be observed. The oxide semiconductor 30 may be expressed as a single layer whose interface is not clearly observed. The oxide semiconductor 30 may be expressed as a single layer.

[0134] Also, a part of the oxide semiconductor 30a or the oxide semiconductor 30c may not be crystallized. Also, a part of the oxide semiconductor 30a or the oxide semiconductor 30c may have a region with lower crystallinity than the CAAC structure remaining. The example shown in FIG. 2B shows a state in which the vicinity of the interface with the layer 29 in the oxide semiconductor 30a is not crystallized, or a region with lower crystallinity than the CAAC structure remains near the interface. FIG. 2C shows a state in which the vicinity of the surface in the oxide semiconductor 30c is not crystallized, or a region with lower crystallinity than the CAAC structure remains near the surface. FIG. 2D shows a state in which the vicinity of the interface with the layer 29 of the oxide semiconductor 30a and the vicinity of the surface of the oxide semiconductor 30c are not crystallized, or a region with lower crystallinity than the CAAC structure remains near the interface with the layer 29 of the oxide semiconductor 30a and the surface of the oxide semiconductor 30c.

[0135] By increasing the crystallinity of the oxide semiconductor layer, an increase in the electrical resistance of a transistor using the oxide semiconductor layer can be suppressed or initial characteristics (particularly, on-state current) of the transistor can be improved, which is expected to make the transistor suitable for high-speed operation. In addition, the reliability of the transistor can be increased, and the on-state current can be increased.

[0136] According to the method for forming an oxide semiconductor layer of one embodiment of the present invention, the crystallinity of metal oxides located above and below a metal oxide having a CAAC structure can be improved, and the entire oxide semiconductor layer can be made into a layer with high crystallinity.

[0137] The oxide semiconductor layer of one embodiment of the present invention has high crystallinity throughout the layer. Therefore, in the oxide semiconductor 30, the boundaries between the stacked films of the oxide semiconductor 30a, the oxide semiconductor 30b, and the oxide semiconductor 30c may not be visible. In particular, it may be difficult to confirm the boundaries between the stacked films after heat treatment. The presence or absence of the boundaries between the stacked films can be confirmed by, for example, cross-sectional TEM, cross-sectional STEM, or the like.

[0138] As described above, by using a metal oxide with a high In content for a transistor, the field effect mobility of the transistor can be increased. On the other hand, an oxide semiconductor with a high In content tends to be polycrystallized. Using a metal oxide with a polycrystalline structure for a transistor adversely affects the initial characteristics or reliability of the transistor. Therefore, by using an oxide semiconductor with a high In content for one or both of the oxide semiconductors 30a and 30c, crystals that reflect the crystal orientation of the oxide semiconductor 30b are formed, and polycrystallization can be suppressed.

[0139] In addition, it is preferable that the degree of lattice mismatch between the crystals of the oxide semiconductor 30b and the crystals of the oxide semiconductor 30a or the oxide semiconductor 30c is small. This allows the oxide semiconductor 30a or the oxide semiconductor 30c to form crystals that reflect the orientation of the crystals of the oxide semiconductor 30b. In this case, for example, in a cross-sectional observation of the oxide semiconductor 30 using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are confirmed in the oxide semiconductor 30a or the oxide semiconductor 30c.

[0140] As long as the degree of lattice mismatch between the crystals of the oxide semiconductor 30b and the crystals of the oxide semiconductor 30a or the oxide semiconductor 30c is small, the crystal structure of the oxide semiconductor 30a or the oxide semiconductor 30c is not particularly limited. The crystal structure of the oxide semiconductor 30a or the oxide semiconductor 30c may be any of a cubic system, a tetragonal system, an orthorhombic system, a hexagonal system, a monoclinic system, and a trigonal system.

[0141] [Composition of oxide semiconductor layer] As described above, the oxide semiconductor 30b preferably has a composition suitable for forming a CAAC structure. The oxide semiconductor 30b can be formed by, for example, a sputtering method. The oxide semiconductor 30b preferably contains, for example, zinc. By containing zinc, the oxide semiconductor 30b becomes a metal oxide with high crystallinity. Furthermore, the oxide semiconductor 30b preferably contains the element M in addition to zinc. By containing the element M in the oxide semiconductor 30b, for example, it is possible to suppress the formation of oxygen vacancies in the metal oxide. Therefore, it is possible to improve the reliability of a transistor to which the oxide semiconductor layer is applied. Specifically, the oxide semiconductor 30b may be a metal oxide having a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:1.2 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:0.5 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:2 [atomic ratio] or a composition close thereto, In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto, In:M:Zn=1:3:2 [atomic ratio] or a composition close thereto, or In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto. The composition close thereto includes a range of ±30% of the desired atomic ratio. It is preferable to use one or more of gallium, aluminum, and tin as the element M.

[0142] The oxide semiconductor 30b may be configured not to include the element M. For example, it may be an In-Zn oxide. Specifically, it may be configured to have a composition of In:Zn=1:1 [atomic ratio] or a composition in the vicinity thereof, In:Zn=2:1 [atomic ratio] or a composition in the vicinity thereof, or In:Zn=4:1 [atomic ratio] or a composition in the vicinity thereof. Alternatively, an indium oxide may be used. It may also be configured to include a trace amount of the element M. For example, it may be configured to have a composition of In:Ga:Zn=4:0.1:1 [atomic ratio] or a composition in the vicinity thereof, or In:Ga:Zn=2:0.1:1 [atomic ratio] or a composition in the vicinity thereof. Also, it may be configured to have a composition of In:Sn:Zn=4:0.1:1 [atomic ratio] or a composition in the vicinity thereof, or In:Sn:Zn=2:0.1:1 [atomic ratio] or a composition in the vicinity thereof.

[0143] The oxide semiconductor 30a and the oxide semiconductor 30c can be a metal oxide having a high ratio of In. The oxide semiconductor 30a and the oxide semiconductor 30c can be formed by, for example, an ALD method. In particular, it is preferable to use a metal oxide having a higher ratio of In than the element M. By using a metal oxide having a high ratio of In, when the oxide semiconductor layer is applied to a transistor, the on-current can be increased and the frequency characteristics can be improved.

[0144] Alternatively, the oxide semiconductor 30a and the oxide semiconductor 30c may be configured to not include the element M. For example, they may be In-Zn oxide. Specifically, they may have a composition of In:Zn=1:1 [atomic ratio] or a composition in the vicinity thereof, In:Zn=2:1 [atomic ratio] or a composition in the vicinity thereof, or In:Zn=4:1 [atomic ratio] or a composition in the vicinity thereof. Alternatively, indium oxide may be used. Also, the oxide semiconductor 30a and the oxide semiconductor 30c may be configured to include a trace amount of the element M. Specifically, they may have a composition of In:Ga:Zn=4:0.1:1 [atomic ratio] or a composition in the vicinity thereof, In:Ga:Zn=2:0.1:1 [atomic ratio] or a composition in the vicinity thereof, In:Sn:Zn=4:0.1:1 [atomic ratio] or a composition in the vicinity thereof, or In:Sn:Zn=2:0.1:1 [atomic ratio] or a composition in the vicinity thereof.

[0145] Moreover, the oxide semiconductor 30a and the oxide semiconductor 30c can be metal oxides having a higher proportion of In than the oxide semiconductor 30b.

[0146] For example, metal oxides having a higher Ga ratio than the oxide semiconductor 30b can be used as the oxide semiconductors 30a and 30c. For example, it is preferable to use metal oxides having a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition close thereto, metal oxides having a composition of In:Ga:Zn=1:3:2 [atomic ratio] or a composition close thereto, or metal oxides having a composition of In:Ga:Zn=1:3:4 [atomic ratio] or a composition close thereto, for the oxide semiconductors 30a and 30c, respectively. By increasing the ratio of Ga, for example, the band gaps of the oxide semiconductors 30a and 30c can be made larger than that of the oxide semiconductor 30b. As a result, the oxide semiconductor 30b is sandwiched between the oxide semiconductors 30a and 30c having a larger band gap, and the oxide semiconductor 30b mainly functions as a current path (channel). By sandwiching the oxide semiconductor 30b between the oxide semiconductors 30a and 30c, it is possible to reduce the trap levels at the interface of the oxide semiconductor 30b and in its vicinity. This makes it possible to realize a buried channel type transistor in which the channel is far from the insulating layer interface, thereby increasing the field effect mobility. In addition, the influence of the interface state that may be formed on the back channel side is reduced, and light degradation of the transistor (e.g., negative bias light degradation) can be suppressed, thereby improving the reliability of the transistor.

[0147] In the oxide semiconductor layer of one embodiment of the present invention, even when the oxide semiconductors 30a and 30c are formed using compositions that make it difficult to form a CAAC structure when they are formed into a single layer, crystal growth occurs with the oxide semiconductor 30b as a nucleus, so that the entire oxide semiconductor layer including the oxide semiconductors 30a and 30c can have the CAAC structure. Alternatively, the CAAC structure can be formed in a region including at least a part of the oxide semiconductors 30a and 30c and the oxide semiconductor 30b.

[0148] In particular, even when the oxide semiconductor 30a and the oxide semiconductor 30c have a composition with a high In content, the oxide semiconductor layer can have suitable crystallinity for use as a semiconductor layer of a transistor. In the oxide semiconductor layer of one embodiment of the present invention, the high In content can improve the on-state characteristics of the transistor, and the highly crystalline CAAC structure can improve reliability.

[0149] The oxide semiconductor 30a and the oxide semiconductor 30c may have different compositions.

[0150] The oxide semiconductor 30a and the oxide semiconductor 30c may be made of a metal oxide having the same composition as the oxide semiconductor 30b. Using the same composition may make it easier for CAAC to occur after heat treatment.

[0151] In addition, an oxide semiconductor layer having a CAAC structure formed using the above-mentioned two types of film formation methods may have one or more of a higher dielectric constant, a higher film density, and a higher film hardness than an oxide semiconductor layer having a CAAC structure formed using one type of film formation method.

[0152] By using an oxide semiconductor layer having a CAAC structure formed by using the above-described two types of film formation methods for a channel formation region of a transistor, a transistor with excellent characteristics (e.g., a transistor with high on-state current, a transistor with high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also referred to as f characteristics), a transistor with high reliability, etc.) can be realized.

[0153] The composition of the metal oxide used in the oxide semiconductor 30 can be analyzed by, for example, EDX, XPS, inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, the analysis may be performed by combining a plurality of these techniques. Note that for elements with low content, the actual content and the content obtained by analysis may differ due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0154] [Oxide semiconductor layer of transistor] The oxide semiconductor layer of one embodiment of the present invention can be used as a semiconductor layer of a transistor.

[0155] When the oxide semiconductor 30 is used as a semiconductor layer of a transistor, the thickness of the oxide semiconductor 30 is, for example, preferably 3 nm to 200 nm, more preferably 3 nm to 100 nm, further preferably 5 nm to 100 nm, further preferably 10 nm to 100 nm, further preferably 10 nm to 70 nm, further preferably 15 nm to 70 nm, further preferably 15 nm to 50 nm, further preferably 20 nm to 50 nm. In addition, in a transistor used in a finer semiconductor device, the thickness of the oxide semiconductor 30 is preferably 1 nm or more, 3 nm or more, or 5 nm or more, and 20 nm or less, 15 nm or less, 12 nm or less, or 10 nm or less.

[0156] The thickness of the oxide semiconductor 30b is preferably, for example, 200 nm or less. When the oxide semiconductor 30b has a layered structure, the thickness is preferably, for example, 1 nm to 200 nm, more preferably 1 nm to 100 nm, and even more preferably 2 nm to 100 nm.

[0157] Alternatively, if the oxide semiconductor 30b can function as a crystal nucleus, the oxide semiconductor 30b may not exist as a layer but may be an aggregate of island-like regions. In such a case, for example, the island-like regions of the oxide semiconductor 30b exist discretely.

[0158] The thickness of each of the oxide semiconductors 30a and 30c is, for example, preferably 1 nm or more and 50 nm or less, more preferably 1 nm or more and 30 nm or less, even more preferably 1 nm or more and 20 nm or less, and still more preferably 2 nm or more and 20 nm or less.

[0159] The oxide semiconductor layer of one embodiment of the present invention contains a metal oxide.

[0160] Metal oxides may have lattice defects. Lattice defects include point defects such as atomic vacancies and heteroatoms, line defects such as dislocations, surface defects such as grain boundaries, and volume defects such as voids. Factors that cause lattice defects include deviations in the ratio of the number of atoms of the constituent elements (excess or shortage of constituent atoms) and impurities.

[0161] When a metal oxide is used for the semiconductor layer of a transistor, lattice defects in the metal oxide can cause carrier generation or capture. Therefore, when a metal oxide with many lattice defects is used for the semiconductor layer of a transistor, the electrical characteristics of the transistor may become unstable. Therefore, it is preferable that the metal oxide used for the semiconductor layer of a transistor has few lattice defects.

[0162] The type of lattice defects likely to exist in a metal oxide and the amount of lattice defects vary depending on the structure of the metal oxide or the method for forming the metal oxide film.

[0163] Therefore, it is preferable to use a metal oxide with high crystallinity for the semiconductor layer of a transistor. For example, it is preferable to use a metal oxide having a CAAC structure or a metal oxide having a single crystal structure. By using such a metal oxide for a transistor, a transistor with good electrical characteristics can be realized. In addition, a highly reliable transistor can be realized.

[0164] In addition, a metal oxide that increases the on-state current of a transistor is preferably used for a channel formation region of the transistor. In order to increase the on-state current of the transistor, it is preferable to increase the mobility of the metal oxide used in the transistor. In order to increase the mobility of the metal oxide, it is necessary to improve the transmission of carriers (electrons in the case of an n-channel transistor) or reduce scattering factors that contribute to the transmission of carriers. Note that carriers flow from the source to the drain through the channel formation region. Therefore, by providing a channel formation region in which carriers can easily flow in the channel length direction, the on-state current of a transistor can be increased.

[0165] [Impurities in oxide semiconductors] Here, the influence of each impurity in an oxide semiconductor will be described.

[0166] It is preferable that the channel formation region of a transistor using an oxide semiconductor for the semiconductor layer has fewer oxygen vacancies or a lower concentration of impurities such as hydrogen, nitrogen, and metal elements than the source and drain regions. O ) and impurities may cause electrical characteristics to fluctuate and reliability to deteriorate. In addition, hydrogen near the oxygen vacancy may cause V O H may be formed, generating electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the transistor is likely to have normally-on characteristics. Therefore, in the channel formation region, V OIt is preferable that H is also reduced. In this way, the channel formation region of the transistor is a high-resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.

[0167] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the concentration of impurities in the oxide semiconductor. Examples of impurities include hydrogen, carbon, and nitrogen. Note that the impurities in the oxide semiconductor refer to, for example, elements other than the main components constituting the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0168] When an oxide semiconductor contains silicon or carbon, which is one of the group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 Less than or equal to 3×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Less than or equal to 3×10 18 atoms / cm 3 Less than 1×10, more preferably 18 atoms / cm 3 The silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 Less than or equal to 3×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Less than or equal to 3×10 18 atoms / cm 3Less than 1×10, more preferably 18 atoms / cm 3 The following applies.

[0169] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor is likely to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Less than or equal to 5×10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 The following applies.

[0170] Furthermore, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to form water, which may form oxygen vacancies. When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. Some of the hydrogen may bond with oxygen bonded to metal atoms to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 20 atoms / cm 3 Less than 5 x 10 19 atoms / cm 3less than 1×10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 less than 1×10 17 atoms / cm 3 Less than.

[0171] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels are formed and carriers are generated in some cases. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 To the following:

[0172] When an oxide semiconductor in which impurities are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0173] [c-axis orientation rate] The oxide semiconductor layer of one embodiment of the present invention has a CAAC structure. The crystallinity of the oxide semiconductor layer of one embodiment of the present invention can be evaluated using crystal orientation, for example.

[0174] The crystal orientation can be obtained from the Fast Fourier Transform (FFT) pattern by performing FFT processing on the TEM image. Specifically, the crystal axis direction can be obtained using the FFT pattern. The FFT pattern obtained by FFT processing reflects reciprocal lattice space information similar to that of the electron diffraction pattern.

[0175] By performing FFT processing for each region in the TEM image of the oxide semiconductor layer, the crystal orientation of each region can be obtained. For example, by obtaining the crystal orientation for each region within a certain area, a map showing the crystal orientation can be formed. Specifically, two spots with high intensity are observed in the FFT pattern of a region having a layered crystal part. The direction of the crystal axis of the region can be obtained from the angle of the line segment connecting the two spots.

[0176] The c-axis orientation rate can be calculated by calculating the ratio of c-axis oriented regions in a map showing crystal orientation. Note that the c-axis oriented regions are defined here as regions whose orientation coincides with the c-axis and regions whose orientation differs from the c-axis by 20° or less.

[0177] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation ratio can be calculated, for example, by TEM observation of a cross section or a plan view of the oxide semiconductor layer. The region where FFT is performed (also referred to as an FFT window) can be, for example, a circle with a diameter of 1.0 nm. Note that the region where FFT is performed is not limited to a circle.

[0178] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation rate is 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and still more preferably 95% or more.

[0179] The c-axis orientation rates of the region where the oxide semiconductor 30a is formed, the region where the oxide semiconductor 30b is formed, and the region where the oxide semiconductor 30c is formed are Rc1, Rc2, and Rc3, respectively. Rc2 is 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Rc3 is 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Rc3 / Rc1 is preferably greater than 1. Rc2 / Rc1 is preferably greater than 1.

[0180] After the oxide semiconductor 30 is produced, the boundaries between the oxide semiconductor 30a, the oxide semiconductor 30b, and the oxide semiconductor 30c may not be clearly observed.

[0181] The oxide semiconductor 30 of one embodiment of the present invention can be divided into three regions, a first region, a second region, and a third region, in this order from the top of the layer 29. Each region is a layer-like region.

[0182] The first region, the second region, and the third region each have a CAAC structure. The c-axis orientation rate of the third region is preferably higher than that of the first region. The c-axis orientation rate of the second region is preferably higher than that of the first region. The c-axis orientation rate of the third region is 80% or more, more preferably 90% or more, and even more preferably 95% or more. The c-axis orientation rate of the second region is 80% or more, more preferably 90% or more, and even more preferably 95% or more.

[0183] The first region is located at a distance of 0 nm to 3 nm from the top surface of the layer 29 , and the third region is located at a distance of 0 nm to 3 nm from the top surface of the oxide semiconductor 30 .

[0184] Or, the layer thickness in each region may be, for example, approximately the same.

[0185] [Method of producing metal oxides using the ALD method] Here, an example of a method for forming a metal oxide film having a three-layered crystal structure by the ALD method will be described with reference to Figs. 3(A) to 3(E). First, a precursor 611a is introduced into a chamber, and the precursor 611a is adsorbed onto the surface of a substrate 610 (see Fig. 3(A). Hereinafter, this process may be referred to as the first step). Here, as shown in Fig. 3(A), the precursor 611a is adsorbed onto the surface of the substrate 610, and a self-termination mechanism of the surface chemical reaction is activated, so that the precursor 611a is not further adsorbed onto the layer of the precursor 611a on the substrate 610. The appropriate range of the substrate temperature in which the self-termination mechanism of the surface chemical reaction is activated is also called the ALD window. The ALD window is determined by the temperature characteristics, vapor pressure, decomposition temperature, etc. of the precursor, and may be, for example, 100°C to 600°C, preferably 200°C to 400°C.

[0186] Next, an inert gas (argon, helium, nitrogen, etc.) is introduced into the chamber to discharge excess precursor 611a and reaction products from the chamber (hereinafter, this step may be referred to as the second step). Instead of introducing an inert gas into the chamber, excess precursor and reaction products may be discharged from the chamber by vacuum evacuation. The second step is also called purging.

[0187] Next, reactant 612a (for example, an oxidizing agent (ozone (O3), oxygen (O2), water (H2O), and plasma, radicals, ions, etc.)) is introduced into the chamber and reacted with precursor 611a adsorbed on the surface of substrate 610, so that some of the components contained in precursor 611a are desorbed while the constituent molecules of precursor 611a are still adsorbed on substrate 610 (see FIG. 3(B). Hereinafter, this step may be referred to as the third step). As a result, a layer of oxide 613a formed by oxidizing part of precursor 611a is formed on the surface of substrate 610.

[0188] Next, excess reactant 612a or reaction products are discharged from the chamber by introducing an inert gas or evacuating (hereinafter, this step may be referred to as a fourth step).

[0189] Next, precursor 611b having a metal element different from precursor 611a is introduced, and the same process as the first step is performed to cause precursor 611b to be adsorbed on the surface of the layer of oxide 613a (see FIG. 3(C)). Here, as shown in FIG. 3(C), the precursor 611b is adsorbed on the layer of oxide 613a, and a self-terminating mechanism of the surface chemical reaction is activated, so that precursor 611b is not further adsorbed on the layer of precursor 611b on substrate 610.

[0190] Next, as in the second step, excess precursor 611b and reaction products are discharged from the chamber by introducing an inert gas or evacuating the chamber.

[0191] Next, as in the third step, reactant 612b is introduced into the chamber. Here, reactant 612b may be the same as reactant 612a or may be different (see FIG. 3(D)). As a result, a layer of oxide 613b formed by oxidizing a part of precursor 611b is formed on the layer of oxide 613a.

[0192] Next, as in the fourth step, excess reactant 612b and reaction products are discharged from the chamber by introducing an inert gas or by vacuum evacuation.

[0193] Furthermore, the first to fourth steps can be performed in a similar manner to form a layer of oxide 613c on the layer of oxide 613b. In this manner, by repeatedly performing the steps of forming oxides 613a to 613c, a metal oxide having a layered crystal structure in which the stacked structure of oxides 613a to 613c is repeated can be formed (see FIG. 3E). In other words, an oxide layer can be formed by performing the first to fourth steps as one set, and by repeating this set, a layered crystal structure in which multiple oxide layers are stacked can be formed.

[0194] The thickness of the metal oxide having a layered crystal structure can be set to 1 nm or more and less than 100 nm, preferably 3 nm or more and less than 20 nm.

[0195] In addition, when forming a metal oxide having a layered crystal structure, it is preferable to perform the steps shown in Figures 3(A) to 3(E) while heating the substrate. For example, the substrate temperature can be set to 200°C or higher and 600°C or lower, preferably 300°C or higher and lower than the decomposition temperature of the precursor. When forming a film by the ALD method using multiple precursors of different types, it is preferable to set the substrate temperature to the decomposition temperature of the lowest precursor among the multiple precursors. This allows the multiple precursors used to be adsorbed to the target (e.g., substrate) without being decomposed during film formation by the ALD method.

[0196] By performing the above film formation while heating the substrate in such a temperature range, impurities such as hydrogen or carbon contained in the precursor and reactant can be removed from the metal oxide in each process from step 1 to step 4. For example, carbon in the metal oxide can be released as CO2 and CO, and hydrogen in the metal oxide can be released as H2O. Furthermore, at the same time as the removal of the impurities, rearrangement of metal atoms and oxygen atoms can be performed, and each oxide layer can be arranged with high order. Therefore, a metal oxide with a highly crystalline layered crystal structure can be formed.

[0197] In order to perform film formation while heating the substrate in the above temperature range, it is preferable that the precursor used in the film formation has a high decomposition temperature. For example, the decomposition temperature of the precursor is preferably 200° C. or more and 700° C. or less, and more preferably 300° C. or more and 600° C. or less. As a precursor having such a high decomposition temperature, it is preferable to use a precursor formed of an inorganic substance (hereinafter referred to as an inorganic precursor). Inorganic precursors generally tend to have a higher decomposition temperature than precursors formed of an organic substance (hereinafter referred to as an organic precursor), and some of them have an ALD window in the above temperature range. In addition, since inorganic precursors do not contain impurities such as hydrogen or carbon, it is possible to prevent an increase in the concentration of impurities such as hydrogen or carbon in the metal oxide film formed.

[0198] Furthermore, it is preferable to perform a heat treatment after the formation of the metal oxide film. In particular, it is preferable to perform a heat treatment continuously without exposing the film to the outside air after the formation of the film by the ALD method. The heat treatment can be performed under the conditions described in FIG. 1(A) to FIG. 1(D).

[0199] By carrying out the heat treatment in this manner, impurities such as hydrogen or carbon contained in the metal oxide can be removed. For example, carbon in the metal oxide can be released as CO2 and CO, and hydrogen in the metal oxide can be released as H2O. Furthermore, at the same time as the removal of the impurities, rearrangement of metal atoms and oxygen atoms can be carried out, improving the crystallinity. Thus, a metal oxide with a highly crystalline layered crystal structure can be formed.

[0200] In addition, after the metal oxide film is formed, it is preferable to perform a microwave treatment in an atmosphere containing oxygen to reduce the impurity concentration in the metal oxide. The impurities include, in particular, hydrogen and carbon. In the above, the metal oxide is subjected to a microwave treatment in an atmosphere containing oxygen, but the present invention is not limited to this. For example, an insulating film, more specifically, a silicon oxide film, located near the metal oxide may be subjected to a microwave treatment in an atmosphere containing oxygen.

[0201] 3, a structure in which the oxides 613a to 613c are stacked repeatedly is described, but the present invention is not limited to this. For example, a metal oxide in which a single layer, two layers, or four or more oxide layers are repeatedly formed may be used.

[0202] In addition, unless otherwise specified in the present specification and the like, when ozone, oxygen, or water is used as a reactant or an oxidant, these are not limited to a gas or molecular state, but also include those in a plasma state, a radical state, and an ion state. When forming a film using an oxidant in a plasma state, a radical state, or an ion state, a plasma ALD apparatus may be used.

[0203] In order to remove impurities such as carbon or hydrogen contained in the precursor, it is preferable to react the precursor with the oxidizing agent sufficiently. For example, the pulse time for introducing the oxidizing agent can be lengthened. Alternatively, the oxidizing agent can be introduced multiple times. When the oxidizing agent is introduced multiple times, the same type of oxidizing agent or different types of oxidizing agents can be introduced. For example, water can be introduced into the chamber as a first oxidizing agent, and then the chamber is evacuated, and ozone or oxygen not containing hydrogen can be introduced into the chamber as a second oxidizing agent, and then the chamber is evacuated.

[0204] In this way, by repeating the introduction of the oxidizing agent and the introduction of the inert gas (or evacuation) multiple times in a short period of time in the chamber, it is possible to more reliably remove excess hydrogen atoms, carbon atoms, chlorine atoms, etc. from the precursor adsorbed on the substrate surface and expel them from the chamber. Also, by increasing the number of types of oxidizing agents to two, it is possible to remove more excess hydrogen atoms, etc. from the precursor adsorbed on the substrate surface. In this way, by preventing hydrogen atoms from being incorporated into the film during film formation, it is possible to reduce the amount of water, hydrogen, etc. contained in the formed film.

[0205] The ALD method is a film formation method in which precursors and reactants are reacted with each other using thermal energy. The temperature required for the reaction of the precursors and reactants is determined by their temperature characteristics, vapor pressure, decomposition temperature, etc., and is 100°C to 600°C, preferably 200°C to 600°C, and more preferably 300°C to 600°C.

[0206] Furthermore, in addition to the above-mentioned precursor and reactant reactions, the ALD method in which a plasma-excited reactant is introduced into the chamber as a third raw material gas is sometimes called the plasma ALD method. In this case, a plasma generating device is provided at the introduction part of the third raw material gas. Inductively Coupled Plasma (ICP) can be used to generate plasma. In contrast, the ALD method in which the precursor and reactant react with thermal energy is sometimes called the thermal ALD method.

[0207] In the plasma ALD method, a plasma-excited reactant is introduced in the third step to form a film. Alternatively, the first to fourth steps are repeated while a plasma-excited reactant (second reactant) is introduced to form a film. In this case, the reactant introduced in the third step is called the first reactant. In the plasma ALD method, the second reactant used in the third raw material gas can be the same material as the oxidizing agent. That is, plasma-excited ozone, oxygen, and water can be used as the second reactant. In addition to the oxidizing agent, a nitriding agent may be used as the second reactant. Nitrogen (N2) or ammonia (NH3) can be used as the nitriding agent. A mixed gas of nitrogen (N2) and hydrogen (H2) can be used as the nitriding agent. For example, a mixed gas of 5% nitrogen (N2) and 95% hydrogen (H2) can be used as the nitriding agent. A nitride film such as a metal nitride film can be formed by forming a film while introducing plasma-excited nitrogen or ammonia.

[0208] In addition, argon (Ar), helium (He) or nitrogen (N2) may be used as a carrier gas for the second reactant. The use of a carrier gas such as argon, helium or nitrogen is preferable because it facilitates plasma discharge and facilitates the generation of a plasma-excited second reactant. In addition, when forming an oxide film such as a metal oxide film using the plasma ALD method, if nitrogen is used as a carrier gas, nitrogen may be mixed into the film and the desired film quality may not be obtained. In this case, it is preferable to use argon or helium as a carrier gas.

[0209] The ALD method can deposit extremely thin films with uniform thickness and has a high surface coverage even on uneven surfaces.

[0210] Here, the atomic arrangement in the crystal when the metal oxide with a layered crystal structure is In-M-Zn oxide will be described with reference to Figures 4(A) to 4(D). In Figures 4(B) and 4(D), atoms are represented by spheres (circles), and bonds between metal atoms and oxygen atoms are represented by lines. In Figures 4(B) and 4(D), the c-axis direction in the crystal structure of In-M-Zn oxide is represented by an arrow in the figure. Also, the ab-plane direction in the crystal structure of In-M-Zn oxide is perpendicular to the c-axis direction represented by the arrow in Figures 4(B) and 4(D).

[0211] 4A is a diagram showing an oxide 660 having an In-M-Zn oxide formed on a structure 650. Here, the structure refers to an element constituting a semiconductor device such as a transistor. The structure 650 includes a substrate, a conductor such as a gate electrode, a source electrode, and a drain electrode, an insulator such as a gate insulating film, an interlayer insulating film, and a base insulating film, a metal oxide, and a semiconductor such as silicon. FIG. 4A shows a case where a surface of the structure 650 on which a film is to be formed is arranged parallel to a substrate (or a base body, not shown).

[0212] Fig. 4(B) is an enlarged view showing the atomic arrangement in the crystal in a region 653 which is a part of the oxide 660 in Fig. 4(A). The composition of the oxide 660 shown in Fig. 4(A) and Fig. 4(B) is In:M:Zn=1:1:1 [atomic ratio], and the crystal structure is a YbFe2O4 type structure. The element M is a metal element with a valence of +3.

[0213] 4B, the crystals of the oxide 660 are formed by repeatedly stacking a layer 621 having indium (In) and oxygen, a layer 631 having an element M and oxygen, and a layer 641 having zinc (Zn) and oxygen in this order. The layer 621, the layer 631, and the layer 641 are arranged substantially parallel to the deposition surface of the structure 650. That is, the ab-plane of the oxide 660 is substantially parallel to the deposition surface of the structure 650, and the c-axis of the oxide 660 is substantially parallel to the normal direction of the deposition surface of the structure 650.

[0214] As shown in FIG. 4B, each of layers 621, 631, and 641 of the above crystals is composed of one metal element and oxygen, and is arranged with good crystallinity, which can increase the mobility of the metal oxide.

[0215] Note that the In-M-Zn oxide with an atomic ratio of In:M:Zn=1:1:1 is not limited to the structure shown in FIG. 4(B). The order of stacking the layers 621, 631, and 641 may be changed. For example, the layers 621, 641, and 631 may be repeatedly stacked in this order. Alternatively, the layers 621, 631, 641, 621, 641, and 631 may be repeatedly stacked in this order. Furthermore, part of the element M in the layer 631 may be substituted with zinc, and part of the zinc in the layer 641 may be substituted with the element M.

[0216] In the above, an example was shown in which an In-M-Zn oxide having a composition of In:M:Zn=1:1:1 [atomic ratio] was formed. (1+α) M (1-α) O3(ZnO) m Crystalline In-M-Zn oxide, represented by (α is a real number greater than 0 and less than 1, and m is a positive number), can similarly have a layered crystal structure. As an example, Figures 4(C) and 4(D) show In-M-Zn oxide with a composition of In:M:Zn = 1:3:4 [atomic ratio].

[0217] Fig. 4(C) is a diagram showing an oxide 662 having an In-M-Zn oxide formed on the structure 650. Fig. 4(D) is an enlarged view showing the atomic arrangement in the crystal in a region 654 which is a part of the oxide 662 in Fig. 4(C).

[0218] 4D, the crystals of the oxide 662 include a layer 622 having indium (In), an element M, and oxygen, a layer 641 having zinc (Zn) and oxygen, and a layer 631 having the element M and oxygen. In the oxide 662, a plurality of layers are repeatedly stacked in the order of the layer 622, the layer 641, the layer 631, and the layer 641. The layer 622, the layer 631, and the layer 641 are arranged approximately parallel to the deposition surface of the structure 650. That is, the ab-plane of the oxide 662 is approximately parallel to the deposition surface of the structure 650, and the c-axis of the oxide 662 is approximately parallel to the normal direction of the deposition surface of the structure 650.

[0219] 4D, the In-M-Zn oxide with an atomic ratio of In:M:Zn=1:3:4 may have a different structure within the range of the atomic ratio of In:M:Zn=1:3:4. For example, the stacking order of the layers 622, 631, and 641 may be changed. A part of the element M in the layer 631 may be substituted with zinc, and a part of the zinc in the layer 641 may be substituted with the element M. The layer 621 or the layer 631 may be formed instead of the layer 622.

[0220] Next, a method for forming the oxide 660 having the In-M-Zn oxide shown in FIG. 4(A) and FIG. 4(B) will be described in detail with reference to FIG. 5(A) to FIG. 6(C).

[0221] First, a source gas containing a precursor having indium is introduced into the chamber, and the precursor is adsorbed on the surface of the structure 650 (see FIG. 5(A)). Here, the source gas contains a carrier gas such as argon, helium, or nitrogen in addition to the precursor. As the precursor having indium, trimethylindium, triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) acetylacetonate, (3-(dimethylamino)propyl)dimethylindium, or the like can be used.

[0222] In addition, an inorganic precursor not containing a hydrocarbon may be used as the precursor containing indium. A halogen-based indium compound such as indium trichloride, indium tribromide, or indium triiodide may be used as the inorganic precursor containing indium. Indium trichloride has a decomposition temperature of about 500° C. or more and 700° C. or less. Therefore, by using indium trichloride, a film can be formed by the ALD method while heating the substrate at about 400° C. or more and 600° C. or less, for example, at 500° C.

[0223] Next, the introduction of the source gas is stopped, and the chamber is purged to discharge excess precursors and reaction products from the chamber.

[0224] Next, an oxidizing agent is introduced into the chamber as a reactant and reacted with the adsorbed precursor to remove components other than indium while leaving indium adsorbed on the substrate, thereby forming a layer 621 in which indium and oxygen are combined (see FIG. 5(B)). As the oxidizing agent, ozone, oxygen, water, etc. can be used. Next, the introduction of the oxidizing agent is stopped, the chamber is purged, and excess reactants and reaction products are discharged from the chamber.

[0225] Next, a source gas containing a precursor having element M is introduced into the chamber, and the precursor is adsorbed onto layer 621 (see FIG. 5(C)). The source gas contains a carrier gas such as argon, helium, or nitrogen in addition to the precursor. When gallium is used as element M, trimethylgallium, triethylgallium, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, diethylchlorogallium, dimethylgallium isopropoxide, or the like can be used as a precursor having gallium.

[0226] In addition, an inorganic precursor not containing a hydrocarbon may be used as the precursor containing gallium. A halogen-based gallium compound such as gallium trichloride, gallium tribromide, or gallium triiodide may be used as the inorganic precursor containing gallium. Gallium trichloride has a decomposition temperature of about 550° C. or more and 700° C. or less. Therefore, by using gallium trichloride, a film can be formed by the ALD method while heating the substrate at about 450° C. or more and 650° C. or less, for example, at 550° C.

[0227] Next, the introduction of the source gas is stopped, and the chamber is purged to discharge excess precursors and reaction products from the chamber.

[0228] Next, an oxidizing agent is introduced into the chamber as a reactant and reacted with the adsorbed precursor to desorb components other than element M while leaving element M adsorbed on the substrate, thereby forming layer 631 in which element M is combined with oxygen (see FIG. 5(D)). At this time, some of the oxygen constituting layer 641 may be adsorbed onto layer 631. Next, the introduction of the oxidizing agent is stopped, and the chamber is purged to discharge excess reactant and reaction products from the chamber.

[0229] Next, a source gas containing a zinc-containing precursor is introduced into the chamber, and the precursor is adsorbed onto the layer 631 (see FIG. 6(A)). At this time, a part of a layer 641 in which zinc and oxygen are combined may be formed. The source gas contains a carrier gas such as argon, helium, or nitrogen in addition to the precursor. As the precursor containing zinc, dimethylzinc, diethylzinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), zinc acetate, etc. can be used.

[0230] In addition, an inorganic precursor not containing a hydrocarbon may be used as the zinc-containing precursor. A halogen-based zinc compound such as zinc dichloride, zinc dibromide, or zinc diiodide may be used as the zinc-containing inorganic precursor. The decomposition temperature of zinc dichloride is about 450° C. or more and 700° C. or less. Therefore, by using zinc dichloride, a film can be formed by the ALD method while heating the substrate at about 350° C. or more and 550° C. or less, for example, at 450° C.

[0231] Next, the introduction of the source gas is stopped, and the chamber is purged to discharge excess precursors and reaction products from the chamber.

[0232] Next, an oxidizing agent is introduced into the chamber as a reactant and reacted with the adsorbed precursor, and components other than zinc are desorbed while zinc is still adsorbed on the substrate, forming a layer 641 in which zinc and oxygen are combined (see FIG. 6(B)). Next, the introduction of the oxidizing agent is stopped, and the chamber is purged to discharge excess reactant and reaction products from the chamber.

[0233] Next, the layer 621 is formed again over the layer 641 by the above-described method (see FIG. 6C). By repeating the above-described method, an oxide 660 can be formed over the substrate or the structure.

[0234] The precursors may contain one or both of carbon and chlorine in addition to the metal element. A film formed using a precursor containing carbon may contain carbon. A film formed using a precursor containing a halogen such as chlorine may contain a halogen such as chlorine.

[0235] As described above, by forming the oxide 660 by the ALD method, a metal oxide having a c-axis oriented approximately parallel to the normal direction of the deposition surface can be formed. With this configuration, the layered crystals of the oxide semiconductor 30 are formed approximately parallel to the channel length direction of the transistor 200, and the on-current of the transistor can be increased.

[0236] 5A to 6C are preferably performed while heating the substrate. For example, the substrate temperature can be set to 200° C. to 600° C., preferably 300° C. to the decomposition temperature of the precursor.

[0237] In order to form a film while heating the substrate in the above temperature range, it is preferable that the precursor used in the film formation has a high decomposition temperature. For example, the decomposition temperature of the precursor is preferably 200° C. or more and 700° C. or less, and more preferably 300° C. or more and 600° C. or less. As a precursor having such a high decomposition temperature, it is preferable to use an inorganic precursor. In general, inorganic precursors tend to have a higher decomposition temperature than organic precursors, so that the precursor is less likely to be decomposed even if the film is formed while heating the substrate as described above.

[0238] As the inorganic precursor, for example, the above-mentioned indium trichloride, gallium trichloride, and zinc dichloride can be used. As described above, the decomposition temperature of these precursors is about 350° C. or more and 700° C. or less, which is considerably higher than the decomposition temperature of general organic precursors. However, as described above, the decomposition temperatures of indium trichloride, gallium trichloride, and zinc dichloride are different from each other. In this way, when performing film formation by the ALD method using multiple different types of precursors, it is preferable to set the substrate temperature to the decomposition temperature of the lowest precursor among the multiple precursors. In the above example, the substrate temperature can be set within a range in which zinc dichloride, which has the lowest decomposition temperature of the precursor, does not decompose. This allows other indium trichloride and gallium trichloride to be adsorbed to the target (for example, a substrate, etc.) without being decomposed.

[0239] 5A to 6C show an example in which the layer 621 is formed as a layer containing indium, the layer 631 is formed thereon as a layer containing element M, and the layer 641 is further formed thereon as a layer containing zinc, but this embodiment is not limited to this. One of the layer 631 and the layer 641 may be formed, the layer 621 may be formed thereon, and the other of the layer 631 and the layer 641 may be formed thereon. Alternatively, one of the layer 631 and the layer 641 may be formed, the other of the layer 631 and the layer 641 may be formed thereon, and the layer 621 may be formed thereon.

[0240] When forming a metal oxide having an atomic ratio different from In:M:Zn=1:1:1 [atomic ratio], the above-mentioned layers 621, 631, and 641 can be formed appropriately according to the atomic ratio. For example, by repeating the formation of layer 641 multiple times before and after the formation of layer 631 as shown in FIG. 6(A), a stack of layers 631 and 641 having the desired number of atoms, number of layers, and thickness can be formed between two layers 621.

[0241] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in the case where a plurality of configuration examples are shown in one embodiment mode in this specification, the configuration examples can be combined as appropriate.

[0242] (Embodiment 2) In this embodiment, a semiconductor device including the oxide semiconductor described in Embodiment 1 and a method for manufacturing the semiconductor device will be described with reference to FIGS.

[0243] <Example of semiconductor device configuration> A configuration example of a semiconductor device will be described with reference to FIG. 7(A) to FIG. 8(B). FIG. 7(A) to FIG. 7(D) are plan views and cross-sectional views of a semiconductor device (transistor 200). FIG. 7(A) is a plan view of the semiconductor device. Also, FIG. 7(B) to FIG. 7(D) are cross-sectional views of the semiconductor device. Here, FIG. 7(B) is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. 7(A), and is also a cross-sectional view of the transistor 200 in the channel length direction. Also, FIG. 7(C) is a cross-sectional view of a portion indicated by a dashed line A3-A4 in FIG. 7(A), and is also a cross-sectional view of the transistor 200 in the channel width direction. Also, FIG. 7(D) is a cross-sectional view of a portion indicated by a dashed line A5-A6 in FIG. 7(A), and is also a cross-sectional view of the transistor 200 in the channel width direction. Note that some elements are omitted in the plan view of FIG. 7(A) for clarity. 8A and 8B are enlarged cross-sectional views of the transistor 200 in the channel length direction.

[0244] The transistor 200 includes a conductor 205 embedded in the insulator 216, an insulator 221 on the insulator 216 and the conductor 205, an insulator 222 on the insulator 221, an insulator 224 on the insulator 222, an oxide semiconductor 230 on the insulator 224, a conductor 242a and a conductor 242b on the oxide semiconductor 230, an insulator 271a on the conductor 242a, an insulator 271b on the conductor 242b, an insulator 250 on the oxide semiconductor 230, and a conductor 260 on the insulator 250.

[0245] The oxide semiconductor 230 has a region functioning as a channel formation region of the transistor 200. The conductor 260 has a region functioning as a first gate electrode (which can also be referred to as an upper gate electrode or a top gate electrode) of the transistor 200. The insulator 250 has a region functioning as a first gate insulator of the transistor 200. The conductor 205 has a region functioning as a second gate electrode (which can also be referred to as a lower gate electrode or a bottom gate electrode) of the transistor 200. The insulators 224, 222, and 221 each have a region functioning as a second gate insulator of the transistor 200. The conductor 242a has a region functioning as one of a source electrode and a drain electrode of the transistor 200. The conductor 242b has a region functioning as the other of the source electrode and the drain electrode of the transistor 200.

[0246] An insulator 275 is provided on the insulator 271a and the insulator 271b, and an insulator 280 is provided on the insulator 275. Openings reaching the insulator 222 and the oxide semiconductor 230 are formed in the insulator 280 and the insulator 275, and the openings overlap with a region between the conductor 242a and the conductor 242b. The insulator 250 and the conductor 260 are disposed inside the openings provided in the insulator 280 and the insulator 275. An insulator 282 is provided in contact with an upper surface of the insulator 280, an upper end of the insulator 250, and an upper surface of the conductor 260. An insulator 283 is provided on the insulator 282. An insulator 214 is provided below the insulator 216 and the conductor 205. An insulator 212 is provided below the insulator 214. Insulator 212, insulator 214, insulator 280, insulator 282, insulator 283, and insulator 285 function as interlayer films.

[0247] An opening reaching the conductor 242a is formed in the insulators 285, 283, 282, 280, 275, and 271a, and the conductor 240a and the insulator 241a are provided in the opening. The insulator 241a is provided in contact with the side wall of the opening, and the conductor 240a is provided inside the insulator 241a. Also, an opening reaching the conductor 242b is formed in the insulators 285, 283, 282, 280, 275, and 271b, and the conductor 240b and the insulator 241b are provided in the opening. The insulator 241b is provided in contact with the side wall of the opening, and the conductor 240b is provided inside the insulator 241b. The conductor 240a and the conductor 240b function as vias that connect a wiring or the like provided over the transistor 200 to the source or drain of the transistor 200.

[0248] Here, the oxide semiconductor 230 corresponds to the oxide semiconductor 30 described in Embodiment 1, and the insulator 224 corresponds to the layer 29 described in Embodiment 1. For details of the oxide semiconductor 230 and the insulator 224, the description in Embodiment 1 can be referred to. In this manner, by using the oxide semiconductor 230, which is an axial growth CAAC, for the channel formation region of the transistor 200, a transistor with favorable on-state current, field-effect mobility, S value, frequency characteristics, and reliability can be provided.

[0249] 8A, the oxide semiconductor 230 can have a structure including an oxide semiconductor 230a over the insulator 224, an oxide semiconductor 230b over the oxide semiconductor 230a, and an oxide semiconductor 230c over the oxide semiconductor 230b. Here, the oxide semiconductor 230a corresponds to the oxide semiconductor 30a described in Embodiment 1, the oxide semiconductor 230b corresponds to the oxide semiconductor 30b described in Embodiment 1, and the oxide semiconductor 230c corresponds to the oxide semiconductor 30c described in Embodiment 1. Therefore, the description in Embodiment 1 can be referred to for details of the oxide semiconductors 230a to 230c.

[0250] A channel formation region and a source region and a drain region sandwiching the channel formation region are formed in the oxide semiconductor 230. At least part of the channel formation region overlaps with the conductor 260. The source region overlaps with the conductor 242a, and the drain region overlaps with the conductor 242b. Note that the source region and the drain region can be interchanged.

[0251] The channel formation region is a high-resistance region with a low carrier concentration because it has fewer oxygen vacancies or a lower impurity concentration than the source and drain regions. Therefore, the channel formation region can be said to be i-type (intrinsic) or substantially i-type.

[0252] In addition, the source and drain regions are low-resistance regions with high carrier concentrations due to a large amount of oxygen vacancies or a high concentration of impurities such as hydrogen, nitrogen, and metal elements. In other words, the source and drain regions are n-type regions (low-resistance regions) with a high carrier concentration compared to the channel formation region.

[0253] The carrier concentration in the channel formation region is 1×10 18 cm -3 Below, 1×10 17 cm -3 Less than 1×10 16 cm -3 Less than 1×10 15 cm -3 Less than 1×10 14 cm -3 Less than 1×10 13 cm -3 Less than 1×10 12 cm -3 Less than 1×10 11 cm -3 Less than or equal to 1×10 10 cm -3 The lower limit of the carrier concentration in the channel formation region is not particularly limited, but is preferably less than 1×10 -9 cm -3 It can be said that:

[0254] Note that when the carrier concentration of the oxide semiconductor 230 is reduced, the impurity concentration in the oxide semiconductor 230 is reduced to reduce the density of defect states. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that an oxide semiconductor (or metal oxide) with a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor (or metal oxide).

[0255] In order to stabilize the electrical characteristics of the transistor 200, it is effective to reduce the impurity concentration in the channel formation region in the oxide semiconductor 230. In order to reduce the impurity concentration in the oxide semiconductor 230, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like. Note that the impurities in the oxide semiconductor 230 refer to, for example, any element other than the main component constituting the oxide semiconductor 230. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0256] In addition, it may be difficult to clearly detect the boundaries between the regions in the oxide semiconductor 230. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may change continuously within each region without being limited to a stepwise change from region to region. That is, the concentrations of metal elements and impurity elements such as hydrogen and nitrogen may decrease in a region closer to the channel formation region.

[0257] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in a region in which a channel is formed in the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may be reduced. OH) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the transistor is likely to have normally-on characteristics (a channel exists even when no voltage is applied to the gate electrode, and a current flows through the transistor). Therefore, in the channel formation region of the oxide semiconductor, impurities, oxygen vacancies, and V O It is preferable that H be reduced as much as possible. In other words, it is preferable that the carrier concentration of a channel formation region in the oxide semiconductor be reduced and the channel formation region be i-type (intrinsic) or substantially i-type.

[0258] In response to this problem, an insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor and heat treatment is performed. In this way, oxygen is supplied from the insulator to the oxide semiconductor, and oxygen vacancies and V O H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or the drain region, the on-current of the transistor 200 may decrease or the field effect mobility may decrease. Furthermore, if the amount of oxygen supplied to the source region or the drain region varies within the substrate surface, the characteristics of a semiconductor device having the transistor may vary. Furthermore, if the amount of oxygen supplied from the insulator to the oxide semiconductor becomes excessively large, the electrical characteristics and reliability of the transistor may be adversely affected. Furthermore, oxygen may diffuse into a conductor such as a gate electrode, a source electrode, or a drain electrode, and the conductor may be oxidized, resulting in a loss of conductivity.

[0259] First, an insulator having a hydrogen barrier property is formed near the transistor 200, and V O It is preferable to reduce H.

[0260] At least one of the insulator 212, the insulator 214, the insulator 221, the insulator 222, the insulator 275, the insulator 282, and the insulator 283 preferably functions as a barrier insulator against hydrogen. At least one of the insulator 212, the insulator 214, the insulator 221, the insulator 222, the insulator 275, the insulator 282, and the insulator 283 preferably functions as a barrier insulator against impurities. At least one of the insulator 212, the insulator 214, the insulator 221, the insulator 222, the insulator 275, the insulator 282, and the insulator 283 preferably functions as a barrier insulator against oxygen. Note that it is not necessarily necessary to provide all of the insulator 212, the insulator 214, the insulator 221, the insulator 222, the insulator 275, the insulator 282, and the insulator 283. If the barrier property against hydrogen, impurities, oxygen, and the like is sufficient, the insulator can be appropriately selected from the insulator 212, the insulator 214, the insulator 221, the insulator 222, the insulator 275, the insulator 282, and the insulator 283. For example, a structure can be used in which the insulator 216 and the conductor 205 are formed in contact with the upper surface of the insulator 212 without providing the insulator 214.

[0261] In this specification etc., a barrier insulator refers to an insulator that has barrier properties. In this specification etc., having barrier properties refers to having a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that has low permeability of a corresponding substance, or a function of suppressing the diffusion of a corresponding substance). Alternatively, it refers to having a function of capturing or fixing a corresponding substance inside the insulator (also referred to as gettering). Note that hydrogen when described as a corresponding substance includes, for example, hydrogen atoms, hydrogen molecules, water molecules, and OH. - In addition, impurities when described as a corresponding substance refer to impurities in the channel formation region or semiconductor layer unless otherwise specified, and refer to at least one of, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. In addition, oxygen when described as a corresponding substance refers to at least one of, for example, oxygen atoms, oxygen molecules, etc.

[0262] As an insulator having a function of suppressing hydrogen diffusion, it is preferable to use, for example, silicon nitride or silicon nitride oxide.Also, for example, aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, oxide containing aluminum and hafnium (hafnium aluminate), oxide containing hafnium and zirconium (hafnium zirconium oxide), gallium oxide, indium gallium zinc oxide, etc. may be used.

[0263] It is preferable to use an insulator having a function of suppressing diffusion of hydrogen for the insulators 212, 221, 275, and 283. For example, silicon nitride, which has a higher hydrogen barrier property, can be used for the insulators 212, 221, 275, and 283.

[0264] As the insulator having the function of capturing or fixing hydrogen, it is preferable to use a metal oxide such as, for example, an oxide containing hafnium, an oxide containing aluminum, an oxide containing aluminum and hafnium (hafnium aluminate), or magnesium oxide. It is preferable that the insulator having the function of capturing or fixing hydrogen has an amorphous structure. In such a metal oxide having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. In other words, it can be said that the metal oxide having an amorphous structure has a high ability to capture or fix hydrogen. By adding silicon to the above metal oxide, polycrystallization can be suppressed and it can be made easier to make it amorphous. Therefore, it is preferable to use a metal oxide in which silicon is added to the above metal oxide (for example, hafnium silicate, aluminum silicate, etc.).

[0265] It is preferable to use an insulator having a function of trapping or fixing hydrogen for the insulator 214, the insulator 222, and the insulator 282. For example, aluminum oxide may be used for the insulator 214 and the insulator 282. Also, for example, it is preferable to use hafnium oxide, which is a high dielectric constant (high-k) material, for the insulator 222 functioning as a second gate insulator.

[0266] Further, the inorganic insulators given as insulators having a function of suppressing hydrogen diffusion and insulators having a function of capturing or fixing hydrogen also have a barrier property against oxygen.

[0267] 8A, an insulator 212 having a function of suppressing diffusion of hydrogen and an insulator 214 having a function of capturing or fixing hydrogen are preferably provided under the transistor 200. Providing the insulator 212 under the transistor 200 can suppress diffusion of hydrogen from a lower layer of the transistor 200. Providing the insulator 214 over the insulator 212 can capture or fix hydrogen contained in the insulator 216 or the like to the insulator 214. This can reduce the hydrogen concentration in the oxide semiconductor 230 and its vicinity.

[0268] 8A, an insulator 221 having a function of suppressing diffusion of hydrogen and an insulator 222 having a function of capturing or fixing hydrogen are preferably provided in the lower part of the transistor 200. By providing the insulator 221 in the lower part of the transistor 200, diffusion of hydrogen from the lower layer of the transistor 200 can be suppressed. By providing the insulator 222 over the insulator 221, hydrogen contained in the insulator 224 or the like can be captured or fixed in the insulator 222. As a result, the hydrogen concentration in the oxide semiconductor 230 and its vicinity can be reduced.

[0269] 8A, an insulator 275 is preferably provided to cover the oxide semiconductor 230, the conductor 242a, the conductor 242b, and the like. By providing the insulator 275 in this manner, diffusion of hydrogen from the insulator 280 to the oxide semiconductor 230, the conductor 242a, the conductor 242b, and the like can be suppressed.

[0270] 8A, an insulator 282 having a function of trapping or fixing hydrogen and an insulator 283 having a function of suppressing diffusion of hydrogen are preferably provided over the transistor 200. Providing the insulator 283 over the transistor 200 can suppress diffusion of hydrogen from an upper layer of the transistor 200. Providing the insulator 282 under the insulator 283 can allow hydrogen contained in the insulator 280 or the like to be trapped or fixed to the insulator 282. This can reduce the hydrogen concentration in the oxide semiconductor 230 and its vicinity.

[0271] In this manner, by surrounding the top and bottom of the transistor 200 with barrier insulators against hydrogen, the diffusion of hydrogen into the oxide semiconductor is reduced, and the V O It is possible to reduce H. As a result, the electrical characteristics and reliability of the transistor 200 can be improved.

[0272] Furthermore, oxygen that is released by heating is preferably contained in the insulator 280. When the oxygen is supplied to the oxide semiconductor 230 through the insulator 250 by heat treatment, oxygen vacancies in the channel formation region can be reduced.

[0273] Alternatively, as shown in FIG. 8A, the insulator 282 may have a layered structure of an insulator 282a and an insulator 282b on the insulator 282a.

[0274] In this case, the insulator 282b is formed by sputtering in an atmosphere containing oxygen gas, so that oxygen can be added to the insulator 280. At this time, by forming the insulator 282b with the insulator 282a formed, oxygen is added through the insulator 282a, so that the amount of oxygen added to the insulator 280 can be controlled. If the insulator 282a is thick, the addition of oxygen is more likely to be hindered, and the amount of oxygen injected into the insulator 280 is reduced. If the insulator 282a is thin, the addition of oxygen is less likely to be hindered, and the amount of oxygen injected into the insulator 280 is increased. For example, by setting the thickness of the insulator 282a to be 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, a suitable amount of oxygen can be supplied to the insulator 280.

[0275] In addition, in order to prevent oxygen from being added to the insulator 280 when the insulator 282a is formed, it is preferable to form the insulator 282a by using the ALD method. In order to make the thickness of the insulator 282a as thin as described above, it is preferable to form the insulator 282a by using the ALD method. The ALD method includes a thermal ALD method in which a reaction between a precursor and a reactant is performed using only thermal energy, and a plasma enhanced ALD method in which a plasma excited reactant is used.

[0276] Some precursors used in the ALD method contain carbon and the like. Therefore, a film formed by the ALD method may contain more impurities such as carbon than a film formed by other film formation methods. Therefore, the insulator 282a may have a higher carbon concentration than the insulator 282b. The amount of impurities can be quantified using SIMS, XPS, or Auger Electron Spectroscopy (AES).

[0277] For example, when both the insulator 282a and the insulator 282b contain aluminum oxide, the insulator 282a may have a higher carbon concentration than the insulator 282b. In this case, the carbon concentration of the insulator 282a is found to be 1×10 18atoms / cm 3 That's it, 1×10 21 atoms / cm 3 The insulator 282a preferably has a carbon concentration of 1×10 19 atoms / cm 3 That's it, 1×10 21 atoms / cm 3 The carbon concentration of the insulator 282b may be in the range of 1×10 to 1×10. 20 atoms / cm 3 The insulator 282b has a carbon concentration of 4.46×10 17 atoms / cm 3 That's it, 1×10 19 atoms / cm 3 It may have the following areas:

[0278] As described above, by performing heat treatment on the insulator 280 in a state in which oxygen released by heating is contained, a suitable amount of oxygen can be supplied to the oxide semiconductor 230 via the insulator 250. In the heat treatment, the insulators 282 and 283 having a barrier property against oxygen are formed on the insulator 280, so that the oxygen contained in the insulator 280 can be prevented from diffusing excessively from the insulator 280. Furthermore, the insulator 275 having a barrier property against oxygen is formed between the insulator 280 and the oxide semiconductor 230, the conductor 242a, and the conductor 242b, so that the oxygen contained in the insulator 280 can be prevented from diffusing excessively from the insulator 280. Furthermore, by performing the heat treatment in a state in which openings are formed in parts of the insulators 280, 282, and 283, part of the oxygen contained in the insulator 280 can be diffused outward, and the amount of oxygen supplied from the insulator 280 to the oxide semiconductor 230 can be adjusted.

[0279] Here, the insulator 250 preferably has a structure that allows oxygen to diffuse from the insulator 280 to the oxide semiconductor 230 and suppresses oxidation of the conductors 242a, 242b, and 260.

[0280] As shown in FIGS. 7B and 7C, the insulator 250 is disposed in openings formed in the insulator 280 and the insulator 275. In the openings, the insulator 250 is formed in contact with a top surface of the insulator 222, a side surface of the insulator 224, a side surface and a top surface of the oxide semiconductor 230, a side surface of the conductor 242a, a side surface of the conductor 242b, a side surface of the insulator 271a, a side surface of the insulator 271b, a side surface of the insulator 275, and a side surface of the insulator 280. As shown in FIG. 8A, when the oxide semiconductor 230 includes the oxide semiconductors 230a to 230c, the insulator 250 is in contact with a side surface of the oxide semiconductor 230a, a side surface of the oxide semiconductor 230b, and a top surface and a side surface of the oxide semiconductor 230c. Here, it is preferable to increase the crystallinity of the oxide semiconductor 230c (the oxide semiconductor 30c shown in FIG. 2A) as described in Embodiment 1. Since the oxide semiconductor 230c has a large contact area with the insulator 250, the carrier mobility can be high when the transistor 200 is on.

[0281] Here, as shown in FIG. 8A, the insulator 250 preferably has a stacked structure of an insulator 250a in contact with the oxide semiconductor 230, an insulator 250b over the insulator 250a, and an insulator 250c over the insulator 250b.

[0282] The insulator 250b is preferably made of silicon oxide or silicon oxynitride having a high dielectric strength. To improve the dielectric strength, the insulator 250b may be thicker than the insulator 250a and the insulator 250d. By using such an oxide insulator, oxygen can be diffused in the insulator 250b by performing a high-temperature heat treatment. Thus, by performing a heat treatment, oxygen contained in the insulator 280 can be supplied to the oxide semiconductor 230 through the insulator 250b. Note that in this specification and the like, an oxynitride refers to a material having a composition that contains more oxygen than nitrogen, and a nitride oxide refers to a material having a composition that contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material having a composition that contains more oxygen than nitrogen, and silicon nitride oxide refers to a material having a composition that contains more nitrogen than oxygen.

[0283] In order to suppress oxidation of the conductor 242a, the conductor 242b, and the conductor 260, it is preferable to provide an oxygen barrier insulator near each of the conductor 242a, the conductor 242b, and the conductor 260. For example, it is preferable to provide an oxygen barrier insulator for the insulator 250a and the insulator 250c.

[0284] The insulator 250a preferably has a barrier property against oxygen. The insulator 250a is preferably less permeable to oxygen than the insulator 250b. The insulator 250a has a region in contact with the side surface of the conductor 242a and the side surface of the conductor 242b. The insulator 250a has a barrier property against oxygen, which can suppress the side surfaces of the conductor 242a and the conductor 242b from being oxidized and the formation of an oxide film on the side surface. This can suppress a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 200. Furthermore, with this structure, the amount of oxygen in the insulator 250b absorbed by the conductor 242a and the conductor 242b can be reduced. Therefore, an appropriate amount of oxygen can be supplied from the insulator 250b to the oxide semiconductor 230, and oxygen vacancies in the channel formation region of the oxide semiconductor 230 can be reduced.

[0285] Furthermore, by providing the insulator 250a between the insulator 280 and the insulator 250b and between the insulator 250b and the oxide semiconductor 230, excessive supply of oxygen from the insulator 280 to the oxide semiconductor 230 can be suppressed and an appropriate amount of oxygen can be supplied to the oxide semiconductor 230. Thus, the amount of oxygen in the channel formation region of the oxide semiconductor 230 and its vicinity can be controlled to an appropriate amount, thereby preventing the transistor 200 from becoming excessively normally-off and improving reliability. Furthermore, excessive oxidation of the source and drain regions can be suppressed, which leads to a decrease in the on-state current or the field-effect mobility of the transistor 200.

[0286] Therefore, the insulator 250a preferably has a thickness that does not excessively hinder the diffusion of oxygen from the insulator 280 to the insulator 250b and the diffusion of oxygen from the insulator 250b to the oxide semiconductor 230. For example, the thickness of the insulator 250a is preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, more preferably 0.5 nm to less than 3.0 nm, and further preferably 0.5 nm to 2.0 nm.

[0287] As described above, it is preferable to appropriately diffuse oxygen from the insulator 280 to the insulator 250b and from the insulator 250b to the oxide semiconductor 230, and to suppress the diffusion of oxygen from the insulator 250b to the conductor 242a and the conductor 242b as much as possible. In the semiconductor device according to this embodiment, the contact area between the insulator 250a and the conductor 242a and the contact area between the insulator 250a and the conductor 242b are much smaller than the contact area between the insulator 250a and the oxide semiconductor 230. In other words, it is estimated that the amount of oxygen diffusing from the insulator 250b to the conductor 242a and the conductor 242b via the insulator 250a is smaller than the amount of oxygen diffusing from the insulator 250b to the oxide semiconductor 230 via the insulator 250a. Therefore, by controlling the amount of oxygen contained in the insulator 280 so that an appropriate amount of oxygen is supplied from the insulator 280 to the insulator 250b and the oxide semiconductor 230, the oxidation of the conductor 242a and the conductor 242b can be reduced.

[0288] The insulator 250a in contact with the channel formation region in the oxide semiconductor 230 preferably has a function of capturing hydrogen or fixing hydrogen. This can reduce the hydrogen concentration in the channel formation region of the oxide semiconductor 230. O By reducing H, the channel formation region can be made i-type or substantially i-type.

[0289] It is also preferable to use a high dielectric constant (high-k) material for the insulator 250a. An example of a high-k material is an oxide containing one or both of aluminum and hafnium. By using a high-k material for the insulator 250a, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. It is also possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator.

[0290] From the above, it is preferable to use an oxide containing one or both of aluminum and hafnium as the insulator 250a, and it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium. Since an amorphous film of aluminum oxide can be formed relatively easily using the ALD method, it is even more preferable to use aluminum oxide having an amorphous structure. In this embodiment, an aluminum oxide film is used as the insulator 250a. Since aluminum oxide has the function of capturing or fixing hydrogen and has a barrier property against oxygen, it can be suitably used as the insulator 250a.

[0291] The insulator 250c also preferably has a barrier property against oxygen. The insulator 250c is provided between the channel formation region of the oxide semiconductor 230 and the conductor 260, and between the insulator 280 and the conductor 260. With this structure, oxygen contained in the channel formation region of the oxide semiconductor 230 can be prevented from diffusing to the conductor 260 and forming oxygen vacancies in the channel formation region of the oxide semiconductor 230. In addition, oxygen contained in the oxide semiconductor 230 and oxygen contained in the insulator 280 can be prevented from diffusing to the conductor 260 and oxidizing the conductor 260. The insulator 250c is preferably at least less permeable to oxygen than the insulator 250b. The insulator 250c preferably has a function of preventing diffusion of hydrogen. This can prevent impurities such as hydrogen contained in the conductor 260 from diffusing to the oxide semiconductor 230. For example, a silicon nitride film is preferably used as the insulator 250c.

[0292] Also, as shown in FIG. 8B, a structure may be used in which an insulator 250d is provided on the insulator 250b. In this case, an insulator that can be used for the insulator 250a can be provided as the insulator 250d. For example, hafnium oxide can be used as the insulator 250d. Here, by providing the insulator 250d between the insulator 250c and the insulator 250b, hydrogen contained in the insulator 250b and the like can be captured and fixed more effectively. Also, a structure in which the insulator 250a, the insulator 250b, and the insulator 250d are provided without providing the insulator 250c can be used.

[0293] With the above-described structure, the channel formation region can be made i-type or substantially i-type, and the source region and drain region can be made n-type, so that a semiconductor device having good electrical characteristics can be provided. Furthermore, with the above-described structure, the semiconductor device can have good electrical characteristics even when miniaturized or highly integrated. Furthermore, miniaturizing the transistor 200 can improve frequency characteristics. Specifically, the cutoff frequency can be improved.

[0294] The insulators 250a to 250d function as part of the first gate insulator. The insulators 250a to 250d are provided in an opening formed in the insulator 280 together with the conductor 260. In order to miniaturize the transistor 200, it is preferable that the thicknesses of the insulators 250a, 250c, and 250d are each thin. The thicknesses of the insulators 250a, 250c, and 250d are each preferably 0.1 nm to 20 nm, more preferably 0.1 nm to 10 nm, more preferably 0.5 nm to 5.0 nm, more preferably 1.0 nm to less than 5.0 nm, and further preferably 1.0 nm to 3.0 nm. Note that the insulators 250a, 250c, and 250d each may have a region having the above-mentioned thickness at least in a portion thereof.

[0295] In order to make the film thicknesses of the insulators 250a to 250d as thin as described above, it is preferable to deposit the insulators 250a to 250d by an ALD method. Also, in order to form the insulators 250a to 250d in openings of the insulator 280 and the like with good coverage, it is preferable to deposit the insulators 250a to 250d by an ALD method.

[0296] In the above, the insulator 250 has been described as having a three-layer structure of the insulators 250a to 250c or a four-layer structure of the insulators 250a to 250d, but the present invention is not limited to this. The insulator 250 can have at least one of the insulators 250a to 250d. By configuring the insulator 250 as one, two, or three layers of the insulators 250a to 250d, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0297] In the transistor 200, the conductor 205 is arranged to overlap with the oxide semiconductor 230 and the conductor 260. The conductor 205 can be formed using any of the conductive materials described in the <<Conductor>> section. Here, the conductor 205 is preferably provided so as to be embedded in an opening formed in the insulator 216. The conductor 205 is preferably provided to extend in the channel width direction as shown in FIGS. 7(A) and 7(C). With this structure, the conductor 205 functions as a wiring when a plurality of transistors are provided.

[0298] 8(A), the conductor 205 preferably has a conductor 205a and a conductor 205b. The conductor 205a is provided in contact with the bottom surface and the side wall of the opening. The conductor 205b is provided so as to fill a recess of the conductor 205a formed along the opening. Here, the height of the upper surface of the conductor 205 coincides or approximately coincides with the height of the upper surface of the insulator 216.

[0299] Here, the conductor 205a preferably has a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it preferably has a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.).

[0300] By using a conductive material having a function of reducing hydrogen diffusion for the conductor 205a, impurities such as hydrogen contained in the conductor 205b can be prevented from diffusing into the oxide semiconductor 230 via the insulator 216 or the like. In addition, by using a conductive material having a function of suppressing oxygen diffusion for the conductor 205a, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 205b. Examples of conductive materials having a function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductor 205a can have a single-layer structure or a multilayer structure of the above conductive materials. For example, the conductor 205a preferably has titanium nitride.

[0301] The conductor 205b is preferably made of a conductive material mainly composed of tungsten, copper, or aluminum. For example, the conductor 205b preferably contains tungsten.

[0302] The conductor 205 can function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. In particular, by applying a negative potential to the conductor 205, the Vth of the transistor 200 can be increased and the off-current can be reduced. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V, compared to not applying a negative potential.

[0303] The electrical resistivity of the conductor 205 is designed taking into consideration the potential applied to the conductor 205, and the film thickness of the conductor 205 is set to match the electrical resistivity. The film thickness of the insulator 216 is approximately the same as that of the conductor 205. Here, it is preferable to make the film thicknesses of the conductor 205 and the insulator 216 thin within a range permitted by the design of the conductor 205. By making the film thickness of the insulator 216 thin, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, and thus diffusion of the impurities into the oxide semiconductor 230 can be suppressed.

[0304] 8A shows a stacked structure of the conductor 205a and the conductor 205b, the present invention is not limited thereto, and the conductor 205 may have a single-layer structure or a stacked structure of three or more layers. For example, the conductor 205a may have a two-layer structure of tantalum nitride and titanium nitride on the tantalum nitride, and the conductor 205b having tungsten may be provided on the conductor 205a. With such a structure, impurities such as hydrogen and metal impurities such as copper contained in the lower layer of the transistor 200 can be prevented from diffusing into the conductor 205.

[0305] Insulator 224, which corresponds to layer 29, functions together with insulators 221 and 222 as a second gate insulator.

[0306] The insulator 224 in contact with the oxide semiconductor 230 can be made of an insulating material described in <<Insulators>>. The insulator 224 preferably contains, for example, silicon oxide or silicon oxynitride. This allows oxygen to be supplied from the insulator 224 to the oxide semiconductor 230, thereby reducing oxygen vacancies. Note that the insulator 224 may have a stacked structure of two or more layers. In this case, the insulator 224 is not limited to a stacked structure made of the same material, and may have a stacked structure made of different materials.

[0307] Similarly to the oxide semiconductor 230, the insulator 224 is preferably processed into an island shape. Thus, when a plurality of transistors 200 are provided, each of the transistors 200 has an insulator 224 of approximately the same size. As a result, the amount of oxygen supplied from the insulator 224 to the oxide semiconductor 230 in each of the transistors 200 becomes approximately the same. Thus, variation in the electrical characteristics of the transistors 200 within the substrate surface can be suppressed.

[0308] However, the insulator 224 does not necessarily have to be processed into an island shape. For example, as shown in Figures 9(A) to 9(D), the insulator 224 may have a shape in which an opening is formed in a part of the insulator 224 instead of being formed into an island shape. Here, Figures 9(A) to 9(D) correspond to Figures 7(A) to 7(D), respectively, and are similar to Figures 7(A) to 7(D) except that the shape of the insulator 224 is different.

[0309] 9A to 9D, the thickness of a region of the insulator 224 that does not overlap with the oxide semiconductor 230 is thinner than the thickness of a region that overlaps with the oxide semiconductor 230. An opening is formed in a region that does not overlap with the oxide semiconductor 230 and overlaps with the insulator 250. When a plurality of transistors are provided over the same substrate, the insulator 224 is formed in this manner, so that the oxide semiconductor 230 of each transistor is formed over the same insulator 224. This can reduce variation in the amount of oxygen supplied from the insulator 224 to the oxide semiconductor 230 of each transistor. Thus, variation in electrical characteristics of each transistor can be reduced.

[0310] Note that in the insulator 224 shown in FIGS. 9A to 9D, an opening is formed in a region that does not overlap with the oxide semiconductor 230 and overlaps with the insulator 250; however, a structure in which the opening is not provided is also possible.

[0311] The conductive materials described in the <<Conductor>> section can be used for the conductor 242a, the conductor 242b, and the conductor 260. In particular, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has a function of suppressing the diffusion of oxygen for the conductor 242a, the conductor 242b, and the conductor 260. Examples of the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductor 242a, the conductor 242b, and the conductor 260. When a conductive material containing metal and nitrogen is used for the conductor 242a, the conductor 242b, and the conductor 260, the conductor 242a, the conductor 242b, and the conductor 260 are conductors that have at least metal and nitrogen.

[0312] It is preferable to use metal nitrides as the conductors 242a and 242b, and it is preferable to use, for example, nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing tantalum and aluminum, nitrides containing titanium and aluminum, etc. For example, tantalum nitride can be used as the conductors 242a and 242b. In addition, for example, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. may also be used. These materials are preferable because they are conductive materials that are difficult to oxidize, or materials that maintain their conductivity even when they absorb oxygen.

[0313] Note that hydrogen contained in the oxide semiconductor 230 or the like may diffuse to the conductor 242a or the conductor 242b. In particular, when a nitride containing tantalum is used for the conductor 242a and the conductor 242b, hydrogen contained in the oxide semiconductor 230 or the like is likely to diffuse to the conductor 242a or the conductor 242b, and the diffused hydrogen may bond to nitrogen in the conductor 242a or the conductor 242b. In other words, hydrogen contained in the oxide semiconductor 230 or the like may be absorbed by the conductor 242a or the conductor 242b.

[0314] The conductor 242a and the conductor 242b may have a laminated structure. In this case, the above-mentioned conductive material may be used for the lower layer of the conductor 242a and the conductor 242b, and a conductive material having higher conductivity may be used for the upper layer of the conductor 242a and the conductor 242b. For example, tantalum nitride may be used for the lower layer, and tungsten may be used for the upper layer.

[0315] The insulators 271a and 271b are inorganic insulators that function as an etching stopper when the conductors 242a and 242b are processed, and protect the conductors 242a and 242b. Since the insulators 271a and 271b are in contact with the conductors 242a and 242b, it is preferable that the insulators 271a and 271b are inorganic insulators that are unlikely to oxidize the conductors 242a and 242b. Therefore, as shown in FIG. 8(A), it is preferable that the insulator 271a has a layered structure of an insulator 271a1 and an insulator 271a2 on the insulator 271a1, and the insulator 271b has a layered structure of an insulator 271b1 and an insulator 271b2 on the insulator 271b1. Here, the insulators 271a1 and 271b1 are preferably made of a nitride insulator that can be used for the insulator 250c so as to prevent the conductors 242a and 242b from being oxidized, and the insulators 271a2 and 271b2 are preferably made of an oxide insulator that can be used for the insulator 250b so as to function as an etching stopper.

[0316] Here, the insulator 271a1 contacts the upper surface of the conductor 242a and a part of the insulator 275, and the insulator 271b1 contacts the upper surface of the conductor 242b and a part of the insulator 275. The insulator 271a2 contacts the upper surface of the insulator 271a1 and the lower surface of the insulator 275, and the insulator 271b2 contacts the upper surface of the insulator 271b1 and the lower surface of the insulator 275. For example, silicon nitride can be used as the insulators 271a1 and 271b1, and silicon oxide can be used as the insulators 271a2 and 271b2.

[0317] Since the insulators that are the basis of the insulators 271a and 271b function as masks for the conductors that are the basis of the conductors 242a and 242b, the conductors 242a and 242b do not have a curved surface between the side surface and the top surface, as shown in FIG. 7(D). As a result, the ends where the side surface and the top surface of the conductors 242a and 242b intersect are angular. By making the ends where the side surface and the top surface of the conductors 242a and 242b intersect angular, the cross-sectional areas of the conductors 242a and 242b are larger than when the ends have a curved surface. Furthermore, by using a nitride insulator that does not easily oxidize metal for the insulators 271a1 and 271b1, it is possible to prevent the conductors 242a and 242b from being excessively oxidized. As a result, the resistance of the conductors 242a and 242b is reduced, and the on-current of the transistors can be increased.

[0318] 7(B) and 7(C), the conductor 260 is disposed in an opening formed in the insulator 280 and the insulator 275. The conductor 260 is provided in the opening so as to cover the top surface of the insulator 222, the side surface of the insulator 224, and the side surface and top surface of the oxide semiconductor 230 via the insulator 250. The top surface of the conductor 260 is disposed so as to be flush or approximately flush with the top end of the insulator 250 and the top surface of the insulator 280.

[0319] In the opening in which the conductor 260 and the insulator 250 are disposed, the sidewall of the opening may be perpendicular or approximately perpendicular to the upper surface of the insulator 222, or may be tapered. By making the sidewall tapered, the coverage of the insulator 250 provided in the opening of the insulator 280 is improved, and defects such as voids can be reduced.

[0320] The conductor 260 functions as a first gate electrode of the transistor 200. Here, the conductor 260 is preferably provided to extend in the channel width direction as shown in Fig. 7(A) and Fig. 7(C). With this structure, when a plurality of transistors are provided, the conductor 260 functions as a wiring.

[0321] 7C, in a cross-sectional view of the transistor 200 in the channel width direction, a curved surface may be formed between the side surface of the oxide semiconductor 230 and the top surface of the oxide semiconductor 230. In other words, the end portions of the side surface and the top surface may be curved (hereinafter also referred to as rounded).

[0322] The radius of curvature of the curved surface is preferably greater than 0 nm and smaller than the film thickness of the oxide semiconductor 230 in the region overlapping with the conductor 242a and the conductor 242b, or smaller than half the length of the region not having the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and less than 20 nm, preferably greater than 1 nm and less than 15 nm, and more preferably greater than 2 nm and less than 10 nm. Such a shape can improve the coverage of the oxide semiconductor 230 with the insulator 250 and the conductor 260.

[0323] In this specification, the structure of a transistor in which the electric field of at least the first gate electrode electrically surrounds the channel formation region is called a surrounded channel (S-channel) structure. The S-channel structure disclosed in this specification has a structure different from the Fin type structure and the planar type structure. On the other hand, the S-channel structure disclosed in this specification can be regarded as a type of Fin type structure. In this specification, the Fin type structure refers to a structure in which the gate electrode is disposed so as to surround at least two or more sides of the channel (specifically, two, three, or four sides, etc.). By adopting the Fin type structure and the S-channel structure, it is possible to obtain a transistor that is more resistant to the short channel effect, in other words, in which the short channel effect is less likely to occur.

[0324] By forming the transistor 200 in the S-channel structure, the channel formation region can be electrically surrounded. Note that the S-channel structure electrically surrounds the channel formation region, and therefore can be said to be substantially equivalent to a GAA (gate all around) structure or a LGAA (lateral gate all around) structure. By forming the transistor 200 in the S-channel structure, the GAA structure, or the LGAA structure, the channel formation region formed at or near the interface between the oxide semiconductor 230 and the gate insulator can be the entire bulk of the oxide semiconductor 230. Therefore, it is possible to improve the current density flowing through the transistor, which is expected to improve the on-state current of the transistor or the field-effect mobility of the transistor.

[0325] In this embodiment, the insulator 224 is provided in an island shape. Therefore, as shown in FIG 7C, at least a part of the bottom surface of the conductor 260 can be provided below the bottom surface of the oxide semiconductor 230. In this manner, the conductor 260 can be provided facing the top surface and side surface of the oxide semiconductor 230, and the electric field of the conductor 260 can be applied to the top surface and side surface of the oxide semiconductor 230. By providing the insulator 224 in an island shape in this manner, the transistor 200 can have an S-channel structure.

[0326] 7C illustrates an example of a transistor having an S-channel structure, but the semiconductor device of one embodiment of the present invention is not limited to this. For example, the transistor structure that can be used in one embodiment of the present invention may be one or more selected from a planar structure, a fin structure, and a GAA structure.

[0327] As shown in Fig. 8(A), it is preferable that the conductor 260 has a two-layer structure. Here, it is preferable that the conductor 260 has a conductor 260a and a conductor 260b arranged on the conductor 260a. For example, it is preferable that the conductor 260a is arranged so as to surround the bottom and side surfaces of the conductor 260b. In this case, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has a function of suppressing the diffusion of oxygen as the conductor 260a.

[0328] The conductor 260a is preferably made of a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

[0329] Furthermore, since the conductor 260a has a function of suppressing the diffusion of oxygen, it is possible to suppress the conductor 260b from being oxidized and its conductivity from being reduced by oxygen contained in the insulator 280, etc. As a conductive material having a function of suppressing the diffusion of oxygen, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0330] Moreover, it is preferable that the conductor 260b is a conductor having high conductivity. For example, the conductor 260b may be a conductive material mainly composed of tungsten, copper, or aluminum. The conductor 260b may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above-mentioned conductive material.

[0331] In the transistor 200, the conductor 260 is formed in a self-aligned manner so as to fill an opening formed in the insulator 280 or the like. By forming the conductor 260 in this manner, the conductor 260 can be arranged so as to overlap the region between the conductor 242a and the conductor 242b without alignment.

[0332] The insulators 216, 280, and 285 each preferably have a dielectric constant lower than that of the insulator 222. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance between wirings can be reduced.

[0333] For example, insulator 216, insulator 280, and insulator 285 each preferably include one or more of silicon oxide, silicon oxynitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, and silicon oxide with vacancies.

[0334] In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferred because they can easily form a region containing oxygen that is desorbed by heating.

[0335] Additionally, the top surfaces of the insulators 216 and 280 may each be flattened.

[0336] It is preferable that the concentration of impurities such as water and hydrogen is reduced in the insulator 280. For example, it is preferable that the insulator 280 has an oxide containing silicon, such as silicon oxide or silicon oxynitride.

[0337] The conductive material described in the <<Conductor>> section can be used for the conductor 240a and the conductor 240b. For the conductor 240a and the conductor 240b, it is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum. The conductor 240a and the conductor 240b may have a layered structure.

[0338] 8(A), the conductor 240a and the conductor 240b may have a two-layer laminated structure. The conductor 240a has a conductor 240a1 formed along the opening and a conductor 240a2 formed inside the conductor 240a1. The conductor 240b has a conductor 240b1 formed along the opening and a conductor 240b2 formed inside the conductor 240b1.

[0339] For the conductor 240a1 and the conductor 240b1, it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen, similar to the conductor 205a. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like. Furthermore, the conductive material having a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a stacked layer. By providing the conductor 240a1 and the conductor 240b1, it is possible to suppress impurities such as water and hydrogen from being mixed into the oxide semiconductor 230 through the conductor 240a2 and the conductor 240b2. Note that for the conductor 240a2 and the conductor 240b2, a conductive material that can be used for the conductor 240a and the conductor 240b described above may be used.

[0340] 7(B), the upper surfaces of the conductors 240a and 240b can be formed to coincide or approximately coincide with the upper surface of the insulator 285. Also, as shown in FIG. 8(A), the lower part of the conductor 240a may be formed to be embedded in the conductor 242a. Similarly, the lower part of the conductor 240b may be formed to be embedded in the conductor 242b.

[0341] The insulator 241a and the insulator 241b may be a barrier insulator that can be used for the insulator 275, etc. For example, silicon nitride may be used for the insulator 241a and the insulator 241b. The insulator 241a and the insulator 241b are provided in contact with the insulator 285, the insulator 283, the insulator 282, the insulator 275, the insulator 271a, and the insulator 271b. This can prevent impurities such as water and hydrogen contained in the insulator 280 and the like from being mixed into the oxide semiconductor 230 through the conductor 240a and the conductor 240b. In particular, silicon nitride is preferable because it has high blocking properties against hydrogen. In addition, oxygen contained in the insulator 280 can be prevented from being absorbed by the conductor 240a and the conductor 240b.

[0342] The insulators 241a and 241b may have a laminated structure. In this case, it is preferable that a first insulator in contact with the side wall of an opening, such as the insulator 280, and a second insulator on the inside thereof are made of a combination of a barrier insulator against oxygen and a barrier insulator against hydrogen.

[0343] <Modification> 7B and the like, insulator 250 contacts the side surface of insulator 280 at the opening provided in insulator 280, but the present invention is not limited to this configuration. For example, an insulator may be provided between insulator 250 and insulator 280 at the opening.

[0344] Modifications of the semiconductor device described in <Structural Example of Semiconductor Device> will be described with reference to Fig. 10(A) to Fig. 11(B). Fig. 10(A) to Fig. 10(D) are plan views and cross-sectional views of a semiconductor device including a transistor 200, and correspond to the plan views and cross-sectional views shown in Fig. 7(A) to Fig. 7(D), respectively. Fig. 11(A) and Fig. 11(B) are enlarged cross-sectional views in the channel length direction of the transistor 200, and correspond to a part of Fig. 8(A) and the enlarged cross-sectional view shown in Fig. 8(B), respectively.

[0345] 10A to 10D is a modified example of the transistor 200 shown in Figures 7A to 7D. Specifically, the transistor 200 shown in Figures 10A to 10D is mainly different from the transistor 200 shown in Figures 7A to 7D in that an insulator 255 is included. Hereinafter, differences from the above description of <Structural example of semiconductor device> will be mainly described, and overlapping parts will be referred to and description thereof will be omitted in some cases.

[0346] 10, each of the conductors 242a and 242b is shown as having a two-layer structure. The conductor 242a has a layered structure of a conductor 242a1 and a conductor 242a2 on the conductor 242a1. The conductor 242b has a layered structure of a conductor 242b1 and a conductor 242b2 on the conductor 242b1. The conductors 242a1 and 242b1 correspond to the lower layers of the conductors 242a and 242b, respectively, and the conductors 242a2 and 242b2 correspond to the upper layers of the conductors 242a and 242b, respectively.

[0347] 10(B) and 10(C), the insulator 255 is disposed inside an opening formed in the insulator 280 and contacts the side surface of the insulator 280, the side surface of the conductor 242a2, the side surface of the conductor 242b2, the top surface of the conductor 242a1, the top surface of the conductor 242b1, and the top surface of the insulator 222 in the opening. In other words, the insulator 255 can be said to be formed in a sidewall shape in contact with the side wall of the opening formed in the insulator 280. Here, the side wall of the opening corresponds to, for example, the side surface of the insulator 280, etc. in the opening.

[0348] Additionally, the insulator 250 contacts the side of the insulator 255 .

[0349] The insulator 255 preferably has a barrier property against oxygen. When the insulator 255 has a barrier property against oxygen, the side surfaces of the conductor 242a and the conductor 242b can be prevented from being oxidized and an oxide film can be prevented from being formed on the side surfaces. This can prevent a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 200.

[0350] The opening provided in the insulator 280 overlaps with the region between the conductor 242a2 and the conductor 242b2. In a top view, the side surface of the insulator 280 at the opening coincides with the side surface of the conductor 242a2 and the side surface of the conductor 242b2. Parts of the conductors 242a1 and 242b1 are formed so as to protrude inwardly from the opening. In other words, the portion of the conductor 242a1 on whose upper surface the insulator 255 is formed is formed so as to protrude toward the conductor 260 side more than the conductor 242a2. Similarly, the portion of the conductor 242b1 on whose upper surface the insulator 255 is formed is formed so as to protrude toward the conductor 260 side more than the conductor 242b2.

[0351] Here, a part of the upper surface of the conductor 242a1 contacts the conductor 242a2, and a part of the upper surface of the conductor 242b1 contacts the conductor 242b2. Therefore, inside the opening, the insulator 255 contacts another part of the upper surface of the conductor 242a1, another part of the upper surface of the conductor 242b1, a side surface of the conductor 242a2, and a side surface of the conductor 242b2. The insulator 250 contacts the upper surface of the oxide semiconductor 230, the side surface of the conductor 242a1, the side surface of the conductor 242b1, and the side surface of the insulator 255.

[0352] The insulator 255 is formed by anisotropic etching in a sidewall shape in contact with the side wall of the opening provided in the insulator 280. The insulator 255 is formed in contact with the side surface of the conductor 242a2 and the side surface of the conductor 242b2 and has a function of protecting the conductor 242a2 and the conductor 242b2.

[0353] The insulator 255 functions as a mask when dividing the conductor 242a1 and the conductor 242b1. Therefore, in a cross-sectional view of the transistor 200 as shown in FIG 11A, the side ends of the insulator 255 preferably coincide with the side ends of the conductor 242a1 and the side ends of the conductor 242b1.

[0354] After the conductor 242a1 and the conductor 242b1 are separated, it is preferable to perform a heat treatment in an atmosphere containing oxygen before forming the insulator 250. At this time, the insulator 255 is formed in contact with the side surface of the conductor 242a2 and the side surface of the conductor 242b2, thereby preventing the conductor 242a2 and the conductor 242b2 from being excessively oxidized. Furthermore, even when a microwave treatment is performed after the conductor 242a1 and the conductor 242b1 are separated, it is possible to suppress the formation of an oxide film on the side surface of the conductor 242a and the conductor 242b.

[0355] The portions of insulator 255, insulator 250, and conductor 260 that are to be placed in an opening provided in insulator 280 are provided to reflect the shape of the opening. Thus, insulator 255 is provided so as to cover the sidewall of the opening, insulator 250 is provided so as to cover the bottom of the opening and insulator 255, and conductor 260 is provided so as to fill the recess of insulator 250.

[0356] As in the above-mentioned <Configuration example of semiconductor device>, the insulator 250 may have a laminated structure. For example, as shown in Fig. 11(A), the insulator 250 may have a three-layer structure of insulator 250a, insulator 250b, and insulator 250c. Also, as shown in Fig. 11(B), the insulator 250 may have a four-layer structure of insulator 250a, insulator 250b, insulator 250c, and insulator 250d.

[0357] The thickness of the insulator 255 is preferably 0.5 nm to 20 nm, more preferably 0.5 nm to 10 nm, and more preferably 0.5 nm to 3 nm. By setting the thickness of the insulator 255 as described above, it is possible to suppress excessive oxidation of the conductor 242a2 and the conductor 242b2. The insulator 255 may have at least a portion having a thickness as described above. Since the insulator 255 is provided in contact with the side wall of the opening formed in the insulator 280, it is preferable to form the insulator 255 using an ALD method or the like, which has good coverage. If the thickness of the insulator 255 is excessively thick, the time required for forming the insulator 255 by the ALD method increases, and productivity decreases, so the thickness of the insulator 255 is preferably within the above range. The insulator 255 preferably has a thickness large enough not to excessively hinder diffusion of excess oxygen from the insulator 280 to the insulator 250b and from the insulator 250b to the oxide semiconductor 230.

[0358] As shown in FIG. 11(A), in a cross-sectional view of the transistor 200 in the channel length direction, the distance L2 between the conductor 242a1 and the conductor 242b1 is smaller than the distance L1 between the conductor 242a2 and the conductor 242b2. Specifically, the difference between the distance L1 and the distance L2 is equal to twice the film thickness of the insulator 255. In other words, the distance L1 is equal to the distance L2 obtained by adding twice the film thickness of the insulator 255. Here, the film thickness of the insulator 255 refers to the width in the A1-A2 direction of at least a part of the insulator 255. With this configuration, it is possible to further shorten the distance between the source and the drain, and accordingly shorten the channel length. Therefore, the frequency characteristics of the transistor 200 can be improved. In this way, by miniaturizing the semiconductor device, a semiconductor device with improved operating speed can be provided.

[0359] The insulator 255 may have a laminated structure of two or more layers. In this case, it is preferable that at least one layer is the inorganic insulator that is not easily oxidized. For example, the first insulator of the insulator 255 may be the inorganic insulator that is not easily oxidized, and the second insulator on the first insulator of the insulator 255 may be an insulator that is applicable to the insulator 250b (e.g., silicon oxide, etc.). It is preferable that the second insulator of the insulator 255 has a lower dielectric constant than the first insulator of the insulator 255. In this way, by making the insulator 255 have a two-layer structure and increasing the film thickness, the distance between the conductor 260 and the conductor 242a or conductor 242b can be increased, and the parasitic capacitance can be reduced.

[0360] <Materials for semiconductor devices> Constituent materials that can be used in the semiconductor device will be described below. Each layer constituting the semiconductor device may have a single layer structure or a multilayer structure.

[0361] <<Substrate>> As the substrate on which the transistor is formed, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used. As the insulating substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria stabilized zirconia substrate), and a resin substrate can be mentioned. As the semiconductor substrate, for example, a semiconductor substrate made of silicon or germanium, and a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide can be mentioned. Furthermore, as the semiconductor substrate, a semiconductor substrate having an insulator region inside the semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate, can be mentioned. As the conductive substrate, for example, a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate can be mentioned. As the substrate, for example, a substrate having a metal nitride, a substrate having a metal oxide, a substrate having a conductor or semiconductor provided on an insulating substrate, a substrate having a conductor or insulator provided on a semiconductor substrate, and a substrate having a semiconductor or insulator provided on a conductive substrate can be mentioned. Alternatively, one or more types of elements may be provided on the substrate, such as a capacitor element, a resistor element, a switch element, a light-emitting element, and a memory element.

[0362] <<Insulators>> Examples of the insulator include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.

[0363] For example, as transistors become smaller and more highly integrated, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the voltage required for transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low relative dielectric constant for the insulator that functions as the interlayer film, it is possible to reduce the parasitic capacitance that occurs between wiring. Therefore, it is preferable to select a material according to the function of the insulator.

[0364] Examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0365] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide having voids, and resin.

[0366] In addition, the transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen. As the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used in a single layer or a stacked layer. Specifically, as the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can be used.

[0367] The insulator functioning as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide semiconductor 230, oxygen vacancies in the oxide semiconductor 230 can be compensated for.

[0368] <<Conductors>> As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements. As the conductor, for example, tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, and oxide containing lanthanum and nickel can be mentioned. In addition, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, and oxide containing lanthanum and nickel are each a conductive material that is difficult to oxidize, or a material that maintains conductivity even when oxygen is absorbed, and therefore are preferable. Alternatively, a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

[0369] When a conductor with a layered structure is used, for example, a layered structure combining the material containing the metal element described above and a conductive material containing oxygen, a layered structure combining the material containing the metal element described above and a conductive material containing nitrogen, or a layered structure combining the material containing the metal element described above and a conductive material containing oxygen and a conductive material containing nitrogen may be applied.

[0370] In addition, when an oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing a metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0371] In particular, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed as a conductor functioning as a gate electrode. The conductive material containing the metal element and nitrogen described above may also be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may also be used. Indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide to which silicon is added may also be used. Indium gallium zinc oxide containing nitrogen may also be used. By using such a material, hydrogen contained in the metal oxide in which the channel is formed may be captured. Alternatively, hydrogen mixed in from an external insulator may be captured.

[0372] <Example of a method for manufacturing a semiconductor device> An example of a method for manufacturing a semiconductor device of one embodiment of the present invention will be described with reference to Figures 12A to 19D. Here, the case of manufacturing the semiconductor device illustrated in Figures 7A to 7D will be described as an example.

[0373] 12 to 15 and 17 to 19 (A) show plan views. Also, each of (B) of FIG. 12 to 15 and 17 to 19 is a cross-sectional view corresponding to a portion indicated by a dashed line A1-A2 in (A) of each figure, and is also a cross-sectional view in the channel length direction of the transistor 200. Also, each of (C) of FIG. 12 to 15 and 17 to 19 is a cross-sectional view corresponding to a portion indicated by a dashed line A3-A4 in (A) of each figure, and is also a cross-sectional view in the channel width direction of the transistor 200. Also, each of (D) of FIG. 12 to 15 and 17 to 19 is a cross-sectional view corresponding to a portion indicated by a dashed line A5-A6 in (A) of each figure, and is also a cross-sectional view in the channel width direction of the transistor 200. 12 to 15 and the plan views of Fig. 17 to 19A, some elements are omitted for clarity. Fig. 16A1 to Fig. 16D1 are cross-sectional views corresponding to a part of Fig. 7B and are cross-sectional views in the channel length direction of the transistor 200. Fig. 16A2 to Fig. 16D2 are cross-sectional views corresponding to a part of Fig. 7C and are cross-sectional views in the channel width direction of the transistor 200.

[0374] In the following, insulating materials for forming insulators, conductive materials for forming conductors, or semiconductor materials for forming semiconductors can be formed as films by appropriately using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0375] First, a substrate (not shown) is prepared, an insulator 212 is formed on the substrate, and an insulator 214 is formed on the insulator 212 (see FIGS. 12A to 12D). The insulator 212 and the insulator 214 can be formed using any of the insulating materials described above. The insulators 212 and 214 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The use of a sputtering method, which does not require the use of molecules containing hydrogen in the deposition gas, is preferable because the hydrogen concentrations in the insulators 212 and 214 can be reduced.

[0376] In this embodiment, silicon nitride is formed as the insulator 212 by a sputtering method, and aluminum oxide is formed as the insulator 214 by a sputtering method. In this manner, by using silicon nitride having a function of suppressing diffusion of hydrogen as the insulator 212, diffusion of hydrogen from a lower layer of the transistor 200 can be suppressed. Furthermore, by using aluminum oxide having a function of capturing or fixing hydrogen as the insulator 214, hydrogen contained in the insulator 216 or the like can be captured or fixed to the insulator 214. As a result, the hydrogen concentration in the oxide semiconductor 230 and its vicinity can be reduced.

[0377] It is preferable to perform heat treatment to reduce water and hydrogen adsorbed to the substrate (including the circuit elements and interlayer films formed over the substrate) before forming the insulator 212. In this embodiment, the heat treatment is performed at 400° C.

[0378] Next, the insulator 216 is deposited over the insulator 214. The insulator 216 is preferably deposited by a sputtering method. By using a sputtering method that does not require the use of molecules containing hydrogen in the deposition gas, the hydrogen concentration in the insulator 216 can be reduced. However, the deposition of the insulator 216 is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may be used as appropriate. In this embodiment, a silicon oxide film is deposited as the insulator 216 by a sputtering method.

[0379] It is preferable that the insulators 212, 214, and 216 are successively formed without exposure to the air. For example, a multi-chamber film formation apparatus can be used. This allows the insulators 212, 214, and 216 to be formed with reduced hydrogen in the films, and further reduces the incorporation of hydrogen into the films between each film formation process.

[0380] Next, an opening is formed in the insulator 216, reaching the insulator 214. The opening is formed in a region where the conductor 205 is to be formed. The opening may be formed by wet etching, but dry etching is preferable for fine processing. For the insulator 214, it is preferable to select an insulator that functions as an etching stopper film when etching the insulator 216. For example, when silicon oxide or silicon oxynitride is used for the insulator 216, it is preferable to use silicon nitride, aluminum oxide, hafnium oxide, or the like for the insulator 214.

[0381] After the opening is formed, a conductive film to be the conductor 205 is formed, and CMP treatment is performed until the insulator 216 is exposed, thereby removing a part of the conductive film to be the conductor 205. In this way, the conductor 205 embedded in the insulator 216 can be formed (see FIGS. 12A to 12D).

[0382] Here, the conductive film that becomes the conductor 205 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like using the above-mentioned conductive material. For example, a tantalum nitride film, a titanium nitride film, and a tungsten film can be laminated using the CVD method. As a result, as shown in Fig. 8(A), the conductor 205 can have a laminated structure of a conductor 205a in which titanium nitride is laminated on tantalum nitride, and a tungsten conductor 205b.

[0383] Next, the insulator 221 is formed over the insulator 216 and the conductor 205 (see FIGS. 12A to 12D).

[0384] The insulator 221 may be any of the above insulators having barrier properties against oxygen, hydrogen, and water. The insulator 221 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, silicon nitride is formed as the insulator 221 by a PEALD method.

[0385] Next, the insulator 222 is formed over the insulator 221 (see FIGS. 12A to 12D).

[0386] As the insulator 222, an insulator containing one or both of an oxide of aluminum and hafnium is preferably formed. Note that, as the insulator containing one or both of an oxide of aluminum and hafnium, for example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used. Alternatively, hafnium zirconium oxide is preferably used. An insulator containing one or both of an oxide of aluminum and hafnium has a barrier property against oxygen, hydrogen, and water. When the insulator 222 has a barrier property against hydrogen and water, hydrogen and water contained in a structure provided around the transistor are prevented from diffusing into the inside of the transistor through the insulator 222, and thus generation of oxygen vacancies in the oxide semiconductor 230 can be suppressed.

[0387] The insulator 222 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, the insulator 222 is formed by a thermal ALD method using hafnium oxide.

[0388] In this embodiment, silicon nitride is formed as the insulator 221 by a PEALD method, and hafnium oxide is formed as the insulator 222 by a thermal ALD method. In this manner, by using silicon nitride having a function of suppressing diffusion of hydrogen as the insulator 221, diffusion of hydrogen from a lower layer of the transistor 200 can be suppressed. Furthermore, by using hafnium oxide having a function of capturing or fixing hydrogen as the insulator 222, hydrogen contained in the insulator 224 or the like can be captured or fixed to the insulator 222. As a result, the hydrogen concentration in the oxide semiconductor 230 and its vicinity can be reduced.

[0389] Next, the insulating film 224f is formed over the insulator 222 (see FIGS. 12A to 12D). As the insulating film 224f, an insulator corresponding to the insulator 224 may be used. By forming the insulating film 224f in this manner, the insulating film 224f is formed parallel or approximately parallel to the surface of the substrate.

[0390] The insulating film 224f can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, silicon oxide is formed as the insulating film 224f by a sputtering method. By using a sputtering method that does not require the use of molecules containing hydrogen in a deposition gas, the hydrogen concentration in the insulating film 224f can be reduced. Because the insulating film 224f comes into contact with the oxide semiconductor 230 in a later step, it is preferable that the hydrogen concentration be reduced in this manner.

[0391] Next, the oxide semiconductor film 230f is formed over the insulating film 224f (see FIGS. 12A to 12D). The oxide semiconductor film 230f may be formed by the same method as that for forming the oxide semiconductor 30 described in Embodiment 1. By forming the oxide semiconductor film 230f in this manner, the oxide semiconductor film 230f is formed parallel or approximately parallel to the surface of the substrate.

[0392] For example, as shown in FIG. 8A, when the oxide semiconductor 230 has a three-layer structure including oxide semiconductors 230a to 230c, films to be the oxide semiconductor 230a and the oxide semiconductor 230c can be formed by an ALD method, and a film to be the oxide semiconductor 230b can be formed by a sputtering method. Specifically, the film to be the oxide semiconductor 230a can be formed to a thickness of 5 nm so as to have an atomic ratio of In:Zn=2:1 or a composition thereabout. Alternatively, indium oxide may be used for the film to be the oxide semiconductor 230a. The film to be the oxide semiconductor 230b can be formed to a thickness of 5 nm using an oxide target having an atomic ratio of In:Ga:Zn=1:1:1.2 or a composition thereabout. Alternatively, the film to be the oxide semiconductor 230c can be formed to a thickness of 10 nm so as to have an atomic ratio of In:Zn=2:1 or a composition thereabout. Alternatively, indium oxide may be used for the film to be the oxide semiconductor 230c.

[0393] Next, heat treatment is preferably performed. The heat treatment is preferably performed within a temperature range in which the oxide semiconductor film 230f is not polycrystallized. The heat treatment of the oxide semiconductor film 230f may be performed by the same method as the heat treatment of the oxide semiconductor 30 described in Embodiment 1.

[0394] For example, the heat treatment can be performed at a flow rate ratio of nitrogen gas and oxygen gas of 4:1 at a temperature of 450° C. for one hour.

[0395] By forming the oxide semiconductor 230 using the above method and then performing heat treatment, the oxide semiconductor 230 can be made into an axially grown CAAC. As a result, the on-state current, the S value, the field-effect mobility, the frequency characteristics, and the like of the transistor 200 can be improved, and a semiconductor device with favorable electrical characteristics can be provided. In addition, a highly reliable semiconductor device can be provided.

[0396] The heat treatment is preferably performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in a nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.

[0397] In addition, the gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and further preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, moisture and the like can be prevented from being introduced into the oxide semiconductor film 230f as much as possible. Note that a highly purified gas can also be used in the heat treatment before and after this step.

[0398] Furthermore, the above-described heat treatment including oxygen gas can reduce impurities such as carbon, water, and hydrogen in the oxide semiconductor film 230f. Reducing the impurities in the film in this manner can improve the crystallinity of the oxide semiconductor film 230f, resulting in a denser and more compact structure. This can increase the crystalline regions in the oxide semiconductor film 230f, thereby reducing in-plane variations in the crystalline regions in the oxide semiconductor film 230f. As a result, in-plane variations in the electrical characteristics of the transistor can be reduced.

[0399] Furthermore, by performing the heat treatment, oxygen can be supplied to the oxide semiconductor film 230f, so that oxygen vacancies in the oxide semiconductor film 230f can be reduced, thereby improving the reliability of the transistor 200.

[0400] Furthermore, by performing heat treatment, hydrogen in the insulator 216, the insulating film 224f, and the oxide semiconductor film 230f moves to the insulator 222 and is absorbed into the insulator 222. In other words, hydrogen in the insulator 216, the insulating film 224f, and the oxide semiconductor film 230f diffuses into the insulator 222. Thus, the hydrogen concentration in the insulator 222 increases, but the hydrogen concentrations in the insulator 216, the insulating film 224f, and the oxide semiconductor film 230f decrease. Note that by providing the insulator 221 in contact with the lower surface of the insulator 222, impurities such as moisture or hydrogen can be prevented from entering from below the insulator 221 during the heat treatment.

[0401] In particular, the insulating film 224f (the future insulator 224) functions as a second gate insulator of the transistor 200, and the oxide semiconductor film 230f (the future oxide semiconductor 230) functions as a channel formation region of the transistor 200. The transistor 200 formed using the insulating film 224f and the oxide semiconductor film 230f in which the hydrogen concentration is reduced has good reliability, which is preferable.

[0402] Next, a conductive film 242f is formed over the oxide semiconductor film 230f (see FIGS. 12A to 12D). As the conductive film 242f, a conductor corresponding to the above-mentioned conductor 242a and the conductor 242b may be used. By forming the conductive film 242f on and in contact with the oxide semiconductor film 230f without performing an etching step or the like after the oxide semiconductor film 230f is formed, the top surface of the oxide semiconductor film 230f can be protected by the conductive film 242f. This can reduce diffusion of impurities into the oxide semiconductor 230 included in the transistor, thereby improving the electrical characteristics and reliability of the semiconductor device.

[0403] The conductive film 242f can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0404] In this embodiment, tantalum nitride is formed as the conductive film 242f by a sputtering method. Note that heat treatment may be performed before the conductive film 242f is formed. The heat treatment may be performed under reduced pressure, and the conductive film 242f may be formed successively without exposure to air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the oxide semiconductor 230 can be removed and the moisture and hydrogen concentrations in the oxide semiconductor 230 can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower.

[0405] Next, an insulating film 271f is formed on the conductive film 242f (see FIGS. 12A to 12D). The insulating film 271f can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 271f is preferably an insulating film having a function of suppressing oxygen permeation. For example, the insulating film 271f can be formed by a sputtering method to form a laminated film of a silicon nitride film and a silicon oxide film on the silicon nitride film. With this configuration, the insulator 271a (insulator 271b) can have a laminated structure of a silicon nitride insulator 271a1 (insulator 271b1) and a silicon oxide insulator 271a2 (insulator 271b2).

[0406] Here, when the insulating film 271f is a laminated film, it is preferable to deposit the films successively without exposing them to the air environment. By depositing the films without exposing them to the air, the vicinity of the interface of the laminated film of the insulating film 271f can be kept clean. It is more preferable to deposit the films successively from the conductive film 242f to the insulating film 271f without exposing them to the air environment.

[0407] Note that heat treatment may be performed before the formation of the insulating film 271f. The heat treatment may be performed under reduced pressure, and the insulating film 271f may be formed successively without exposure to air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the conductive film 242f can be removed and the moisture and hydrogen concentrations in the conductive film 242f can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower.

[0408] Next, the insulating film 224f, the oxide semiconductor film 230f, the conductive film 242f, and the insulating film 271f are processed into island shapes by lithography to form the insulator 224, the oxide semiconductor 230, the conductor 242A, and the insulator 271A (see FIGS. 13A to 13D).

[0409] The above processing can be performed by a dry etching method or a wet etching method. Dry etching is suitable for fine processing. The insulating film 224f, the oxide semiconductor film 230f, the conductive film 242f, and the insulating film 271f may be processed under different conditions.

[0410] Here, the insulator 224, the oxide semiconductor 230, the conductor 242A, and the insulator 271A are preferably processed collectively into an island shape. In this case, a side end of the conductor 242A preferably coincides or substantially coincides with a side end of the oxide semiconductor 230. Furthermore, a side end of the insulator 224 preferably coincides or substantially coincides with a side end of the oxide semiconductor 230. Furthermore, a side end of the insulator 271A preferably coincides or substantially coincides with a side end of the conductor 242A. With such a structure, the number of steps for manufacturing the semiconductor device of one embodiment of the present invention can be reduced. Thus, a method for manufacturing a semiconductor device with high productivity can be provided.

[0411] The insulator 224, the oxide semiconductor 230, the conductor 242A, and the insulator 271A are formed so as to at least partially overlap with the conductor 205. The insulator 222 is exposed in a region not overlapping with the insulator 224, the oxide semiconductor 230, the conductor 242A, or the insulator 271A. However, this is not limited thereto, and the insulator 224 may remain on the insulator 222 in a region not overlapping with the oxide semiconductor 230. In this case, the insulator 224 does not have an island shape but has an opening in part as in the transistor 200 in FIGS. 9A to 9D.

[0412] 13(B) to 13(D), the side surfaces of the insulator 224, the oxide semiconductor 230, the conductor 242A, and the insulator 271A may be tapered. The taper angle of the side surfaces of the insulator 224, the oxide semiconductor 230, the conductor 242A, and the insulator 271A may be, for example, greater than or equal to 60° and less than 90°. By tapering the side surfaces in this manner, the coverage of the insulator 275 and the like can be improved in subsequent steps, and defects such as voids can be reduced.

[0413] Furthermore, without being limited to the above, the side surfaces of the insulator 224, the oxide semiconductor 230, the conductor 242A, and the insulator 271A may be perpendicular or approximately perpendicular to the top surface of the insulator 222. With such a configuration, it is possible to reduce the area and increase the density when providing multiple transistors.

[0414] In the lithography method, first, the resist is exposed through a mask. Next, the exposed area is removed or left using a developer to form a resist mask. Next, a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape by etching through the resist mask. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Also, a liquid immersion technique may be used in which a liquid (e.g., water) is filled between the substrate and the projection lens and exposure is performed. Also, an electron beam or an ion beam may be used instead of the light described above. When an electron beam or an ion beam is used, a photomask may not be used in some cases.

[0415] In addition, the resist mask that is no longer needed after processing can be removed by performing a dry etching process such as ashing using oxygen plasma (hereinafter sometimes referred to as oxygen plasma treatment), a wet etching process, a dry etching process followed by a wet etching process, or a wet etching process followed by a dry etching process.

[0416] Further, a hard mask made of an insulator or a conductor may be used under the resist mask. When using a hard mask, an insulating film or a conductive film that is to be a hard mask material is formed on the insulating film 271f, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask of a desired shape. For example, tungsten may be used as the hard mask material. Etching of the insulating film 271f and the like may be performed after removing the resist mask, or may be performed while leaving the resist mask. In the latter case, the resist mask may disappear during etching. The hard mask may be removed by etching after etching of the oxide semiconductor film 230f and the like. On the other hand, if the material of the hard mask does not affect a later process or can be used in a later process, it is not necessarily necessary to remove the hard mask.

[0417] Also, a SOC (Spin On Carbon) film and a SOG (Spin On Glass) film may be formed between the workpiece and the resist mask. By using the SOC film and the SOG film as a mask, it is possible to improve adhesion with the resist mask and improve the durability of the mask pattern. For example, a SOC film, a SOG film, and a resist mask can be formed in this order on the workpiece, and then a lithography method can be performed.

[0418] As the etching gas for the dry etching process, an etching gas containing a halogen can be used, and specifically, an etching gas containing one or more of fluorine, chlorine, and bromine can be used. For example, as the etching gas, C4F6 gas, C5F6 gas, C4F8 gas, CF4 gas, SF6 gas, CHF3 gas, CH2F2 gas, Cl2 gas, BCl3 gas, SiCl4 gas, or BBr3 gas can be used alone or in a mixture of two or more gases. In addition, oxygen gas, carbon dioxide gas, nitrogen gas, helium gas, argon gas, hydrogen gas, or hydrocarbon gas can be appropriately added to the above etching gas. In addition, depending on the object to be processed in the dry etching process, a gas containing a hydrocarbon gas or hydrogen gas without containing a halogen gas can be used as the etching gas. As the hydrocarbon used in the etching gas, methane (CH4), ethane (C2H6), propane (C3H8), butane (C4H 10 ), ethylene (C2H4), propylene (C3H6), acetylene (C2H2), and propyne (C3H4) can be used. The etching conditions can be appropriately set according to the target to be etched.

[0419] As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes can be configured to apply a high frequency voltage to one of the parallel plate electrodes. Or, it can be configured to apply a high frequency voltage of the same frequency to each of the parallel plate electrodes. Also, it can be configured to apply a plurality of different high frequency voltages to the parallel plate electrodes. Such a CCP etching apparatus is called a dual frequency excitation capacitively coupled plasma (DF-CCP) etching apparatus. In the DF-CCP etching apparatus, it can be configured to apply a high frequency voltage of different frequencies to each of the parallel plate electrodes. Or, it can be configured to apply a plurality of different high frequency voltages to one of the parallel plate electrodes. Or, a dry etching apparatus having a high density plasma source can be used. As the dry etching apparatus having a high density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus or the like can be used. The etching device can be appropriately set according to the object to be etched. In the above-mentioned dry etching device, reactive ion etching can be performed by applying a high frequency voltage to the electrode on the substrate side to generate a self-bias potential. In reactive ion etching, etching is performed by accelerating ion species in the plasma and colliding them with the workpiece, so that highly anisotropic etching can be performed.

[0420] In addition, in the above etching process, the insulator 271A can be made to function as an etching stopper that protects the conductor 242A. For example, if a metal hard mask is formed on the insulator 271A in the above etching process, it may be difficult to obtain an etching selectivity with respect to the conductor 242A when removing the hard mask. However, by forming the insulator 271A on the conductor 242A, the insulator 271A can be made to function as an etching stopper that protects the conductor 242A in the etching process for removing the hard mask. This can prevent a curved surface from being formed between the side surface and the top surface of the conductor 242A, so that the conductors 242a and 242b that are formed later have corner-shaped ends where the side surface and the top surface intersect, as shown in FIG. 7(D). By making the end where the side surface and the top surface of the conductor 242A intersect into a corner shape, the cross-sectional area of ​​the conductor 242A becomes larger than when the end has a curved surface. Furthermore, by using a nitride insulator that does not easily oxidize metal for the insulator 271A, it is possible to prevent the conductor 242A from being excessively oxidized, thereby reducing the resistance of the conductor 242a and the conductor 242b, and thus increasing the on-current of the transistor.

[0421] Furthermore, by processing the insulator 224 into an island shape, the insulator 275 can be provided in contact with the side surface of the insulator 224 and the top surface of the insulator 222 in a process described later. That is, the insulator 224 can be separated from the insulator 280 by the insulator 275. With this structure, impurities such as excessive oxygen and hydrogen can be prevented from entering the oxide semiconductor 230 from the insulator 280 through the insulator 224.

[0422] Next, the insulator 275 is formed to cover the insulator 224, the oxide semiconductor 230, the conductor 242A, and the insulator 271A, and then the insulator 280 is formed over the insulator 275 (see FIGS. 14A to 14D). The insulator 275 and the insulator 280 may be formed using the insulating material described above.

[0423] Here, it is preferable that the insulator 275 contacts the upper surface of the insulator 222 .

[0424] It is preferable to form an insulator having a flat upper surface as the insulator 280 by forming an insulating film to be the insulator 280 and performing a CMP process on the insulating film. Note that a silicon nitride film may be formed on the insulator 280 by, for example, a sputtering method, and the CMP process may be performed until the silicon nitride reaches the insulator 280.

[0425] Insulator 275 and insulator 280 can each be deposited using, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0426] It is preferable to use an insulator having a function of suppressing oxygen permeation for the insulator 275. For example, it is preferable to form a silicon nitride film as the insulator 275 by using a PEALD method. Alternatively, the insulator 275 may be configured by forming an aluminum oxide film by using a sputtering method and then forming a silicon nitride film thereon by using a PEALD method. By forming the insulator 275 with the above structure, it is possible to improve the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0427] In this manner, the oxide semiconductor 230 and the conductor 242A can be covered with the insulator 275 having a function of suppressing the diffusion of oxygen. This makes it possible to suppress the direct diffusion of oxygen from the insulator 280, etc., to the oxide semiconductor 230 and the conductor 242A in a later process.

[0428] It is also preferable to form a film of silicon oxide as the insulator 280 by a sputtering method. The insulating film to be the insulator 280 can be formed by a sputtering method in an atmosphere containing oxygen, so that the insulator 280 contains excess oxygen. The hydrogen concentration in the insulator 280 can be reduced by using a sputtering method that does not require the use of molecules containing hydrogen in the deposition gas. Note that a heat treatment may be performed before the deposition of the insulating film. The heat treatment may be performed under reduced pressure, and the insulating film may be deposited continuously without exposure to the air. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the insulator 275, for example, can be removed. The heat treatment conditions described above can be used for the heat treatment.

[0429] Next, the conductor 242A, the insulator 271A, the insulator 275, and the insulator 280 are processed by lithography to form openings reaching the oxide semiconductor 230 and the insulator 222 (see FIGS. 15A to 15D). Here, the conductor 242A is divided to form the conductor 242a and the conductor 242b, and the insulator 271A is divided to form the insulator 271a and the insulator 271b. The openings formed in the insulator 280 and the insulator 275 overlap with the oxide semiconductor 230 and the conductor 205.

[0430] The lithography method can be appropriately used as described above. In order to finely process the openings in the insulator 280, it is preferable to use a lithography method using short-wavelength light such as EUV light or an electron beam. For example, openings can be formed in the insulator 280 and the conductor 242a and the conductor 242b can be formed by using the method shown in Figures 16(A1) to 16(D2).

[0431] First, a coating film 277 is formed on the insulator 280, and then a coating film 278 is formed (see FIGS. 16(A1) and 16(A2)). The coating films 277 and 278 may have a function of improving adhesion between a resist mask described later and the insulator 280. The coating films 277 and 278 may be formed by, for example, a spin coating method. A non-photosensitive organic resin may be used as the coating films 277 and 278.

[0432] Here, the coating film 278 functions as a mask in an etching process for processing the coating film 277. Therefore, in the etching conditions for the coating film 277, it is preferable that the etching rate of the coating film 278 is smaller than the etching rate of the coating film 277. For example, the coating film 277 can be a film containing carbon, and the coating film 278 can be a film containing silicon and carbon. In this embodiment, an SOC film is formed as the coating film 277, and an SOG film is formed as the coating film 278.

[0433] In addition, the coating film 277 and the coating film 278 contain an organic solvent such as alcohol at the time of coating, but the organic matter contained therein may be reduced or removed during the subsequent steps or when the semiconductor device is completed. In addition, the coating film may be provided as needed, and the coating film may be configured as a single layer, or when only a resist mask described later is sufficient, a coating film may not be provided.

[0434] Next, a resist mask 279 having an opening is formed on the coating film 278 by using a lithography method (see FIG. 16(A1) and FIG. 16(A2)). The resist mask 279 can be formed by exposing a resist to, for example, KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Also, a liquid immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens and exposure is performed. Also, an electron beam or an ion beam may be used instead of the light described above. Note that when an electron beam or an ion beam is used, it may not be necessary to use a mask.

[0435] In the steps according to Fig. 16(B1) to Fig. 16(D2), it is preferable to process the workpiece using a dry etching method. The dry etching method is suitable for forming an opening with a high aspect ratio because it is possible to perform anisotropic etching. When performing anisotropic etching, for example, reactive ion etching is preferably performed. Note that the above description can be referred to for the conditions of the dry etching method and the dry etching apparatus. Note that it is preferable to perform the steps according to Fig. 16(B1) to Fig. 16(D2) continuously without exposure to the outside air. For example, a multi-chamber etching apparatus may be used to perform the processing without exposure to the outside air.

[0436] First, the coating film 278 is processed using a resist mask 279 to form the coating film 278 having an opening. For example, when a SOG film is used for the coating film 278, an etching process can be performed using a DF-CCP etching device and CF4 as an etching gas.

[0437] Next, the coating film 277 is processed using the coating film 278 as a mask to form the coating film 277 having an opening (see FIG. 16(B1) and FIG. 16(B2)). For example, when an SOC film is used for the coating film 277, an etching process can be performed using a DF-CCP etching device and H2 and N2 as etching gases. Here, since an SOG film is used for the coating film 278, it is possible to prevent the coating film 278 from disappearing during the etching process of the coating film 277.

[0438] It is preferable to simultaneously remove the resist mask 279 during processing of the coating film 277. Since an SOC film is used for the coating film 277, the resist mask 279 can be easily removed. If the resist mask 279 remains after the coating film 277 is formed, it is preferable to remove the resist mask 279.

[0439] Next, the coating film 277 is used as a mask to process the insulator 280 to form the insulator 280 having an opening. For example, when a silicon oxide film is used for the insulator 280, the etching process can be performed using a DF-CCP etching apparatus and etching gases of C4F8, C4F6, O2, and Ar.

[0440] Furthermore, the coating film 277 is used as a mask to process the insulator 275 and the insulator 271A to form the insulator 275, the insulator 271a, and the insulator 271b having openings (see FIG. 16(C1) and FIG. 16(C2)). For example, when a silicon oxide film and a silicon nitride film are used for the insulator 275 and the insulator 271A, an etching process can be performed using a DF-CCP etching device and CH2F2, O2, and Ar as etching gas. At this time, the conductor 242A and the insulator 222 can function as an etching stopper. In addition, it is preferable to simultaneously remove the coating film 278 during processing of the insulator 275 and the insulator 271A.

[0441] After the insulators 271a and 271b are formed, it is preferable to perform a dry etching process such as ashing using oxygen plasma to remove the coating film 277. However, this is not limited to this, and the coating film 277 may be removed after the conductors 242a and 242b are formed.

[0442] Next, it is preferable to remove the surface oxide film of the conductor 242A using the insulator 280 as a mask. For example, when a tantalum nitride film is used for the conductor 242A, an etching process can be performed using an ICP etching apparatus and BCl3 and Cl2 as etching gases.

[0443] Furthermore, the conductor 242A is processed using the insulator 280 as a mask to form the conductor 242a and the conductor 242b (see FIGS. 16D1 and 16D2). For example, when a tantalum nitride film is used for the conductor 242A, an etching process can be performed using an ICP etching apparatus and Cl2 and Ar as an etching gas. At this time, the oxide semiconductor 230 and the insulator 222 can function as an etching stopper. At this time, as shown in FIG. 16D2, in a cross-sectional view of the transistor 200 in the channel width direction, a curved surface may be formed between the side surface of the oxide semiconductor 230 and the top surface of the oxide semiconductor 230. That is, the end of the side surface and the end of the top surface may be rounded.

[0444] Further, a recess might be formed in a portion of the oxide semiconductor 230 that is exposed from the conductor 242a and the conductor 242b. In other words, on the top surface of the oxide semiconductor 230, a region sandwiched between the conductor 242a and the conductor 242b might be lower in height than a region overlapping with the conductor 242a and a region overlapping with the conductor 242b.

[0445] In this manner, openings can be formed in the insulator 275 and the insulator 280, and the insulator 271a, the insulator 271b, the conductor 242a, and the conductor 242b can be formed.

[0446] Note that an ashing process using oxygen plasma may be performed after processing the conductor 242A. By performing such an oxygen plasma process, impurities generated in the above etching process and diffused into the oxide semiconductor 230 and the like can be removed. Examples of the impurities include those originating from components contained in the workpiece of the above etching process and components contained in the gas used in the etching process. Examples of the impurities include chlorine, fluorine, tantalum, silicon, and hafnium. By removing the impurities attached to the oxide semiconductor 230 in this manner, the electrical characteristics and reliability of the transistor can be improved.

[0447] In addition, the processing of the conductor 242A and the oxygen plasma treatment can be performed consecutively without exposure to the outside air. For example, a multi-chamber etching device can be used to perform the treatment without exposure to the outside air.

[0448] In addition, in order to remove impurities and the like attached to the surface of the oxide semiconductor 230 in the above etching step, a cleaning treatment is preferably performed. Examples of the cleaning method include wet cleaning using a cleaning solution or the like (which can also be called a wet etching treatment), plasma treatment using plasma, and cleaning by heat treatment, and the above cleaning methods may be combined as appropriate. Note that the above grooves may become deeper due to the cleaning treatment.

[0449] The wet cleaning may be performed using an aqueous solution in which one or more of oxalic acid, phosphoric acid, and hydrofluoric acid are diluted with carbonated water or pure water. The wet cleaning may also be performed using an aqueous solution in which ammonia water is diluted with carbonated water or pure water. The wet cleaning may also be performed using pure water or carbonated water. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Alternatively, these cleaning methods may be combined as appropriate.

[0450] In this specification, an aqueous solution of hydrofluoric acid diluted with pure water may be called diluted hydrofluoric acid, and an aqueous solution of ammonia water diluted with pure water may be called diluted ammonia water. The concentration and temperature of the aqueous solution are appropriately adjusted depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water is preferably 0.01% to 5%, more preferably 0.1% to 0.5%. The hydrogen fluoride concentration of the diluted hydrofluoric acid is preferably 0.01 ppm to 100 ppm, more preferably 0.1 ppm to 10 ppm.

[0451] Note that the ultrasonic cleaning is preferably performed at a frequency of 200 kHz or more, more preferably at a frequency of 900 kHz or more, in order to reduce damage to the oxide semiconductor 230 and the like.

[0452] The above cleaning process may be performed multiple times, and the cleaning solution may be changed for each cleaning process. For example, a first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and a second cleaning process may be performed using pure water or carbonated water.

[0453] In this embodiment, wet cleaning is performed using carbonated water as the cleaning treatment. By performing such cleaning treatment, impurities attached to the surface of the oxide semiconductor 230 or diffused inside can be removed. Furthermore, the surface layer of the oxide semiconductor 230 that is damaged by the etching treatment can also be removed.

[0454] It is preferable to perform a heat treatment after the etching or the cleaning. The temperature of the heat treatment is 100° C. to 650° C., preferably 250° C. to 600° C., more preferably 300° C. to 550° C., and further preferably 350° C. to 400° C. The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. The heat treatment is preferably performed in an atmosphere containing oxygen, and is preferably performed at a temperature of 350° C. for one hour with a flow rate ratio of nitrogen gas to oxygen gas of 4:1. In this way, oxygen can be supplied to the oxide semiconductor 230, thereby reducing oxygen vacancies. In addition, by performing such a heat treatment, the crystallinity of the oxide semiconductor 230 can be improved. Furthermore, the supplied oxygen reacts with hydrogen remaining in the oxide semiconductor 230, and the hydrogen can be removed as H2O (dehydration). As a result, hydrogen remaining in the oxide semiconductor 230 recombines with the oxygen vacancies to form V OThe formation of H can be suppressed. Thus, the electrical characteristics of the transistor including the oxide semiconductor 230 can be improved, and the reliability can be improved. Furthermore, variation in the electrical characteristics of a plurality of transistors formed over the same substrate can be suppressed. Note that the heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in an oxygen atmosphere, the heat treatment may be successively performed in a nitrogen atmosphere without exposure to the air. The heat treatment can also serve as the heat treatment described in Embodiment 1. Thus, the heat treatment may cause a crystal region of the oxide semiconductor 230 to grow.

[0455] Note that when heat treatment is performed with the conductor 242a and the conductor 242b in contact with the oxide semiconductor 230, the sheet resistance of a region of the oxide semiconductor 230 overlapping with the conductor 242a and the region of the oxide semiconductor 230 overlapping with the conductor 242b may decrease. Also, the carrier concentration may increase. Thus, the resistance of the region of the oxide semiconductor 230 overlapping with the conductor 242a and the region of the oxide semiconductor 230 overlapping with the conductor 242b can be reduced in a self-aligned manner.

[0456] Next, an insulating film 250f to be the insulator 250 is formed so as to cover the openings formed in the insulator 280 and the like (see FIGS. 17A to 17D). Here, the insulating film 250f is formed along the openings of the insulator 280 and the insulator 275. The insulating film 250f is in contact with the insulator 280, the conductor 242a, the conductor 242b, the insulator 222, the insulator 224, and the oxide semiconductor 230.

[0457] The insulating film 250f can be formed by sputtering, CVD, MBE, PLD, or ALD. For example, the insulating film 250f is preferably formed by ALD. The insulating film 250f is preferably formed to a thin thickness, and it is necessary to reduce the variation in the thickness. In contrast, the ALD method is a film formation method in which a precursor and a reactant (e.g., an oxidizing agent) are alternately introduced, and the thickness can be adjusted by the number of times this cycle is repeated, so that precise thickness adjustment is possible. In addition, the insulating film 250f needs to be formed with good coverage on the bottom and side surfaces of the opening. By using the ALD method, layers of atoms can be deposited one by one on the bottom and side surfaces of the opening, so that the insulating film 250f can be formed with good coverage on the opening.

[0458] When the insulating film 250f is formed by an ALD method, ozone (O3), oxygen (O2), water (H2O), or the like can be used as an oxidizing agent. By using ozone (O3), oxygen (O2), or the like that does not contain hydrogen as an oxidizing agent, the amount of hydrogen that diffuses into the oxide semiconductor 230 can be reduced.

[0459] The insulator 250 can have a layered structure as shown in Fig. 8(B) etc. In the following, a method for forming an insulating film 250f will be described when the insulator 250 has a four-layer structure of an insulator 250a, an insulator 250b, an insulator 250d, and an insulator 250c, as in Fig. 8(B).

[0460] First, a film to become insulator 250a is formed so as to cover an opening formed in insulator 280 or the like, and then a film to become insulator 250b is formed on the film to become insulator 250a. In this embodiment, an aluminum oxide film is formed by thermal ALD as the film to become insulator 250a, and a silicon oxide film is formed by PEALD as the film to become insulator 250b.

[0461] Next, it is preferable to perform microwave treatment in an atmosphere containing oxygen. Here, the microwave treatment refers to treatment using a device having a power source that generates high-density plasma using microwaves, for example. In addition, in this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0462] In the microwave treatment, it is preferable to use a microwave treatment device having a power source that generates high-density plasma using microwaves. Here, the frequency of the microwave treatment device is preferably 300 MHz to 300 GHz, more preferably 2.4 GHz to 2.5 GHz, and can be, for example, 2.45 GHz. By using high-density plasma, high-density oxygen radicals can be generated. In addition, the power of the power source that applies microwaves of the microwave treatment device is preferably 1000 W to 10000 W, more preferably 2000 W to 5000 W. In addition, the microwave treatment device may have a power source that applies RF to the substrate side. In addition, by applying RF to the substrate side, oxygen ions generated by high-density plasma can be efficiently guided into the oxide semiconductor 230.

[0463] The microwave treatment is preferably carried out under reduced pressure, and the pressure is preferably 10 Pa to 1000 Pa, and more preferably 300 Pa to 700 Pa. The treatment temperature is preferably 750° C. or less, more preferably 500° C. or less, and can be, for example, about 250° C. After the oxygen plasma treatment, a heat treatment may be carried out continuously without exposure to the outside air. The temperature of the heat treatment is, for example, preferably 100° C. to 750° C., and more preferably 300° C. to 500° C.

[0464] Also, for example, the microwave treatment can be performed using oxygen gas and argon gas. Here, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 0% and less than 100%. Preferably, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 0% and less than 50%. More preferably, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 10% and less than 40%. Still more preferably, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 10% and less than 30%. In this way, by performing the microwave treatment in an atmosphere containing oxygen, the carrier concentration of the region exposed from the opening of the oxide semiconductor 230 can be reduced. Also, by preventing an excessive amount of oxygen from being introduced into the chamber in the microwave treatment, the carrier concentration of the oxide semiconductor 230 can be prevented from being excessively reduced.

[0465] By performing microwave treatment in an atmosphere containing oxygen, oxygen gas can be turned into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be applied to the region between the conductor 242a and the conductor 242b of the oxide semiconductor 230. The action of the plasma, microwaves, etc. can reduce the V O H can be split into oxygen vacancies and hydrogen, and the hydrogen can be removed from the region. When forming the structure shown in FIG. 8(B) or the like, it is preferable to use an insulating film (such as aluminum oxide) that has the function of capturing or fixing hydrogen as the film that becomes the insulator 250a. With this configuration, hydrogen generated by microwave treatment can be captured or fixed in the film that becomes the insulator 250a. In this way, the V included in the channel formation region can be O As a result, oxygen vacancies in the channel formation region and V O By supplying oxygen radicals generated by the oxygen plasma to the oxygen vacancies formed in the channel formation region, the oxygen vacancies in the channel formation region can be further reduced, and the carrier concentration can be reduced.

[0466] The oxygen injected into the channel formation region can be in various forms, such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (also called O radicals, which are atoms, molecules, or ions with an unpaired electron). Note that the oxygen injected into the channel formation region is preferably in one or more of the above forms, and is particularly preferably in the form of oxygen radicals. In addition, the film quality of the insulator 250 can be improved, thereby improving the reliability of the transistor.

[0467] Meanwhile, the oxide semiconductor 230 has a region overlapping with either the conductor 242a or the conductor 242b. The region can function as a source region or a drain region. Here, the conductor 242a and the conductor 242b preferably function as a shielding film against the action of microwaves, high frequency waves such as RF, oxygen plasma, and the like when performing microwave treatment in an atmosphere containing oxygen. For this reason, the conductor 242a and the conductor 242b preferably have a function of shielding electromagnetic waves of 300 MHz or more and 300 GHz or less, for example, 2.4 GHz or more and 2.5 GHz or less.

[0468] The conductors 242a and 242b shield against the effects of microwaves, high frequency waves such as RF, oxygen plasma, and the like, and therefore these effects do not extend to regions of the oxide semiconductor 230 that overlap with either the conductor 242a or the conductor 242b. As a result, the microwave treatment can reduce the V O Since there is no reduction in H and no excessive supply of oxygen, a decrease in the carrier concentration can be prevented.

[0469] In this manner, oxygen vacancies and V O By removing H, the channel formation region can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the region that functions as the source region or drain region can be suppressed, and the conductivity (state of being a low resistance region) before the microwave treatment can be maintained. This suppresses fluctuations in the electrical characteristics of the transistor, and suppresses variations in the electrical characteristics of the transistor within the substrate surface.

[0470] Furthermore, by modifying the film quality of the film to be the insulator 250a and the film to be the insulator 250b by microwave treatment, the diffusion of hydrogen, water, impurities, and the like can be suppressed. Therefore, a post-process such as deposition of a conductive film to be the conductor 260 or a post-treatment such as heat treatment can suppress the diffusion of hydrogen, water, impurities, and the like through the insulator 250 into the oxide semiconductor 230 and the like. In this way, by improving the film quality of the insulator 250, the reliability of the transistor can be improved.

[0471] Next, a film that will become the insulator 250d is formed on the film that will become the insulator 250b. In this embodiment, a hafnium oxide film is formed by a thermal ALD method as the film that will become the insulator 250d. Note that microwave processing may be performed again after the film that will become the insulator 250d is formed.

[0472] Next, a film that will become the insulator 250c is formed on the film that will become the insulator 250d. In this embodiment, a silicon nitride film is formed by the PEALD method as the film that will become the insulator 250c. In this manner, the insulating film 250f having the films that will become the insulators 250a to 250d can be formed.

[0473] In the above, an example has been described in which the microwave treatment is performed after the film to be the insulator 250b and after the film to be the insulator 250d are formed, but the present invention is not limited to this. A configuration may be used in which the microwave treatment is performed after the film to be the insulator 250c is formed. Alternatively, a configuration may be used in which the microwave treatment is performed before the film to be the insulator 250a is formed. A configuration may be used in which the microwave treatment is performed three or more times. In addition, the microwave treatment may serve as the heat treatment described in embodiment 1 in some cases. Thus, the microwave treatment may cause a crystalline region of the oxide semiconductor 230 to grow.

[0474] Moreover, heat treatment may be performed while the reduced pressure state is maintained after the microwave treatment. By performing such treatment, hydrogen in the insulating film and the oxide semiconductor 230 can be efficiently removed. Alternatively, the step of performing heat treatment may be repeated multiple times while the reduced pressure state is maintained after the microwave treatment. By repeatedly performing the heat treatment, hydrogen in the insulating film and the oxide semiconductor 230 can be more efficiently removed. Note that the heat treatment temperature is preferably 300° C. or higher and 500° C. or lower. The above heat treatment can also serve as the heat treatment described in Embodiment 1. Thus, the above heat treatment may cause a crystal region of the oxide semiconductor 230 to grow.

[0475] Next, a conductive film 260f to be the conductor 260 is formed (see FIGS. 17A to 17D). The conductive film 260f can be formed by using the above-mentioned conductive material by a sputtering method, a CVD method, an MBE method, a PLD method, a plating method, or an ALD method. For example, the conductive film 260f can be formed by stacking a titanium nitride film and a tungsten film by a CVD method. As shown in FIG. 8A, the conductor 260 can have a stacked structure of a titanium nitride conductor 260a and a tungsten conductor 260b. Note that the conductive film 260f may be formed while heating the substrate. The substrate heating can serve as the heat treatment described in Embodiment 1. Thus, the substrate heating may cause a crystal region of the oxide semiconductor 230 to grow.

[0476] Next, the insulating film 250f and the conductive film 260f are polished by CMP until the insulator 280 is exposed. That is, the portions of the insulating film 250f and the conductive film 260f exposed from the opening are removed. As a result, the insulator 250 and the conductor 260 (the conductor 260a and the conductor 260b) are formed in the opening overlapping the conductor 205 (see FIGS. 18(A) to 18(D)).

[0477] As a result, the insulator 250 is provided in the opening in contact with the conductor 242a, the conductor 242b, the oxide semiconductor 230, the insulator 224, and the insulator 222. The conductor 260 is arranged to fill the opening with the insulator 250 interposed therebetween. In this manner, the transistor 200 is formed.

[0478] Next, the insulator 282 is deposited over the insulator 250, the conductor 260, and the insulator 280 (see Figures 19(A) to 19(D)). The insulator 282 can be deposited by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulator 282 is preferably deposited by a sputtering method. By using a sputtering method that does not require the use of molecules containing hydrogen in the deposition gas, the hydrogen concentration in the insulator 282 can be reduced.

[0479] 8(A), the insulator 282 preferably has a layered structure of an insulator 282a and an insulator 282b. Here, the insulator 282a is preferably formed by an ALD method, and the insulator 282b is preferably formed by a sputtering method.

[0480] In this embodiment, the insulator 282a can be formed of aluminum oxide by thermal ALD. Here, the thickness of the insulator 282a can be 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less.

[0481] By forming the insulator 282a by the ALD method, the insulator 282a can be formed without causing excessive damage to the surface on which it is formed. Therefore, excessive damage can be prevented from being formed on the upper end of the insulator 250 and the upper surface of the conductor 260, thereby improving the electrical characteristics and reliability of the transistor 200.

[0482] Furthermore, by forming the insulator 282a by an ALD method, the insulator 282a can be formed without adding oxygen to the insulator 280. This makes it possible to prevent an excessive amount of oxygen from being added to the insulator 280. As a result, the electrical characteristics and reliability of the transistor 200 can be improved.

[0483] In this embodiment, aluminum oxide can be deposited as the insulator 282b by a sputtering method. By using a sputtering method in which molecules containing hydrogen are not required in a deposition gas, the hydrogen concentration in the insulator 282 can be reduced.

[0484] Here, by forming the insulator 282b in an oxygen-containing atmosphere by using a sputtering method, oxygen can be added to the insulator 280 while the insulator 282b is being formed. This allows the insulator 280 to contain excess oxygen. At this time, it is preferable to form the insulator 282b while heating the substrate. Here, by forming the insulator 282b on the insulator 282a, oxygen is added through the insulator 282a, so that the amount of oxygen injected into the insulator 280 can be controlled. If the insulator 282a is thick, the above-mentioned addition of oxygen is more likely to be hindered, and the amount of oxygen injected into the insulator 280 is reduced. If the insulator 282a is thin, the above-mentioned addition of oxygen is less likely to be hindered, and the amount of oxygen injected into the insulator 280 is increased. For example, by setting the thickness of the insulator 282a within the above range, a sufficient amount of oxygen can be supplied to the oxide semiconductor 230, and an excessive amount of oxygen can be prevented from being supplied to the oxide semiconductor 230. This can improve the electrical characteristics and reliability of the transistor 200. Note that oxygen can be added to the top end of the insulator 250 as well as the insulator 280 when the insulator 282b is formed.

[0485] Furthermore, by forming the insulator 282b on the insulator 282a, the upper end of the insulator 250 and the upper surface of the conductor 260 can be protected from the impact of ion collisions caused by the sputtering formation of the insulator 282b.

[0486] The aluminum oxide film is formed using an aluminum target in an atmosphere containing oxygen gas. The amount of oxygen injected into the insulator 280 can be controlled by the magnitude of the bias power applied to the substrate by the sputtering method. For example, the smaller the bias power, the smaller the amount of oxygen injected into the insulator 280, and the amount of oxygen is more likely to be saturated even if the film thickness of the insulator 282b is thin. Also, the larger the bias power, the larger the amount of oxygen injected into the insulator 280. By reducing the bias power, the amount of oxygen injected into the insulator 280 can be suppressed. When the substrate bias is applied by an RF power source, the RF frequency is preferably 10 MHz or more. Typically, it is 13.56 MHz. The higher the RF frequency, the smaller the damage to the substrate can be.

[0487] Furthermore, heat treatment may be performed before the insulator 282b is formed. The heat treatment may be performed under reduced pressure, and the insulator 282b may be formed continuously without exposure to air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulator 280 can be captured or fixed to the insulator 282a, thereby reducing the moisture and hydrogen concentrations in the insulator 280. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the temperature of the heat treatment is 250° C.

[0488] Next, the insulator 283 is formed over the insulator 282 (see Figures 19(A) to 19(D)). The insulator 283 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulator 283 is preferably formed by a sputtering method. By using a sputtering method that does not require the use of molecules containing hydrogen in the deposition gas, the hydrogen concentration in the insulator 283 can be reduced. In this embodiment, silicon nitride is formed as the insulator 283 by a sputtering method.

[0489] In this embodiment, silicon nitride is formed as the insulator 283 by a sputtering method, and aluminum oxide is formed as the insulator 282 by a thermal ALD method and a sputtering method. In this manner, by using silicon nitride having a function of suppressing diffusion of hydrogen as the insulator 283, diffusion of hydrogen from the upper layer of the transistor 200 can be suppressed. Furthermore, by using aluminum oxide having a function of capturing or fixing hydrogen as the insulator 282, hydrogen contained in the insulator 280 or the like can be captured or fixed to the insulator 282. As a result, the hydrogen concentration in the oxide semiconductor 230 and its vicinity can be reduced.

[0490] Next, the insulator 285 is formed over the insulator 283 (see Figures 19(A) to 19(D)). The insulator 285 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulator 285 is preferably formed by a sputtering method. By using a sputtering method that does not require the use of molecules containing hydrogen in the deposition gas, the hydrogen concentration in the insulator 285 can be reduced. In this embodiment, silicon oxide is formed as the insulator 285 by a sputtering method.

[0491] Here, it is preferable to successively form the insulators 282, 283, and 285 by a sputtering method without exposing them to the air environment. By forming the films without exposing them to the air, it is possible to prevent impurities or moisture from the air environment from adhering to the insulators 282, 283, and 285, and it is possible to keep the vicinity of the interface between the insulators 282 and 283, and the vicinity of the interface between the insulators 283 and 285 clean.

[0492] Next, an opening is formed in the insulator 271a, the insulator 275, the insulator 280, the insulator 282, the insulator 283, and the insulator 285 so as to reach the conductor 242a, and an opening is formed in the insulator 271b, the insulator 275, the insulator 280, the insulator 282, the insulator 283, and the insulator 285 so as to reach the conductor 242b. The opening may be formed by using a lithography method. In forming the opening, it is preferable to process the workpiece by using a dry etching method. The dry etching method is suitable for forming an opening with a high aspect ratio because it is possible to perform anisotropic etching. When performing anisotropic etching, it is preferable to perform, for example, reactive ion etching. Note that the above description can be referred to for the conditions of the dry etching method and the dry etching device. Note that the shape of the opening when viewed from above can be a circle, an approximately circle such as an ellipse, a polygon such as a rectangle, a polygon such as a rectangle with rounded corners, or the like.

[0493] Next, after the openings are formed, heat treatment is performed. The temperature of the heat treatment can be 100° C. or higher and 600° C. or lower, preferably 250° C. or higher and 550° C. or lower, more preferably 350° C. or higher and 450° C. or lower. Note that the heat treatment is preferably performed in a nitrogen gas or inert gas atmosphere. The heat treatment is preferably performed in an atmosphere not containing an oxidizing gas or an oxygen gas because the conductor 242a and the conductor 242b are exposed. For example, the heat treatment is preferably performed in a nitrogen gas atmosphere at a temperature of 400° C. for one hour. Note that the heat treatment may be performed under reduced pressure. By the heat treatment, oxygen contained in the insulator 280 can be supplied to the oxide semiconductor 230 through the insulator 250. As a result, oxygen vacancies in the channel formation region of the oxide semiconductor 230 can be reduced. The heat treatment can also serve as the heat treatment described in Embodiment 1. Therefore, the heat treatment may cause a crystal region of the oxide semiconductor 230 to grow.

[0494] Here, since the side surface of the insulator 280 is exposed at the opening, the heat treatment causes oxygen contained in the insulator 280 to diffuse outward, thereby controlling the amount of oxygen contained in the insulator 280. Meanwhile, since the insulators 282 and 283 having a barrier property against oxygen are provided on the insulator 280, oxygen does not diffuse outward from the upper surface of the insulator 280. This can prevent excessive oxygen from diffusing outward from the insulator 280, which would cause oxygen vacancies in the insulator 280. In addition, the oxide semiconductor 230, the conductor 242a, and the conductor 242b are covered with the insulator 275. This can prevent an excessive amount of oxygen from diffusing directly from the insulator 280 to the oxide semiconductor 230, the conductor 242a, and the conductor 242b during the heat treatment.

[0495] As described above, in the formation of the insulator 282b, oxygen is added to the insulator 280 through the insulator 282a, so that the amount of oxygen added to the insulator 280 can be controlled. Furthermore, the heat treatment causes oxygen to diffuse outward from the side surface of the insulator 280, so that the amount of oxygen in the insulator 280 can be made more suitable. In this manner, oxygen is supplied to the oxide semiconductor 230 from the insulator 280 in which the amount of oxygen is adjusted, so that a suitable amount of oxygen can be supplied to the oxide semiconductor 230. This reduces oxygen vacancies in the oxide semiconductor 230, and prevents an excessive amount of oxygen from being supplied to the oxide semiconductor 230. Thus, the electrical characteristics and reliability of the transistor 200 can be improved. Furthermore, the step of exposing the side surface of the insulator 280 can be combined with the step of forming openings into which the conductors 240a and 240b are embedded, so that the manufacturing process of the semiconductor device can be simplified.

[0496] By performing the heat treatment, hydrogen contained in the insulator 280, the insulator 250, and the oxide semiconductor 230 moves to the insulator 282 and is trapped in the insulator 282. In other words, hydrogen contained in the insulator 280, the insulator 250, and the oxide semiconductor 230 diffuses into the insulator 282. Thus, the hydrogen concentration in the insulator 282 is increased, but the hydrogen concentrations in the insulator 280, the insulator 250, and the oxide semiconductor 230 are decreased. Note that by providing the insulator 283 in contact with the top surface of the insulator 282, impurities such as moisture or hydrogen can be prevented from entering from above the insulator 283 during the heat treatment. By performing the heat treatment, hydrogen contained in the insulator 216, the insulator 224, and the oxide semiconductor 230 moves to the insulator 222 and is trapped in the insulator 222. In other words, hydrogen contained in the insulator 216, the insulator 224, and the oxide semiconductor 230 diffuses into the insulator 222. As a result, the hydrogen concentration in the insulator 222 is high, but the hydrogen concentrations in the insulator 216, the insulator 224, and the oxide semiconductor 230 are low. Note that by providing the insulator 221 in contact with the lower surface of the insulator 222, impurities such as moisture or hydrogen can be prevented from entering from below the insulator 221 during the heat treatment.

[0497] Next, an insulating film to become the insulator 241a and the insulator 241b is formed along the shape of the opening. The insulating film can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film to become the insulator 241a and the insulator 241b is preferably formed by using an ALD method because it is formed in an opening with a large aspect ratio. In addition, it is preferable to use an insulating film having a function of suppressing oxygen permeation as the insulating film to become the insulator 241a and the insulator 241b. For example, it is preferable to form a silicon nitride film by using a PEALD method. Silicon nitride is preferable because it has a high blocking property against hydrogen.

[0498] Next, the insulating film is anisotropically etched to form the insulator 241a and the insulator 241b. Here, the insulator 241a is formed so as to cover the side wall of the opening on the conductor 242a, and the insulator 241b is formed so as to cover the side wall of the opening on the conductor 242b. A dry etching method or the like may be used for anisotropically etching the insulating film to become the insulator 241a and the insulator 241b. For example, reactive ion etching is preferably performed. By providing the insulator 241a and the insulator 241b on the side wall of the opening, it is possible to suppress the permeation of oxygen from the outside and prevent the oxidation of the conductor 240a and the conductor 240b to be formed next. In addition, it is possible to prevent impurities such as water and hydrogen contained in the insulator 280 from diffusing into the conductor 240a and the conductor 240b. Note that the anisotropic etching may form a recess in a part of the upper surface of the conductor 242a and the conductor 242b.

[0499] Next, a conductive film that becomes the conductor 240a and the conductor 240b is formed. The conductive film is preferably a laminated structure including a conductor that has a function of suppressing the permeation of impurities such as water and hydrogen. For example, the conductive film may be a laminated structure of tantalum nitride, titanium nitride, or the like, and tungsten, molybdenum, copper, or the like. The conductive film that becomes the conductor 240a and the conductor 240b can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0500] Next, CMP processing is performed to remove parts of the conductive film that will become the conductor 240a and the conductor 240b, exposing the top surface of the insulator 285. As a result, the conductive film remains only in the openings, and the conductors 240a and 240b have flat top surfaces (see Figures 7(A) to 7(D)). Note that the CMP processing may remove parts of the top surface of the insulator 285.

[0501] After the conductor 240a and the conductor 240b are formed, heat treatment may be further performed. The heat treatment can be performed under conditions similar to those of the above heat treatment. By performing the heat treatment, the amount of oxygen supplied to the oxide semiconductor 230 can be adjusted. As a result, the electrical characteristics and reliability of the transistor 200 can be improved.

[0502] In this manner, the semiconductor device shown in FIGS. 7A to 7D can be manufactured.

[0503] The semiconductor device according to this embodiment includes an OS transistor. In this embodiment, by using an axial growth CAAC for an oxide semiconductor layer of the OS transistor, a semiconductor device with favorable electrical characteristics can be provided. For example, the on-state current, the S value, the field-effect mobility, the frequency characteristics, and the like of the transistor can be improved. In addition, a highly reliable semiconductor device can be provided.

[0504] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in the case where a plurality of configuration examples are shown in one embodiment mode in this specification, the configuration examples can be combined as appropriate.

[0505] (Embodiment 3) In this embodiment, a semiconductor device 900 according to one embodiment of the present invention will be described. The semiconductor device 900 can function as a memory device.

[0506] Fig. 20 shows a block diagram illustrating a configuration example of a semiconductor device 900. The semiconductor device 900 shown in Fig. 20 has a driver circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Fig. 20 shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.

[0507] The transistor described in Embodiment 2 can be used as the memory cell 950. By using the transistor, the operation speed of the memory device can be improved. Furthermore, the memory device can be miniaturized and highly integrated. Furthermore, the capacitance per area of ​​the memory device can be increased.

[0508] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generating circuit 928.

[0509] In the semiconductor device 900, each circuit, each signal, and each voltage can be appropriately selected or omitted as necessary. Alternatively, other circuits or other signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0510] Moreover, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may be generated by the control circuit 912.

[0511] The control circuit 912 is a logic circuit having a function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0512] The voltage generating circuit 928 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 928. For example, when an H-level signal is provided as the signal WAKE, the signal CLK is input to the voltage generating circuit 928, and the voltage generating circuit 928 generates a negative voltage.

[0513] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950. The peripheral circuit 911 has a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0514] The row decoder 941 and the column decoder 942 have a function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has a function of selecting a row specified by the row decoder 941. The column driver 924 has a function of writing data to the memory cell 950, a function of reading data from the memory cell 950, a function of holding the read data, and the like.

[0515] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory cell 950. The data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is a signal RDA.

[0516] PSW931 is the V to the peripheral circuit 915 DDThe PSW 932 has the function of controlling the supply of V HM In this embodiment, the high power supply voltage of the semiconductor device 900 is V DD and the low power supply voltage is GND (ground potential). Also, V HM is the high power supply voltage used to drive the word line high, and V DD 20, in the peripheral circuit 915, V DD Although the number of power domains to which the power is supplied is set to one, it is also possible to set it to multiple. In this case, a power switch may be provided for each power domain.

[0517] 21A to 21H, examples of other memory cell configurations that can be applied to the memory cell 950 will be described.

[0518] [DOSRAM] 21A shows an example of a circuit configuration of a memory cell of a DRAM. In this specification and the like, a DRAM using an OS transistor is referred to as a dynamic oxide semiconductor random access memory (DOSRAM). The memory cell 951 includes a transistor M1 and a capacitor CA.

[0519] The transistor M1 may have a front gate (sometimes simply called a gate) and a back gate. In this case, the back gate may be connected to a wiring to which a constant potential or a signal is applied. The front gate and the back gate may be connected to each other.

[0520] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, a second terminal of the transistor M1 is connected to the wiring BIL, a gate of the transistor M1 is connected to the wiring WOL, and a second terminal of the capacitance element CA is connected to the wiring CAL.

[0521] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to the wiring CAL.

[0522] Data is written and read by applying a high-level potential to the wiring WOL to turn on the transistor M1 and connect the wiring BIL to the first terminal of the capacitor CA.

[0523] Further, a memory cell that can be used as the memory cell 950 is not limited to the memory cell 951, and the circuit configuration can be changed. For example, the memory cell 952 shown in FIG. 21B may be used. The memory cell 952 is an example of a memory cell that does not include a capacitor CA and a wiring CAL. The first terminal of the transistor M1 is in an electrically floating state.

[0524] In the memory cell 952, the potential written through the transistor M1 is held in a capacitance (also referred to as a parasitic capacitance) between the first terminal and the gate, which is indicated by a dashed line. With this configuration, the configuration of the memory cell can be significantly simplified.

[0525] Note that the OS transistor described in Embodiment 2 is preferably used as the transistor M1. By using the OS transistor described in Embodiment 2, the operation speed of the memory device can be improved. Furthermore, the area occupied by the memory cell can be reduced. Furthermore, the OS transistor has a characteristic of having an extremely small off-state current. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made extremely low. That is, since written data can be held by the transistor M1 for a long time, the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be eliminated. Since the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 951 and the memory cell 952.

[0526] Here, an example of the structure of a DOSRAM will be described with reference to Fig. 22. In Fig. 22, the X direction is parallel to the channel width direction of the illustrated transistor, the Y direction is perpendicular to the X direction, and the Z direction is perpendicular to the X and Y directions.

[0527] As shown in FIG. 22, the memory cell 951 includes a transistor M1 and a capacitor CA. An insulator 284 is provided over the transistor M1. The insulator 284 may be an insulator applicable to the insulator 216. The transistor M1 has a similar configuration to the transistor 200 described in embodiment 2, and the same components are denoted by the same reference numerals. For details of the transistor 200, refer to embodiment 2. A conductor 240b (conductor 240b1 and conductor 240b2) is provided in contact with one of the source electrode and drain electrode (conductor 242b) of the transistor M1. The conductor 240b extends in the Z direction and functions as a wiring BIL. The conductor 260 of the transistor 200 extends in the X direction and functions as a wiring WOL.

[0528] The capacitor CA includes a conductor 453 over the conductor 242a, an insulator 454 over the conductor 453, and a conductor 460 (a conductor 460a and a conductor 460b) over the insulator 454.

[0529] At least a portion of the conductor 453, the insulator 454, and the conductor 460 is disposed inside the openings provided in the insulators 271a, 275, 280, 282, 283, and 285, respectively. Ends of the conductors 453, 454, and 460 are located at least on the insulator 283, and preferably on the insulator 285. The insulator 454 is provided so as to cover the end of the conductor 453. This allows the conductor 453 and the conductor 460 to be electrically insulated from each other.

[0530] The capacitance of the capacitive element CA can be increased by increasing the depth of the openings provided in the insulators 271a, 275, 280, 282, 283, and 285 (i.e., increasing the thickness of one or more of the insulators 271a, 275, 280, 282, 283, and 285). By increasing the capacitance per unit area of ​​the capacitive element CA, the miniaturization or high integration of the memory device can be achieved.

[0531] The conductor 453 has a region that functions as one electrode (lower electrode) of the capacitor CA. The insulator 454 has a region that functions as a dielectric of the capacitor CA. The conductor 460 has a region that functions as the other electrode (upper electrode) of the capacitor CA. The upper part of the conductor 460 can be extended to function as a wiring CAL. The capacitor CA forms a metal-insulator-metal (MIM) capacitor.

[0532] The conductor 242a provided over and overlapping with the oxide semiconductor 230 functions as an electrode electrically connected to a lower electrode of the capacitor CA.

[0533] The conductor 453 and the conductor 460 of the capacitor CA can be formed using any of the conductors that can be used for the conductor 205 or the conductor 260. The conductor 453 and the conductor 460 are preferably formed using a film formation method with good coverage such as an ALD method or a CVD method. For example, the conductor 453 can be made of titanium nitride or tantalum nitride formed using an ALD method or a CVD method.

[0534] In addition, the upper surface of the conductor 242a is in contact with the lower surface of the conductor 453. Here, by using a conductive material with good conductivity as the conductor 242a, the contact resistance between the conductor 453 and the conductor 242a can be reduced.

[0535] Alternatively, the conductor 460a may be made of titanium nitride formed by an ALD method or a CVD method, and the conductor 460b may be made of tungsten formed by a CVD method. If the adhesion of tungsten to the insulator 454 is sufficiently high, the conductor 460 may have a single layer structure of tungsten formed by a CVD method.

[0536] The insulator 454 of the capacitor CA is preferably made of a high-k material as described in the previous embodiment. By using such a high-k material, the insulator 454 can be made thick enough to suppress leakage current and the capacitance of the capacitor CA can be sufficiently ensured. In addition, the insulator 454 is preferably formed by a film formation method with good coverage, such as an ALD method or a CVD method.

[0537] In addition, it is preferable to use insulators made of the above materials in a laminated manner, and it is preferable to use a laminated structure of a material with a high relative dielectric constant (high-k) and a material with a higher dielectric strength than the high relative dielectric constant (high-k) material. For example, an insulator laminated in the order of zirconium oxide, aluminum oxide, and zirconium oxide can be used as the insulator 454. Also, for example, an insulator laminated in the order of zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide can be used. Also, for example, an insulator laminated in the order of hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide can be used. By using an insulator with a relatively high dielectric strength such as aluminum oxide in a laminated manner, the dielectric strength is improved and electrostatic breakdown of the capacitance element CA can be suppressed.

[0538] Furthermore, a material that can have ferroelectricity may be used as the insulator 454. Examples of the material that can have ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO X (X is a real number greater than 0). Examples of materials that can have ferroelectricity include materials in which an element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to hafnium oxide. Here, the ratio of the number of hafnium atoms to the number of element J1 can be set appropriately, for example, the ratio of the number of hafnium atoms to the number of element J1 can be set to 1:1 or close thereto. Examples of materials that can have ferroelectricity include materials in which an element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to zirconium oxide. Also, the ratio of the number of zirconium atoms to the number of element J2 can be set appropriately, for example, the ratio of the number of zirconium atoms to the number of element J2 can be set to 1:1 or close thereto. In addition, lead titanate (PbTiO XPiezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may also be used.

[0539] In addition, examples of materials that can have ferroelectricity include metal nitrides having elements M1, M2, and nitrogen. Here, the element M1 is one or more selected from aluminum, gallium, indium, and the like. In addition, the element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, and the like. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set appropriately. In addition, metal oxides having elements M1 and nitrogen may have ferroelectricity even if they do not contain element M2. In addition, examples of materials that can have ferroelectricity include materials in which element M3 is added to the above metal nitrides. In addition, element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, and the like. Here, the ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be set appropriately.

[0540] Moreover, examples of materials that can have ferroelectricity include perovskite-type oxynitrides such as SrTaO2N and BaTaO2N, and GaFeO3 with a κ-alumina structure.

[0541] In the above description, metal oxides and metal nitrides are exemplified, but the present invention is not limited thereto. For example, metal oxynitrides in which nitrogen is added to the above-mentioned metal oxides, or metal oxynitrides in which oxygen is added to the above-mentioned metal nitrides, etc. may be used.

[0542] As a material capable of having ferroelectricity, for example, a mixture or compound made of a plurality of materials selected from the materials listed above can be used. Alternatively, the insulator 454 can have a laminated structure made of a plurality of materials selected from the materials listed above. However, the crystal structure (characteristics) of the materials listed above may change depending on not only the film formation conditions but also various processes, so in this specification, not only materials that exhibit ferroelectricity are called ferroelectrics, but also materials capable of having ferroelectricity.

[0543] A ferroelectric is an insulator, and has a property that polarization occurs inside when an electric field is applied from the outside, and the polarization remains even when the electric field is made zero. Therefore, a nonvolatile memory element can be formed by using a capacitance element (hereinafter, sometimes called a ferroelectric capacitor) using this material as a dielectric. A nonvolatile memory element using a ferroelectric capacitor is sometimes called a FeRAM (Ferroelectric Random Access Memory), a ferroelectric memory, etc. For example, a ferroelectric memory has a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is electrically connected to one terminal of the ferroelectric capacitor. Therefore, when a ferroelectric capacitor is used as the capacitance element CA, the memory device shown in this embodiment functions as a ferroelectric memory.

[0544] It is said that ferroelectricity is expressed by displacing oxygen or nitrogen in crystals contained in the ferroelectric layer due to an external electric field. It is also presumed that the expression of ferroelectricity depends on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, in order for the insulator 454 to express ferroelectricity, the insulator 454 needs to include crystals. In particular, it is preferable for the insulator 454 to include crystals having an orthorhombic crystal structure, since ferroelectricity is expressed. The crystal structure of the crystals contained in the insulator 454 may be one or more selected from a cubic crystal system, a tetragonal crystal system, an orthorhombic crystal system, a monoclinic crystal system, and a hexagonal crystal system. The insulator 454 may have an amorphous structure. In this case, the insulator 454 may be a composite structure having an amorphous structure and a crystalline structure.

[0545] The deeper the openings provided in the insulators 271a, 275, 280, 282, 283, and 285 are (that is, the thicker one or more of the insulators 271a, 275, 280, 282, 283, and 285 are), the larger the capacitance of the capacitance element CA can be. For example, the capacitance of the capacitance element CA can be set by adjusting the film thickness of the insulator 285. Specifically, the film thickness of the insulator 285 can be set in the range of 50 nm to 250 nm, and the depth of the opening can be set to about 150 nm to 350 nm. By forming the capacitance element CA in such a range, it is possible to provide the capacitance element CA with sufficient capacitance and prevent the height of one layer from becoming excessively high in a semiconductor device in which a plurality of memory cell layers are stacked. Note that a configuration may be adopted in which the capacitance of the capacitance element provided in each memory cell is different in each of the plurality of memory cell layers. In this configuration, for example, the thickness of the insulator 285 provided in each memory cell layer may be made different.

[0546] In an opening in the insulator 285 or the like in which the capacitor CA is disposed, a sidewall of the opening may be perpendicular or approximately perpendicular to the top surface of the insulator 222, or may be tapered. By making the sidewall tapered, the coverage of the conductor 453 or the like provided in the opening of the insulator 285 or the like can be improved, and defects such as voids can be reduced.

[0547] The conductor 242b provided so as to overlap the oxide semiconductor 230 functions as a wiring electrically connected to the conductor 240b. For example, in FIG. 22, the upper surface and side end portions of the conductor 242b are electrically connected to the conductor 240b extending in the Z direction.

[0548] Since the conductor 240b directly contacts at least one of the upper surface and side end of the conductor 242b, there is no need to provide a separate electrode for connection, and therefore the area occupied by the memory array can be reduced. Furthermore, the integration degree of the memory cells is improved, and the memory capacity of the memory device can be increased. Note that the conductor 240b preferably contacts a part of the upper surface and the side end of the conductor 242b. Since the conductor 240b contacts multiple surfaces of the conductor 242b, the contact resistance between the conductor 240b and the conductor 242b can be reduced.

[0549] Conductor 240b is disposed within openings formed in insulator 216, insulator 221, insulator 222, insulator 224, insulator 271b, insulator 275, insulator 280, insulator 282, insulator 283, insulator 285, and insulator 284.

[0550] 22, the insulator 241b is preferably provided in contact with the side surface of the conductor 240b. Specifically, the insulator 241b is provided in contact with the inner walls of the openings of the insulators 216, 221, 222, 224, 271b, 275, 280, 282, 283, 285, and 284. The insulator 241b is also formed on the side surface of the oxide semiconductor 230 that is formed to protrude inward of the openings. Here, at least a part of the conductor 242b is exposed from the insulator 241b and is in contact with the conductor 240b. That is, the conductor 240b is provided so as to fill the inside of the openings via the insulator 241b.

[0551] 22, the uppermost portion of the insulator 241b formed below the conductor 242b is preferably located below the upper surface of the conductor 242b. With this configuration, the conductor 240b can be in contact with at least a part of the side end portion of the conductor 242b. The insulator 241b formed below the conductor 242b preferably has a region in contact with a side surface of the oxide semiconductor 230. With this configuration, impurities such as water and hydrogen contained in the insulator 280 can be prevented from entering the oxide semiconductor 230 through the conductor 240b.

[0552] Furthermore, in the opening where the conduct...

Claims

1. An oxide semiconductor layer containing indium formed over a substrate, the oxide semiconductor layer is formed parallel or substantially parallel to a surface of the substrate; the oxide semiconductor layer has a first region, a second region on the first region, and a third region on the second region; the first region is located at a distance of 0 nm to 3 nm substantially perpendicularly from a surface on which the oxide semiconductor layer is to be formed, In a cross-sectional observation of the oxide semiconductor layer using a transmission electron microscope, bright points arranged in layers in a direction parallel to a surface on which the oxide semiconductor layer is formed are confirmed in each of the first region, the second region, and the third region. An oxide semiconductor layer.

2. In claim 1, the second region comprises zinc; the second region has crystals; The c-axis of the crystal is approximately parallel to a normal direction of a surface on which the oxide semiconductor layer is formed.

3. In claim 1, The second region has a higher c-axis orientation rate than the first region.

4. In claim 1, The third region has a higher c-axis orientation rate than the first region.

5. In claim 1, a content of indium in the first region is higher than a content of indium in the second region; an indium content in the third region being higher than an indium content in the second region;

6. In any one of claims 1 to 5, The oxide semiconductor layer is formed on an insulator, The insulator has an amorphous structure. An oxide semiconductor layer.

7. a first insulator on a substrate, an oxide semiconductor layer on the first insulator, a second insulator on the oxide semiconductor layer, and a conductor on the second insulator; the first insulator and the oxide semiconductor layer are formed parallel or substantially parallel to a surface of the substrate; the oxide semiconductor layer contains indium, the oxide semiconductor layer has a first region, a second region on the first region, and a third region on the second region; the first region is located at a distance of 0 nm to 3 nm substantially perpendicularly from a surface on which the oxide semiconductor layer is to be formed, In a cross-sectional observation of the oxide semiconductor layer using a transmission electron microscope, bright points arranged in layers in a direction parallel to a surface on which the oxide semiconductor layer is formed are confirmed in each of the first region, the second region, and the third region. Semiconductor device.

8. In claim 7, the second region comprises zinc; the second region has crystals; a c-axis of the crystal is approximately parallel to a normal direction of a surface on which the oxide semiconductor layer is formed.

9. In claim 7, The semiconductor device, wherein the c-axis orientation rate in the second region is higher than the c-axis orientation rate in the first region.

10. In claim 7, The semiconductor device, wherein the c-axis orientation rate in the third region is higher than the c-axis orientation rate in the first region.

11. In claim 7, a content of indium in the first region is higher than a content of indium in the second region; A semiconductor device, wherein the third region has a higher indium content than the second region.

12. In any one of claims 7 to 11, The first insulator has an amorphous structure. Semiconductor device.

13. In claim 12, a third insulator covering the first insulator and the oxide semiconductor layer; the third insulator has an opening reaching the oxide semiconductor layer; the second insulator and the conductor are disposed within the opening. Semiconductor device.

14. In claim 13, the second insulator is in contact with the third region; Semiconductor device.

15. A method for manufacturing a semiconductor device including an oxide semiconductor layer containing first to third metal oxides, first to third insulators, and a conductor, depositing the first insulator on a substrate; forming the oxide semiconductor layer on the first insulator; The oxide semiconductor layer is subjected to heat treatment. The first insulator and the oxide semiconductor layer are processed into an island shape; forming a third insulator to cover the first insulator and the oxide semiconductor layer; forming an opening in the third insulator that reaches the oxide semiconductor layer; forming the second insulator in the opening; forming the conductor on the second insulator in the opening; In the step of forming the oxide semiconductor layer, forming a film of the first metal oxide; forming a film of the second metal oxide on the first metal oxide; forming a third metal oxide film on the second metal oxide film; Each of the first metal oxide and the third metal oxide is formed by an ALD method using a precursor containing indium and an oxidizing agent; The second metal oxide is formed by a sputtering method using a sputtering target containing indium. A method for manufacturing a semiconductor device.

16. In claim 15, The sputtering target comprises zinc, The method for manufacturing a semiconductor device, wherein the sputtering is performed in an atmosphere containing oxygen.

17. In claim 15, The method for manufacturing a semiconductor device, wherein the temperature for heating the substrate in the ALD method is 100° C. or higher and 350° C. or lower.

18. In claim 15, In a cross-sectional observation of the oxide semiconductor layer using a transmission electron microscope, bright spots arranged in layers in a direction parallel to a surface on which the oxide semiconductor layer is formed are observed in each of the first metal oxide, the second metal oxide, and the third metal oxide.

19. In claim 15, No clear boundary is observed between the first metal oxide and the second metal oxide; A method for manufacturing a semiconductor device, wherein no clear boundary is observed between the second metal oxide and the third metal oxide.

20. In claim 15, The temperature of the heat treatment is 350° C. or higher and 550° C. or lower.

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