CMOS image sensing devices

Abstract

To provide image sensing devices which include photodiodes with large charge capacities even in the case of small-size elements with high integration.SOLUTION: The invention relates to a dual vertical transfer gate, and a transistor and a CMOS image sensing device that include the same. In one embodiment, a gate of the dual vertical transfer transistor has two poles extended to an n-type region of a photodiode, and a connecting portion connecting the two poles to each other, and includes a first insulating pattern between the poles and on the substrate.SELECTED DRAWING: Figure 12A

Description

[Technical field]

[0001] The present invention relates to a CMOS image sensing device, and more particularly to a circuit including a transistor having a vertical channel gate, a CMOS image sensing device having the circuit as a unit pixel circuit, and a method for manufacturing the unit pixel circuit including the vertical channel gate and the CMOS image sensing device. [Background technology]

[0002] An image sensing device, or image sensor, is a semiconductor device that converts optical signals into electrical signals. Image sensing devices are implemented as integrated circuits using complementary metal oxide semiconductor (CMOS) devices or charge coupled devices (CCDs) on a substrate.

[0003] Until the 1990s, CCDs were widely used because they had better optical characteristics than CMOS devices. However, after pinned PDs were applied and circuit-based noise reduction technology was developed, CIS devices, which have a simpler structure and are easier to manufacture, are used far more frequently. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent No. 11,521,997 B2 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide an image sensing device including a photodiode (PD) having a high charge capacity even in a small-sized device due to high integration. Another object of the present invention is to provide a transistor including a three-dimensional gate having excellent negative charge transfer efficiency.

[0006] Furthermore, one objective of the present invention is to prevent a phenomenon in which an electric field is concentrated between two poles and negative charges entering between the two poles are not transferred well to the FD (potential hump), and a phenomenon in which negative charges flow back between the poles in the FD region (backflow). [Means for solving the problem]

[0007] As an embodiment of the present invention, the present invention provides a transistor including a first n-type region disposed under a gate, two gate poles extending to the n-type region, a gate having a connection portion connecting the two gate poles, a second n-type region adjacent to the gate, and a first insulating pattern between the gate poles and on a substrate. Exemplarily, the first insulating pattern may include one or more composite layers selected from silicon nitride film (SixNy), silicon oxide film (SiO2), silicon oxynitride film (SiON), silicon carbon oxide film (SiOC), silicon carbonitride film (SiCN), and silicon carbonitride film (SiOCN). As another embodiment, the first insulating pattern may include a void.

[0008] In another embodiment, the present invention provides a transistor including an n-type region of a photodiode disposed below a gate, a gate having two poles extending to the n-type region and a connection portion connecting the two poles, a floating diffusion region adjacent to the gate, a first insulating pattern between the poles, and on a substrate.

[0009] In another embodiment of the present invention, there is provided a unit circuit including a first transistor including a first n-type region in a first substrate, two poles extending to the first n-type region, a gate having a connection portion connecting the two poles, a second n-type region adjacent to the gate, a first insulating pattern between the poles and on the first substrate, and a second transistor in a second substrate, wherein the second n-type region of the first substrate and the gate of the second transistor of the second substrate are connected.

[0010] In another embodiment of the present invention, the present invention provides a unit circuit including a PD region in a first substrate, two poles extending to an n-type region of the PD, a gate having a connection portion connecting the two poles, an FD region adjacent to the gate, a transfer transistor including a first insulating pattern between the poles and on the first substrate, and a source follower transistor in a second substrate, in which the FD region of the first substrate and the gate of the source follower transistor of the second substrate are connected.

[0011] In another embodiment of the present invention, there is provided an image sensing device including a PD region, two poles extending to an n-type region of the PD, a gate having a connection portion connecting the two poles, and a first insulating pattern between the poles, the image sensing device including a first substrate including an FD region, a second substrate including a source follower transistor, and a third substrate including a logic circuit, wherein the FD region of the first substrate is connected to the gate of the source follower transistor of the second substrate. Effect of the Invention

[0012] In the transistor and the device including the transistor according to the present embodiment, when a gate having two poles is used to transfer negative charges from a PD formed deep to the bottom of a substrate to an FD region, a backflow phenomenon in which negative charges are drawn by a high electric field formed by the two poles and a connection part can be prevented. The transistor and the device including the transistor according to the present embodiment exhibit excellent negative charge mobility and can also improve light conversion efficiency.

[0013] As image sensing devices become more highly integrated, the unit pixel circuits become smaller, the photodiodes PD become deeper, the gate poles become thinner, and the distance between the poles becomes narrower. The present invention can prevent the backflow of electric field caused by the miniaturization of devices. It can also prevent the problem of electric field rise caused by the portions extending outward from the poles as well as between the gate poles. As such, the present invention is expected to be more effective as devices are miniaturized and the applied processes are further miniaturized.

[0014] In addition, in terms of device design, there is no need to connect two gate poles with separate wiring, which simplifies wiring connection and does not cause misalignment problems when forming contacts to connect the wiring and the gate pole, which is advantageous in terms of device placement margin.

[0015] Pixel sizes are becoming smaller and smaller to improve the integration and performance of image sensing devices. In order to reduce pixel sizes and effectively arrange the pixels while ensuring device performance, stacked image sensing devices can be manufactured by applying 'substrate stacking technology'. The present invention can be applied to substrate stacking technology, which involves a pixel substrate manufacturing process in which pixel circuits are separated and manufactured on separate substrates, and then bonding two pixel substrates to manufacture an image sensing device, without complicated processes or many additional processes. As such, the present invention is compatible with cutting-edge processes for improving the integration and performance of image sensing devices, and is expected to be used more widely as image sensing devices become more miniaturized.

[0016] In this embodiment, the first insulating pattern is formed on the substrate surface and between the two poles to reduce the electric field in the area between the two poles, thereby preventing a potential hump in which the negative charge between the two poles is not transferred to the FD, and a backflow in which the negative charge flows back between the poles in the FD area. [Brief description of the drawings]

[0017] [Figure 1] FIG. 1 is a cross-sectional view of a two-stack CMOS image sensing CIS device according to one embodiment of the present invention. [Diagram 2] FIG. 2 is a cross-sectional view of another embodiment of a two-stack CMOS image sensing CIS device. [Diagram 3] FIG. 1 is a cross-sectional view of a triple-stack CMOS image sensing CIS device according to one embodiment of the present invention. [Figure 4] FIG. 2 is a cross-sectional view of a three-stack CMOS image sensing CIS device according to another embodiment of the present invention. [Diagram 5] FIG. 2 is a cross-sectional view of another embodiment of the present invention of a three-stack CMOS image sensing CIS device. [Figure 6] FIG. 2 is a cross-sectional view of another embodiment of the present invention of a three-stack CMOS image sensing CIS device. [Figure 7A] This is a circuit diagram in which a photodiode PD shares a unit pixel processing circuit. [Figure 7B] This is a circuit diagram in which a photodiode PD shares a unit pixel processing circuit. [Figure 8A] FIG. 1 is a circuit diagram in which a first substrate including a photodiode is bonded to a second substrate including a unit pixel processing circuit, with the photodiodes sharing the unit pixel processing circuit. [Figure 8B] FIG. 1 is a circuit diagram in which a first substrate including a photodiode is bonded to a second substrate including a unit pixel processing circuit, with the photodiodes sharing the unit pixel processing circuit. [Figure 8C]FIG. 1 is a circuit diagram in which a first substrate including a photodiode is bonded to a second substrate including a unit pixel processing circuit, with the photodiodes sharing the unit pixel processing circuit. [Figure 9A] 1 is a layout diagram of a 2-PD shared pixel in which two photodiodes PD form one pixel. [Figure 9B] 1 is a layout diagram of a 2-PD shared pixel in which two photodiodes PD form one pixel. [Figure 10A] 1 is a layout diagram of a 4-PD shared pixel in which four photodiodes PD form one pixel. [Figure 10B] 1 is a layout diagram of a 4-PD shared pixel in which four photodiodes PD form one pixel. [Figure 11A] FIG. 2 is a side view of a dual vertical transfer gate dVTG according to an embodiment of the present invention. [Figure 11B] FIG. 2 is a side view of a dual vertical transfer gate dVTG according to an embodiment of the present invention. [Figure 11C] FIG. 2 is a side view of a dual vertical transfer gate dVTG according to an embodiment of the present invention. [Figure 11D] FIG. 2 is a side view of a dual vertical transfer gate dVTG according to an embodiment of the present invention. [Figure 11E] FIG. 2 is a side view of a dual vertical transfer gate dVTG according to an embodiment of the present invention. [Figure 11F] FIG. 2 is a side view of a dual vertical transfer gate dVTG according to an embodiment of the present invention. [Figure 12A] FIG. 1 is a side view of a dual vertical transfer gate with definitions of names and dimensions when viewed from one direction or the other. [Figure 12B] FIG. 1 is a side view of a dual vertical transfer gate with definitions of names and dimensions when viewed from one direction or the other. [Figure 13A] FIG. 13 is a side view of a dual vertical transfer gate as a comparison technology. [Figure 13B] FIG. 13 is a side view of a dual vertical transfer gate as a comparison technology. [Figure 14A] 4 is a diagram illustrating a manufacturing process of a first substrate including a unit pixel circuit according to an embodiment. [Figure 14B] 4A to 4C are diagrams illustrating a manufacturing process of a first substrate including a unit pixel circuit according to an embodiment. [Figure 14C] 4A to 4C are diagrams illustrating a manufacturing process of a first substrate including a unit pixel circuit according to an embodiment. [Figure 14D] 4A to 4C are diagrams illustrating a manufacturing process of a first substrate including a unit pixel circuit according to an embodiment. [Figure 14E] 4A to 4C are diagrams illustrating a manufacturing process of a first substrate including a unit pixel circuit according to an embodiment. [Figure 14F] 4A to 4C are diagrams illustrating a manufacturing process of a first substrate including a unit pixel circuit according to an embodiment. [Figure 14G] 4A to 4C are diagrams illustrating a manufacturing process of a first substrate including a unit pixel circuit according to an embodiment. [Figure 14H] 4A to 4C are diagrams illustrating a manufacturing process of a first substrate including a unit pixel circuit according to an embodiment. [Figure 14I] 4A to 4C are diagrams illustrating a manufacturing process of a first substrate including a unit pixel circuit according to an embodiment. [Figure 15A] 1 is a diagram illustrating a manufacturing process of a CMOS image sensing device including a unit pixel circuit and a logic circuit according to an embodiment. [Figure 15B] 1 is a diagram illustrating a manufacturing process of a CMOS image sensing device including a unit pixel circuit and a logic circuit according to an embodiment. [Figure 15C] 1 is a diagram illustrating a manufacturing process of a CMOS image sensing device including a unit pixel circuit and a logic circuit according to an embodiment. [Figure 15D] 1 is a diagram illustrating a manufacturing process of a CMOS image sensing device including a unit pixel circuit and a logic circuit according to an embodiment. [Figure 15E]1 is a diagram illustrating a manufacturing process of a CMOS image sensing device including a unit pixel circuit and a logic circuit according to an embodiment. [Figure 16A] 11 is a diagram illustrating a process for manufacturing a first pixel substrate including a dual vertical transfer gate according to another embodiment. [Figure 16B] 11 is a diagram illustrating a process for manufacturing a first pixel substrate including a dual vertical transfer gate according to another embodiment. [Figure 16C] 11 is a diagram illustrating a process for manufacturing a first pixel substrate including a dual vertical transfer gate according to another embodiment. [Figure 16D] 11 is a diagram illustrating a process for manufacturing a first pixel substrate including a dual vertical transfer gate according to another embodiment. [Figure 16E] 11 is a diagram illustrating a process for manufacturing a first pixel substrate including a dual vertical transfer gate according to another embodiment. [Figure 16F] 11 is a diagram illustrating a process for manufacturing a first pixel substrate including a dual vertical transfer gate according to another embodiment. [Figure 16G] 11 is a diagram illustrating a process for manufacturing a first pixel substrate including a dual vertical transfer gate according to another embodiment. [Figure 17A] 11 is a diagram showing a manufacturing process of a CMOS image sensing device including a unit pixel circuit and a logic circuit according to another embodiment. [Figure 17B] 11 is a diagram showing a manufacturing process of a CMOS image sensing device including a unit pixel circuit and a logic circuit according to another embodiment. [Figure 17C] 11 is a diagram showing a manufacturing process of a CMOS image sensing device including a unit pixel circuit and a logic circuit according to another embodiment. [Figure 17D] 11 is a diagram showing a manufacturing process of a CMOS image sensing device including a unit pixel circuit and a logic circuit according to another embodiment. [Figure 17E]11 is a diagram showing a manufacturing process of a CMOS image sensing device including a unit pixel circuit and a logic circuit according to another embodiment. [Figure 17F] 11 is a diagram showing a manufacturing process of a CMOS image sensing device including a unit pixel circuit and a logic circuit according to another embodiment. [Figure 18] 11 is a diagram showing a manufacturing process of a CMOS image sensing device including a unit pixel circuit and a logic circuit according to another embodiment. [Figure 19A] 11 is a diagram illustrating a manufacturing process of a CMOS image sensing device including a unit pixel circuit and a logic circuit according to another embodiment of the present invention; [Figure 19B] 11 is a diagram illustrating a manufacturing process of a CMOS image sensing device including a unit pixel circuit and a logic circuit according to another embodiment of the present invention; [Figure 19C] 11 is a diagram illustrating a manufacturing process of a CMOS image sensing device including a unit pixel circuit and a logic circuit according to another embodiment of the present invention; [Figure 19D] 11 is a diagram illustrating a manufacturing process of a CMOS image sensing device including a unit pixel circuit and a logic circuit according to another embodiment of the present invention; [Figure 20] 11 is a diagram showing a manufacturing process of a CMOS image sensing device including a unit pixel circuit and a logic circuit in another manner. [Figure 21] 1 is a flow chart showing a manufacturing process of a CMOS image sensing device according to an embodiment of the present invention; [Figure 22] 4 is a flow chart illustrating a manufacturing process of a first pixel substrate including a dual vertical transfer gate according to an embodiment of the present invention. [Figure 23] 1 is a flow chart illustrating a substrate bonding method according to an embodiment of the present invention; [Figure 24]1 is a flow chart showing a position and formation method of an I / O pad according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] As high-resolution video is required, a highly integrated image sensor is required. As the integration density of the image sensor increases, the size of the elements constituting the image sensor becomes smaller and smaller. That is, as the number of pixels in the image sensor increases, the size of the elements in the pixel becomes smaller, and the area occupied by the photodiode PD in the pixel becomes smaller and smaller.

[0019] In order to realize a photodiode with sufficient full well capacity even when the pixel size is reduced, a so-called deep photodiode can be formed in which a region extending from a region separated by a certain distance on the front side of the substrate to a portion adjacent to the back side is formed as an n-type region of the photodiode.

[0020] The n-type regions (n-PD) of the deep photodiodes may be surrounded and isolated from each other by an isolation member such as a p-type region and / or a deep trench isolation (DTI).

[0021] In order to effectively extract the negative charges generated in the n-type region formed vertically and deeply, a vertical transfer gate (VTG) can be used. The vertical transfer gate can have one or two poles that extend to the n-type region (n-PD region) of the photodiode in the substrate. In this embodiment, a vertical transfer gate having two poles is more preferable in terms of charge transfer efficiency.

[0022] 12A, the vertical transfer gate 120 includes two poles P1 and P2 extending from the substrate surface 100a through the substrate 100 to the n-type region n-PD of the photodiode. A gate insulating film 122 may be provided between the vertical transfer gate 120 and the substrate 100. The poles P1 and P2 each extend to a depth L from the substrate surface 100a and have a width W on the substrate surface 100a. The vertical transfer gate 120 may also include a connection part C connecting the two poles P1 and P2 on the substrate 100 and an extension part E extending horizontally away from the connection part C. The poles P1 and P2 may be spaced apart via a gap.

[0023] 12B is a cross-sectional view of the vertical transfer gate 120 when viewed in a direction perpendicular to that of FIG 12A. In FIG 12B, the two poles P1 and P2 are overlapped to appear as one pole, and a floating diffusion region FD is formed adjacent to the two poles P1 and P2, and an STI for isolating regions in the substrate 100 can be formed.

[0024] However, as shown in Fig. 13A, when using a vertical transfer gate 1320 in which two poles P1 and P2 are extended to the n-PD region of the photodiode, a potential hump occurs in which the electric field is concentrated between the two poles and the negative charge between the two poles is not transferred well to the floating diffusion region FD (not shown), and a backflow occurs in which the negative charge flows back between the poles in the FD region. Fig. 13A shows a comparative technology, with reference numeral 100 representing a substrate and reference numeral 1322 representing a gate insulating film.

[0025] As shown in Fig. 13B, when a structure in which vertical transfer gates 1320 and 1321 each having one pole are connected by a wiring 1345, i.e., a transfer gate without a gate connection part C is applied, it is possible to reduce or prevent such adverse effects, but the wiring is complicated and misalignment problems may occur when forming contacts 1340 and 1341. Therefore, the smaller the pixel size, the more disadvantageous it is in terms of the manufacturing process. Here, Fig. 13B shows a comparative technology, and reference numerals 1320 and 1321 each represent a single vertical transfer gate.

[0026] 12A and 12B, an embodiment of the present invention can reduce the electric field effect between the poles P1 and P2 by interposing a first insulating pattern 125 between the transfer gate 120 and the substrate 100. Also, by interposing the first insulating pattern 125 in the region between the poles where the electric field concentration effect is large, the charge transfer efficiency can be improved. The first insulating pattern 125 will be described in more detail below.

[0027] Hereinafter, specific embodiments of the present invention will be described with reference to the accompanying drawings.

[0028] First, referring to Fig. 11A, which is a side view of a dual vertical transfer gate dVTG according to an embodiment of the present invention, the vertical transfer gate 120 has two poles P1 and P2 that extend to an n-type photodiode region n-PD in a substrate 100, and a connection part C that connects the two poles. Although not shown in Fig. 11A, an n-type floating diffusion region FD is disposed in the substrate 100 adjacent to the gate as shown in Fig. 12B when viewed in a direction perpendicular to the cross section of Fig. 11A.

[0029] The substrate 100 is a substrate on which elements including photodiodes, transistors, and electrode nodes are formed. The substrate 100 is a semiconductor wafer and can be cut into IC chips. The substrate 100 includes a silicon semiconductor or a compound semiconductor such as GaN, and is doped with n-type or p-type impurities to provide an n-type substrate or a p-type substrate, respectively. In one embodiment of the present invention, the embodiment of Figs. 11A to 11E provides a p-type substrate, and forms n-type doped gates and source / drains on / on the p-type substrate to form an n-type MOSFET element. The n-type region n-PD of the photodiode serves as a source region, and the floating diffusion region FD serves as a drain region.

[0030] A p-type region of the substrate 100 forms a p-n junction with the n-type region n-PD to form a photodiode. In one embodiment of the present invention, p-doping is additionally performed on the p-type region to form different doping concentrations, and the p-type region surrounds the n-PD region and separates pixels from each other together with the isolation member 130.

[0031] 11A, a first insulating film 126 is formed on the substrate 100 and between at least the first pole P1 and the second pole P2. The first insulating film 126 is interposed between at least the substrate 100 and the gate 120 such that the connection portion C of the gate 120 is vertically spaced from the substrate 100. As an example, the first insulating film 126 includes a first insulating pattern 125, which is disposed between the connection portion C and the substrate 100. In this manner, the electric field formed by the gate portion disposed on the substrate 100, for example, the connection portion C, is reduced, thereby reducing / preventing undesirable phenomena caused by the electric field concentration between the two poles P1 and P2.

[0032] Meanwhile, a native oxide layer may be formed between the first insulating layer 126 and the substrate 100, between the poles P1 and P2, and between the first insulating pattern 125 and the substrate 100. When the first insulating layer 126 includes SixNy, the first insulating layer 126 may additionally include a thin oxide layer (x, y are real numbers greater than 0).

[0033] 11A, a first insulating layer 126 may be applied under the gate and partially or entirely on the substrate, and may be used as an etch stop layer.

[0034] In addition, a gate insulating film 122 is interposed between the gate 120 and the substrate 100. Also, pixels are separated from each other by an isolating member 130, and a photodiode is formed between the isolating members 130. The isolating members 130 are provided to electrically separate adjacent pixels, and are made of an insulating material such as SiO 2 , Si x N y , SiON, and SiOC, or a composite film. In one embodiment, the separation member 130 includes a first insulating layer 132 and a second insulating layer 131. The first insulating layer 132 is SiO 2 The second insulating layer 131 is a liner-shaped Si x N y Further, the isolation member 130 may further include a conductive layer 136 therein for applying a bias. The conductive layer 136 may include, for example, doped polysilicon, tungsten (W).

[0035] FIG. 11B shows a structure in which a portion of the gate insulating film 122 exposed during the patterning process has been removed, according to another embodiment of the present invention.

[0036] 11C shows a structure according to another embodiment of the present invention, in which a gate extension E is formed on a substrate 100 and extended in a horizontal direction. Even if the gate extension E is formed as in FIG. 11C, the electric field generated by the gate extension E can be reduced, which is advantageous in terms of freedom of gate design and process margin.

[0037] 11D shows another embodiment of the present invention in which a gate insulating film 122 is formed only on the side and back surfaces of the poles P1 and P2 in the substrate 100. The gate insulating film 122 can be separated between the poles P1 and P2. The gate insulating film 122 in this structure can be formed of a silicon oxide film by oxidizing the exposed substrate 100. As an optional modification in the process, the gate insulating film 122 can be doped with an element such as nitrogen to strengthen the film quality and change the energy band gap, or can be formed by adding other films in another method.

[0038] 11E is another embodiment of the present invention, which is a modified form of FIG. 11B, and differs from the embodiment of FIG. 11B in that the first insulating film 126 on the substrate 100 is removed, leaving only the first insulating pattern 125 between the two poles P1 and P2. As an example process, dry etching is performed on the front surface of the substrate to remove the exposed first insulating film 126, and the first insulating pattern 125 hidden by the gate connector remains.

[0039] 11F shows a structure in which a void 127 is formed partially or entirely between the gate poles P1 and P2 on the substrate 100 as another embodiment of the present invention. If the void 127 is formed, the dielectric constant can be further reduced, and therefore the electric field between the gate poles P1 and P2 can be reduced. The void 127 can be a region that does not contain a solid defined by at least one of the first insulating pattern 125, the substrate 100, and the gate insulating film 122.

[0040] Next, Fig. 12A is a side view of a dual vertical transfer gate according to an embodiment of the present invention, cut in a direction in which two poles P1 and P2 are visible, and Fig. 12B is a side view seen when cut in a direction perpendicular to the direction of Fig. 12A. The names and dimensions of the gate of the present invention will be described with reference to Figures 12A and 12B. The gate 120 includes two poles P1 and P2 extending below the substrate 100. Each of the two poles P1 and P2 has a width W and a depth L on the substrate surface 100a, and there is a gap between the poles P1 and P2 on the substrate surface 100a.

[0041] Also, the two poles P1 and P2 may have substantially the same size and shape, or may have different sizes, depending on the shape and position of the gate. However, the drawings of the present invention illustrate poles having substantially the same features as an exemplary embodiment. The poles P1 and P2 may have a shape that narrows in width as it goes downward perpendicular to the substrate surface 100a. Also, since the shape of the end portion that contacts the photodiode in the substrate 100 has a curved surface, it is possible to prevent the formation of a potential electric field barrier.

[0042] As an embodiment of the present invention, the gate 120 has a connection part C connecting two poles P1 and P2, and may optionally further include an extension part E extending in the horizontal direction. The connection part C connects the two poles, and a contact of a wiring is landed on the connection part C.

[0043] 12B, each of the poles P1 and P2 is formed deep to the n-type region n-PD of the photodiode and adjacent to the floating diffusion region FD. It may also be adjacent to the element isolation region STI formed on the substrate surface 100a. Assuming that the gate 120 is an nMOSFET doped with n-type, when it is turned on above the operation voltage, a channel is formed around the poles P1 and P2 to transfer the negative charges formed in the n-PD to the floating diffusion region FD.

[0044] 12A, a first insulating pattern 125 formed on a substrate 100 may be disposed substantially flat with a thickness d. The first insulating pattern 125 may be formed to a thickness of 5 to 50 nm, and preferably, 10 to 50 nm.

[0045] The first insulating pattern 125 may include a silicon nitride layer (SixNy), or may be SiON, SiONC, SiO 2 , SiOC, or a composite film thereof. In another embodiment, the first insulating pattern 125 may include voids to reduce the electric field concentration effect.

[0046] In an embodiment of the present invention, the greater the electric field value concentrated between the poles P1 and P2, in other words, the finer the device, the greater the electric field reduction effect through the first insulating pattern 125 is expected. In one embodiment of the present invention, the width W of the poles P1 and P2 may be 50 to 200 nm, and the depth L of the poles P1 and P2 may be 200 to 500 nm. The aspect ratio (L / W) of the poles P1 and P2 may be 1 to 10, preferably 1.5 to 10, and more preferably 3 to 10. Also, the gap between the poles P1 and P2 may be 10 to 80 nm on the substrate surface 100a. The narrower the gap between the poles P1 and P2, the greater the electric field value, and when the first insulating pattern 125 is formed, the greater the electric field reduction effect by the first insulating pattern 125. The gap between the poles P1 and P2 may be equal to or smaller than the width W of the gate pole. Preferably, the gap between the poles P1, P2 is less than the width W of the poles, between 1 / 2 and 1 / 5 of the width W.

[0047] In this way, the electric field concentration reduction effect of the present invention can be obtained more effectively as the device is miniaturized, and is particularly suitable for devices having a pixel size of less than 1.5 um, preferably less than 1.2 um, and more preferably less than 1.0 um. Here, the pixel size refers to the longest length among the horizontal and vertical lengths of the planar shape of a unit pixel.

[0048] In one embodiment, the present invention provides an image sensing device including a vertical transfer gate including a first insulating pattern 125 on a substrate 100 and at least between a first pole P1 and a second pole P2 of a gate 120. As image sensing devices become more sophisticated and miniaturized, a stacked image sensing device can be provided by forming a separate substrate and then bonding the substrate to increase light efficiency and integrate pixels.

[0049] 1 shows a cross-sectional view of a two-stack CMOS image sensing CIS device according to an embodiment of the present invention. Referring to FIG. 1, a pixel substrate 100 including an analog circuit for driving pixels, a peripheral circuit for supplying power and generating various control signals, and a logic / peripheral substrate 300 including a logic circuit (e.g., an ISP block) for processing image signals are separately provided, and the pixel substrate 100 and the logic / peripheral substrate 300 are bonded so that their front surfaces face each other to form a stack image sensing device.

[0050] 1, an isolation member 130 is formed on a substrate 100 to separate pixels within the substrate. The isolation member may be a deep trench isolation (DTI) extending from the front to the back of the substrate. In one embodiment, a bias may be applied to prevent loss of negative charges formed from light and increase light efficiency, and for this purpose, a conductive layer 136 may be additionally included in the isolation member.

[0051] The photodiode is disposed between isolators 130 in the substrate 100, and the n-type region of the photodiode, n-PD, 110, is disposed in the substrate and in an area below the device on the substrate. The isolators 130 can be of the same size or have different thicknesses depending on the design and location of the pixel (see, for example, isolators 134).

[0052] The substrate 100 has a front and a back surface. Devices and nodes such as transistors are formed on the front surface. An isolation region is formed on the front surface of the substrate 100 to define a substrate active region, and a vertical transfer gate 120 is formed in the substrate 100 active region. The vertical transfer gate 120 has two poles P1 and P2 extending downward from the substrate to an n-PD region, and a connection part C on the substrate 100 to connect the two poles. A gate insulating film 122 is interposed between the two poles P1 and P2 and the substrate 100.

[0053] A first insulating pattern 125 having a thickness d is provided on the front surface of the substrate 100. The first insulating pattern 125 is disposed on the substrate at least between the gate poles P1 and P2. As an optional embodiment, a gap may be included between the gate poles P1 and P2. In the embodiment in which a gap is formed, the first insulating pattern 125 may be partially left between the gate poles or may be completely removed.

[0054] Analog elements for driving pixels may be included on the front side of the substrate 100 in addition to the vertical transfer gate 120. As shown in Figures 7A and 7B, a device according to an embodiment may include a reset transistor RG, a source follower transistor SF for amplifying a signal, a selection transistor, and a ground node.

[0055] Next, various wirings 145 and contacts 140 are formed in the interlayer insulating film 150 of the pixel substrate 100. For example, in the embodiment of FIG. 1, the contact 140 is connected to the connection portion C of the vertical transfer gate 120, and is electrically connected to the bonding pad 180 via the wiring 145. The bonding pad 180 may include a copper (Cu) pad, and is joined and electrically connected to the bonding pad of the paired substrate. The bonding pad 180 is electrically connected to the bonding pad of the paired substrate, but may additionally include a dummy pad for substrate bonding.

[0056] Meanwhile, in a rear-illuminated BSI image sensing device, various optical elements are formed on the rear side of a substrate 100 where light enters. Referring to Fig. 1, microlenses 175, R, G, B color filters 170, and a grid 172 are formed in a pixel region on the rear side of the substrate 100. The microlenses 175 are arranged to focus within the pixel, and the further away from the center the microlenses 175 are, the more offset they may be from the n-type region 110 of the photodiode.

[0057] The back surface of the pixel substrate 100 may be thinned by chemical and physical polishing (CMP) to increase the light receiving rate. Then, a second insulating film 178 may be formed to prevent the consumption of negative charges. The second insulating film 178 may be a hafnium oxide film (HfO 2 ) and aluminum oxide film (Al 2 O 3 ), tantalum oxide film (TaO x ) may be included. Also, in order to increase light efficiency, an anti-reflection film 179 may be included on the second insulating film 178. In the stoichiometric formula notation for expressing an inorganic material, x and y indicate a compounding ratio and are real numbers greater than 0. For example, silicon nitride may be expressed as SixNy, where x and y are both real numbers greater than 0.

[0058] A light blocking member 173 may be formed in the optical black area surrounding the pixel array to observe a reference signal.

[0059] 1, various elements may be formed on the front side of the logic / peripheral substrate 300. For example, an isolation region 330 is formed in the substrate 300 to define an active region, and a gate 320 is formed in the active region to form a transistor. Also, various wirings 345 and contacts 340 electrically connected to the transistors are formed on the substrate 300. The wirings 345 and contacts 340 are insulated by an interlayer insulating film 350. In the present application, the contacts 340 are conductors for vertical connection. The contacts 340 may include vias that connect the wirings as well as the substrate and the wirings.

[0060] As described above, the pixel substrate 100 and the logic / peri substrate 300 are bonded by a bonding process. The bonding process may include, for example, a wafer bonding process for bonding wafers together, and electrical connection may be ensured by bonding between the bonding pads. As shown in FIG. 1, the bonding pad 180 of the pixel substrate 100 is bonded to the bonding pad 380 of the logic / peri substrate 300, and a dummy pad may be additionally provided for inter-substrate bonding. The two bonding pads 180 and 380 may include Cu, forming Cu-Cu bonding.

[0061] The image sensing device of the present invention includes an I / O pad for transmitting and receiving signals to and from the outside, for control, and for power supply. As an embodiment, in the two-stack rear light receiving method, since the thickness of the rear surface of the pixel substrate 100 is thin, an I / O pad can be formed on the rear surface of the pixel substrate 100. Referring to FIG. 1, a TSV (through silicon via) 194 is shown, which penetrates the rear surface of the pixel substrate 100 through the TSV 194 and is connected to a connecting wire 145 disposed inside a first portion including the pixel substrate 100 and a landing pad 347 disposed inside a second portion including the logic / peripheral substrate 300. An insulating film 195 is provided between the TSV 194 and the substrate 100 to insulate the substrate 100 from the via. An I / O pad 192 can be included on the TSV 194, and the surface of the rear surface of the substrate is protected by an insulating layer and / or a passivation layer. The insulating layer and / or the passivation layer can include the same material as the microlens layer.

[0062] 2 is a cross-sectional view of a two-stack CMOS image sensing device according to another embodiment of the present invention. The embodiment is generally the same as that of FIG. 1, except that the TSVs 194 penetrating the pixel substrate 100 may be directly connected to landing pads 347 inside the second portion including the logic / peripheral substrate 300. The TSVs 194 may not be connected to wiring in the first portion including the pixel substrate 100.

[0063] 2 has a stack structure in which the pixel substrate 100 and the logic / peri substrate 300 are bonded to each other as in FIG 1. The pixel substrate 100 is bonded to a front surface thereof, and the rear surface thereof is removed to increase the light receiving efficiency of the photodiode, so that the thickness of the pixel substrate 100 is thinner than that of the logic / peri substrate 300. Therefore, it is advantageous in terms of process convenience to form an I / O pad part by penetrating the TSV 194 to the rear surface of the pixel substrate 100.

[0064] In another embodiment of the present invention, the pixel circuits can be formed on two separate substrates and then bonded together to produce a two-stack pixel substrate, which is then joined to a logic / peripheral substrate to ultimately provide a three-stack image sensing device.

[0065] 7A and 7B are circuit diagrams in which photodiodes PD share a unit pixel processing circuit, in which two photodiodes PD share a unit pixel processing circuit in Fig. 7A, and four photodiodes PD share a unit pixel processing circuit in Fig. 7B.

[0066] Referring to FIG. 7A, the p-node of the photodiode PD is connected to ground, and the n-node is connected to a transfer gate TG transistor. The drain of the transfer gate TG transistor is connected to a floating diffusion region FD (not shown). Each photodiode shares the floating diffusion region FD via a transfer gate TG. When the transfer gate TG is turned on, the negative charge of the corresponding photodiode PD is transferred to the floating diffusion region FD. The floating diffusion region FD is also connected in parallel to a reset gate RG transistor and a source follower SF. When the reset gate RG transistor is turned on, the charge of the floating diffusion region FD is removed and set to a reference point of the charge. When the reset gate RG transistor is turned off, the source follower SF transistor is a kind of common drain amplifier that transmits an analog signal to the bit line Vout by generating a gate voltage according to the charge amount of the floating diffusion region FD. The drains of the reset transistor RG and the source follower SF are all connected to Vdd. When the selection transistor SEL is turned on, a corresponding pixel is selected from among the pixels sharing the bit line. These transistors are nMOS transistors and should be understood to be nMOS transistors unless otherwise stated in the text.

[0067] Referring to the embodiments of Figures 7A and 8A, the photodiode PD, the transfer gate TG transistor, the floating diffusion region FD, and the ground node can be formed on a first pixel substrate, and the shared unit pixel circuit can be formed on another substrate, i.e., a second pixel substrate.

[0068] 8A is a circuit diagram in which a first pixel substrate on which a photodiode PD, a transfer gate TG transistor, a floating diffusion region FD, and a ground node are formed, and a second pixel substrate on which a unit pixel circuit including a reset RG transistor, a source follower SF transistor, and a selection transistor SEL is formed are bonded by substrate bonding, for example, Cu-Cu bonding. Therefore, even with a small pixel size, a sufficiently large analog element can be secured, so that a high-precision, high-performance image sensing device can be manufactured.

[0069] 8A is also simple in terms of wiring connections. In particular, the first pixel substrate including the photodiode PD, the transfer gate transistor TG, the floating diffusion region FD, and the ground node GND does not include a bit line, so the number of wirings can be reduced. In this embodiment of the present invention, the wiring of the first pixel substrate is two layers, but in another embodiment, it can be made in one layer (excluding the number of Cu bonding pads).

[0070] 7B is a circuit diagram in which four photodiodes PD share one floating diffusion region FD (not shown) and unit pixel circuits RG, SF, and SEL. The number of photodiodes PD shared by the unit pixel circuit is not limited to two or four, and eight PDs can be shared and used as shown in FIG. 8C, and can be expanded to 16 or more depending on the circuit design.

[0071] Also, the four PDs can be operated separately as shown in Figures 10A and 10B, or two photodiodes PD can be operated as a pair as shown in Figures 9A and 9B. Briefly, the pair operation can be used as an independent photodiode at high illumination and as one photodiode at low illumination. Referring to Figure 8B, the embodiment of Figure 7B can be modified to use multiple pixel substrates as described with reference to Figure 8A.

[0072] 9A, 9B, 10A, and 10B are layout diagrams of a first pixel substrate including a photodiode PD, a transfer gate TG, a floating diffusion region FD, and a ground node.

[0073] 9A and 9B, when viewed from above the first pixel substrate, the unit pixels are divided by an isolation member 930. The area within the pixel is divided by another isolation member 940, and the STI defines an active area.

[0074] The transfer gate 920 is between the n-type region n-PD of the photodiode and the floating diffusion region FD, 950, and opens and closes the connection from n-PD to FD. The gate 920 has two poles P1, P2 that extend deeply below the substrate. Also, a gate connection part C is disposed on the substrate and electrically connects the two poles P1, P2. In the embodiment of FIG. 9, the planar pattern of the gate is rectangular, and the two poles P1, P2 are disposed symmetrically and have the same features, but can be changed according to the arrangement of the device in the pixel, and the two poles P1, P2 can also be disposed asymmetrically and made with different features. In the present invention, a first insulating pattern, which is not a gate insulating film, is formed on the substrate and between the first pole and the second pole.

[0075] The floating diffusion region FD 950 is shared with the n-type regions n-PD of the two photodiodes, and a contact connected to the second pixel substrate may be disposed in the floating diffusion region FD.

[0076] A ground node 970 is disposed at a position spaced apart from the n-PD region. A ground voltage can be applied to the p-region of the photodiode through the ground node 970.

[0077] 9A, two photodiodes PD can be paired with each other, and two adjacent pixels can share one lens, and the two adjacent pixels can be operated as separate pixels when the illumination is high, and can be used as one pixel when the illumination is low.

[0078] 9B is a layout diagram of a portion of a 2-PD shared pixel array including two adjacent pixels shown in FIG. 9A. The floating diffusion region FD (not shown) of the first shared pixel PX1 may be arranged to face the floating diffusion region FD (not shown) of the second shared pixel PX2 located vertically below. In this facing arrangement, it is easy to connect the floating diffusion region FD1 (not shown) of the first shared pixel PX1 and the floating diffusion region FD2 (not shown) of the second shared pixel PX2.

[0079] On the other hand, even when connected to a circuit including a source follower SF transistor, a reset gate RG transistor, and a selection transistor SEL formed on a second pixel substrate, two 2-PD shared pixels PX1 and PX2 or PX3 and PX4 can share an analog circuit within one pixel. In this way, the efficiency of device integration can be improved, and a larger sized analog circuit can be used even under the constraints of a small pixel size, resulting in improved characteristics.

[0080] In an embodiment such as FIG. 9B, an embodiment in which one 2-PD shared pixel of a first pixel substrate is connected to a pixel analog unit circuit of a second pixel substrate corresponds to the connection of FIG. 8A, and in another embodiment, an arrangement of two 2-PD shared pixels corresponds to the circuit connection of FIG. 8B.

[0081] The analog circuit formed in the second pixel substrate may be manufactured by a process different from that of the first pixel substrate. For example, in one embodiment of the present invention, the transfer gate of the first pixel substrate is formed in a dual vertical transfer gate shape having two poles, and a first insulating pattern is provided on the substrate. On the other hand, the second pixel substrate may not have a first insulating pattern formed on the substrate, and a planar type gate may be formed thereon, or in another embodiment, a FinFET type gate may be formed thereon. Furthermore, the gates of the devices in the second pixel substrate may be formed by different processes or may be manufactured in different shapes.

[0082] 10A and 10B are layout diagrams of a 4-PD shared pixel in which four photodiodes PD form one big pixel. FIG 10A is an enlarged view of the first sub-pixel Px1 in FIG 10B.

[0083] 10A, when viewed from the top of the first pixel substrate, the unit pixels are divided by an isolation member 1030. An area within the pixel is an isolation member 1040 having different STI to define an active area.

[0084] The transfer gate 1020 is located between the n-type region n-PD of the photodiode and the floating diffusion region FD, 1050, and opens and closes the connection between the n-PD and the floating diffusion region 1050. The gate 1020 has two poles P1 and P2 that extend deep below the substrate to the n-PD.

[0085] Also, the gate may be extended in a diagonal direction and formed to match the shape of the n-PD region exposed on the substrate surface, for example, the gate may be formed in a polygonal or rectangular shape. The gate connection part C is located on the substrate and electrically connects two poles P1 and P2.

[0086] In the embodiment of Fig. 10A, the planar shape of the gate is a polygon, and the two poles P1, P2 are arranged symmetrically and have the same features, but can be changed according to the arrangement of the device in the pixel, and the two poles P1, P2 can also be arranged asymmetrically and made with different features. In the present invention, a first insulating pattern 125, which is not a gate insulating film, is formed on the substrate and between the first pole and the second pole.

[0087] As shown in FIG. 10B, since the isolation member 1030 does not extend to the center but is open, the four subpixels Px1, Px2, Px3, and Px4 share a floating diffusion region FD, 1050, and a contact connecting to the second pixel substrate can be disposed in the floating diffusion region 1050.

[0088] 10A, a ground node 1070 is disposed at a position spaced apart from the n-PD region. A ground voltage can be applied to the p-region of the photodiode through the ground node 1070.

[0089] Referring to FIG. 10B, four photodiodes PD can operate together, and four sub-pixels Px1, Px2, Px3, and Px4 can share one lens. They can operate as individual pixels when the illumination is high, and can be used as one pixel when the illumination is low. The 4-PD shared pixel arrangement as shown in FIG. 10B can correspond to the circuit diagram of FIG. 8B. In this case, each PD in FIG. 10B means a photodiode of a sub-pixel. Even in such a 4-PD shared pixel arrangement, a pixel analog circuit of a second pixel substrate can be connected to a plurality of 4-PD shared pixels to form a circuit in which, for example, eight sub-pixels are shared as shown in FIG. 8C, and can be expanded to a circuit in which 16 or more sub-pixels are shared.

[0090] Also, as with the embodiment shown in FIGS. 9A and 9B, in the embodiment of FIGS. 10A and 10B, the second pixel substrate can be manufactured using a process different from that for manufacturing the devices in the first pixel substrate, and the devices in the second pixel substrate can be formed with gates of different shapes and sizes.

[0091] Another embodiment of the present invention provides a three-stack CMOS image sensing CIS device that includes two pixel substrates and one logic / periphery substrate.

[0092] 3 shows a cross-sectional view of a three-stack CMOS image sensing CIS device including two pixel substrates and one logic / peripheral substrate. Referring to FIG. 3, a stacked image sensing device is provided in which a first pixel substrate 100 including a light receiving element, a photodiode, and a transfer gate, a second pixel substrate 200 including a pixel analog circuit that converts an optical signal generated by the photodiode into an analog signal, and a logic / peripheral substrate 300 including a peripheral circuit that supplies power and generates various control signals, and a logic circuit (e.g., an ISP block) for processing an image signal are bonded.

[0093] The arrangement of devices on the first pixel substrate 100 in FIG. 3 is shown arranged along the cutting line AA' in FIG. 9A. To separate pixels in the first pixel substrate 100, an isolation member 130 is formed in the substrate. The isolation member may be a deep trench isolation (DTI) extending from the front side to the back side of the substrate. The conductive layer 136 in the isolation member for applying a bias, the change in the thickness of the isolation member, and the description of the element isolation region are the same as those described in FIG. 1.

[0094] A photodiode is disposed between isolating members 130 in the first pixel substrate 100, and an n-type region n-PD, 110 of the photodiode is disposed in the substrate and in a region below the element on the substrate.

[0095] The first pixel substrate 100 has a front surface and a back surface. A vertical transfer gate 120 is formed on the front surface of the substrate 100. The vertical transfer gate 120 has two poles P1 and P2 extending downward from the substrate to the n-PD region, and a connection part C connecting the two poles on the substrate. A gate insulating film 122 is interposed between the two poles P1 and P2 and the substrate 100.

[0096] The front surface of the substrate 100 includes a first insulating pattern 125. The first insulating pattern 125 is disposed on the substrate at least between the gate poles P1 and P2. As an optional embodiment, a gap may be included between the gate poles P1 and P2. In the embodiment where a gap is formed, the first insulating pattern 125 may be partially left between the gate poles or may be completely removed.

[0097] The arrangement of a single pixel in the first pixel substrate, e.g., the arrangement of the n-type region n-PD of the photodiode PD, the vertical transfer gate 120, and the ground node GND (not shown), may be, for example, one or a pair of 2-PD shared pixel arrangements (FIGS. 9A, 9B), or a pixel arrangement shared by four sub-pixels (see FIGS. 10A, 10B), as previously described in FIGS. 9A, 9B, and 10A, 10B.

[0098] 3 shows the pixel layout of FIGs. 9A and 9B as an embodiment. In cross section taken along section line AA' in FIG. 9A, a floating diffusion region FD (not shown) is disposed on the front side of the first pixel substrate 100, between adjacent vertical transfer gates 120, and toward the rear side of the isolation member 130. A contact is formed on the floating diffusion region FD, and is connected to the gate 220 of the source follower transistor via bonding between corresponding pads 180, 280.

[0099] Various wirings 145 and contacts 140 are provided in an interlayer insulating film 150 on the first pixel substrate 100. For example, in the embodiment of Fig. 3, the contact 140 is separated from the connection portion C of the vertical transfer gate 120 and is electrically connected to the bonding pad 180 via the wiring 145. The bonding pad 180 may include a copper (Cu) pad, and is joined and electrically connected to the paired bonding pad 280 of the second pixel substrate 200. The bonding pads 180 and 280 may be electrically connected to different conductive structures, and may additionally include a dummy pad for substrate bonding.

[0100] Meanwhile, in a rear-illuminated BSI image sensing device as shown in Fig. 1, various optical elements are formed on the rear side of a substrate 100 where light enters. Referring to Fig. 3, microlenses 175, R, G, B color filters 170, and a grid 172 are formed in a pixel region on the rear side of the substrate 100. For descriptions of the offset arrangement of the microlenses 175, chemical and physical polishing, formation of a rear insulating film, and an optical black region, please refer to the description of Fig. 1.

[0101] As shown in Fig. 3, a second pixel substrate 200 including a pixel analog circuit is formed. The pixel analog circuit includes a source follower SF, a reset gate RG transistor, and a selection transistor SEL as shown in Fig. 7A. The pixel analog circuit formed in the second pixel substrate 200 converts an optical signal generated by a photodiode into an analog signal. The pixel analog circuit is formed in an active region separated by an element isolation region STI.

[0102] The first pixel substrate 100 is bonded to the second pixel substrate 200. In the embodiment shown in Fig. 3, the first pixel substrate 100 and the second pixel substrate 200 are bonded in a face-to-face manner. The interlayer insulating film 150 of the first pixel substrate 100 is bonded to the interlayer insulating film 250 of the second pixel substrate 200 to form a bonding interface.

[0103] In addition, the devices or circuits of the two substrates may be electrically connected by bonding the bonding pads disposed at the bonding interface. 220 denotes a source follower SF gate, which is connected to the floating diffusion region FD of the first pixel substrate 100. The bonding pad 180 of the first pixel substrate 100 and the bonding pad 280 of the second pixel substrate 200 may all be bonding pads containing Cu.

[0104] The pixel analog circuit of the second pixel substrate 200 may be connected to one pixel of the first pixel substrate 100, and more preferably, to a plurality of pixels of the first pixel substrate 100. If the pixel unit circuits are arranged separately on two substrates as shown in Fig. 3, devices can be arranged effectively even in a narrow pixel area. If a part of the analog circuit is arranged on the second substrate, a larger sized analog circuit can be arranged, and thus signal characteristics such as a signal-to-noise ratio (SNR) can be more favorably achieved.

[0105] 3, the second pixel substrate 200 is disposed between the first pixel substrate 100 and the third logic / periphery substrate 300, and a via TSV 260 is formed penetrating the second pixel substrate 200 to connect a device in the first pixel substrate 100 to a device in the third logic / periphery substrate 300. In order to insulate the TSV 260 from the second pixel substrate 200, an insulating film may be formed on the exposed surface of the second pixel substrate 200 penetrating the second pixel substrate 200. The substrate etching process for forming the TSV 260 may be performed by dry etching and / or wet etching. Also, a chemical and physical polishing (CMP) process may be performed on the substrate 200 to reduce the thickness of the substrate. If the substrate is thinned and a TSV process is performed, the aspect ratio of the TSV 260 is improved, and the TSV 260 may be formed from the back surface of the substrate.

[0106] 3, various elements may be formed on the front side of the logic / periphery substrate 300. For example, an element isolation region STI is formed in the substrate 300 to define an active region, and a gate 320 is formed in the active region to form a transistor. Various wiring 345 and contacts 340 are also formed on the substrate 300 to be electrically connected to the transistor. The wiring 345 and contacts 340 are insulated by an interlayer insulating film 350.

[0107] The logic / peri substrate 300 and the second pixel substrate 200 have a bonded interface therebetween. In one embodiment, the front surface of the logic / peri substrate 300 and the rear surface of the second pixel substrate 200 may be bonded. The second pixel substrate 200 and the logic / peri substrate 300 are bonded by a bonding process. The bonding process may include, for example, a wafer bonding process for bonding wafers together, and electrical connection may be ensured by bonding between bonding pads. In this case, an additional process may be performed on the rear surface of the second pixel substrate 200 to provide an insulating film and contacts / vias and / or bonding pads, and similarly, a substrate bonding may be performed with the front surface of the logic / peri substrate 300 on which the contacts / vias and / or bonding pads are provided.

[0108] In addition, the image sensing device of the present invention includes an I / O pad for transmitting and receiving signals to and from the outside, for control, and for power supply. In one embodiment, in a 3-stack rear light receiving type (i.e., two pixel substrates and one logic / peripheral substrate), since the rear thickness of the first pixel substrate 100 is thin, an I / O pad 192 may be formed on the rear surface of the first pixel substrate 100. Referring to FIG. 3, a TSV 194 is shown penetrating the rear surface of the pixel substrate 100 through a TSV 194 and connected to a landing pad 247 disposed on the second pixel substrate 200.

[0109] To insulate the substrate 100 from the vias, the TSVs 194 are separated from the substrate 100 by an insulating film 195. I / O pads 192 may be included on the TSVs 194, and the rear surface of the substrate 100 is protected by a second insulating film 178 and / or a passivation layer 176. The second insulating film 178 and / or the passivation layer 176 may include the same material as the microlens layer.

[0110] In addition, the I / O pads 192 may be connected to devices in the logic / peripheral substrate 300 through the TSVs 260 pre-formed in the second pixel substrate 200 and the vertical and horizontal wirings 249 and 248. In one embodiment of the present invention, the number of connected vertical and horizontal wirings may be multiple to reduce resistance and improve signal transmission speed.

[0111] 3 provides a stacked image sensing device in which two pixel substrates are bonded front-to-front and one logic / peripheral substrate is bonded front-to-back. In the present invention, by using a dual vertical transfer gate 120 in which a first insulating pattern 125 is formed between gate poles, wiring connection is simplified and negative charge transfer efficiency can be improved. In one embodiment, the number of wirings in the first pixel substrate 100 may be one, and the number of wirings in the second pixel substrate 200 may be two.

[0112] Next, FIG. 4 is a cross-sectional view of a three-stack CMOS image sensing CIS device according to another embodiment of the present invention.

[0113] Referring to FIG. 4, similar to FIG. 3, the first pixel substrate 100 and the second pixel substrate 200 are wafer-bonded front-to-front and have a bonding interface, and the second pixel substrate 200 and the logic / peripheral substrate 300 are wafer-bonded back-to-front and have another bonding interface.

[0114] The rear surface of the first pixel substrate 100 having the photodiode and the transfer gate 120 serves as a light receiving portion, and various optical elements such as a color filter and a microlens are disposed on the rear surface.

[0115] A transfer gate 120 having two poles P extending to the n-type region n-PD 110 of the photodiode is formed on the first pixel substrate 100, and a first insulating pattern 125 is formed on the substrate and between the two poles. In addition, the description of the isolation member, various wiring connections, and bonding pads 180 are the same as those described in FIG.

[0116] A source follower transistor, a reset transistor, a selection transistor and an analog pixel circuit are formed on the second pixel substrate 200 and are connected to the devices of the first pixel substrate 100 through bonding pads 280 and 180. For example, the floating diffusion region of the first pixel substrate 100 is connected to the gate 220 of the source follower transistor of the second pixel substrate 200. The analog elements of the second pixel substrate 200 may be connected to one pixel of the first pixel substrate 100 or to multiple pixels.

[0117] In addition, the second pixel substrate 200 may include TSVs 260 penetrating the substrate 200 for connection between the first pixel substrate 100 and the logic / peripheral substrate 300. Other details regarding the wiring arrangement of the second pixel substrate 200, the formation of TSVs, and wafer bonding with the first pixel substrate 100 are the same as those described in FIG.

[0118] The logic / peripheral substrate 300 includes peripheral circuits required for driving pixel circuits and logic circuits for image signal processing.

[0119] 3, in the embodiment shown in FIG. 4, logic / peri substrate 300 includes a pad region. Specifically, TSVs 394 are formed on the back surface of logic / peri substrate 300 after processing to penetrate logic / peri substrate 300 and be insulated from substrate 300. A passivation layer 376 may be formed on the back surface of the substrate, and I / O pads 392 may be formed after removing a portion of passivation layer 376. In this embodiment, optionally, in order to facilitate the formation of TSVs 394 in logic / peri substrate 300, the logic / peri substrate 300 may be thinned before the TSV process.

[0120] 4, if a pad section is formed on the back surface of the logic / peripheral substrate 300, it can be directly connected to the power supply section in the logic / peripheral substrate 300 via, for example, the landing pad 347 in the logic / peripheral substrate 300, and the signal can be immediately sent to the AP or CPU after image processing in the image processing section ISP. In this way, the wiring connection is simple and the area of ​​the pixel substrate is widely used, which is advantageous for high integration.

[0121] Regarding the logic / periphery substrate 300 in FIG. 4, the description regarding the formation of elements on the substrate, the formation of wiring and contacts / vias, and the front-to-back bonding with the second pixel substrate 200 is the same as that described in FIG. 3, and the description of FIG. 3 is referred to.

[0122] In the embodiment of FIG. 4, the number of layers of wiring formed on the first pixel substrate 100 may be one or two, and the number of layers of wiring formed on the second pixel substrate 200 may be two or three.

[0123] FIG. 5 is a cross-sectional view of another embodiment of the present invention of a three-stack CMOS image sensing CIS device.

[0124] 5, the embodiment of FIG. 5 also has two bonding interfaces formed by bonding a first pixel substrate 100, a second pixel substrate 200, and a logic / peripheral substrate 300. A transfer gate 120 having two poles P1 and P2 extending to an n-type region n-PD, 110 of a photodiode in the substrate is formed on the front side of the first pixel substrate 100, and a first insulating pattern 125 is formed on the substrate 100 and between the two poles P1 and P2.

[0125] Light enters the back surface of the substrate 100, where light receiving elements such as color filters and microlenses are formed.

[0126] The second pixel substrate 200 has a source follower transistor, a reset transistor, a selection transistor and an analog pixel circuit formed thereon. The second pixel substrate 200 is connected to the devices of the first pixel substrate 100 through bonding pads 280 and 180. For example, the floating diffusion region of the first pixel substrate 100 is connected to the gate 220 of the source follower transistor of the second pixel substrate 200. The analog elements of the second pixel substrate 200 may be connected to one pixel of the first pixel substrate 100 or to a plurality of pixels. The second pixel substrate 200 may also include a TSV 260 penetrating the substrate 200 for connection between the first pixel substrate 100 and the logic / peripheral substrate 300.

[0127] 5 is different from the embodiment of FIG 4 in that the front side of the first pixel substrate 100 and the back side of the second pixel substrate 200 are bonded to form a bonding interface. The second pixel substrate 200 and the logic / peripheral substrate 300 are bonded in a front-to-front manner to form a bonding interface.

[0128] 5, a pad region may be provided on the back surface of logic / periphery substrate 300. TSVs 394 may be formed after forming substrate and insulating film 395 through substrate 300. Alternatively, TSVs 394 may be formed after thinning substrate 300 by, for example, chemical-physical polishing (CMP).

[0129] For other details regarding the wiring arrangement of the first and second pixel substrates 100 and 200, the formation of the TSV 260 of the second pixel substrate 200, the formation of a substrate surface insulating film, and the connection and sharing between the pixels of the first pixel substrate 100 and the analog circuits of the second pixel substrate 200, please refer to and cite the explanations given in Figures 3 and 4.

[0130] On the other hand, in FIG. 5, the first pixel substrate 100 is formed with two wiring layers, but the first pixel substrate 100 may be formed with one wiring layer.

[0131] 6 is a cross-sectional view of a three-stack CMOS image sensing CIS device according to another embodiment of the present invention, in which the first pixel substrate 100, the second pixel substrate 200, and the logic / peripheral substrate 300 have the same devices and wiring connections as those of the embodiment of FIG.

[0132] 6 differs from FIG 5 in that a pad region is formed on the rear surface of the first pixel substrate 100. To this end, an insulating film 195 is formed through the rear surface of the first pixel substrate, and then a TSV 194 is formed. In this case, the TSV 194 can be connected to devices of the logic / peripheral substrate 300 through the landing pad 147 and the TSV 260 formed in the second pixel substrate 200.

[0133] Next, a method for manufacturing a device having a first insulating pattern and including a vertical transfer gate, a substrate including the same, and a stack image sensing device including the same according to the present invention will be described.

[0134] 21 is a flowchart showing a manufacturing process of a CMOS image sensing device according to an embodiment of the present invention. The manufacturing flow of the CMOS image sensing device according to an embodiment of the present invention includes the steps of (S100) providing a substrate including a pixel substrate and a logic / peripheral substrate, (S200) bonding the substrates, (S300) forming optical elements on a light receiving surface, and (S400) forming I / O pads.

[0135] 22 is a flow chart showing a manufacturing process of a substrate including a dual vertical transfer gate and a first insulating pattern according to an embodiment of the present invention. This process is included in the (S100) process of FIG. 21. The manufacturing process flow of a substrate 100 including a dual vertical transfer gate and a first insulating pattern according to an embodiment of the present invention includes: (S110) forming an isolation member, for example, STI, DTI, on the substrate 100 to specify an active region; (S120) forming a well region, an n-type region of a photodiode, an n-PD, a p-type region, and a floating diffusion region FD by ion doping, for example, ion implantation; (S130) applying a first insulating film on the substrate surface; (S140) forming a dual vertical transfer gate dVTG on the substrate; and (S150) forming wiring and contacts / vias. (S150) includes forming a bonding pad and an interlayer insulating film. (S200) The bonding method of the substrates is classified into a bonding method of one pixel substrate and one logic / peripheral substrate (two substrate stacking method) and a bonding method of two pixel substrates and one logic / peripheral substrate (three substrate stacking method).

[0136] 23, the three-substrate stack method illustrated in the first column includes a step of bonding a first pixel substrate and a second pixel substrate in a front-to-front bonding manner (S220), a step of forming TSVs in the second pixel substrate (S222), and a step of bonding the back surface of the second pixel substrate to the logic / peripheral substrate (S224). When performing the step (S222), CMP may be performed on the second pixel substrate to thin the thickness of the substrate, and the TSVs may be formed.

[0137] As in the three-substrate stack method shown in the second column of Figure 23, first, a step of forming a TSV in a second pixel substrate (S222) may be performed, a step of bonding the back surface of the second pixel substrate to the logic / peripheral substrate (S224) may be performed, and a step of bonding the first pixel substrate and the second pixel substrate in a front-to-front bonding manner (S220) may be performed.

[0138] 23, the three-substrate stack method includes a step of bonding a second pixel substrate and a logic / peripheral substrate in a front-to-front manner (S230), a step of forming TSVs in the second pixel substrate (S232), and a step of bonding the first pixel substrate and the second pixel substrate in a front-to-back manner (S234). When performing step 232, CMP may be performed on the second pixel substrate to thin the substrate and form the TSVs.

[0139] As in the three-substrate stack method shown in the fourth column of FIG. 23, first, step 232 of forming a TSV in the second pixel substrate may be performed, then step S234 of bonding the front side of the first pixel substrate to the back side of the second pixel substrate may be performed, and step S230 of bonding the second pixel substrate to the logic / peripheral substrate in a front-to-front bonding manner may be performed.

[0140] As in the two-substrate stack method illustrated in the fifth row of FIG. 23, the pixel substrate and the logic / peripheral substrate can be bonded face-to-face (S240).

[0141] In the step of forming an I / O pad (S400), a method of forming an I / O pad can be determined depending on which of the outermost substrates is to be formed when stacked. Referring to FIG. 24, the I / O pad forming method (S400) includes a method of forming a pad part on a logic / peri substrate (S410) and a method of forming a pad part on a back surface of a pixel substrate or a first pixel substrate (S420). When a pad part is formed on a logic / peri substrate (S410), a TSV is formed on a back surface of the logic / peri substrate. Or, when a pad part is formed on a first pixel substrate (S420), a TSV is formed on a back surface of the first substrate or a first pixel substrate.

[0142] Next, a method for manufacturing the two-stack image sensing device (bonding one pixel substrate and one logic / peripheral substrate) according to one embodiment of the present invention will be described.

[0143] 14A to 14I are cross-sectional views of a first substrate including a photodiode, a first insulating layer, and a vertical transfer gate according to an embodiment of the present invention. Each of Fig. 14A to Fig. 14I is a cross-sectional view taken along the line of Fig. 12B. Here, the first insulating layer includes a first insulating pattern, and the first insulating pattern is formed between poles P1 and P2 of the vertical dual transfer gate on the substrate.

[0144] 14A provides a substrate, with an active region defined through an isolating member on the surface of the substrate. The substrate 100 may include a silicon substrate, a compound semiconductor (e.g., indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (SiGe), indium arsenide (InAs), silicon carbide (SiC), or other suitable compound semiconductor material). The silicon substrate may include a bulk silicon layer or a silicon-on-insulator (SOI) substrate layer.

[0145] The substrate 100 may include one or more dopants to form an n-type or p-type substrate. In the present invention, a p-type substrate is preferred, and the substrate may be implanted with boron (B), aluminum (Al), or indium (In) dopants.

[0146] The isolation member 137 includes STI, and may be formed by forming an opening through a photolithography technique and filling it with an insulating material such as SiO2, SixNy, or a composite film.

[0147] As shown in Figure 14B, a deep trench is formed, for example by dry etching, and filled with an insulating material to form isolation members 130 to isolate pixel areas. In one embodiment, a conductive layer 136 can be formed to apply a bias to the isolation members. Conductive materials include polysilicon and tungsten. An insulating layer 131 can be applied to the trench to insulate the conductive material.

[0148] As shown in Fig. 14C, ion implantation can be performed on the surface of the substrate to form a well region 960, a floating diffusion region FD, 950, and an n-type region n-PD of a photodiode. Also, in order to change the concentration of the p region according to the position, a p-dopant (e.g., N, P, As) can be implanted into the p region. For example, a p-dopant can be implanted around the isolation member 130 to increase the p concentration surrounding the n-PD, or a p-type photodiode can be formed by increasing the p concentration on the surface of the substrate 100, and a GND node can be formed.

[0149] As shown in FIG. 14D, a first insulating film 126 is applied to the surface of the substrate 100. The first insulating film 126 is made of Si x N y , SiON, SiONC, SiO 2 In another embodiment, the present invention includes a film made of aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), Tantalum pentoxide (Ta 2 O 5 ), titanium oxide (TiO 2 ).

[0150] A deposition process can be used to apply the first insulating film 126 to the surface of the substrate. In one embodiment, the deposition process includes chemical vapor deposition (CVD).

[0151] When a silicon nitride film is applied as the first insulating film 126, a liner 129 may be provided in advance to prevent peeling. The liner 129 may be a silicon oxide film.

[0152] 14E, openings 121 are formed in the substrate. In one embodiment, two openings 121 are formed per gate. The opening formation step includes forming and patterning a photomask on the substrate, and then performing a dry etching process. In various embodiments, plasma assisted dry etching can be performed to increase anisotropy.

[0153] 14F, a gate insulating film 122 is formed in the opening 121. The gate insulating film may be a silicon oxide film, a silicon nitride film, or a composite film thereof, and may be formed into a thin, strong film by performing atomic layer deposition (ALD) or oxidation in the exposed opening.

[0154] As process optional variations, the film may be doped with elements such as nitrogen to enhance film properties and change the energy band gap, or other films may be deposited as additional layers.

[0155] It is also understood that in the present invention, an annealing process can be selectively performed before or after the deposition and ion implantation processes.

[0156] After the gate dielectric is deposited, the opening 121 may be filled with first polysilicon 120a.

[0157] Referring to FIG. 14G, a photomask 160 is formed and then a portion of the first insulating film 126 is removed using the photomask.

[0158] 14H, a gate insulating film is formed in the area exposed by the photomask patterning, and then a second polysilicon film is deposited. Then, patterning is performed again to form gates. The gates include dual vertical transfer gates 120 and gates of different analog circuits such as source follower SF and reset gate RG.

[0159] During this process, spacers 124 can be selectively formed around and on top of the gate.

[0160] 14I, after forming the PD and transistors on the substrate, the contacts 140 and the wiring 145 are formed and insulated with an interlayer insulating film to protect the conductive layer. A bonding pad 180 may be formed on the surface of the interlayer insulating film.

[0161] 15A to 15E illustrate a bonding process and an I / O pad formation process between a pixel substrate 100 and a logic / peripheral substrate 300 in a method for manufacturing a two-stack image sensing device according to an embodiment of the present invention.

[0162] 15A, a pixel substrate 100 and a logic / peri substrate 300 are provided. The logic / peri substrate 300 includes a gate 320, various contacts 340, wiring 345, and a bonding pad 380 on an interlayer insulating film 350.

[0163] The logic / periphery substrate 300 may be formed in a process separate from the pixel substrate 100, and the type of transistor may include silicon gate or metal gate transistors, and may include planar transistors or FinFET transistors.

[0164] 15B, the front surfaces of the pixel substrate 100 and the logic / peripheral substrate 300 are aligned and wafer-bonded to face each other. Bonding pads 180 and 380 are aligned and bonded to the bonding interfaces of the two substrates.

[0165] 15C, a portion of the back surface of the pixel substrate 100 is removed, and a second insulating film 178 is applied. The second insulating film 178 includes a hafnium oxide film, a tantalum oxide film, and an aluminum oxide film, and prevents negative charges generated in the photodiode from being trapped or dissipated on the removed substrate surface. An anti-reflective film 179 can be applied thereon.

[0166] The process of removing the back surface of the pixel substrate 100 includes chemical-physical polishing (CMP). In one embodiment, the back surface can be removed to the extent that the isolation members 130 are exposed.

[0167] 15D, after forming an insulating film on the rear surface of the pixel substrate 100, a grid 172, a color filter 170, a light blocking member 173, and a microlens 175 are formed. The grid 172 is formed in the pixel array to prevent crosstalk between adjacent pixels, and the light blocking member 173 is formed in the optical black area OB. The grid 172 and the light blocking member 173 in the pixel array are made of the same material and can be formed together in one process.

[0168] 15E, an opening is formed through the substrate on the back surface of the pixel substrate 100, for example to a landing pad 347 on the logic / peripheral substrate 300. An insulating film 195 is then applied to insulate the substrate 100, and then filled with a conductive material to form the TSVs 194. Conductive materials include polysilicon and tungsten. The opening may be formed through a passivation layer 176 on the back surface of the substrate 100, and the passivation layer 176 may be the same material as the material forming the microlens layer. I / O pads may be formed on the exposed TSVs.

[0169] Figures 16A to 16G are views showing a manufacturing process of a first pixel substrate 100 according to another embodiment of the present invention. Figures 16A to 16G show a manufacturing process of a first pixel substrate 100 having a photodiode PD and a transfer gate TG on the front side in the arrangement shown in Figure 8B or 8C. The source follower SF, the reset gate RG transistor, and the selection transistor SEL are manufactured in a separate second pixel substrate. Figures 16A to 16G are cross-sectional views seen in the direction of Figure 12B.

[0170] Referring to Fig. 16A, a substrate 100 is provided and an active region is defined on the surface of the substrate through an isolating member. The substrate 100 may include a silicon substrate or a compound semiconductor (e.g., indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (SiGe), indium arsenide (InAs), silicon carbide (SiC), or other suitable compound semiconductor material). The silicon substrate may include a bulk silicon layer or a silicon-on-insulator (SOI) substrate layer. The doping implantation for the substrate 100 is as described in Fig. 14A.

[0171] The isolation member 137 includes STI, and an opening is formed through a photolithography technique, and the isolation member 137 is formed of SiO 2 Or Si x N y and may be filled with an insulating material such as a composite film.

[0172] 16B, a deep trench is formed, for example by dry etching, and filled with an insulating material, for example including silicon oxide and / or silicon nitride, to form an isolation member 130. The isolation member 130 isolates pixel regions. In an embodiment, a conductive layer 136 may be formed to apply a bias to the isolation member. For the application of the conductive layer and the insulating layer 131, see the description of FIG. 14B.

[0173] As shown in Fig. 16C, ion implantation can be performed on the surface of the substrate to form a well region 960, a floating diffusion region FD, 950, and an n-type region n-PD of a photodiode. Also, in order to change the concentration of the p region according to the position, a p-dopant (e.g., N, P, As) can be implanted into the p region. For example, a p-dopant can be implanted around the isolation member 130 to increase the p concentration surrounding the n-PD, or a p-type photodiode can be formed by increasing the p concentration on the surface of the substrate 100, and a GND node can be formed.

[0174] As shown in FIG. 16D, a first insulating film 126 is formed on the surface of the substrate 100. The first insulating film 126 is made of Si x N y , SiON, SiONC, SiO 2 In another embodiment, the present invention includes a film made of aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), Tantalum pentoxide (Ta 2 O 5 ), titanium oxide (TiO 2 ).

[0175] A deposition process can be used to apply the first insulating film 126 to the surface of the substrate. In one embodiment, the deposition process includes chemical vapor deposition (CVD).

[0176] When a silicon nitride film is applied as the first insulating film 126, a liner 129 may be applied in advance to prevent peeling. The liner 129 may be a silicon oxide film.

[0177] Referring to FIG. 16E, an opening 121 is formed in the substrate. In one embodiment, two openings 121 are formed per gate. The opening forming step includes forming a photomask on the substrate, patterning the photomask, and then performing a dry etching process. In various embodiments, plasma assisted dry etching can be performed to increase anisotropy. The opening is formed to reach the n-type region n-PD of the photodiode in the substrate.

[0178] Referring to FIG. 16F, a gate insulating film 122 is formed in the opening 121. The gate insulating film can be a silicon oxide film, a silicon nitride film, or a composite film thereof, and can be formed to have a strong film quality even in a thin thickness by performing atomic layer deposition (ALD) or an oxidation process on the exposed opening. After applying the gate insulating film, polysilicon is filled and patterned to form the gate 120. The gate manufacturing process can be performed in two steps, where a first polysilicon is filled in the opening 121, a second polysilicon is applied again, and then patterned to form the gate. During the patterning process, spacers 124 can be selectively formed around and on the gate.

[0179] In this embodiment, the first insulating film 126 applied to the surface of the substrate 100 can be left as an etch stop film in the next process, while in another embodiment, the first insulating film 126 exposed by patterning the photomask 160 can be selectively removed.

[0180] 16G, after forming the PD and transistor on the substrate, the contact 140 and the wiring 145 are formed and insulated with an interlayer insulating film to protect the conductive layer. A bonding pad 180 may be formed on the surface of the interlayer insulating film. The number of wiring layers may be one or two. The bonding pad 180 may include copper.

[0181] 17A to 17F are diagrams illustrating a process for manufacturing an image sensing device in which two pixel substrates and a logic / peripheral substrate are stacked. The process for bonding a first pixel substrate 100, a second pixel substrate 200, and a logic / peripheral substrate 300 and forming optical elements and I / O pads will be described.

[0182] 17A, a second pixel substrate 200 is provided in addition to the first pixel substrate 100. The second pixel substrate 200 has a source follower SF, a reset RG transistor, and a selection transistor SEL formed on an active region partitioned by an isolation region 237.

[0183] The second pixel substrate 200 may be fabricated using a process different from that of the first pixel substrate 100 and may include planar transistors or FinFet transistors.

[0184] A contact 240, a wiring 245, and a bonding pad 280 for electrical connection are formed on the second pixel substrate 200 and are insulated by an interlayer isolation film.

[0185] 17B, ​​the front surfaces of the first pixel substrate 100 and the second pixel substrate 200 are aligned and wafer-bonded to face each other. Bonding pads 180 and 280 are aligned and bonded to the bonding interfaces of the two substrates.

[0186] 17C, an opening is formed at the rear surface of the second pixel substrate 200, penetrating the substrate until it reaches, for example, a wiring at the front surface of the second pixel substrate 200. Next, an insulating film is formed to insulate the substrate 200, and then a conductive material is filled to form the TSV 260. The conductive material may include polysilicon or tungsten. In the process of forming the opening, a passivation layer may be formed on the rear surface of the substrate 200, and if a portion of the passivation layer is removed, the TSV 260 may have a shape protruding from the rear surface of the second pixel substrate 200.

[0187] 17D, a logic / peri substrate 300 is provided separately. For the manufacturing process of the logic / peri substrate 300, refer to the description of FIG. 15A.

[0188] The front side of the logic / periphery substrate 300 and the back side of the second pixel substrate 200 are aligned and bonded to form a three-layer stack.

[0189] 17E, a portion of the rear surface of the first pixel substrate 100 is removed, and a single layer or multiple layers of insulating films 178 and 179 are applied. For the description of the second insulating film 178 and the anti-reflection film 179, refer to FIGS. 15C and 15D.

[0190] The process of removing the back surface of the pixel substrate 100 includes chemical-physical polishing (CMP). In one embodiment, the back surface can be removed to the extent that the isolation members 130 are exposed.

[0191] Next, an insulating film is formed on the rear surface of the pixel substrate 100, and optical elements such as a grid 172, a color filter 170, a light blocking member 173, and a microlens 175 are then formed. For the manufacturing process and description of the optical elements, please refer to FIG. 15D.

[0192] 17F, an opening is formed through the substrate at the backside of the logic / peri substrate 300, for example to a landing pad 347 on the logic / peri substrate 300. An insulating film 395 is then applied to insulate the substrate 300, and then filled with a conductive material to form a TSV 394. Conductive materials include polysilicon and tungsten. The opening may be formed through the passivation layer 376 at the backside of the substrate 300. I / O pads 392 may be formed on the exposed TSVs.

[0193] 18 is a diagram showing a manufacturing process of another embodiment of a CMOS image sensing device including a unit pixel circuit and a logic circuit. Referring to FIG. 18, an insulating film 195 is applied to the rear surface of a first pixel substrate 100 through the substrate, and then a TSV 194 is formed. For the description of the type of filling conductive material, the passivation layer 176, and the I / O pad 192, refer to the description of FIG. 15.

[0194] 19A to 19D show a process for manufacturing an image sensing device in which the front surface of a first pixel substrate 100 and the rear surface of a second pixel substrate 200 are combined together, according to another embodiment of the present invention.

[0195] 19A, a second pixel substrate 200 and a logic / periphery substrate 300 are separately provided. For the description of the second pixel substrate 200, refer to FIG. 17A, and for the description of the logic / periphery substrate 300, refer to FIG.

[0196] 19B, the front surface of the second pixel substrate 200 and the front surface of the logic / peri substrate 300 are wafer bonded to face each other. At the bonding interface, the bonding pads 281 of the second pixel substrate and the bonding pads 380 of the logic / peri substrate are aligned and bonded.

[0197] 19B, after the second pixel substrate 200 and the logic / peripheral substrate 300 are bonded (front-to-front) as in Fig. 19A, openings are formed in the rear surface of the second pixel substrate 200, insulated, and then filled with a conductive material to form the TSVs 260. In one embodiment, the rear surface of the substrate may be removed before the TSV formation process.

[0198] Next, the second pixel substrate 200 and the first pixel substrate 100 are bonded to each other so that the rear surface of the second pixel substrate 200 faces the front surface of the first pixel substrate 100. At the bonding interface, the bonding pads 280 of the second pixel substrate 200 and the bonding pads 180 of the first pixel substrate 100 are aligned and bonded.

[0199] 19C, a part of the back surface of the first pixel substrate 100 is removed, an insulating film is formed, and an optical element is formed. For the removal of the back surface, the insulating film, and the formation of the optical element, refer to the description of FIGS. 15C and 15D.

[0200] 19D, a passivation layer 376 is formed on the back surface of the logic / peri substrate 300, an opening is formed through the back surface of the substrate 300, an insulating film 395 is formed in the opening, and a conductive material is filled to form a TSV 394. In one embodiment, the TSV 394 is connected to a landing pad 347 of the logic / peri substrate 300.

[0201] 20 is a diagram showing a process for manufacturing a CMOS image sensing device including a unit pixel circuit and a logic circuit in another manner, which is different from the embodiment in FIG 19 in that a pad region is defined on the rear surface of the first pixel substrate 100, and a TSV 194 is formed by penetrating an opening toward the rear surface.

[0202] Thus, the present invention relates to a dual vertical transfer gate having two poles extending to an n-type region of a photodiode and a first insulating pattern on a substrate and between the poles, and to a CMOS image sensing device including the same. The CMOS image sensing device includes a stacked image sensing device in which one or two pixel substrates and a logic / peri substrate are stacked. The stacked image sensing device may utilize a wafer bonding technique. In another embodiment of the present invention, a substrate 200 may be stacked on a pixel substrate 100, so that a front surface of the logic / peri substrate 300 faces a front surface of the second pixel substrate 200. [Industrial Applicability]

[0203] The present invention can be formed by an integrated circuit technology in which a semiconductor element is formed on a substrate. In addition, the present invention can be applied to a substrate stack technology without complicated processes or additional processes. Therefore, the present invention is expected to have higher applicability and excellent effects as the performance and integration of image sensing devices become higher.

[0204] Although the present invention relates to an image sensing device including a semiconductor, embodiments and products embodied in accordance with the concept of the present invention may be applied and / or integrated into not only electrical and electronic products, but also medical, health, construction, machinery, and exterior products. [Explanation of symbols]

[0205] 100 pixel board 120 Vertical Transfer Gate 122 Gate insulating film 125 First insulation pattern 126 First insulating film 130 Separation member 300 Logic / Peripheral Board C connection part E Gate Extension FD Floating diffusion area P1, P2 pole STI element isolation area

Claims

1. Gate and an n-type source region disposed under the gate; an n-type drain region disposed in the substrate adjacent the gate; a gate insulating film between the gate and the substrate; a first insulating pattern between the gate insulating film and the substrate; Including, The gate is Two poles extending to the source region; A connection portion that connects the two poles; Including, The first insulating pattern is disposed between the poles.

2. The transistor of claim 1 , wherein the first insulating pattern has a thickness of 5 to 50 nm.

3. The first insulating pattern is Si ｘ N ｙ 2. The transistor of claim 1 , comprising:

4. The transistor of claim 1 , wherein the pole has a width of 50 to 200 nm at the surface of the substrate.

5. 2. The transistor of claim 1, wherein the pole has a depth of 200 to 500 nm from the surface of the substrate.

6. The transistor of claim 5 , wherein the aspect ratio of the pole is between 1 and 10.

7. The transistor of claim 4 , wherein the spacing between the poles is between 10 and 80 nm at the surface of the substrate.

8. The first insulating pattern is made of SiON, SiONC, or SiO ２ 2. The transistor according to claim 1, which is made of any one film selected from the group consisting of films made of silicon carbide (SiOC), silicon dioxide (SiO2), and a composite film thereof.

9. The transistor of claim 3 , wherein the first insulating pattern comprises a void.

10. 4. The transistor of claim 3, further comprising an etch stop layer on the substrate adjacent to the gate and at the same level as the first insulating pattern.

11. a first substrate including a photodiode region, a transfer transistor, and a floating diffusion region; The transfer transistor includes a first substrate, a gate having two poles extending to an n-type region of the photodiode and a connection portion connecting the two poles, and a first insulating pattern between the poles; a second substrate including a source follower transistor; a third substrate including a logic circuit; Including, The floating diffusion region of the first substrate and the gate of the source follower transistor of the second substrate are electrically connected to each other.

12. 12. The image sensing device of claim 11, wherein the floating diffusion region of the first substrate and the gate of the source follower transistor of the second substrate are connected by Cu-Cu bonding.

13. The image sensing device of claim 12 , wherein a front surface of the third substrate is coupled to a rear surface of the second substrate.

14. The image sensing device of claim 12 , further comprising a via penetrating a rear surface of the third substrate and an I / O pad coupled to the via.

15. 12. The image sensing device of claim 11, wherein the floating diffusion region of the first substrate and the gate of the source follower transistor of the second substrate are coupled by a via that passes through the second substrate.

16. The image sensing device of claim 15 , wherein a front surface of the third substrate is coupled to a front surface of the second substrate.

17. The image sensing device of claim 15 , further comprising a via penetrating a rear surface of the third substrate and an I / O pad coupled to the via.

18. The image sensing device of claim 16, wherein the second substrate and the third substrate are connected by Cu-Cu bonding.

19. The image sensing device of claim 15 , wherein the first substrate includes two layers of metal wiring.

20. The image sensing device of claim 12 , further comprising a dummy bonding pad connecting the first substrate and the second substrate.

Images