Image formation device and light-emitting device

Abstract

To provide an image formation device including a light-emitting device that is improved in a structure of a light-emitting chip and a drive circuit.SOLUTION: An image formation device includes a light-emitting device having a surface at which an electrode layer and a light-emitting layer are formed and including a silicon wafer provided with a drive circuit for driving the light-emitting layer.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a light emitting device and an image forming apparatus, and more particularly to an electrophotographic printer. [Background technology]

[0002] In a printer, which is an electrophotographic image forming apparatus, a method of exposing a photosensitive drum to light using an exposure head to form a latent image is generally known. Here, for example, LEDs (Light Emitting Diodes) or organic electroluminescence (Organic Electro Luminescence) are used for the exposure head. The exposure head is composed of a row of light emitting elements arranged in the longitudinal direction of the photosensitive drum, and a rod lens array that forms an image of light from the row of light emitting elements on the photosensitive drum. LEDs and organic electroluminescence are known to have a surface light emitting shape in which the direction of light irradiation from the light emitting surface is the same as that of the rod lens array. Here, the length of the row of light emitting elements is determined according to the width of the image area on the photosensitive drum, and the interval between the light emitting elements is determined according to the resolution of the printer. For example, in the case of a 1200 dpi printer, the pixel interval is 21.16 μm, and therefore the interval between the light emitting elements is also an interval corresponding to 21.16 μm. Printers using such exposure heads use fewer parts than laser scanning printers, which scan a photosensitive drum with a laser beam deflected by a rotating polygon mirror, making it easier to make the device smaller and less expensive.

[0003] Patent Document 1 discloses an exposure head in which a light-emitting chip and a signal generating circuit as a drive circuit for driving the light-emitting chip are individually mounted on a circuit board. The signal generating circuit transmits a light emission signal to the light-emitting chip via wiring on the printed circuit board to cause the light-emitting element of the light-emitting chip to emit light. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2017-183436 A Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention aims to improve the structure of the light emitting chip and the driving circuit disclosed in Patent Document 1. [Means for solving the problem]

[0006] In order to solve the above-mentioned problems, the present invention has the following configuration. (1) An image forming apparatus comprising: a photoconductor that is driven to rotate about a rotation axis; an exposure head including a light emitting device, a circuit board on which the light emitting device is mounted, and a lens array that guides light emitted from the light emitting device to a surface of the photoconductor; and a controller that outputs image data for driving the light emitting device to the circuit board, wherein the light emitting device includes a silicon wafer including a drive circuit for driving the light emitting device, a first electrode layer arranged in a direction approximately parallel to the rotation axis of the photoconductor and including a plurality of electrodes, a layered second electrode layer that is light transmissive, and a light emitting layer formed in a layered manner between the first electrode layer and the second electrode layer and that emits light when a voltage is applied thereto, and a layered body formed on a surface of the silicon wafer, wherein the drive circuit includes a voltage generation circuit that generates a drive voltage, and a pulse signal generation circuit that generates a pulse signal for each of the plurality of electrodes based on the image data, and the drive circuit applies the drive voltage generated by the voltage generation circuit in response to the pulse signal to each of the plurality of electrodes. (2) A light-emitting device comprising: a silicon wafer including a circuit; a first electrode layer including a plurality of electrodes; a layered second electrode layer capable of transmitting light; and a light-emitting layer formed in a layered form between the first electrode layer and the second electrode layer and emitting light when a voltage is applied thereto; and a layered body formed on a surface of the silicon wafer; the drive circuit including a voltage generation circuit that generates a drive voltage; and a pulse signal generation circuit that generates a pulse signal for each of the plurality of electrodes based on drive data; and the drive circuit applies the drive voltage generated by the voltage generation circuit in response to the pulse signal to each of the plurality of electrodes. Effect of the Invention

[0007] It is possible to provide a light emitting device that causes a layered body including a light emitting layer formed on the surface of a silicon wafer to emit light by a drive circuit provided on the silicon wafer, and an image forming apparatus using the same. [Brief description of the drawings]

[0008] [Figure 1] 1 is a diagram showing a configuration of an image forming apparatus. [Diagram 2] FIG. 1 shows the configuration of an exposure head. [Diagram 3] Diagram showing the structure of a printed circuit board [Figure 4] Diagram showing the structure of a silicon substrate [Diagram 5] Cross-sectional view of a light-emitting region and a configuration diagram of a light-emitting device [Figure 6] Block diagram of the image controller and printed circuit board [Figure 7] Circuit diagram inside the light-emitting device [Figure 8] FIG. 1 shows the waveforms of each signal and the shift of image data. [Figure 9] FIG. 1 is an explanatory diagram of a pulse signal generating unit and a diagram showing the waveforms of each signal. [Figure 10] Circuit diagram inside the light-emitting device [Figure 11] Analog block diagram, driver circuit diagram [Figure 12] FIG. 1 is an explanatory diagram of a pulse signal generating unit and a diagram showing the waveforms of each signal. [Figure 13] A diagram showing a printed circuit board and an explanation of the correction amount p [Figure 14] A diagram showing the position of the lower electrode in the short side direction and a diagram showing the waveforms of each signal [Figure 15] FIG. 1 shows a modified example of a printed circuit board. [Figure 16] A cross-sectional view of a light-emitting region as a modified example, and a configuration diagram of a light-emitting device [Figure 17] Conceptual diagram of multiple exposure [Figure 18] FIG. 1 shows a modified example of a circuit in a light emitting device. [Figure 19] FIG. 1 shows waveforms of signals and image data in multiple exposures. [Figure 20] FIG. 13 is a diagram showing a modified example of a circuit in a light emitting device for switching the light emission order. [Figure 21] Timing chart for explaining chip select signals [Figure 22] A block diagram showing a modified example of the image controller and the printed circuit board. [Diagram 23] Timing chart for explaining a modified chip select signal DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. EXAMPLES

[0010] [Configuration of image forming device] Fig. 1 is a schematic cross-sectional view showing the configuration of an electrophotographic image forming apparatus in Example 1. The image forming apparatus shown in Fig. 1 is a multifunction peripheral (MFP) equipped with a scanner function and a printer function, and is composed of a scanner unit 100, an image creating unit 103, a fixing unit 104, a paper feed / transport unit 105, and a printer control unit (not shown) that controls these. The scanner unit 100 illuminates a document placed on a document table to optically read the document image, and converts the read image into an electrical signal to create image data.

[0011] The imaging unit 103 includes four image forming stations arranged in the order of cyan (C), magenta (M), yellow (Y), and black (K) along the rotation direction (counterclockwise direction) of an endless conveyor belt 111. The four image forming stations have the same configuration, and each image forming station includes a photosensitive drum 102, which is a photosensitive body that rotates in the direction of the arrow (clockwise direction), an exposure head 106, a charger 107, and a developing device 108. The suffixes a, b, c, and d of the photosensitive drum 102, the exposure head 106, the charger 107, and the developing device 108 indicate that the configuration corresponds to the image forming stations black (K), yellow (Y), magenta (M), and cyan (C), respectively. In the following, the suffixes of the symbols will be omitted except when referring to a specific photosensitive drum, etc.

[0012] In the image forming unit 103, the photosensitive drum 102 is rotated and charged by the charger 107. An exposure head 106, which is an exposure means, causes a light emitting device to emit light in accordance with image data, and the light generated by the light emitting device is collected on the photosensitive drum 102 (on the photoconductor) by a rod lens array to form an electrostatic latent image. A developer 108, which is a development means, develops the electrostatic latent image formed on the photosensitive drum 102 with toner. Then, the developed toner image is transferred to a recording paper on a conveyor belt 111 that conveys the recording paper. Such a series of electrophotographic processes are executed at each image forming station. During image formation, after a predetermined time has elapsed since the start of image formation at the cyan (C) image forming station, image forming operations are executed in sequence at each of the magenta (M), yellow (Y), and black (K) image forming stations. As a result, a full-color image is formed.

[0013] The image forming apparatus shown in FIG. 1 includes, as units for feeding recording paper, in-body paper feeding units 109a and 109b of a paper feeding / transporting unit 105, an external paper feeding unit 109c which is a large-capacity paper feeding unit, and a manual paper feeding unit 109d. During image formation, recording paper is fed from a paper feeding unit designated in advance, and the fed recording paper is transported to a registration roller 110. The registration roller 110 transports the recording paper to a transport belt 111 at the timing when the toner image formed in the image forming unit 103 described above is transferred to the recording paper. The toner images formed on the photosensitive drums 102 of the image forming stations are sequentially transferred to the recording paper transported by the transport belt 111. The recording paper to which the unfixed toner image has been transferred is transported to a fixing unit 104. The fixing unit 104 has a built-in heat source such as a halogen heater, and fixes the toner image on the recording paper to the recording paper by applying heat and pressure with two rollers. The recording paper on which the toner image has been fixed by the fixing unit 104 is discharged by a discharge roller 112 to the outside of the image forming apparatus.

[0014] An optical sensor 113, which is a detection unit, is disposed at a position facing the conveyor belt 111 downstream of the black (K) image forming station in the recording paper conveying direction. The optical sensor 113 detects the position of a test image formed on the conveyor belt 111 in order to derive the amount of color shift of the toner image between the image forming stations. The amount of color shift derived by the optical sensor 113 is notified to an image controller unit 700 (see FIG. 6) described later, etc., and the image position of each color is corrected so that a full-color toner image without color shift is transferred onto the recording paper. In addition, a printer control unit (not shown) executes an image forming operation while controlling the scanner unit 100, the image creating unit 103, the fixing unit 104, the paper feed / conveying unit 105, etc. described above, in response to an instruction from an MFP control unit (not shown) that controls the entire multifunction peripheral (MFP).

[0015] Here, as an example of an electrophotographic image forming apparatus, an image forming apparatus that directly transfers a toner image formed on the photosensitive drum 102 of each image forming station onto recording paper on a conveyor belt 111 has been described. The present invention is not limited to printers that directly transfer a toner image on the photosensitive drum 102 onto recording paper. For example, the present invention can also be applied to an image forming apparatus that includes a primary transfer unit that transfers the toner image on the photosensitive drum 102 onto an intermediate transfer belt, and a secondary transfer unit that transfers the toner image on the intermediate transfer belt onto recording paper.

[0016] [Exposure head configuration] Next, the exposure head 106 that exposes the photosensitive drum 102 will be described with reference to Fig. 2. Fig. 2(a) is a perspective view showing the positional relationship between the exposure head 106 and the photosensitive drum 102, and Fig. 2(b) is a diagram for explaining the internal configuration of the exposure head 106 and how a light beam from the exposure head 106 is focused on the photosensitive drum 102 by a rod lens array 203. As shown in Fig. 2(a), the exposure head 106 is attached to the image forming apparatus by an attachment member (not shown) at a position above the photosensitive drum 102 that rotates in the direction of the arrow and facing the photosensitive drum 102 (Fig. 1).

[0017] As shown in FIG. 2(b), the exposure head 106 is composed of a printed circuit board 202, a light emitting device group 400 mounted on the printed circuit board 202, a rod lens array 203, and a housing 204. The rod lens array 203 and the printed circuit board 202 are attached to the housing 204. As shown in FIG. 2, the rod lens array 203 is disposed between the light emitting device group 400 and the photosensitive drum 102. The rod lens array 203 is provided along the longitudinal direction of the printed circuit board 202, and focuses the light beams emitted by the light emitting device group 400 on the photosensitive drum 102. In the factory, the exposure head 106 is assembled and adjusted by itself, and the focus and the amount of light are adjusted. Here, the assembly and adjustment are performed so that the distance between the photosensitive drum 102 and the rod lens array 203 and the distance between the rod lens array 203 and the light emitting device group 400 are set to a predetermined interval. As a result, the light from the light emitting device group 400 is imaged on the photosensitive drum 102. Therefore, when adjusting the focus at the factory, the mounting position of the rod lens array 203 is adjusted so that the distance between the rod lens array 203 and the light emitting device group 400 is a predetermined value. Also, when adjusting the amount of light at the factory, a voltage to be applied to the light emitting device 401, which will be described later, is adjusted by driving a lower electrode of the light emitting device 401, which will be described later, so that the light condensed on the photosensitive drum 102 via the rod lens array 203 has a predetermined amount of light.

[0018] [Configuration of the light-emitting device group] Fig. 3 is a diagram illustrating the printed circuit board 202 and the light emitting device group 400 mounted on the printed circuit board 202. Fig. 3(a) is a schematic diagram showing the configuration of the surface of the printed circuit board 202 on which the light emitting device group 400 is mounted, and Fig. 3(b) is a schematic diagram showing the configuration of the surface (second surface) of the printed circuit board 202 opposite to the surface (first surface) on which the light emitting device group 400 is mounted.

[0019] As shown in FIG. 3(a), the light emitting device group 400 mounted on the printed circuit board 202, which is the second board, has a configuration in which 20 light emitting devices 401-1 to 401-20, which are independent chips, are arranged in two rows in a staggered pattern along the longitudinal direction of the printed circuit board 202. That is, on the printed circuit board 202 (second board), odd-numbered light emitting devices 401-1... (401-2n+1: n ≧ 0) and even-numbered light emitting devices 401-2... (401-2n: n ≧ 1) are arranged at different positions in the rotation direction of the photosensitive drum 102. The light emitting devices 401-1 to 401-20 may be collectively referred to as light emitting devices 401. In FIG. 3(a), the up-down direction indicates the rotation direction of the photosensitive drum 102, which is the first direction, and the horizontal direction indicates the longitudinal direction, which is the second direction perpendicular to the first direction. The longitudinal direction is also a cross direction that crosses the rotation direction of the photosensitive drum 102. Inside each light-emitting device 401, there are a total of 748 lower electrodes, which will be described later. In this embodiment, the lower electrodes are arranged at intervals of 21.16 μm (≒2.54 cm / 1200 dots). As a result, the arrangement distance from end to end of the 748 lower electrodes in one light-emitting device 401 is about 15.8 mm (≒21.16 μm×748). The light-emitting device group 400 is composed of 20 light-emitting devices 401. The number of lower electrodes that can be exposed in the light-emitting device group 400 is 14,960 (=748 electrodes×20 chips), and the light-emitting device group 400 can perform exposure corresponding to an image width in the longitudinal direction of about 316 mm (≒about 15.8 mm×20 chips).

[0020] 3(b), a connector 305 is mounted on the surface of the printed circuit board 202 opposite to the surface on which the light emitting device group 400 is mounted. The connector 305 is a connector for connecting a control signal and a power supply line for controlling the light emitting device group 400 from an image controller unit 700 (see FIG. 6) described later, and each of the light emitting devices 401-1 to 401-20 is driven via the connector 305.

[0021] Fig. 3(c) is a diagram showing the boundary between chips of light emitting devices 401 arranged in two rows in the longitudinal direction, where the horizontal direction is the longitudinal direction of the light emitting device group 400 in Fig. 3(a) and a plurality of light emitting devices 401 are arranged. Fig. 3(c) shows the boundary between chips of light emitting device 401 (the portion where the ends of chips overlap in the longitudinal direction (overlapping portion)). Even at the boundary between light emitting device 401-n and light emitting device 401-n+1, ​​the pitch of the lower electrodes at the ends between different light emitting devices 401 (the distance (L) between the center points of two lower electrodes) is approximately 21.16 µm, which is the pitch for a resolution of 1200 dpi.

[0022] The light emitting devices 401 are arranged in two rows, one above the other, in the short direction, as follows: That is, the upper and lower light emitting devices 401 are arranged so that the interval between the lower electrodes (described later) (indicated by the arrow S in the figure) is about 105 μm (a distance that is an integer multiple of the resolution of 5 pixels at 1200 dpi and 10 pixels at 2400 dpi). The interval between the light emitting points in the longitudinal direction of the exposure head 106 (indicated by the arrow L in the figure) is about 21.16 μm (one pixel at 1200 dpi). In the present invention, the intervals S and L between the light emitting devices 401 do not have to be limited to the values ​​mentioned above.

[0023] [Configuration of the light-emitting device] FIG. 4 is a schematic diagram showing the internal configuration of the light-emitting device 401. As shown in FIG. 4, the longitudinal direction of the light-emitting device 401 is the X direction, and the lateral direction is the Y direction. Here, the Y direction is the rotation direction of the photosensitive drum 102, in other words, the movement direction of the photosensitive surface (photoconductor surface) of the rotating photosensitive drum 102. The X direction is a direction that is approximately perpendicular to the Y direction, that is, the rotation direction of the photosensitive drum 102. It is also a direction that is approximately parallel to the rotation direction of the photosensitive drum 102. Note that approximately perpendicular allows a tilt of about ±1° with respect to an angle of 90°, and approximately parallel allows a tilt of about ±1° with respect to an angle of 0° between them. In the light-emitting device 401, wire bonding pads (hereinafter referred to as WB pads) 601-1, 601-2, 601-3, and 601-4 are formed on a silicon substrate 402 that is a first substrate. Note that a circuit section 602 (indicated by a broken line) that is a driving section is built into the silicon substrate 402. A configuration including an analog driving circuit, a digital control circuit, or both can be used as the circuit portion 602. Power supply to the circuit portion 602 and input / output of signals from outside the light emitting device 401 are performed via a WB pad 601.

[0024] The light-emitting device 401 of this embodiment includes a linear light-emitting region 604 extending along the rotation axis direction of the photosensitive drum 102. The light-emitting region 604 includes an anode, a cathode, and a light-emitting layer 450 (see FIG. 5 ), which will be described later, and is a region that emits light when a potential difference occurs between the anode and the cathode.

[0025] A silicon wafer is used as the silicon substrate 402. This has the following advantages. That is, silicon substrates have the advantage that high-speed, highly functional circuits can be formed at high density because the process technology for forming integrated circuits has been developed and silicon substrates are already used as substrates for various integrated circuits. In addition, silicon substrates have the advantage that large-diameter wafers are available and can be obtained at low cost.

[0026] In this embodiment, the circuit section 602 is provided with a drive circuit for driving the light emitting region 604, including a data transfer section for generating a signal for making the light emitting region 604 emit light (hereinafter referred to as a light emitting signal), a light emitting signal generation section, and a drive voltage generation circuit for generating a drive voltage to be applied to the lower electrode. The circuit section 602 is then formed as an integrated circuit on the silicon substrate 402. The lower electrodes are evaporated onto the silicon substrate 402 so as to be electrically connected. This makes it possible to increase the light emission cycle and reduce the number of wire bonds to the lower electrodes.

[0027] [Light-emitting area configuration] The light emitting device 401 will be described in more detail with reference to FIG. 5. The X direction in FIG. 5 indicates the longitudinal direction of the exposure head 106. The Z direction is the direction in which each layer of the layer structure described later overlaps (lamination direction). FIG. 5(a) is an enlarged view of a main part of the schematic diagram of the AA cross section in FIG. 4. FIG. 5(a) is a schematic diagram of lower electrodes 410-1 to 410-748 described later as viewed from the Y direction. As shown in FIG. 5(a) and FIG. 5(c), the light emitting device 401 includes a silicon substrate 402, lower electrodes 410-1 to 410-748, a light emitting layer 450, and an upper electrode 460. The silicon substrate 402 is a driving substrate on which driving circuits including driving units corresponding to the lower electrodes 410-1 to 410-748 described later are formed in the manufacturing process.

[0028] As shown in Fig. 5(a) and Fig. 5(c), the lower electrodes 410-1 to 410-748 (cathodes) are a plurality of electrodes formed in a layered form (first electrode layer) on the silicon substrate 402. The lower electrodes 410-1 to 410-748 are formed on a plurality of driving units built into the silicon substrate 402 by using a Si integrated circuit processing technology together with the manufacturing process for manufacturing the silicon substrate 402. The lower electrodes 410-1 to 410-748 are preferably made of a metal having a high reflectance with respect to the emission wavelength of the light-emitting layer 450 described later. Therefore, the lower electrodes 410-1 to 410-748 preferably contain silver (Ag), aluminum (Al), or an alloy thereof, a silver-magnesium alloy, or the like.

[0029] 5, lower electrodes 410-1 to 410-748 are electrodes provided corresponding to each pixel in the X direction. That is, lower electrodes 410-1 to 410-748 are electrodes provided to form one pixel each. Lower electrodes 410-1 to 410-748 form a first electrode row.

[0030] In this embodiment, the width W of the lower electrodes 410-1 to 410-748 in the X direction corresponds to the width of one pixel. The interval d is the distance (arrangement interval) between the lower electrodes in the X direction. Since the lower electrodes 410-1 to 410-748 are formed on the silicon substrate 402 with an interval d therebetween, the multiple driving units formed on the silicon substrate 402 can individually control the voltages of the lower electrodes 410-1 to 410-748. The interval d is filled with the organic material of the light-emitting layer 450, and the lower electrodes are partitioned by the organic material.

[0031] In the light emitting device 401 of this embodiment, the width W of the lower electrodes 410-1 to 410-748 is set to 20.90 μm as a nominal dimension, and the interval d is set to 0.26 μm as a nominal dimension. That is, the light emitting device 401 of this embodiment has one lower electrode 410 every 21.16 μm in the X direction. Since 21.16 μm is the size of one pixel at 1200 dpi, the width of each lower electrode 410 in the X direction has a size equivalent to one pixel corresponding to the output resolution of the image forming device of this embodiment. Note that the process rule in the light emitting device 401 of this embodiment is about 0.2 μm, which is highly accurate, and it is possible to form the width d with a resolution of 0.26 μm.

[0032] 5B, the width of the lower electrodes 410-1 to 410-748 in the Y direction, which is the rotation direction of the photosensitive drum 102, is also W. That is, the lower electrodes 410-1 to 410-748 in this embodiment are 20.90 μm square, and the area of ​​the lower electrode 410 is 436.81 μm. 2 This means that the area of ​​one pixel is 447.7456 μm 2It occupies about 97.6% of the total area of ​​the lower electrode 410. The organic light emitting material emits less light than an LED. On the other hand, by forming the lower electrode 410 on the silicon substrate 402 with a square shape and a small distance between adjacent lower electrodes as described above, it is possible to secure a light emitting area for obtaining a light amount sufficient to change the potential of the photosensitive drum 102. It is preferable to secure a lower electrode area of ​​90% or more of the area occupied by one pixel. Therefore, for an image forming device with an output resolution of 1200 dpi, it is preferable to form the lower electrode 410 with a side width of about 20.07 μm or more, and for an image forming device with an output resolution of 2400 dpi, it is preferable to form the lower electrode 410 with a side width of about 10.04 μm or more.

[0033] On the other hand, the upper limit of the occupied area of ​​the lower electrode 410 should be set based on the transmittance of the rod lens array 203 and the upper electrode 460 described later, but in this embodiment, the upper limit is set to 110% with respect to the occupied area of ​​one pixel. If it is designed to be larger than 110% with respect to the occupied area of ​​one pixel, the size of the pixel formed when exposing the highly sensitive photosensitive drum 102 may greatly exceed the resolution, so the upper limit of the occupied area of ​​the lower electrode 410 is set to 110%. Therefore, for an image forming device with an output resolution of 1200 dpi, it is desirable to form the width of one side of the lower electrode 410 to be approximately 22.19 μm or less, and for an image forming device with an output resolution of 2400 dpi, it is desirable to form the width of one side of the lower electrode 410 to be approximately 11.10 μm or less. In other words, it is preferable that the range of the occupied area of ​​the lower electrode 410 with respect to the occupied area of ​​one pixel is 90% or more and 110% or less.

[0034] The shape of the lower electrode 410 is not limited to a square, and may be any shape, such as a polygon with more than a square, a circle, an ellipse, etc., as long as it emits light of an exposure area size corresponding to the output resolution of the image forming device and the image quality of the output image produced by that light is at a level that satisfies the design specifications of the image forming device.

[0035] Next, the light emitting layer 450 will be described. The light emitting layer 450 is formed by being laminated on the silicon substrate 402 on which the lower electrodes 410-1 to 410-748 are formed. That is, the light emitting layer 450 is laminated on the lower electrodes 410-1 to 410-748 in the portion where the lower electrodes 410-1 to 410-748 are formed. The light emitting layer 450 is laminated on the silicon substrate 402 in the portion where the lower electrodes 410-1 to 410-748 are not formed. In this embodiment, the light emitting layer 450 in the light emitting device 401 is formed so as to straddle all of the lower electrodes 410-1 to 410-748, but the embodiment is not limited to this. For example, the light emitting layer 450 may be formed so as to be separately laminated on each lower electrode in the same manner as the lower electrodes 410-1 to 410-748, or the lower electrodes 410-1 to 410-748 may be divided into a plurality of groups, and one light emitting layer may be laminated on the lower electrode belonging to each divided group.

[0036] For example, an organic material can be used for the light-emitting layer 450. The light-emitting layer 450, which is an organic EL film, is a laminated structure including functional layers such as an electron transport layer, a hole transport layer, an electron injection layer, a hole injection layer, an electron blocking layer, and a hole blocking layer. The light-emitting layer 450 may be made of an inorganic material having light-emitting properties other than an organic material.

[0037] An upper electrode 460 (anode) is laminated (second electrode layer) on the light emitting layer 450. The lower electrode 410, the light emitting layer 450, and the upper electrode 460 form a layered body. The upper electrode 460 is an electrode that can transmit (is transmissive to) light of the emission wavelength of the light emitting layer 450. For this reason, the upper electrode 460 of this embodiment employs a material containing indium tin oxide (ITO) as a transparent electrode. An indium tin oxide electrode has a transmittance of 80% or more for light in the visible light region, and is therefore suitable as an electrode for an organic EL device.

[0038] The upper electrode 460 is formed on the opposite side of the lower electrodes 410-1 to 410-748 with at least the light emitting layer 450 sandwiched therebetween. That is, in the Z direction, the light emitting layer 450 is disposed between the upper electrode 460 and the lower electrodes 410-1 to 410-748, and when the lower electrodes 410-1 to 410-748 are projected onto the upper electrode 460 in the Z direction, the region in which the lower electrodes 410-1 to 410-748 are formed falls within the region in which the upper electrode 460 is formed. Note that the transparent electrode does not have to be laminated over the entire light emitting layer 450, but in order to efficiently emit the light generated in the light emitting layer 450 to the outside of the light emitting device 401, it is preferable that the area occupied by the upper electrode 460 is 100% or more of the area occupied by one pixel, and more preferably 120% or more. The upper limit of the area occupied by the upper electrode 460 is arbitrarily designed depending on the areas of the silicon substrate 402 and the light emitting layer 450. Wiring may be provided in the upper electrode 460 other than the portion through which light passes.

[0039] The upper electrode 460 in this embodiment is an anode provided in common to each of the lower electrodes 410-1 to 410-748, but it may be provided individually for each of the lower electrodes 410-1 to 410-748, or one upper electrode may be provided for each set of lower electrodes.

[0040] The drive circuit controls the potential of each of the lower electrodes 410-1 to 410-748 based on image data in order to generate a potential difference between the upper electrode 460 and any one of the lower electrodes 410-1 to 410-748.

[0041] The light emitting device 401 in this embodiment is a so-called top emission type emission device. When a voltage is applied to the upper electrode 460, which is an anode, and the lower electrode 410, which is a cathode, and a potential difference is generated between the two, electrons flow from the cathode into the light emitting layer 450, and holes flow from the anode into the light emitting layer 450. Then, the electrons and holes are recombined in the light emitting layer 450, causing the light emitting layer 450 to emit light. When the light emitting layer 450 emits light, the light toward the upper electrode 460 passes through the upper electrode 460 and is emitted from the light emitting device 401 in the direction of arrow A shown in FIG. 5. In addition, the light from the light emitting layer 450 toward the lower electrode 410 is reflected by the lower electrode 410 toward the upper electrode 460, and the reflected light also passes through the upper electrode 460 and is emitted from the light emitting device 401. Although there is a time difference in the emission timing from the upper electrode 460 between the light emitted directly from the light emitting layer 450 toward the upper electrode 460 and the light reflected by each of the lower electrodes 410 and emitted from the upper electrode 460, the layers of the light emitting device 401 are extremely thin, so that the emission can be regarded as occurring almost simultaneously. Note that the light emitting device of this embodiment may be of a bottom emission type.

[0042] By using a transparent electrode such as indium tin oxide as the upper electrode 460, the aperture ratio, which indicates the light transmittance of the electrode, can be made substantially equal to the transmittance of the upper electrode 460. In other words, since there is substantially no portion other than the upper electrode 460 that attenuates or blocks light, the light emitted from the light-emitting layer 450 is attenuated as little as possible or becomes outgoing light without being blocked.

[0043] Furthermore, as described above, by forming the lower electrodes 410-1 to 410-748 using a highly accurate Si integrated circuit processing technique, the lower electrodes 410-1 to 410-748 can be arranged at a high density. Therefore, most of the area of ​​the light emitting region 604 (here, the total area of ​​the lower electrodes 410-1 to 410-748 and the area of ​​the region between adjacent lower electrodes) can be allocated to the lower electrodes 410-1 to 410-748. In other words, the exposure head has a high utilization efficiency of the light emitting region per unit area.

[0044] When a light-emitting material that is vulnerable to moisture, such as an organic EL layer or an inorganic EL layer, is used as the light-emitting layer 450, it is desirable to seal the light-emitting region 604 to prevent moisture from entering the region. As a sealing method, for example, a sealing film is formed by forming a single or laminated thin film of silicon oxide, silicon nitride, aluminum oxide, etc. As a method for forming the sealing film, a method that has excellent covering performance for structures such as steps is preferable, and for example, an atomic layer deposition method (ALD method) can be used. Note that the material, configuration, and forming method of the sealing film are merely examples, and are not limited to the above examples, and appropriate methods may be selected.

[0045] [Control Block] 6 shows a block diagram of the image controller unit 700 and the printed circuit board 202. Hereinafter, the chip select signal is designated as cs_x, the line synchronization signal as lsync_x, the clock signal as clk, and the image data signal as data. In the first embodiment, a single color process will be described for the sake of simplicity, but the same process is performed in parallel for four colors.

[0046] (Image controller) Image data generated by the scanner unit 100 is input to the image controller unit 700 as a processor that is at least one IC. The image controller unit 700 transmits a control signal for controlling the printed circuit board 202 to the printed circuit board 202 via a cable such as a flexible flat cable. The image data input to the image controller unit 700 may be data generated by the scanner unit 100 as described above, or may be data transferred from a personal computer via a network device (not shown). The control signals are a chip select signal cs_x indicating the effective range of the image data, a clock signal clk, an image data signal data, a line synchronization signal lsync_x indicating the division of each line of the image data, and a communication signal with the CPU 703. Each signal is transmitted to the light emitting device 401 in the printed circuit board 202 via a chip select signal line 705, a clock signal line 706, an image data signal line 707, a line synchronization signal line 708, and a communication signal line 709. The image controller unit 700 processes the image data and the print timing. The image data generating unit 701 performs dithering processing on image data received from the scanner unit 100 or from outside the image forming apparatus at a resolution instructed by the CPU 703 to generate image data for print output. In the first embodiment, the dithering processing is performed at a resolution of, for example, 1200 dpi.

[0047] The synchronization signal generating unit 704 generates a line synchronization signal lsync_x, which is a second signal. The CPU 703 instructs the synchronization signal generating unit 704 on the time interval of the signal period as one line period for a predetermined rotation speed of the photosensitive drum 102. Here, one line period is a period in which the surface of the photosensitive drum 102 moves by a pixel size of 1200 dpi (approximately 21.16 μm) in the rotation direction. For example, when printing is performed at a speed of 200 mm / s in the conveying direction of the recording paper, the CPU 703 instructs the synchronization signal generating unit 704 on the time interval as one line period of 105.8 μs (two decimal places and below are omitted). The speed in the conveying direction is calculated by the CPU 703 using a set value (fixed value) of the printing speed (image forming speed) set in a control unit (not shown) that controls the speed of the photosensitive drum 102. The printing speed is set, for example, according to the type of recording paper.

[0048] The chip data conversion unit 702 divides one line of image data for each light emitting device 401 in synchronization with a line synchronization signal lsync_x generated by a synchronization signal generation unit 704. The chip data conversion unit 702 transmits the image data divided for each light emitting device 401 together with a clock signal clk and a chip select signal cs_x to the printed circuit board 202. The clock signal clk is a signal that serves as a reference for control.

[0049] (Printed circuit board) Next, the configuration of the printed circuit board 202 will be described. The head information storage unit 710 is a storage device that stores head information such as the amount of light emitted by each light emitting device 401 and mounting position information, and is connected to the CPU 703 via a communication signal line 709. A clock signal line 706, an image data signal line 707, a line synchronization signal line 708, and a communication signal line 709 extending from the image controller 700 are branched and connected to each of the light emitting devices 401. A chip select signal line 705 for transmitting a chip select signal extending from the image controller 700 is connected to the light emitting device 401-1. In addition, the output of the light emitting device 401-1 is connected to the input of the light emitting device 401-2 via a signal line 711-1, and the output of the light emitting device 401-2 is connected to the input of the light emitting device 401-3 via a signal line 711-2. In this way, the chip select signal line 705 (or the signal line 711) is connected in a so-called daisy chain (cascade connection) via each light emitting device 401. Each light emitting device 401 controls the voltage of the lower electrode of the light emitting device 401 based on the set values ​​set by the chip select signal line 705, the clock signal line 706, the line synchronization signal line 708, the image data signal line 707, and the communication signal line 709. In addition, each light emitting device 401-n generates a chip select signal for the next (backward) light emitting device 401-n+1.

[0050] [Circuit configuration inside the light-emitting device] FIG. 7(a) shows a circuit block diagram in the light emitting device 401. The circuit section 602 in the light emitting device 401 has a digital section 800 and an analog section 806. The digital section 800 has a function of generating a pulse signal for driving the lower electrode 410-n based on a set value previously set by a communication signal and various signals in synchronization with a clock signal clk, and transmitting the generated pulse signal to the analog section 806 via a pulse signal line 907. Here, the various signals refer to a chip select signal cs_x, an image data signal data, and a line synchronization signal lsync_x. The digital section 800 also has a function of generating a chip select signal for the next light emitting device 401 from the input chip select signal cs_x.

[0051] [Digital Department] The communication IF unit 801 controls writing and reading of setting values ​​to the register unit 802 based on a communication signal from the CPU 703. The register unit 802 stores setting values ​​(preset setting values) required for operation. The setting values ​​include exposure timing information used in the data storage unit 804, width and phase information of a pulse signal generated by the pulse signal generation unit 805, setting information of a driving voltage set by the analog unit 806, and the like. Note that since the driving voltage can be derived from the resistance value between the lower electrode and the upper electrode, and the range of this resistance value is known in advance, information on the driving current may be stored instead of the setting information of the driving voltage. The register unit 802 stores at least one of these pieces of information. The chip select signal generation unit 803, which is a first generation unit, delays the chip select signal cs_x, which is the first signal input, generates a chip select signal for the next light emitting device 401, and transmits it via the signal line 711. The chip select signal is an enable signal that allows the light emitting device 401 to sample image data. The data storage unit 804 receives and holds image data output by the image controller 700 via a data signal line 707 while the input chip select signal cs_x is valid, and outputs the image data to a pulse signal generation unit 805 in synchronization with a line synchronization signal lsync_x. Details will be described later.

[0052] The pulse signal generating unit 805 generates a pulse signal based on the width information and phase information of the pulse signal set in the register unit 802 in accordance with the image data input from the data storage unit 804, and outputs the pulse signal to the analog unit 806. Details will be described later. The analog unit 806 generates a signal required to drive the lower electrode based on the pulse signal generated in the digital unit 800. Details will be described later.

[0053] (Image data storage section) Next, the operation of the data storage unit 804 will be described. The data storage unit 804 of the first embodiment is built into the light emitting device 401. An example will be described in which the chip select signal cs_x and the line synchronization signal lsync_x are negative logic signals, but they may be positive logic. FIG. 7(b) is a circuit configuration diagram of the data storage unit 804. The clock gate circuit 810 outputs the logical product of the inverted signal of the chip select signal cs_x and the clock signal clk. The clock gate circuit 810 outputs the clock signal s_clk to the flip-flop circuit 811 only when the chip select signal cs_x is valid.

[0054] The flip-flop circuit 811 receives the image data signal data input to the data storage unit 804 as the original input. The flip-flop circuits 811 are connected in series in the same number as the number of lower electrodes 410 provided in the longitudinal direction of the light emitting device 401 (748 in the first embodiment), forming a shift register. The flip-flop circuit 811 operates in response to a clock signal s_clk sent from the clock gate circuit 810. Specifically, the top flip-flop circuit 811 of the shift register samples the image data output by the image controller 700 in response to the clock signal s_clk, and each flip-flop circuit 811 shifts the sampled image data to the flip-flop circuit in the subsequent stage. The flip-flop circuits 811 and the flip-flop circuits 812 are provided in the longitudinal direction of the lower electrodes 410 in the same number as the number of lower electrodes 410 (748 in the first embodiment).

[0055] A flip-flop circuit 812 serving as a register receives the output of the flip-flop circuit 811 and operates in response to the line synchronization signal lsync_x. The output of the flip-flop circuit 812 is output to the pulse signal generating unit 805 as image data buf_data_0_000 to buf_data_0_747.

[0056] FIG. 8 is a timing chart showing the operation of the data storage unit 804 in the longitudinal direction of the light emitting device 401. In FIG. 8, (i) shows the waveform of the clock signal clk, (ii) shows the waveform of the line synchronization signal lsync_x, (iii) shows the waveform of the chip select signal cs_x, and (iv) shows the image data signal data as 000 to 747. Here, "000" indicates image data corresponding to the lower electrode 410-1, for example, and "747" indicates image data corresponding to the lower electrodes 410-748. The shaded portion of the image data signal data indicates data that is invalid as image data. (v) indicates image data dly_data_000, etc., which is the output of the flip-flop circuit 811, and (vi) indicates image data buf_data_0_000, etc., which is the output of the flip-flop circuit 812.

[0057] During the period from time T0 to time T1 when the chip select signal cs_x is 0 (cs_x=0 (low level)), the image data is shifted through the serially connected flip-flop circuits 811 as follows. Time T1 is the time when cs_x=0 is captured by the rising edge of the clock signal clk. That is, the image data is shifted in the order of data → dly_data_000 → dly_data_001 → ... → dly_data_747. During the period when the chip select signal cs_x is at low level (cs_x=0), the clock signals clk are input in the same number as the number of bottom electrodes 410 in the longitudinal direction of the light emitting device 401, that is, 748. In this way, image data for one line is held in dly_data_000 to dly_data_747.

[0058] After time T1, the chip select signal cs_x is 1 (cs_x=1 (high level)), so no shift operation is performed and the image data at time T1 is held. For example, the image data dly_data_000 held in the first flip-flop circuit 811 after time T1 is 747. When the line synchronization signal lsync_x becomes 0 (lsync_x=0 (low level)) at time T2, one line's worth of image data is simultaneously output to the pulse signal generating unit 805 as buf_data_0_000 to buf_data_0_747. Time T2 is the time when lsync_x=0 is captured by the rising edge of the clock signal clk. That is, the image data dly_data_000 etc. held in the flip-flop circuit 811 are output to the pulse signal generating unit 805 as image data buf_data_0_000 etc. via the flip-flop circuit 812.

[0059] (Pulse signal generation section) The pulse signal generating unit 805 will be described. When the number of lower electrodes 410 is n, there are also n pulse signal generating units 805, the same number as the number of lower electrodes 410. In the first embodiment, pulse signal generating units 805-1 to 805-748 are provided for lower electrodes 410-1 to 410-748. Note that the pulse signal generating units 805 provided for each lower electrode 410 have the same structure. Therefore, pulse signal generating unit 805-1 will be described as an example here.

[0060] 9(a) shows a block diagram of the pulse signal generating unit 805-1. The pulse signal generating unit 805-1 has a pulse width selecting unit 901, an output determining unit 903, and a counter unit 904. The pulse width selecting unit 901 converts image data input from the data storage unit 804 into a pulse width b in accordance with a pulse width table of a pulse signal set by the register unit 802. Table 1 shows the pulse width table which is a conversion table for converting image data into a pulse width b.

[0061] [Table 1] In Table 1, the first column shows image data, and the second column shows the pulse width b of the pulse signal corresponding to the image data. For example, the image data is 4 bits ([3:0]) (0 to 15).

[0062] For example, when the input of image data is 2, the pulse width selection unit 901 (pulse width determination unit) outputs the pulse width b to the output determination unit 903 as 8 based on the pulse width Table of Table 1 set by the register unit 802. However, the pulse width Table shown in Table 1 is only an example, and the bit width of the image data and the pulse width may be different from the example of Table 1, and the value of the pulse width b may also be set arbitrarily. The pulse width table stored in the register unit 802 may be set individually for each lower electrode 410, or may be common.

[0063] The light emitting layers 450 corresponding to the lower electrodes 410 may have different light quantities even when the pulse signal has the same pulse width due to process variations. The variation in the light quantity for each of the light emitting layers 450 corresponding to the lower electrodes 410-1 to 410-748 causes unevenness in the electrostatic latent image formed on the photosensitive drum 102, resulting in unevenness in the printed image. In order to eliminate the unevenness in the electrostatic latent image, the pulse width of the output pulse signal is changed so that an image with a dot width suited to the input image data is formed by setting a pulse width table for each of the lower electrodes 410-1 to 410-748 according to the measured light quantity. By setting the pulse width table for each of the lower electrodes 410-1 to 410-748 through the above control, it is possible to correct the unevenness in the printed image caused by the variation in the light quantity for each of the light emitting layers 450 corresponding to the lower electrodes 410-1 to 410-748. The light amount of the light emitting layers 450 corresponding to the lower electrodes 410-1 to 410-748 is measured in a factory or by installing a light amount measuring device (not shown) at a position opposite the exposure head .

[0064] The counter unit 904 counts the clock signal clk input from the image controller 700 via the clock signal line 706, and resets the count to 1 for each period c of the line synchronization signal lsync_x (hereinafter referred to as the line synchronization signal period) (timing C-1 and timing C-2 in FIG. 9B). The line synchronization signal period is shown as timing C-1 and C-2 in FIG. 9B, which will be described later. The output of the counter unit 904 is represented as count, and the count is input to the output determination unit 903. In the first embodiment, the count is set to 1 by resetting, but it does not have to be 1. In the first embodiment, the count method of the clock signal clk is up-counting, but it may be down-counting. The counter unit 904 may be provided for each pulse signal generation unit 805 corresponding to each lower electrode 410, or may be shared.

[0065] The operation of the output determination unit 903 will be described with reference to Fig. 9(b). In Fig. 9(b), (i) shows the waveform of the clock signal clk, (ii) shows the waveform of the line synchronization signal lsync_x, (iii) shows the value of count which is the output of the counter unit 904, and (iv) shows the waveform of the pulse signal generated by the pulse signal generation unit 805.

[0066] The output determination unit 903 generates a pulse signal according to the count input from the counter unit 904 and the pulse width b output from the pulse width selection unit 901. The output determination unit 903 sets the output pulse signal to a high level at the timing when the line synchronization signal lsync_x is at a low level at the rising edge of the clock signal clk (timings C-1 and C-2). The output determination unit 903 then sets the output pulse signal to a low level at the timing when the count matches the pulse width b at the rising edge of the clock signal clk (timing B). In this way, the output determination unit 903 generates a pulse signal.

[0067] [Digital section modification] The clock signal clk and line synchronization signal lsync_x used in the pulse signal generating unit 805 may be as follows. For example, they may be generated individually by the image controller unit 700 and input to the pulse signal generating unit 805 via a pulse generation clock signal line 910 and a pulse generation line synchronization signal line 912 as shown in Fig. 10. However, as shown in Fig. 7(a), by using a clock signal line 706 and a line synchronization signal line 708 for inputting the clock signal clk and the line synchronization signal lsync_s used in the pulse signal generating unit 805, it is possible to reduce the wiring on the printed circuit board 202.

[0068] [Analog section] 11(a) shows a block diagram of the analog unit 806. In the first embodiment, for the sake of simplicity, the driving units 1001-1 and 1001-2 that drive the two lower electrodes 410-1 and 410-2 in the lower electrodes 410-1 to 410-748 are illustrated and described. However, it is assumed that similar driving units 1001-3 to 1001-748 are formed corresponding to the lower electrodes 410-3 to 410-748. Also, as described above, it is the light emitting layer 450 in the regions corresponding to the lower electrodes 410-1 and 410-2 that actually emits light by driving the lower electrodes 410-1 and 410-2.

[0069] The pulse signal generating units 805-1 and 805-2 generate pulse signals that control the emission (ON) timing of the lower electrodes 410-1 and 410-2. The pulse signal generating units 805-1 and 805-2 input the pulse signals to the driving units 1001-1 and 1001-2 via the pulse signal lines 907-1 and 907-2.

[0070] A digital-to-analog converter (hereinafter, referred to as DAC) 1002 supplies an analog voltage for determining a drive current to the drivers 1001-1 and 1001-2 via a signal line 1003 based on the data set in the register unit 802. That is, the digital-to-analog converter 1002 functions as a voltage generating unit for generating a drive voltage to be applied to the lower electrodes 410-3 to 410-748. A driver selecting unit 1007 supplies a driver selecting signal for selecting the drivers 1001-1 and 1001-2 to the drivers 1001-1 and 1001-2 via signal lines 1004 and 1005 based on the data set in the register unit 802. The driver selecting signal is generated so that only the signal connected to the selected driver 1001 is at a high level. For example, when the driver 1001-1 is selected, a high-level driver select signal is supplied only to the signal line 1004, and a low-level driver select signal is supplied to signal lines 1005 and the like connected to other drivers 1001-2 and the like. In the first embodiment, the driver select signal is positive logic, but it may be negative logic.

[0071] The analog voltage input via the signal line 1003 is set for each of the drivers 1001-1 and 1001-2 at the timing selected by the driver selection unit 1007 (the timing when the driver selection signal becomes high level). The CPU 703 sequentially selects the drivers 1001-1 and 1001-2 via the register unit 802, and sets a voltage corresponding to the selected driver 1001-1 and 1001-2. In this way, the CPU 703 sets analog voltages (drive voltages) for all the drivers 1001 using one DAC 1002. By the above-mentioned operation, the analog voltage and pulse signal that determine the drive current are input to the drivers 1001-1 and 1001-2, and voltages are applied independently to the lower electrodes 410-1 and 410-2 by the drive circuits described below.

[0072] (Drive unit) 11(b) shows the circuit of the driver 1001-1 that drives the lower electrode 410-1. The driver 1001 for the other lower electrodes is also driven by a similar circuit. A MOS field effect transistor (hereinafter referred to as MOSFET) 1102 supplies a drive current to the lower electrode 410-1 according to the gate voltage value, and controls the current so that the drive current is turned off (light is turned off) when the gate voltage is at a low level.

[0073] A pulse signal line 907-1 is connected to the gate terminal of the MOSFET 1104, and when the pulse signal is at a high level, the voltage charged in the capacitor 1106 is transferred to the MOSFET 1102. A drive unit select signal (transmitted from a signal line 1004) sent from the drive unit selection unit 1007 is connected to the gate terminal of the MOSFET 1107. When the received drive unit select signal is at a high level, the MOSFET 1107 turns on and charges the analog voltage (transmitted from a signal line 1003) output from the DAC 1002 to the capacitor 1106. In the first embodiment, the DAC 1002 sets an analog voltage in the capacitor 1106 at a timing before image formation, and keeps the MOSFET 1107 in an off state during the image formation period, thereby maintaining the voltage level.

[0074] Through this operation, MOSFET 1102 supplies a drive current to lower electrode 410 in response to the set analog voltage and pulse signal. If the input capacitance of lower electrode 410-1 is large and the response speed when turned off is slow, it is possible to speed up the turn-off speed by using MOSFET 1103. A signal obtained by logically inverting a pulse signal by inverter 1105 is input to the gate terminal of MOSFET 1103. When the pulse signal is at a low level, the gate terminal of MOSFET 1103 becomes a high level, and the charge stored in the input capacitance of lower electrode 410-1 is forcibly discharged.

[0075] As described above, in the first embodiment, the light emitting region 604 and the circuit unit 602 are provided in the same silicon substrate 402. This makes it possible to suppress the costs for wire bonding and the area of ​​the wiring substrate, while providing a drive signal generating circuit for each lower electrode and controlling the pulse width of the pulse signal and the light emission timing in minute time units.

[0076] As described above, according to the first embodiment, the costs for wire bonding and the area of ​​the wiring board can be reduced. EXAMPLES

[0077] [Pulse signal generation section] In the second embodiment, the configuration of the entire image forming apparatus, the configuration of the exposure head 106, and the configuration of the silicon substrate 402 are the same as those in the first embodiment. Since the difference from the first embodiment is the configuration of the pulse signal generating unit 805, the difference from the first embodiment in the pulse signal generating unit 805 will be described. When the number of lower electrodes 410 is n, there are also n pulse signal generating units 805, the same number as the number of lower electrodes 410, but the structure of the pulse signal generating units 805 for each lower electrode 410 is the same. Therefore, the pulse signal generating unit 805-1 will be described here as an example.

[0078] FIG. 12(a) shows a block diagram of the pulse signal generating unit 805-1 of the second embodiment. The difference from the pulse signal generating unit 805-1 shown in FIG. 9(a) of the first embodiment is that a pulse delay time a, which is a first time transmitted from the register unit 802, is provided at the input. The counter unit 904 of the second embodiment has a pulse delay time counter 1201 and a pulse width counter 1203. The output of the pulse delay time counter 1201 is count_a, and the output of the pulse width counter 1203 is count_b. The operation of the counter unit 904 and the output determining unit 903 will be described with reference to FIG. 12(b). Here, (i), (ii), and (v) of FIG. 12(b) are graphs similar to (i), (ii), and (iv) of FIG. 9(b), and the description thereof will be omitted. (iii) of FIG. 12(b) shows the value of count_a, which is the output of the pulse delay time counter 1201, and (iv) shows the value of count_b, which is the output of the pulse width counter 1203.

[0079] The pulse delay time counter 1201 receives the clock signal clk and the line synchronization signal lsync_x as inputs. The pulse delay time counter 1201 counts the clock signal clk and resets the count to 1 at the timing when the line synchronization signal lsync_x is at a low level at the rising edge of the clock signal clk (timings C-1 and C-2).

[0080] The pulse width counter 1203 receives the clock signal clk, count_a, and pulse delay time a as input. The pulse width counter 1203 counts the clock signal clk, and resets the count to 1 at the timing (timing A) when count_a coincides with the pulse delay time a at the rising edge of the clock signal clk. The counter unit 904 outputs count_a and count_b to the output determination unit 903.

[0081] The output determining unit 903 sets the pulse signal to high level at the timing (timing A) when count_a coincides with the pulse delay time a at the rising edge of the clock signal clk. On the other hand, the output determining unit 903 sets the pulse signal to low level at the timing (timing B) when count_b coincides with the pulse width b at the rising edge of the clock signal clk. In this way, the output determining unit 903 generates a pulse signal delayed according to the pulse delay time a.

[0082] The pulse delay time a can be changed in units of the cycle of the clock signal clk (hereinafter, referred to as the clock signal cycle) by rewriting the memory of the register unit 802. In the second embodiment, the values ​​of count_a and count_b are set to 1 by resetting, but they do not have to be 1. In the second embodiment, the counting method of the clock signal clk is up-counting, but it may be down-counting. Furthermore, although the counter unit 904 has two counters, the number of counters does not have to be two. For example, one counter may perform the operations of the pulse delay time counter 1201 and the pulse width counter 1203.

[0083] [Light emission timing control according to the position of the light emitting device] Using the configuration of the second embodiment, a method for controlling the light emission timing according to the position of the light emitting device 401 on the printed circuit board 202 will be described. When the light emitting devices 401-1 to 401-20 are arranged in a staggered pattern on the printed circuit board 202, there are cases where the light emitting devices 401-1 to 401-20 are shifted from their original mounting positions due to the influence of mounting accuracy. Therefore, the positions of the lower electrodes 410 may differ from each other in the short direction of the light emitting device 401. If the position of the lower electrode 410 is shifted, a shift occurs on the printed image, so that it is necessary to correct the light emission timing according to the position of the lower electrode 410. Hereinafter, a method for correcting the light emission timing according to the position of the lower electrode 410 will be described. Since the light emission timing correction performed in each of the light emitting devices 401-1 to 401-20 is the same, the light emitting device 401-1 will be taken as an example for description.

[0084] FIG. 13(a) shows a part of an enlarged view of the lower electrode mounting surface of the printed circuit board 202. After the light emitting device 401-1 is mounted on the printed circuit board 202, the following values ​​are measured. That is, the position y1, which is the first distance, and the position y748, which is the second distance, are measured relative to a reference position (hereinafter referred to as the reference position) of the lower electrode 410-1 at one end of the light emitting device 401-1 and the lower electrode 410-748 at the other end. The measured positions y1 and y748 are stored as position data in the head information storage unit 710. The reference position (hereinafter referred to as the reference position) of the positions y1 and y748 is set to, for example, the most upstream position in the rotation direction of the photosensitive drum 102 where the lower electrode 410 is arranged when the light emitting devices 401-1 to 401-20 are mounted. In the second embodiment, the position of the lower electrode 410-748 at the right end of the light emitting device 401-5 in FIG. 13(a) is set to the reference position indicated by the dashed line.

[0085] The CPU 703 reads information on the positions y1 and y748 of the lower electrodes 410-1 and 410-748 at both ends of the light-emitting device 401-1 from the head information storage unit 710, and calculates the correction amount for each lower electrode 410. For example, the position ym, which is the third distance of the m-th lower electrode 410-m from the left end of the light-emitting device 401-1 in FIG. 13(a), can be obtained by the following formula (1). ym=y1+(m-1)(y748-y1) / 747 Formula (1)

[0086] Note that positions y1 to y748 of all lower electrodes 410 in light emitting device 401-1 relative to the reference position may be measured and stored in head information storage unit 710 as correction amounts for each lower electrode 410. Furthermore, the positions of both ends or all of lower electrodes 410 of light emitting device 401 may be measured at a factory or after exposure head 106 is attached to an image forming apparatus.

[0087] The CPU 703 divides the correction amount for each lower electrode 410 into an amount for one line unit in the short-side direction of the light-emitting device 401 and an amount less than one line. Here, the amount for one line unit among the obtained correction amounts is set as a correction amount p to be corrected by the image controller unit 700, and the amount less than one line is set as a correction amount q to be corrected by the pulse signal generating unit 805. For example, a case will be described in which the CPU 703 obtains the correction amount of a certain lower electrode 410 as 110.8 μm. Here, when the resolution of the light-emitting device 401 in the short-side direction is 1200 dpi, 105.8 μm, which corresponds to 5 lines out of the correction amount of 110.8 μm, is set as a correction amount p to be corrected by the image controller unit 700 (p=105.8 μm). That is, the correction amount p is an integer (=1, 2, . . .) times (for example, 5 times) an amount (for example, 105.8 μm) corresponding to the first resolution (for example, 1200 dpi) (for example, 21.16 μm). Further, 5 μm, which is an amount less than one line (an amount less than the amount corresponding to the first resolution) out of the correction amount 110.8 μm, is set as the correction amount q to be corrected in the pulse signal generating section 805 (q=5 μm).

[0088] The image controller unit 700 generates a read timing signal for image data according to the correction amount p of each lower electrode 410 in the CPU 703, and outputs the signal to the chip data converter 702 via a signal line 709. The chip data converter 702 delays the image data by one line in accordance with the read timing signal and outputs the image data.

[0089] The output timing control of image data according to the correction amount p performed by the image controller unit 700 will be described with reference to FIG. 13(b). The image controller unit 700 stores image data generated by the image data generation unit 701 for multiple lines in a storage unit (not shown). FIG. 13(b) is a diagram showing image data stored in the storage unit. The left and right of FIG. 13(b) indicate the longitudinal direction of the light emitting device 401. In FIG. 13(b), each rectangular block represents image data for each pixel stored in the storage unit, and colored blocks represent image data to be output. For example, the second from the left (lower electrode 410-2) has a correction amount p of 1, and one line is corrected by the image controller unit 700, and image data is output to the first colored line.

[0090] When the correction amount p of a certain lower electrode 410 in the longitudinal direction of the light emitting device 401 is n lines, the CPU 703 generates a read timing signal to output image data of the nth line in FIG. 13(b) delayed by n lines. The chip data conversion unit 702 reads and outputs image data (colored blocks in FIG. 13(b)) according to the read timing signal. This makes it possible to output image data of lines according to the correction amount p for each lower electrode 410 as shown in FIG. 13(b). However, although the image data held in the storage unit (not shown) is 5 lines (0 to 4 lines) as an example in FIG. 13(b), it is not limited to 5 lines. As described above, the image controller unit 700 functions as a correction unit.

[0091] The pulse signal generating unit 805 performs the correction by delaying the light emission timing according to the correction amount q of each lower electrode 410. When converting the correction amount q in the pulse signal generating unit 805 into a delay time of the light emission timing, the CPU 703 calculates the delay time using formula (2). Delay time = (correction amount q / photosensitive drum surface speed) / clock signal period Equation (2) The CPU 703 obtains the delay time for each lower electrode 410 and stores it as a pulse delay time a in the register unit 802. The pulse signal generating unit 805 generates a pulse signal having a light emission timing according to the pulse delay time a stored in the register unit 802, thereby correcting the difference (positional deviation during mounting) from the reference position for each lower electrode 410 with an accuracy of the clock signal period x the photosensitive drum surface speed.

[0092] As an example, a method for correcting the positions of lower electrodes 410-i and lower electrodes 410-j in a certain light-emitting device 401 shown in Fig. 14(a) will be described. However, the number of lower electrodes in the light-emitting device 401 is omitted in Fig. 14(a). The resolution in the short direction of the light-emitting device 401 is 1200 dpi (approximately 21.16 µm), and the surface speed of the photosensitive drum 102 is 200 mm / s. In addition, the line synchronization signal period is c, the clock signal frequency is 40 MHz, and the pulse width of the pulse signal corresponding to each lower electrode 410 is b.

[0093] (Lower electrode 410-i) The position yi of the lower electrode 410-i with respect to the reference position is set to 4 μm. In this case, the correction amount q in the pulse signal generating unit 805-i is 4 μm, and the pulse delay time a is calculated to be 800 clk from the formula (2). The pulse signal generating unit 805-i generates a pulse signal represented by the timing chart of FIG. 14(b). Here, (i) to (v) in FIG. 14(b) are the same as (i) to (v) in FIG. 12(b), and the description will be omitted.

[0094] (Lower electrode 410-j) Similarly, the position yj of the lower electrode 410-j relative to the reference position is set to 23.16 μm. The correction amount 23.16 μm is divided into a correction amount p (1 line) and a correction amount q (=2 μm=23.16 μm-21.16 μm). In this case, if the pulse signal generating unit 805 performs a light emission timing correction corresponding to 23.16 μm, the pulse delay time a becomes larger than the line synchronization signal period, and a correct pulse signal is not output. Therefore, the correction amount p for one line unit in the short side direction of the light emitting device 401, which is 21.16 μm for one line, is corrected in the image controller unit 700. As a result, the correction amount q in the pulse signal generating unit 805 becomes 2 μm, and the pulse delay time a is calculated to be 400 clk from the formula (2). The pulse signal generating unit 805-j generates a pulse signal represented by the timing chart in FIG. 14(c). Here, (i) to (v) in FIG. 14(c) are similar to (i) to (v) in FIG. 12(b), and the description thereof will be omitted.

[0095] In addition, not only the mounting positions of the light emitting devices 401-1 to 401-20, but also the mounting position of the exposure head 106 may be measured, calculated, and corrected in the same manner. The measurements and calculations may be performed at a factory or in the image forming apparatus body. The above-mentioned control regarding the correction according to each lower electrode 410 may be performed for each lower electrode 410, or may be performed for a group of several lower electrodes 410. Furthermore, the variation in the amount of light emitted by the light emitting layer 450 corresponding to each lower electrode 410 may be corrected by a pulse signal (light emission timing signal) generated by the pulse signal generating unit 805. As described above, the image controller unit 700 performs correction in units of one line according to the position of each lower electrode 410, and the pulse signal generating unit 805 performs correction in units of less than one line. This allows the misalignment of the printed image due to the position of each lower electrode 410 to be corrected with an accuracy of the clock signal period x the photosensitive drum surface speed.

[0096] As described above, according to the second embodiment, the costs for wire bonding and the area of ​​the wiring board can be reduced. EXAMPLES

[0097] Example 3 differs from Example 1 in the configuration of the exposure head 106 and the configuration of the silicon substrate 1502. In particular, Example 3 differs from Example 1 in the arrangement of the lower electrodes, and the configuration of the drive circuit provided on the silicon substrate of the lower electrodes differs partially from Examples 1 and 2. Below, the example will be described focusing on the differences from Examples 1 and 2.

[0098] [Configuration of the light-emitting device group] 15 is a diagram showing the state of the boundary between chips of light emitting devices 1501 arranged in two rows in the longitudinal direction, and the arrangement of electrodes. Each light emitting device 1501 of this embodiment has two rows of lower electrodes arranged along the longitudinal direction. The distance between adjacent lower electrodes is the same as in Example 1.

[0099] [Light-emitting area configuration] The light emitting device 1501 will be described in more detail with reference to FIG. 16. The X direction in FIG. 16 indicates the longitudinal direction of the exposure head 106. The Z direction is the direction in which each layer of the layer structure described later overlaps (lamination direction). FIG. 16(a) is an enlarged view of a main part of the schematic diagram of the AA cross section in FIG. 4. FIG. 16(a) is a schematic diagram of lower electrodes 410-1 to 410-748 described later as viewed from the Y direction. As shown in FIG. 16(a) and FIG. 16(c), the light emitting device 1501 includes a silicon substrate 1502, lower electrodes 410-1 to 410-748, lower electrodes 420-1 to 420-748, a light emitting layer 450, and an upper electrode 460. The silicon substrate 1502 is a driving substrate on which driving circuits including driving units corresponding to the lower electrodes 410-1 to 410-748 described later are formed in the manufacturing process.

[0100] The lower electrodes 410-1 to 410-748 (cathodes) shown in FIGS. 16(a) and 16(c) correspond to the lower electrodes shown in FIG. 5, and therefore a description thereof will be omitted.

[0101] 16, light emitting device 1501 of this embodiment includes lower electrodes 420-1 to 420-748 in addition to lower electrodes 410-1 to 410-748. Lower electrodes 420-1 to 420-748 are a plurality of electrodes formed in layers (first electrode layer) on silicon substrate 1502, similar to lower electrodes 410-1 to 410-748. Lower electrodes 420-1 to 420-748 form a second electrode row. That is, light emitting device 1501 includes lower electrodes that are two-dimensionally arranged. The size, shape, and arrangement in the X direction of lower electrodes 420-1 to 420-748 are similar to those of lower electrodes 410-1 to 410-748, and therefore description thereof will be omitted.

[0102] The lower electrodes 420-1 to 420-748 (second electrode row) are arranged at a distance d from the lower electrodes 410-1 to 410-748 (first electrode row) in the Y direction. The lower electrode 420-1 is arranged adjacent to the lower electrode 410-1 in the Y direction, and similarly, the lower electrodes 420-2 to 420-748 are arranged adjacent to the lower electrodes 410-2 to 410-748, respectively. Note that, as in this embodiment, it is not necessarily required to design the distance between the lower electrodes in the X direction and the distance between the lower electrodes in the Y direction to be equal, but it is desirable to design the distance between the lower electrodes in both directions to be equal in order to efficiently arrange the lower electrodes within a predetermined area. In addition, in this embodiment, a light emitting device having two electrode rows is illustrated as an example for the sake of simplicity of explanation, but the number of electrode rows may be any number of rows, such as three or more, as shown in FIG. 16(d). For example, similarly to the above, lower electrodes 430-1 to 430-748 may be arranged adjacent to lower electrodes 420-1 to 420-748, respectively, and further, lower electrodes 440-1 to 440-748 may be arranged adjacent to lower electrodes 430-1 to 430-748. In the following, for ease of explanation, the explanation will be given taking light emitting device 1501 having lower electrodes 410-1 to 410-748 and lower electrodes 420-1 to 420-748 as an example.

[0103] When the lower electrode 410-1 and the lower electrode 420-1 are driven simultaneously, the distance between the central positions exposed by driving both electrodes on the photosensitive drum 102 is shifted by W+d in the rotation direction of the photosensitive drum 102. The image forming apparatus of this embodiment exposes an area corresponding to one pixel in the output resolution of the image forming apparatus by driving a plurality of lower electrodes (e.g., the lower electrode 410-1 and the lower electrode 420-1) adjacent in the rotation direction of the photosensitive drum 102. Therefore, by providing a time difference between the timing of voltage application to the lower electrode 410-1 and the timing of voltage application to the lower electrode 420-1 according to the rotation speed of the photosensitive drum 102, the area corresponding to one pixel can be exposed multiple times (multiple exposure).

[0104] Next, light emitting layer 450 in this embodiment will be described. Light emitting layer 450 is formed by being laminated on silicon substrate 1502 on which lower electrodes 410-1 to 410-748 and lower electrodes 420-1 to 420-748 are formed. That is, light emitting layer 450 is laminated on lower electrodes 410-1 to 410-748 and lower electrodes 420-1 to 420-748 in the portions where lower electrodes 410-1 to 410-748 and lower electrodes 420-1 to 420-748 are formed. Light emitting layer 450 is laminated on silicon substrate 1502 in the portions where lower electrodes 410-1 to 410-748 and lower electrodes 420-1 to 420-748 are not formed. In this embodiment, in light emitting device 1501, light emitting layer 450 is formed so as to extend across all of lower electrodes 410-1 to 410-748 and lower electrodes 420-1 to 420-748, but the embodiment is not limited to this. For example, light emitting layer 450 may be formed so as to be separated and laminated on each lower electrode, similar to lower electrodes 410-1 to 410-748 and lower electrodes 420-1 to 420-748, or lower electrodes 410-1 to 410-748 and lower electrodes 420-1 to 420-748 may be divided into a plurality of groups, and one light emitting layer may be laminated on the lower electrode belonging to each divided group.

[0105] [Exposure area shape of multiple exposures] FIG. 17 shows the positional relationship of the exposure area (spot) during multiple exposure. FIG. 17 shows the exposure area on the exposure head 106 exposed by driving the lower electrode 410-n (n is a natural number of 1≦n≦748) and the lower electrode 420-n adjacent thereto in the Y direction. That is, FIG. 17 shows the exposure area of ​​two lower electrodes 410-n and lower electrode 420-n arranged in the Y direction for the n-th lower electrode among the 748 lower electrodes arranged in the X direction. When a voltage for making the light-emitting layer 450 emit light is applied to the lower electrode 410-n and the lower electrode 420-n in the Y direction of the silicon substrate 1502 at substantially the same time, the exposure area corresponding to the lower electrode 410-n and the exposure area corresponding to the lower electrode 420-n are at different positions in the Y direction as shown in FIG. 17(a). The position of each exposure area is the same as the arrangement relationship between the lower electrode 410-n and the lower electrode 420-n in the Y direction. In other words, the center-to-center distance between the exposure regions in the Y direction is W (μm)+d (μm).

[0106] 17(b) shows the state of the exposure area when the timing of applying electric charge to the lower electrode 420-n arranged so as to expose the downstream side of the lower electrode 410-n in the rotation direction of the photosensitive drum 102 (hereinafter referred to as the lighting timing) is delayed according to equation (3) in accordance with the rotation direction and rotation speed Vdr (mm / s) of the photosensitive drum 102. The timing T at which the positions of the exposure areas formed on the photosensitive drum 102 coincide is controlled based on the delay time Tdelay calculated by equation (3). Tdelay = ((W + d) ÷ 1000) ÷ Vdr Equation (3) In this embodiment, the light emission signal is generated so that the maximum light emission time Tw of each lower electrode corresponding to each pixel is equal to the time corresponding to the interval of one line in the Y direction, and is expressed by equation (4) using the resolution (e.g., 1200 dpi) and the rotation speed Vdr. Tw=(25.4÷1200)÷Vdr Formula (4) The multiple exposure enables exposure at approximately the same position on the photosensitive drum 102 using the lower electrode 410-n and the lower electrode 420-n, and the amount of light received by the photosensitive drum 102 can be increased in proportion to the number of lower electrodes arranged in the Y direction. Note that, in order to maintain such an effect, it is preferable that the positional deviation of the exposure areas on the photosensitive drum 102 of the lower electrodes subjected to multiple exposure is small.

[0107] Figure 17(c) shows an example in which the positions of the exposure areas on the photosensitive drum 102 are misaligned in multiple exposure. In this example, the two exposure areas produced by multiple exposure do not completely overlap, but do partially overlap. Ideally, it is preferable for the two exposure areas to approximately match (completely overlap) as in Figure 17(b), because this results in sharp dots. However, even if the exposure areas partially overlap as in Figure 17(c), the required density can be obtained, although the sharpness of the dots is degraded compared to Figure 17(b).

[0108] For this reason, the light emission timing is controlled within the allowable error ΔT of the light emission timing so that the time Tdelay falls within the range of equation (5) for the size Ws (μm) of the exposure area, even if there are variations in control. ΔT=(Ws÷1000)÷Vdr Formula (5)

[0109] [Control Block] The image controller unit 700 and the printed circuit board 202 will be described. In the following, the chip select signal is cs_x, the line synchronization signal is lsync_x, the clock signal is clk, and the image data signal is data. In this embodiment, to simplify the explanation, a single color process will be described, but the same process is performed in parallel for four colors.

[0110] [Circuit configuration inside the light-emitting device] The circuit block diagram in the light emitting device 1501 is the same as that in FIG. 7(a), so FIG. 7(a) is used. The circuit section 602 in the light emitting device 1501 has a digital section 800 and an analog section 806. The digital section 800 has a function of generating a pulse signal for driving the lower electrodes 410-n, 420-n based on a set value previously set by a communication signal and various signals in synchronization with a clock signal clk, and transmitting the generated pulse signal to the analog section 806 via a pulse signal line 907. Here, the various signals refer to a chip select signal cs_x, an image data signal data, and a line synchronization signal lsync_x. The digital section 800 also has a function of generating a chip select signal for the next light emitting device 1501 from the input chip select signal cs_x.

[0111] [Digital Department] The communication IF unit 801 controls writing and reading of setting values ​​to the register unit 802 based on a communication signal from the CPU 703. The register unit 802 stores setting values ​​(preset setting values) required for operation. The setting values ​​include exposure timing information used in the data storage unit 804, width and phase information of a pulse signal generated by the pulse signal generation unit 805, setting information of a driving voltage set by the analog unit 806, and the like. Note that since the driving voltage can be derived from the resistance value between the lower electrode and the upper electrode, and the range of this resistance value is known in advance, information on the driving current may be stored instead of the setting information of the driving voltage. The register unit 802 stores at least one of these pieces of information. The chip select signal generation unit 803, which is a second generation unit, delays the chip select signal cs_x, which is the first signal input, generates a chip select signal for the next light emitting device 1501, and transmits it via the signal line 711. The data storage unit 804 receives and holds image data output by the image controller 700 via a data signal line 707 while the input chip select signal cs_x is valid, and outputs the image data to a pulse signal generation unit 805 in synchronization with a line synchronization signal lsync_x. Details will be described later.

[0112] The pulse signal generating unit 805 generates a pulse signal based on the width information and phase information of the pulse signal set in the register unit 802 in accordance with the image data input from the data storage unit 804, and outputs the pulse signal to the analog unit 806. Details will be described later. The analog unit 806 generates a signal required to drive the lower electrode based on the pulse signal generated in the digital unit 800. Details will be described later.

[0113] (Data storage section) Next, the operation of the data storage unit 804 will be described. The data storage unit 804 of the third embodiment is built into the light emitting device 1501. An example will be described in which the chip select signal cs_x and the line synchronization signal lsync_x are negative logic signals, but they may be positive logic. FIG. 18 is a circuit configuration diagram of the data storage unit 804. The clock gate circuit 810 outputs the logical product of the inverted signal of the chip select signal cs_x and the clock signal clk. The clock gate circuit 810 outputs the clock signal s_clk to the flip-flop circuit 811 only when the chip select signal cs_x is valid.

[0114] The flip-flop circuit 811 receives the image data signal data input to the data storage unit 804 as a fundamental input. The flip-flop circuits 811 are connected in series in the same number (748 in this embodiment) as the number of lower electrodes 410, 420 provided in the longitudinal direction of the light emitting device 1501. The flip-flop circuits 811 operate in response to a clock signal s_clk sent from the clock gate circuit 810. The output of the flip-flop circuit 811 is output as image data dly_data_000 to dly_data_747 to the next flip-flop circuit 811 and flip-flop circuit 812 connected adjacently. The flip-flop circuits 811 and flip-flop circuits 812 are provided in the longitudinal direction of the lower electrodes 410, 420 in the same number as the number of lower electrodes (748 in this embodiment).

[0115] The flip-flop circuit 812 receives the output of the flip-flop circuit 811 as input and operates according to the line synchronization signal lsync_x. The output of the flip-flop circuit 812 is output as image data buf_data_0_000 to buf_data_0_747 to the pulse signal generating units 805 (805-1, 805-3, 805-5...) and the flip-flop circuit 813. Each of the flip-flop circuits 812 functions as a memory circuit, and the flip-flop circuit 812 provided for one lower electrode row (lower electrodes 410-1 to 410-748) functions as a memory circuit group (or a first memory circuit group). The pulse signal generating units 805-1, 805-3, 805-5... function as a first pulse signal generating unit group that generates a first pulse signal. It should be noted that pulse signal generating section 805-1 generates a pulse signal for driving lower electrode 410-1, pulse signal generating section 805-3 generates a pulse signal for driving lower electrode 410-2, and pulse signal generating section 805-5 generates a pulse signal for driving lower electrode 410-3.

[0116] The flip-flop circuit 813 receives the output of the flip-flop circuit 812 as an input and operates according to the multiple exposure timing signal lshift_0. The output of the flip-flop circuit 813 is output as image data buf_data_1_000 to buf_data_1_747 to the pulse signal generating units 805 (805-2, 805-4, 805-6,...). Each of the flip-flop circuits 813 functions as a memory circuit, and the flip-flop circuit 813 provided for one lower electrode row (420-1 to 420-748) functions as a memory circuit group (or a second memory circuit group). The pulse signal generating units 805-2, 805-4, 805-6,... function as a second pulse signal generating unit group that generates a second pulse signal. It should be noted that pulse signal generating section 805-2 generates a pulse signal for driving lower electrode 420-1, pulse signal generating section 805-4 generates a pulse signal for driving lower electrode 420-2, and pulse signal generating section 805-6 generates a pulse signal for driving lower electrode 420-3.

[0117] That is, the flip-flop circuit 811, the flip-flop circuit 812, and the flip-flop circuit 813 function as a memory that temporarily stores driving data for controlling the voltage applied to the lower electrode.

[0118] The multiplex timing signal generating unit 814, which is a first generating unit, generates a multiple exposure timing signal lshift_0, which is a timing signal, based on the line synchronization signal lsync_x, the clock signal clk, and the multiple timing setting signal lshift_start. That is, the multiplex timing signal generating unit 814 generates a multiple exposure timing signal lshif_0 for generating pulse signals at timings different from those of the pulse signal generating units 805-1, 805-3, etc., for the pulse signal generating units 805-2, 805-4, etc. In this embodiment, the multiplex timing signal generating unit 814 delays the line synchronization signal lsync_x by a set value set in the multiplex timing setting signal lshift_start to generate the multiple exposure timing signal lshift_0. For example, when the multiplex timing setting signal lshift_start is set to 1 (lshift_start=1), the multiple exposure timing signal lshift_0 becomes a signal in which the line synchronization signal lsync_x is delayed by one cycle of the clock signal clk. The multiple timing signal generating unit 814 generates a multiple exposure timing signal lshift_0 based on the rotation speed of the photosensitive drum 102. That is, the multiple timing setting signal lshift_start is set based on the delay time Tdelay obtained by the above-mentioned equation (3).

[0119] Fig. 19 is a timing chart showing the operation of the data storage unit 804 in the Y direction. Fig. 19 shows the waveform of the line synchronization signal lsync_x in (i), and the image data buf_data_0_000 and the like which are the output of the flip-flop circuit 812 in (ii). Fig. 19 shows the waveform of the multiple exposure timing signal lshift_0 in (iii), and the image data buf_data_1_000 and the like which are the output of the flip-flop circuit 813 in (iv). Fig. 19 representatively explains the image data buf_data_0_000 which is the output of the flip-flop circuit 812 at the leftmost end of Fig. 18, and the image data buf_data_1_000 which is the output of the flip-flop circuit 813. The same is true for all of the image data buf_data_0_001 to buf_data_0_747 and buf_data_1_001 to buf_data_1_747.

[0120] As described in Fig. 8, image data dly_data_000 is input to the flip-flop circuit 812 at time T10 in Fig. 19, which is the timing when the line synchronization signal lsync_x=0 at time T0 in Fig. 8. Then, the value of the image data dly_data_000 is output from the flip-flop circuit 812 as image data buf_data_0_000. At time T11, the multiple exposure timing signal lshift_0 is input to the flip-flop circuit 813 as a low level (lshift_0=0). Then, the value of the image data buf_data_0_000 output from the flip-flop circuit 812 is output from the flip-flop circuit 813 to the pulse signal generating unit 805 as image data buf_data_1_000. In this way, the data output to the pulse signal generating unit 805 as buf_data_0_000 when lsync_x=0 is output again to the pulse signal generating unit 805 as buf_data_1_000 at the next timing of lshift_0=0. Here, the time T11 when the multiple exposure timing signal lshift_0 becomes low level is a timing delayed by the multiple timing setting signal lshift_start from the time T10 when the line synchronization signal lsync_x becomes low level. The image data buf_data_0_000 is output to the pulse signal generating unit 805 corresponding to the lower electrode used for the first exposure in the Y direction on the photosensitive drum 102. Also, the image data buf_data_1_000 is output to the pulse signal generating unit 805 corresponding to the lower electrode used for the later exposure in the Y direction on the photosensitive drum 102. In this way, multiple exposure is realized.

[0121] In this embodiment, the configuration for multiple exposure using two lower electrodes 410-n and 420-n arranged in the Y direction has been described as an example, but the number of lower electrodes used for multiple exposure is not limited to two. When increasing the number of lower electrodes used for multiple exposure (when multiple exposure is performed for m=3 or more columns), the flip-flop circuits 812 (748 pieces) and 813 (748 pieces) shown in FIG. 18 can be increased to m columns (m×748 pieces). This makes it possible to hold image data corresponding to m columns (m×748 pieces). In addition, by increasing the number of pulse signal generating units 805 connected to the flip-flop circuits for m columns to m columns (m×748 pieces), the light emission timing of each of the m columns (m×748 pieces) of lower electrodes can be controlled, and multiple exposure for m columns can be performed.

[0122] In this embodiment, a flip-flop circuit has been described as an example of a means for holding image data of each lower electrode. In this configuration, flip-flop circuits are arranged in parallel with lower electrodes 410-1 to 410-748, thereby forming a simpler circuit with a smaller wiring area. On the other hand, even if flip-flop circuits are not used, the following configuration can be used. That is, as long as there is a memory circuit (e.g., RAM, etc.) corresponding to the lower electrodes and a control unit that controls the read timing and write timing to the memory circuit, it is not necessary to use a flip-flop circuit.

[0123] By increasing the number of lower electrodes used for multiple exposure and making it possible to select the number of lower electrode rows used for multiple exposure, more dynamic control of the light quantity becomes possible. For example, in a configuration in which the number m of lower electrode rows is m=10 and the lower electrodes are arranged in the Y direction, it becomes possible to select 2 to 10 lower electrode rows used for multiple exposure according to the image formation speed of the image forming apparatus. This makes it possible to change the light output in 9 stages. Therefore, it is possible to reduce the control range of the drive current of each lower electrode, and it becomes possible to drive the lower electrodes under almost equal drive current conditions at all times. For example, when the lower electrodes are driven with a low current (i.e., a low light amount), there are cases in which the response of the lower electrodes is slow and a predetermined light amount cannot be obtained. In such cases, the multiple exposure of this embodiment makes it possible to stably drive the lower electrodes. In this way, when selecting which of the multiple rows of lower electrodes to use, a reset terminal may be added to the flip-flop circuits 812, 813, etc., and a configuration may be adopted in which the output of image data is selectively stopped. In addition to this method, a means for stopping the output of the pulse signal may be added to the pulse signal generating unit 805.

[0124] As for the analog section 806 shown in FIG. 7(a), the configuration of the analog section for each lower electrode is the same as that shown in FIG. 11(b) of the first embodiment, and therefore the description thereof will be omitted.

[0125] [Switching the driving direction of the bottom electrode (for staggered arrangement)] As described above, in this embodiment, the light emitting devices 1501 are arranged in a staggered pattern (hereinafter, referred to as a staggered arrangement) on the printed circuit board 202. When the light emitting devices 1501 are arranged in a staggered pattern, good imaging characteristics can be obtained by arranging the lower electrodes close to the center of the lens in the short side direction of the rod lens array 203. When an inexpensive rod lens array is used, there is a limit to the opening of the rod lens, so if the arrangement of the lower electrodes is too far from the center of the rod lens, light may not reach the opening of the rod lens, and light may not be able to be emitted onto the photosensitive drum 102. For this reason, it is effective to arrange the lower electrode rows closer to one side in the short side direction from the center of the light emitting device 1501, and to arrange each lower electrode row as close as possible to the center of the rod lens.

[0126] In FIG. 15, the center of the rod lens array 203 in the short side direction is indicated by a dashed line as L_center. The rod lens array 203 and the light emitting devices 1501 are mounted so that the center line (hereinafter referred to as the center line) L_center of the rod lens array 203 in the short side direction coincides with the center of the two light emitting devices 1501 arranged in a staggered manner. The lower electrodes of the light emitting devices 1501 are arranged at a position closer to the center line L_center than the center of the light emitting device 1501. Here, in the light emitting device 1501A (one of the first substrates), the surface on the side farther from the light emitting device 1501B is defined as an end surface 311, and the surface on the side closer to the light emitting device 1501B is defined as an end surface 310. In addition, in the light emitting device 1501B (the other first substrate), the surface on the side farther from the light emitting device 1501A is defined as an end surface 311, and the surface on the side closer to the light emitting device 1501B is defined as an end surface 310. In each of the light emitting devices 1501, the lower electrodes 410 and 420 are disposed close to the end face 310 side.

[0127] By arranging the lower electrodes 410 and 420 in this manner, light from each of the lower electrodes is incident on the opening of the rod lens array 203. In this embodiment, the lower electrodes in the light emitting device 1501 are arranged at a position shifted to one side from the center in the short side direction of the light emitting device 1501. The mounting direction of each of the light emitting devices 1501 is determined so that the end face 310 of each of the light emitting devices 1501 is on the center line L_center side. That is, in the silicon substrate 1502, the multiple lower electrodes 410 and 420 are arranged on the side closer to the center (center line L_center) in the short side direction of the rod lens array 203. When the light emitting devices 1501 are arranged in a two-row staggered arrangement, the light emitting devices 1501A and 1501B are arranged so that the light emitting points approach the center line L_center while being inverted by 180° from each other.

[0128] In this way, the mounting direction of the light emitting device 1501 is determined so that the position of the lower electrode is shifted to one side within the light emitting device 1501 and the lower electrode approaches the center line L_center. This makes it possible to obtain good imaging characteristics. Meanwhile, as described above, by arranging the light emitting devices 1501 in different mounting directions, it is necessary to control the order of driving the lower electrodes in the Y direction according to the direction of the light emitting device 1501. For example, in the light emitting device 1501A, the lower electrode on the side closer to the end face 311 (upper side in the figure) is driven first, and in the light emitting device 1501B, the lower electrode on the side closer to the end face 310 (upper side in the figure) is driven first. A control method in such a case will be described below.

[0129] (Circuit with selector) FIG. 20 is a circuit block diagram inside light emitting device 1501 that switches the light emission order of lower electrodes 410-1 to 410-748 in the short-side direction of printed circuit board 202. As in FIG. 18, a case where two rows of lower electrodes 410-1 to 410-748 and lower electrodes 420-1 to 420-748 are provided in the Y direction will be described. In addition to the circuit configuration described in FIG. 18, data storage unit 804 has selectors 2200-12, 2200-34, 2200-56, .... Selector 2200-12 switches the combination of connections between flip-flop circuit 812 and flip-flop circuit 813 and pulse signal generating unit 805-1 and pulse signal generating unit 805-2. Selector 2200-34 switches the combination of connections between flip-flop circuit 812 and flip-flop circuit 813 and pulse signal generating unit 805-3 and pulse signal generating unit 805-4. The selector 2200-56 switches the combination of connections between the flip-flop circuit 812 and the flip-flop circuit 813 and the pulse signal generating unit 805-5 and the pulse signal generating unit 805-6.

[0130] The selectors 2200-12, 2200-34, 2200-56, ... are collectively referred to as the selector 2200. The selector 2200 is capable of switching the connection relationship with the pulse signal generating unit 805, which is the destination of image data from the flip-flop circuits 812 and 813. In other words, the selector 2200 functions as a selection unit that selects a combination of connections between the first and second memory circuit groups and the first and second pulse signal generating unit groups.

[0131] For example, in one light emitting device 1501 in the longitudinal direction of the staggered arrangement, flip-flop circuit 812 is connected to pulse signal generating unit 805-1, and flip-flop circuit 813 is connected to pulse signal generating unit 805-2. In the other light emitting device 1501 in the longitudinal direction of the staggered arrangement, flip-flop circuit 812 is connected to pulse signal generating unit 805-2, and flip-flop circuit 813 is connected to pulse signal generating unit 805-1. The connection information of selector 2200 is set in a predetermined register of register unit 802 based on a communication signal from CPU 703. It is assumed that the connection of selector 2200 is controlled based on the connection information (register value) set in register unit 802.

[0132] As described above, by having a means for switching the driving order of the lower electrodes, it becomes possible to perform multiple exposure regardless of the arrangement direction of the light emitting device 1501 on the printed circuit board 202. In this embodiment, the usefulness of the staggered arrangement has been explained, but it is also useful when the same exposure head is used in a plurality of different image forming apparatuses. The driving order is selected according to the rotation direction of the photosensitive drum 102 and the mounting direction of the exposure head. This makes it possible to use the same exposure head even in image forming apparatuses in which the rotation direction of the photosensitive drum 102 is different.

[0133] As described above, in this embodiment, by arranging the lower electrodes in the Y direction and performing multiple exposure, it is possible to increase the optical output of the exposure head, and it is possible to increase the speed of the image forming device and to deal with photosensitive materials that require a larger amount of light. In addition, by forming the lower electrode row and the circuit part 602 on a silicon substrate, it is possible to increase the resolution of the output and improve the performance of the control by making it possible to incorporate a large-scale logic circuit of the light-emitting device.

[0134] Also, it has a means for generating image data for multiple exposure within the silicon substrate 1502. This makes it possible to generate the necessary image data without increasing the wiring (wire bonding) of the interface of the light emitting device 1501. By optimally arranging the memory circuit (flip-flop circuit), it becomes possible to optimize the wiring area. Furthermore, it is possible to control the light emission timing according to the printing speed and resolution of the image forming apparatus and the interval between the lower electrodes of the light emitting device 1501. This makes it possible to sharpen the exposure area on the photosensitive drum 102 by multiple exposure.

[0135] As described above, according to this embodiment, it is possible to propose an exposure head that can be driven at high speed with a higher optical output. EXAMPLES

[0136] In the fourth embodiment, a method of transferring image data from the image controller unit 700 to each light emitting device 401 using the above-mentioned chip select signal will be described by taking the configuration of the first embodiment as an example. Note that the image data transfer method of this embodiment is also applicable to the second and third embodiments.

[0137] FIG. 21 is a timing chart showing the relationship between (i) a clock signal clk, (ii) a line synchronization signal lsync_x, (iii) chip select signals cs_x, cs_x_1 to cs_x_19, and (iv) an image data signal data.

[0138] In FIG. 21, cs_x represents the chip select signal line 705 in FIG. 6, cs_x_1 represents the chip select signal input to the light emitting device 401-2 via the signal line 711-1 in FIG. 6, cs_x_2 represents the chip select signal input to the light emitting device 401-3 via the signal line 711-2 in FIG. 6, and cs_x_19 represents the chip select signal input to the light emitting device 401-20. In addition, image data for driving one line of the lower electrode in the n-th light emitting device 401-n is represented as data(n-1). For example, image data for driving one line of the lower electrode in the first light emitting device 401-1 is data0. The image controller 700 sets the chip select signal cs_x to Low for the number of clock cycles ΔT0 cycles required to transfer image data for driving one line of the lower electrode in the light emitting device 401-1. In this embodiment, image data for one lower electrode is transferred per clock cycle, and ΔT0 is 748 cycles. It should be noted that the image data for a plurality of lower electrodes may be transferred in one cycle, or one piece of image data may be transferred in multiple cycles.

[0139] The chip select signal generating unit 803 built in the light emitting device 401-1 outputs a chip select signal cs_x_1 obtained by delaying the chip select signal cs_x input to the light emitting device 401-1 by ΔT1 cycles. Here, ΔT1 is a value obtained by adding a delay required for generating the chip select signal to ΔT0. In this embodiment, it takes two cycles to generate a signal, and ΔT1=750 cycles. In this way, the chip select signal generating unit 803 can generate the chip select signal cs_x_1 so that it does not become Low at the same time as cs_x. Similarly, the chip select signal generating units 803 built in the other light emitting devices 401-2 and onward generate new chip select signals so that the chip select signal input from the previous light emitting device does not become Low at the same time as the input chip select signal, and transfer them to the light emitting devices in the following stages in order. That is, each light emitting device samples image data by the input chip select signal, delays the input chip select signal by a predetermined amount, and passes it to the light emitting device in the following stage. As a result, each chip select signal goes Low in the order of cs_x → cs_x_1 → cs_x_2 → ... → cs_x_19. In addition, the period ΔT2 of the line synchronization signal lsync_x is set to a value greater than the time it takes for cs_x_19 to be input to the light emitting device 401-20 in order to send image data to all light emitting devices 401. This can be expressed as an equation as follows. ΔT2 ≧ ΔT1 × 20

[0140] The image controller unit 700 controls so that the section where cs_x_19 is Low does not overlap with the next section where cs_x is Low, and sends image data data0 to data19 to the image data signal line 707 with an interval of (ΔT1-ΔT0) cycles in accordance with each chip select signal. The chip select signal is also input to the data storage unit 804 built in each light emitting device 401. The data storage unit 804 can receive image data from the image data signal 707 by inputting a chip select signal of low level. That is, during one cycle of Lsync_x, only one of the light emitting devices 401-1 to 401-20 can receive image data from the image controller 700 via the image data signal line 707. By passing the chip select signal from the light emitting device 401-1 to the light emitting device 401-20 in order, the image controller unit 700 can distribute and send each image data to each light emitting device 401 via the common image data signal line 707 and one chip select signal line.

[0141] As described above, by cascading the light emitting devices using chip select signals, it is possible to suppress an increase in the number of signal lines even if the bit width of the image data signal lines is increased.

[0142] (Modification) A modified example of the fourth embodiment will be described using Figures 22 and 23. Figure 22 shows a block diagram of an image controller unit 700 and a printed circuit board 202 in the modified example. What differs from Figure 6 of the first embodiment is that a second image data signal line 1307 (second signal line) is additionally output from the chip data conversion unit 702 in addition to an image data signal line 707 (hereinafter, referred to as a first image data signal line or a first signal line for distinction), and in the signal line connection to the light emitting device 401 in the printed circuit board 202.

[0143] In the chip data conversion unit 702 of this embodiment, one line of image data is divided into first image data for the light emitting devices 401-2, 401-4, ... arranged on the lower side of the printed circuit board 202 in Fig. 22 in synchronization with the line synchronization signal generated by the synchronization signal generation unit 704, and second image data for the light emitting devices 401-1, 401-3, ... arranged on the upper side of the printed circuit board 202 in Fig. 22, and sent to the printed circuit board 202 together with a clock signal and a chip select signal. The first image data and the second image data are sent separately. Other configurations of the image controller unit 700 are the same as those of the first embodiment.

[0144] Next, the configuration of the printed circuit board 202 will be described. The head information storage unit 710 is the same as in the first embodiment. The clock signal line 706, the line synchronization signal line 708, and the communication signal line 709 are connected to all of the light emitting devices 401. The first image data signal line 707 is connected to the light emitting devices 401-2, 401-4, ... arranged on the lower side of the printed circuit board 202 in the figure. That is, the first image data signal line 707 is used in common for the light emitting devices 401-2, 401-4, ... for transmitting image data. The second image data signal line 1307 is connected to the light emitting devices 401-1, 401-3, ... arranged on the upper side of the printed circuit board 202 in the figure. That is, the second image data signal line 1307 is used in common for the light emitting devices 401-1, 401-3, ... for transmitting image data. The light emitting devices 401-2, 401-4, . . . are defined as a first group of light emitting elements, and the light emitting devices 401-1, 401-3, . . . are defined as a second group of light emitting elements.

[0145] Chip select signal line 705 is connected to the input of light emitting device 401-1, the output of light emitting device 401-1 is connected to the input of light emitting device 401-3 via signal line 711-1, and so on, forming a cascade connection of the upper light emitting devices. Chip select signal line 705 is also connected to the input of light emitting device 401-2, the output of light emitting device 401-2 is connected to the input of light emitting device 401-4 via signal line 711-2, and so on, forming a cascade connection of the lower light emitting devices. The operation of each light emitting device 401 is the same as in the first embodiment.

[0146] Next, a description will be given of image data transfer from the image controller unit 700 to the light emitting device 401 in this embodiment. Fig. 23 is a timing chart showing the relationship between (i) the clock signal clk, (ii) the line synchronization signal lsync_x, (iii) the chip select signals cs_x, cs_x_1 to cs_x_19, and (iv) the first image data signal data_1 and the second image data signal data_2. In Fig. 23, cs_x represents a chip select signal input to the light emitting device 401-1 and the light emitting device 401-2 via the chip select signal line 705 in Fig. 22, cs_x_1 represents a chip select signal input to the light emitting device 401-3 via the signal line 711-1 in Fig. 22, cs_x_2 represents a chip select signal input to the light emitting device 401-4 via the signal line 711-2 in Fig. 22, cs_x_3 represents a chip select signal input to the light emitting device 401-5 via the signal line 711-3 in Fig. 23, cs_x_4 represents a chip select signal input to the light emitting device 401-6 via the signal line 711-4 in Fig. 23, cs_x_18 represents a chip select signal input to the light emitting device 401-19, and cs_x_19 represents a chip select signal input to the light emitting device 401-20. The notation of image data is the same as in Fig. 21.

[0147] The low width ΔT0 of the chip select signal cs_x and the generation of the chip select signal in the light emitting device 401 are the same as in the first embodiment. In this embodiment, the chip select signal cs_x is input to the light emitting devices 401-1 and 401-2, which are cascade-connected at the upper and lower sides, respectively. As a result, the chip select signals are in parallel in a system where the signals go low in sequence from cs_x to cs_x_1 to cs_x_3 to ... to cs_x_19, and in a system where the signals go low in sequence from cs_x to cs_x_2 to cs_x_4 to ... to cs_x_18, and two identical chip select signals are generated at a time.

[0148] The cycle ΔT2 of the line synchronization signal lsync_x is constrained by the following equation since the number of stages of the cascade connection is half that of the first embodiment. ΔT2 ≧ ΔT1 × 10

[0149] The image controller unit 700 controls the chip select signals cs_x_18 and cs_x_19 so that the period when they are low does not overlap with the period when the chip select signal cs_x next goes low, and sends image data data1, data3..., data19 to the first image data signal line 707 and data0, data2..., data18 to the second image data signal line 1307 in accordance with each chip select signal, with an interval of (ΔT1-ΔT0) cycles between each.

[0150] As described above, by providing multiple systems for cascading the light emitting devices 401 using chip select signals and running the image data signal lines in parallel, it is possible to relax the lower limit constraint on the period of the line synchronization signal lsync_x and improve productivity. Note that, although this embodiment is divided into two systems, it may be divided into three or four systems.

[0151] As described above, according to this embodiment, it is possible to propose an exposure head that can be driven at high speed with a higher optical output. [Explanation of symbols]

[0152] 202 Printed circuit board 401 Light emitting device 402 Silicon Substrate 410 Lower electrode 602 Circuit section 604 Light-emitting area

Claims

1. An image forming apparatus, A photoconductor that is rotated around a rotation axis; an exposure head including a light emitting device, a circuit board on which the light emitting device is mounted, and a lens array that guides the light emitted from the light emitting device to a photoconductor surface; a controller that outputs image data for driving the light emitting device to the circuit board; The light emitting device comprises: a silicon wafer including a driving circuit for driving the light emitting device; a first electrode layer including a plurality of electrodes arranged in a direction substantially parallel to the rotation axis of the photoconductor; a second electrode layer in a layered form through which light can pass; and a light emitting layer formed in a layered form between the first electrode layer and the second electrode layer and emitting light when a voltage is applied thereto; and a layered body formed on a surface of the silicon wafer; The image forming apparatus is characterized in that the drive circuit includes a voltage generation circuit that generates a drive voltage, and a pulse signal generation circuit that generates a pulse signal for each of the plurality of electrodes based on the image data, and the drive circuit applies the drive voltage generated by the voltage generation circuit in response to the pulse signal to each of the plurality of electrodes.

2. 2. The image forming apparatus according to claim 1, wherein the first electrode layer is formed separately on the surface of the silicon wafer, the light-emitting layer is formed in a layered form on the first electrode layer, and the second electrode layer is formed on the opposite side to the side on which the silicon wafer is disposed, with the light-emitting layer sandwiched therebetween.

3. the drive circuit includes a shift register including a plurality of flip-flop circuits corresponding to the plurality of electrodes, respectively, for storing the image data; and a register including a plurality of flip-flop circuits corresponding to the plurality of electrodes, respectively, and individually connected to the plurality of flip-flop circuits of the shift register, 2. The image forming apparatus according to claim 1, wherein the pulse signal generating section generates the pulse signal based on image data stored in a flip-flop circuit of the register.

4. the controller generates a clock signal and a line synchronization signal; the shift register samples the image data output by the controller in synchronization with the clock signal and shifts the image data in the plurality of flip-flop circuits; 4. The image forming apparatus according to claim 3, wherein image data stored in each of the flip-flop circuits corresponding to the lower electrodes of the shift register are transferred to the flip-flop circuits of the register in response to the line synchronization signal.

5. 5. The image forming apparatus according to claim 1, wherein a plurality of the light emitting devices are arranged on the circuit board along a direction substantially parallel to the axis of rotation.

6. the controller and the plurality of light-emitting devices are connected by a common signal line in order to transmit the image data from the controller to the plurality of light-emitting devices; The image forming apparatus according to claim 5, characterized in that the controller outputs an enable signal to one of the plurality of light-emitting devices to enable sampling of the image data, and each of the plurality of light-emitting devices sequentially passes on the enable signal with a delay starting from the one light-emitting device.

7. the plurality of light-emitting devices are divided into a first group of light-emitting devices connected to the controller by a common signal line for transmitting the image data, and a second group of light-emitting devices connected to the controller by a common second signal line for transmitting the image data; The image forming apparatus of claim 5, characterized in that the controller outputs an enable signal for enabling sampling of the image data to one of the plurality of light-emitting devices included in the first group of light-emitting devices and one of the plurality of light-emitting devices included in the second group of light-emitting devices, and each of the plurality of light-emitting devices included in each group of light-emitting devices delays and sequentially passes on the enable signal starting from each of the one light-emitting devices.

8. a silicon wafer containing a circuit; a layered body formed on a surface of the silicon wafer, the layered body including a first electrode layer including a plurality of electrodes, a layered second electrode layer through which light can pass, and a light-emitting layer formed in a layered state between the first electrode layer and the second electrode layer and emitting light when a voltage is applied thereto; The light-emitting device is characterized in that the drive circuit includes a voltage generation circuit that generates a drive voltage, and a pulse signal generation circuit that generates a pulse signal for each of the multiple electrodes based on drive data, and the drive circuit applies the drive voltage generated by the voltage generation circuit in response to the pulse signal to each of the multiple electrodes.

9. 9. The light-emitting device according to claim 8, wherein the first electrode layer is formed separately on the surface of the silicon wafer, the light-emitting layer is formed in a layered form on the first electrode layer, and the second electrode layer is formed on the opposite side to the side on which the silicon wafer is disposed, with the light-emitting layer sandwiched therebetween.

10. the drive circuit includes a shift register including a plurality of flip-flop circuits corresponding to the plurality of electrodes, respectively, for storing the drive data; and a register including a plurality of flip-flop circuits corresponding to the plurality of electrodes, respectively, and individually connected to the plurality of flip-flop circuits of the shift register, 10. The light emitting device according to claim 8, wherein the pulse signal generating section generates the pulse signal based on image data stored in a flip-flop circuit of the register.

Images