Vcsel with integrated ESD protection

Abstract

To provide a VCSEL device with a lithographic aperture and integrated electrostatic discharge event protection.SOLUTION: A VCSEL device includes multiple layers forming a protection diode outside of a lithographic aperture area, the protection diode having a surface area that is greater than a surface area of the lithographic aperture.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] This disclosure relates generally to vertical cavity surface emitting lasers (VCSELs) with electrostatic discharge (ESD) protection. [Background technology]

[0002]

[0002] Aspects of the present disclosure relate to VCSELs with integrated ESD protection. Conventional solutions for VCSELs with ESD protection may have various problems. In this regard, conventional systems and methods for VCSELs with ESD protection may be costly, cumbersome, and / or inefficient.

[0003]

[0003] The limitations and drawbacks of conventional systems and methods will become apparent to those skilled in the art through a comparison of such approaches with certain aspects of the present methods and systems described in the remainder of this disclosure with reference to the drawings. Summary of the Invention

[0004] A VCSEL with ESD protection is shown and / or described in connection with at least one of the drawings and more fully described in the claims.

[0005] These and other advantages, aspects and novel features of the present disclosure, as well as details of the illustrated embodiments, will become more fully understood from the following description and drawings. [Brief description of the drawings]

[0005]

[0006] The various features and advantages of the present disclosure will become more readily understood by reference to the following detailed description, taken in conjunction with the accompanying drawings, in which like reference characters indicate like structural elements and in which: [Figure 1]

[0007] FIG. 1 illustrates an exemplary ESD protection circuit for an ESD sensitive light emitting diode. [Diagram 2]

[0008] FIG. 1 shows a VCSEL with an oxide aperture. [Diagram 3]

[0009] FIG. 1 illustrates a VCSEL with a lithographic tunnel junction aperture and integrated ESD protection diode functionality. [Figure 4]

[0010] FIG. 4 is an equivalent circuit diagram showing the functioning of the VCSEL according to FIG. [Diagram 5]

[0011] FIG. 1 illustrates a VCSEL with a lithographic aperture defined by an opening in an n-blocking layer with integrated ESD protection diode functionality. [Figure 6]

[0012] FIG. 6 is an equivalent circuit diagram showing the functioning of a VCSEL according to FIG. 5. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0006]

[0013] The following discussion provides various examples of semiconductor devices and methods of manufacturing semiconductor devices. Such examples are not limiting, and the appended claims should not be limited to the particular examples disclosed. In the following discussion, the terms "examples" and "for example" are not limiting.

[0007]

[0014] The figures show general schemes of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the present disclosure. Additionally, elements in the drawing figures are not necessarily drawn to scale. For example, the dimensions of some elements in the figures may be exaggerated relative to other elements to help improve understanding of the embodiments discussed in this disclosure. The same reference numbers in different figures refer to the same elements.

[0008]

[0015] The term "or" means any one or more of the items in the list joined by "or." As an example, "x or y" means any element in the three element set {(x),(y),(x,y)}. As another example, "x,y, or z" means any element in the seven element set {(x),(y),(z),(x,y),(x,z),(y,z),(x,y,z)}.

[0009]

[0016] The terms "comprises," "comprising," "includes," and / or "including" are "open-ended" terms and specify the presence of stated features but do not exclude the presence or addition of one or more other features.

[0010]

[0017] Terms such as "first", "second" and the like are used herein to describe various elements, but these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Thus, for example, a first element discussed in this disclosure can also be called a second element without departing from the teachings of this disclosure.

[0011]

[0018] Unless otherwise specified, the term "coupled" may be used to describe two elements that are in direct contact with each other or two elements that are indirectly connected by one or more other elements. For example, if element A is coupled to element B, element A may be in direct contact with element B or indirectly connected to element B by an intervening element C. Similarly, the terms "over" or "on" may be used to describe two elements that are in direct contact with each other or two elements that are indirectly connected by one or more other elements.

[0012]

[0019] Referring now to FIG. 1, an exemplary ESD protection circuit is shown including a light emitting diode (LD) 10, a protection diode 20, a voltage source 30, an ESD current flow 50 with an associated ESD voltage 55, and a normal current flow 40 with an associated normal operating voltage 45.

[0013]

[0020] The light emitting diode 10 may be operable to emit light by an applied voltage / current. The light emitting diode 10 may be a vertical cavity surface emitting laser, or VCSEL. A VCSEL is a type of semiconductor laser diode in which a laser beam is emitted vertically from the top facet. VCSELs are used in a variety of laser products.

[0014]

[0021] The ESD protection diode 20 may be coupled to the LD 10 as shown in Figure 1. The voltage source 30 may represent a device operable to provide a fixed or variable voltage to the electrical circuit of Figure 1. The depicted voltage source 30 may represent a source of normal operating voltage 45 and normal current flow 40, as well as ESD current flow 50 and ESD voltage 55.

[0015]

[0022] VCSELs may be sensitive to ESD events due to their small aperture. That is, the LD 10 may be damaged if excessive voltage and / or current is applied to it, for example by the voltage source 30 shown. For an ESD sensitive device such as the LD 10, a protection diode 20 may be coupled in parallel, but in reverse, with the ESD sensitive laser diode 10, as shown. The protection diode 20 may be selected or designed to be highly resistive during normal operation, allowing substantially all of the current to flow through the ESD sensitive laser diode 10. This is illustrated in FIG. 1 by the normal current flow 40 with an associated exemplary normal voltage 45. In normal operation, the positive The normal voltage 45 is lower than the (reverse) breakthrough voltage VBR associated with the protection diode 20. When an electrostatic discharge occurs, the ESD voltage 55 may exceed the breakthrough voltage VBR, as illustrated by the ESD current flow 50, and the ESD current flow 50 may flow across the protection diode 20 in the reverse direction. Correspondingly, the breakthrough voltage VBR of the protection diode 20 is preferably higher than the normal operating voltage 45 and lower in magnitude than the voltage that may damage the LD10. In this manner, an ESD sensitive device, for example, the LD10, may be protected from electrostatic discharge by the protection diode 20 coupled in reverse and in parallel therewith, as illustrated in FIG. 1. According to normal diode operation, the forward breakdown voltage of the protection diode 20 may be substantially lower than the (reverse) breakdown voltage VBR. If an electrostatic discharge causes a voltage to be applied in the forward direction of the protection diode 20, the protection diode 20 can short out at a forward voltage substantially lower than the reverse breakthrough voltage, preventing damage to the ESD sensitive device LD10, and thus LD10 can be protected.

[0016]

[0023] 2 shows an exemplary cross-section of a VCSEL device 100 with an oxide aperture. Shown are ohmic n-contact layer 180, substrate n-GaAs layer 170, n-DBR layer 160, active region 150, oxide aperture layer 140, p-DBR layer 130, mesa layer 110, and ohmic p-contact layer 120. Additionally, electron flow 190 and hole flow 200 are shown. The cross-section of the VCSEL device 100 may be that of a cylindrical structure, for example, having a circular, elliptical, rectangular, or any other shaped cross-section.

[0017]

[0024] The VCSEL 100 can be fabricated using, for example, lithographic semiconductor fabrication processes. The ohmic n-contact 180 can be operable as an electrical coupling contact for a negative voltage terminal. Similarly, the ohmic p-contact 120 can be operable as an electrical coupling contact for a positive voltage terminal.

[0018]

[0025] The p-DBR 130 may be a p-type distributed Bragg reflector (DBR). The n-DBR 160 may be an n-type distributed Bragg reflector. The p-DBR 130 and the n-DBR 160 may be operable as resonant mirrors of a laser. The n-type may refer to doping with impurities to provide additional electrons, and the p-type may refer to doping with impurities to provide additional holes.

[0019]

[0026] The oxide aperture 140 may be operable to allow emission of light generated by the VCSEL 100 perpendicular to the active region 150. The oxide layer may confine current flow (200 / 190) to the aperture region 140 as illustrated in FIG. 2. The active region 150 may have appropriate energy levels to allow stimulated emission of light such that an injection of energy may provide an excess of excited atoms between the resonator system that may be formed between the p-DBR 130 and n-DBR 160 mirrors. The active region 150 may include quantum wells, quantum dashes, or quantum dots.

[0020]

[0027] Substrate n-GaAs 170 may be an n-type gallium arsenide (GaAs) substrate layer. According to various embodiments of the present patent, substrate 170 may be any suitable material, including but not limited to indium phosphide (InP), gallium nitride (GaN), silicon (Si), and silicon carbide (SiC).

[0021]

[0028] Mesa 110 is an area on a semiconductor wafer where semiconductor has not been etched away, resulting in mesa 110 rising above the surrounding area.

[0022]

[0029] In the event of an electrostatic discharge (ESD) event, a discharge current flow may occur through the area of ​​the oxide aperture 140, as illustrated by hole flow 200 and electron flow 190 in Figure 2. Because the area of ​​the aperture 140 is limited (compared to the area of ​​the mesa 110), the discharge current density in the oxide aperture 140 area may be high and may damage the active region layer 150 of the VCSEL 100. Therefore, it may be advantageous to integrate a structure similar to the ESD protection diode 20 directly into the VCSEL, as illustrated in Figure 3.

[0023]

[0030] FIG. 3 shows an exemplary tunnel junction configuration VCSEL with an integrated protection diode structure. Referring to FIG. 3, a VCSEL 300 in a tunnel junction configuration is shown. The VCSEL may include a mesa 110, an ohmic p-contact 120, an ohmic n-contact 180, an n-DBR 160a, an active region 150, an n-DBR 160, and a substrate n-GaAs 170 layer. The same reference numbers refer to similar layers as in FIG. 2. The n-DBR 160a may be similar to the n-DBR 160. An electron flow 190 is shown. An electron discharge flow 350 is shown. An exemplary protection diode symbol 360 and a tunnel diode symbol 380 are shown. The protection diode symbol 360 may represent an np junction diode formed by the p-type cavity 310 / pn blocking layer 320 and the n-DBR 160a. The tunnel diode 380 symbol denotes a tunnel diode formed by the p-type cavity 310 / pn blocking layer 320 / tunnel junction layer 330 and the n-DBR 160a layer.

[0024]

[0031] Further shown are a p-type cavity 310, a p-n blocking layer 320 and a tunnel junction layer 330. The p-n blocking layer 320 may be operable to block current flow during normal operation (i.e., lower voltages, e.g., less than 5V). An n-type cavity 390 is also shown.

[0025]

[0032] The lithographic aperture VCSEL 300 may rely on a conductive aperture (formed by the tunnel junction layer 330) for current and optical mode confinement, while the surrounding regions are made non-conductive. This may be accomplished by first growing the bottom n-DBR mirror 160, then the n-cavity 390, the active region 150 (including quantum wells, quantum dashes or quantum dots) and the partial p-cavity 310. The tunnel junction layer 330 may be highly doped (e.g., >10 19 cm -3 ) p++ layers and highly doped (e.g. >10 19 cm -3 ) n++ layer. An aperture is defined in tunnel junction layer 330. To form an aperture in tunnel junction layer 330, the n++ layer (from which tunnel junction layer 330 is formed) may be removed / etched outside of the lithographic aperture, and the wafer may be n-type doped (e.g., 10 17 cm -3 Just 10% off 18 cm -3 During the first generation, a thin film is overgrown in the remaining cavity, which is the top n-DBR mirror 160a. In this case, current flow and optical mode confinement may be provided by the tunnel junction. Outside the aperture formed by the tunnel junction layer 330, current may be blocked due to the pn junction formed by the pn blocking layer 320 / p-type cavity 310 and the n-DBR 160a in the opposite direction.

[0026]

[0033] 3, during normal operation, the voltage applied to the VCSEL 300 may be well below the breakdown voltage of the blocking pn junction layer, and thus current flow during operation is limited to the tunnel junction aperture 330. The blocking pn junction may be formed between the n-DBR 160a and the pn blocking layer 320 / p-type cavity 310. Current flow is indicated by the electron flow 190 with dashed arrows. In the event of an electrostatic discharge, the voltage may exceed the breakdown voltage of the pn blocking layers (n-DBR 160a and pn blocking layer 320 / p-type cavity 310) and Thus, the electrostatic discharge current 350 (illustrated by solid arrows) can flow mostly around the tunnel junction 330 since the available conductive area is much larger during diode breakdown. In this case, the current density in the active region below the tunnel junction layer 330 may be correspondingly reduced. In accordance with various embodiments of the present patent, the layers formed in the VCSEL 300 by the mesa 110 and underlying layers allow for the formation of protection diodes 360 and 370 (not symbolically shown, see also FIG. 4). The protection diodes may be formed between the n-DBR 160a and the pn blocking layer 320 / p-type cavity 310.

[0027]

[0034] To make the ESD protection efficient, the current blocking pn junction area may be as large as practically possible, since it is limited by the mesa 110 surface area. In this case, the ESD current may be distributed over the entire corresponding mesa 110 surface area, resulting in a lower current density and therefore less damage potential. The breakdown voltage of the pn blocking layer 320 is advantageously above 5V. The breakdown voltage may be adjusted by appropriate selection of the doping and thickness of the p-type layer (pn blocking layer 320 / p-type cavity 310) and the n-type layer (n-DBR 160a). In some examples, there may be additional layers on top of the pn blocking layer 320. Also, in some examples, the n-DBR 160a may include additional layers with different doping to form a non-uniformly doped n-DBR 160a. Thus, the bottom n-DBR 160 and the bottom half of the cavity below the active region 150 may be n-doped; in the case of the npn blocking configuration shown in FIG. 3 (from n-DBR 160a, pn blocking layer 320 / p-type cavity 310 / active region 150, and n-DBR 160), the back half of the cavity above the active region 150 may be p-doped and the top n-DBR 160a may be n-doped. The total thickness of the p-doped layers is preferably >50 nm, and the doping may be, for example, 10 17 cm -3 and <10 19 cm -3 The doping in the n-DBR 160a should be in the range of <10 to reduce quantum tunneling of carriers between the p-doped and n-doped layers, which can result in inefficient current blocking. 19 cm -3 Meanwhile, the breakdown voltage of the np-n ESD protection diode (formed by n-DBR 160a, pn blocking layer 320 / p-type cavity 310 / active area 150 and n-DBR 160) may be selected to be <50V to avoid potential damage to the lithographic aperture (in tunnel junction layer 330) in the event of an ESD event and before the ESD protection diode 360 ​​opens in reverse mode.

[0028]

[0035] Additionally, the use of an n-DBR 160a mirror on top of the VCSEL 300 provides improved electrical conductivity compared to the p-DBR 130 as illustrated in Figure 2 for the VCSEL 100 with an oxide aperture. This improved electrical conductivity may reduce the heat generated in an ESD event near sensitive areas of the VCSEL 300, thus providing additional protection.

[0029]

[0036] Figure 4 shows an equivalent circuit diagram for the VCSEL structure of Figure 3, illustrating the diode arrangement formed by the layers in Figure 3. Shown are voltage / current source 30, ESD voltage 55, normal operating voltage 45, ESD current 50, normal operating current 40, protection diodes 360, 370, tunnel diode 380, and light emitting diode 10. Like reference numbers are analogous to elements in previous figures.

[0030]

[0037] The protection diode symbol 360 symbolizes a pn junction diode formed by the p-type cavity 310 / pn blocking layer 320 and the n-DBR 160a. The tunnel diode 380 symbol represents a tunnel diode that may be formed by the p-type cavity 310 / pn blocking layer 320 / tunnel junction layer 330 and the n-DBR 160a layer. The protection diode 370 may symbolize the pn junction formed by the p-cavity 320 / active region 150 and the n-DBR 160 (not symbolized in FIG. 3).

[0031]

[0038] In normal operation, the operating voltage 45 can be below the breakdown voltage VBR of the protection diode 360 ​​(or the reverse diode 370, not shown). The normal operating current 40 can effectively flow only through the tunnel diode 380 and LD10. When an electrostatic discharge event occurs and the ESD voltage 55 exceeds the breakdown voltage VBR, the protection diode 360 ​​becomes conductive and the ESD current 50 can flow mostly through the protection diodes 360, 370. Thus, in the event of an ESD event, the protection diodes 360, 370 are effectively shorted, thus protecting the tunnel diode 380 and LD10 from excessive ESD voltage / current.

[0032]

[0039] FIG. 5 shows a VCSEL diode based on a pnp current blocking configuration with integrated ESD protection diode. FIG. 5 shows a VCSEL 500 including a mesa 110, an ohmic p-contact 120, a p-DBR 130, an n-blocking layer 510, a p-type cavity 310, an active region 150, an n-DBR 160, an n-GaAs substrate 170, and an ohmic n-contact 180. Additionally, electron flow 190 and hole flow 200 are shown. A symbolic protection diode 360 ​​is shown, as formed by the p-DBR 130 layer, the n-blocking layer 510, and the p-type cavity 310. An n-type cavity 390 is also shown. The same reference numbers refer to similar elements as in the previous figures.

[0033]

[0040] As illustrated in FIG. 5, ESD protection can also be introduced in the lithographic aperture using a current n-blocking layer 510. In the VCSEL 500, the n-doped current blocking layer 510 can be grown during the first epitaxial step. This layer 510 can be part of the illustrated ESD protection diode 360. During the wafer fabrication process, the lithographic aperture can be defined by etching through the n-doped layer 510 as shown in FIG. 5. After the definition of the lithographic aperture, the wafer on the n-blocking layer 510 can be overgrown with the top p-doped p-DBR 130 mirror. Thus, in the region of the lithographic aperture, the n-doped layer 510 can be etched to allow current to flow directly from the p-doped p-type cavity 310 to the p-doped p-DBR 130 mirror. The lithographic aperture can also provide optical mode confinement for the VCSEL 500.

[0034]

[0041] In the embodiment of the present patent in FIG. 5, during normal operation, the voltage applied to the VCSEL 500 is below the breakdown voltage of the n-blocking layer 510, so normal current flow is restricted to the aperture opened in the pnp layer (indicated by the yellow dashed arrow). When an ESD event occurs, a higher voltage may exceed the breakdown voltage of the n-blocking layer 510, and thus the ESD current (red solid arrow) may flow outside the aperture. Since the area of ​​the n-blocking layer 510 around the aperture is typically much larger than the aperture area itself, the ESD current will be distributed over a much larger surface area as it is effectively defined by the mesa cross-sectional area. This feature is illustrated in FIG. 6.

[0035]

[0042] 6 shows an equivalent circuit diagram of a VCSEL 500. Shown are voltage / current source 30, ESD voltage 55, normal operating voltage 45, ESD current flow 50, normal operating current 40, protection diodes 360, 370, and light emitting diode 10. The same reference numbers refer to similar elements shown in other figures.

[0036]

[0043] During normal operation, i.e., when the operating voltage 45 is below the breakdown voltage VBR, the protection diodes 360, 370 block current flow and allow the normal current 40 to flow through LD 10. In this case, the current will flow through the aperture region, as illustrated by the dashed arrow in FIG. 5. If an ESD event occurs and the ESD voltage 55 may exceed the breakdown voltage VBR, the protection diodes 360 and 370 effectively short out, allowing the ESD current 50 to flow through the protection diodes 360, 370. This protects LD 10 from current and voltage spikes that may damage it.

[0037]

[0044] Therefore, the mesa 110 cross-sectional area may be selected to be as large as practical to minimize the ESD event current density through the aperture, thus protecting the VCSEL 500. That is, the n-blocking layer 510 surface area may be made large.

[0038]

[0045] According to various embodiments of this patent, the breakdown voltage of n-blocking layer 510 can be preferably made greater than 5V, for example, by selecting the desired doping and thicknesses of the p-type and n-type layers in FIG.

[0039]

[0046] In the case of the pnp blocking diode configuration shown in FIG. 5 formed by the p-type cavity 310 above the active region 150, the n-blocking layer 510 and the p-DBR 130 mirror, the thickness of the n-blocking layer 510 may be >50 nm and the doping may be 10 17 cm -3 and 10 19 cm -3 The doping in the p-DBR layer 130 may be in the range between <10 19 cm -3Such doping levels are advantageous in preventing quantum tunneling of carriers between the n-doped and p-doped layers, which can result in inefficient current blocking. The breakdown voltage VBR of the pn-p ESD protection diodes 360, 370 may be designed to be <50V to prevent damage to the lithographic aperture in the event of an ESD event.

[0040]

[0047] The structures disclosed in Figures 3 and 5 can be fabricated, for example, using a two-step epitaxy method with an intermediate lithographic step.

[0048] Although the present disclosure includes references to specific embodiments, it will be understood by those skilled in the art that various modifications can be made and equivalents can be substituted without departing from the scope of the disclosure. However, changes may be made to the disclosed embodiments without departing from the scope of the disclosure. Thus, the present disclosure is not limited to the disclosed embodiments, but is intended to include all embodiments falling within the scope of the appended claims. [Explanation of symbols]

[0041] 10 Laser Diode 20 Protection Diode 30 Voltage / Current Sources 40 normal operating current 45 Normal operating voltage 50 ESD current 100 VCSEL 110 Mesa 120 Ohmic p-contact 130p-DBR 140 Oxide Aperture 150 active area 160 n-DBR 160a n-DBR 170 Substrate n-GaAs 180 Ohmic n-contact 190 Electronic Flow 200 Hole Flow 300 VCSEL 310 p-type cavity 320 pn blocking layer 330 Tunnel Junction Layer 350 Electron Discharge Flow 360 Protection Diode 370 Protection Diode 380 Tunnel Diode 390 n-type cavity 510 n blocking layer VBR Breakdown Voltage DBR Distributed Bragg Reflector

Claims

1. 1. A VCSEL device comprising a lithographic aperture and electrostatic discharge event protection, comprising: a plurality of layers forming a protection diode outside the area of ​​the lithographic aperture, the protection diode having a surface area greater than a surface area of ​​the lithographic aperture; VCSEL device.

2. 10. The device of claim 1, wherein the protection diode is in a reverse mode during normal operation and blocks current flow in an area outside the lithographic aperture.

3. 10. The device of claim 1, wherein the protection diode is in reverse mode and breaks down during an electrostatic discharge event, allowing current flow in an area outside the lithographic aperture area.

4. The device of claim 1 , wherein the lithographic aperture is defined by a tunnel junction layer.

5. 2. The device of claim 1, wherein the plurality of layers form an npn junction to form the protection diode.

6. 6. The device of claim 5, wherein the npn junction has a reverse breakdown voltage between 5 and 50 volts, or between 3 and 100 volts.

7. 10. The device of claim 1, wherein the pn blocking layers of the multiple layers forming a protection diode have a reverse breakdown voltage greater than 5 volts or greater than 3 volts.

8. 6. The device of claim 5, wherein a top n-DBR layer of the npn junction above the tunnel junction is highly conductive to thermally protect the VCSEL in an electrostatic discharge event.

9. 9. The device of claim 8, wherein the top n-DBR layer of the npn junction has a higher electrical conductivity than the p-type cavity.

10. 10. The device of claim 1 , wherein the lithographic aperture is defined by an opening in an n-blocking layer.

11. 2. The device of claim 1, wherein the plurality of layers form a pnp junction to form the protection diode.

12. The device of claim 11 , wherein the pnp junction can have a reverse breakdown voltage between 5 and 50 volts, or between 3 and 100 volts.

13. 10. The device of claim 1, wherein the n-blocking layer of the plurality of layers forming a protection diode has a reverse breakdown voltage greater than 5 volts or greater than 3 volts.

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