Semiconductor device manufacturing method

Abstract

To provide a technology capable of suppressing peeling of a coating film while reducing an ineffective area.SOLUTION: A semiconductor device manufacturing method includes a preparation step of preparing a semiconductor structure and a dicing step of dicing a dicing line region. The thickness of a side monitor electrode is smaller than the thickness of a coating film, and the relationship of 15>b>1.15×d+6.88 is satisfied between a distance b [μm] between the coating film and the side monitor electrode and a length d [mm] of the side monitor electrode in an extension direction of the dicing line region in a plan view.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] A semiconductor chip has been proposed in which a coating film is provided in the termination region. In such a semiconductor chip, after the coating film is formed with a developer, if the developer remains in a recess adjacent to the coating film, the coating film is peeled off by the developer. In response to this problem, Patent Document 1 proposes a technology for covering the recess with a coating film and suppressing the retention of the developer, thereby suppressing the peeling off of the coating film. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2014 / 013581 Summary of the Invention [Problem to be solved by the invention]

[0004] If a coating film is provided near the dicing line, the coating film may be caught during dicing using a blade. For this reason, the coating film needs to be provided at a certain distance from the dicing line. However, if an opening is provided as in the technology of Patent Document 1, the distance between the coating film and the dicing line needs to be greater than the certain distance. As a result, there is a problem that the invalid area in the semiconductor substrate becomes large, and the manufacturing cost of the semiconductor device increases. In addition, if a side monitor electrode is provided to monitor the electrical characteristics of the semiconductor chip during the manufacturing process, there is a problem that the invalid area in the semiconductor substrate becomes large, and the manufacturing cost of the semiconductor device increases.

[0005] Therefore, the present disclosure has been made in consideration of the above-mentioned problems, and has an object to provide a technique that can suppress peeling of a coating film while reducing the ineffective area. [Means for solving the problem]

[0006] A method for manufacturing a semiconductor device according to the present disclosure includes a preparation step of preparing a semiconductor structure in which a termination region of a semiconductor chip and a dicing line region adjacent to the termination region in a planar view are defined, and a dicing step of dicing the dicing line region, the semiconductor structure including a semiconductor substrate in which the termination region and the dicing line region are defined, a side monitor electrode provided on the semiconductor substrate in the dicing line region, a passivation film provided from an upper portion of the semiconductor substrate in the termination region to an upper portion of the side monitor electrode, and a coating film provided on the passivation film in the termination region, a thickness of the side monitor electrode is smaller than a thickness of the coating film, and a relationship of 15>b>1.15×d+6.88 is satisfied between a distance b [μm] between the coating film and the side monitor electrode and a length d [mm] of the side monitor electrode in an extension direction of the dicing line region in a planar view. Effect of the Invention

[0007] According to the present disclosure, the thickness of the side monitor electrode is smaller than that of the coating film, and the relationship between the distance b [μm] between the coating film and the side monitor electrode and the length d [mm] of the side monitor electrode in the extension direction of the dicing line region in a plan view is 15>b>1.15×d+6.88. With this configuration, it is possible to reduce the ineffective area and suppress peeling of the coating film. [Brief description of the drawings]

[0008] [Figure 1] 1 is a plan view showing a configuration of a semiconductor structure according to a first embodiment. [Diagram 2] 1 is a plan view showing a configuration of a semiconductor structure according to a first embodiment. [Diagram 3]1 is a cross-sectional view showing a configuration of a semiconductor structure according to a first embodiment. [Figure 4] 5A to 5C are diagrams showing experimental results for the semiconductor structure according to the first embodiment. [Diagram 5] FIG. 11 is a cross-sectional view showing a configuration of a semiconductor structure according to a second embodiment. [Figure 6] FIG. 11 is a plan view showing a configuration of a semiconductor structure according to a second embodiment. [Figure 7] FIG. 11 is a plan view showing a configuration of a semiconductor structure according to a modified example of the second embodiment. [Figure 8] FIG. 11 is a cross-sectional view showing a configuration of a semiconductor structure according to a modified example of the second embodiment. [Figure 9] FIG. 11 is a cross-sectional view showing a configuration of a semiconductor structure according to a modified example of the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, the embodiments will be described with reference to the accompanying drawings. The features described in each of the following embodiments are merely examples, and not all features are necessarily required. In addition, in the following description, similar components in multiple embodiments are given the same or similar reference numerals, and different components are mainly described. In addition, in the following description, specific positions and directions such as "upper", "lower", "left", "right", "front" or "back" do not necessarily correspond to positions and directions in actual implementation.

[0010] <Embodiment 1> 1 is a plan view showing the configuration of a semiconductor structure according to the first embodiment. The semiconductor structure is prepared in a semiconductor structure preparation step during the manufacturing process of a semiconductor device. In the semiconductor structure, a cell structure region 11a and a termination region 11b of a semiconductor chip 11, and a dicing line region 12 are defined.

[0011] Semiconductor elements are provided in the cell structure region 11a. The semiconductor elements include at least one of MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), RC-IGBTs (Reverse Conducting - IGBTs), SBDs (Schottky Barrier Diodes), and PNDs (PN junction diodes). In this specification, for example, at least one of A, B, C, ..., and Z means any one of all combinations of one or more elements extracted from the group of A, B, C, ..., and Z.

[0012] The termination region 11b is a region that surrounds the cell structure region 11a in a plan view and maintains the withstand voltage of the cell structure region 11a.

[0013] The dicing line region 12 is a region provided between adjacent semiconductor chips 11 in a plan view and adjacent to the termination region 11b of each semiconductor chip 11. The semiconductor chips 11 are separated and individualized by a dicing process in which dicing is performed on the dicing line region 12 of the semiconductor structure. The width of the dicing line region 12 is often, for example, 80 to 120 μm to ensure a width through which a dicing blade such as a grindstone blade can pass.

[0014] Fig. 2 is an enlarged plan view of a portion surrounded by a dashed line in Fig. 1, and Fig. 3 is a cross-sectional view taken along line A-A' in Fig. 2. As shown in Fig. 2 and Fig. 3, the semiconductor structure includes a semiconductor substrate 1, a side monitor electrode 2, a passivation film 3, and a covering film 4.

[0015] The semiconductor substrate 1 in FIG. 3 is made of, for example, silicon (Si) or a wide band gap semiconductor, and includes at least one of a normal semiconductor wafer and an epitaxial growth layer. Wide band gap semiconductors include, for example, silicon carbide (SiC), gallium nitride (GaN), diamond, etc. When the semiconductor substrate 1 is made of a wide band gap semiconductor, stable operation under high temperature and high voltage and high switching speed are possible for the semiconductor element. However, since the price of the semiconductor substrate 1 made of SiC is high, it is required to reduce the invalid area in the semiconductor substrate 1 as much as possible from the viewpoint of reducing the cost of the semiconductor device. In contrast, according to the present embodiment 1, it is possible to reduce the invalid area in the semiconductor substrate 1 as described below.

[0016] 1 is provided on the semiconductor substrate 1, and a cell structure region 11a, a termination region 11b, and a dicing line region 12 are defined. A front surface electrode of the semiconductor chip 11 is formed on the front surface of the semiconductor substrate 1, and a back surface electrode of the semiconductor chip 11 is formed on the back surface of the semiconductor substrate 1. Note that the back surface of the semiconductor substrate 1 may be ground before the back surface electrode is formed.

[0017] As shown in FIG. 3, the side monitor electrode 2 is provided on the semiconductor substrate 1 in the dicing line region 12. The side monitor electrode 2 is provided to find abnormalities during the manufacturing process of the semiconductor device. For example, a diffusion layer is provided on the semiconductor substrate 1 under the side monitor electrode 2, and the diffusion layer is formed simultaneously with the cell diffusion layer constituting the semiconductor element in the cell structure region 11a. An operator can find abnormalities during the manufacturing process at a relatively early stage by electrically connecting a probe to the side monitor electrode 2 and measuring the resistance of the diffusion layer under the side monitor electrode 2 before dicing. In addition, in the unlikely event that an operator finds a characteristic defect in the semiconductor chip 11, the operator can trace back and identify the abnormal process by analyzing the measured value of the side monitor electrode 2. In addition, an operator can also realize line management by comparing the transition of the characteristic value obtained from the side monitor electrode 2.

[0018] The side monitor electrode 2 is provided in at least one location in the dicing line region 12 in the exposure shot. Although it depends on the size of the semiconductor chip 11, it is preferable to provide multiple side monitor electrodes 2 in a size that fits on one side of the semiconductor chip 11. Since marks for alignment during the exposure process are often provided at the intersections where the dicing line regions 12 intersect, it is preferable not to provide a side monitor electrode 2 at the intersections. The side monitor electrode 2 is made of, for example, AlSi.

[0019] The passivation film 3 is provided from the upper part of the semiconductor substrate 1 in the termination region 11b to the upper part of the side monitor electrode 2. The passivation film 3 provided as an insulating film on the semiconductor substrate 1 in the termination region 11b has the function of suppressing creeping discharge of the semiconductor chip 11, similar to the covering film 4 described below. The passivation film 3 has an opening that partially exposes the upper part of the side monitor electrode 2 that is electrically connected to the probe. For example, a silicon oxide film or nitride film is deposited on the upper surface of the semiconductor substrate 1, and then etched through a resist in a photolithography process to form a pattern of the passivation film 3.

[0020] The coating film 4 is provided on the passivation film 3 in the termination region 11b. If the coating film 4 gets caught in the grinding blade during dicing, it may cause clogging, reducing productivity, or chipping, which is the occurrence of chipping at the end of the semiconductor chip 11. For this reason, as shown in Figures 2 and 3, the coating film 4 exposes the passivation film 3 in the dicing line region 12.

[0021] The coating film 4 is made of, for example, photosensitive polyimide. The pattern of the coating film 4 is formed by a development step included in the preparation step of the semiconductor structure. For example, a photosensitive polyimide precursor solution is applied onto the semiconductor substrate 1 on which the passivation film 3 is provided, and then pre-baked, and then formed into an arbitrary pattern by a photolithography process, and then baked to form the coating film 4. If the photosensitive polyimide is applied to the wafer and then selectively exposed to light using a mask, the exposed portion will dissolve in the developer, and the coating film 4 can be formed in an arbitrary pattern.

[0022] The coating film 4 provided as an insulating film on the passivation film 3 in the termination region 11b has a function of suppressing creeping discharge of the semiconductor chip 11. In addition, since the coating film 4 made of polyimide has flexibility, it has a function of protecting the structure of the termination region 11b of the semiconductor chip 11 from stresses caused by the expansion and contraction of external sealing materials. After the back surface of the semiconductor substrate 1 is ground so that the thickness of the semiconductor substrate 1 becomes, for example, about 100 μm or less, the warping of the semiconductor substrate 1 after the grinding process becomes large, making it difficult to form the passivation film 3 or the coating film 4. For this reason, it is preferable to form the passivation film 3 or the coating film 4 before the grinding process of the semiconductor substrate 1.

[0023] According to the above-mentioned configuration, since the side monitor electrode 2 is provided on the dicing line region 12, a region dedicated to the side monitor electrode 2 is not required. This makes it possible to reduce the ineffective region in the semiconductor substrate 1. However, since a recess is formed between the side monitor electrode 2 and the coating film 4 as shown in FIG. 3, there is a possibility that the developer used to form the coating film 4 may accumulate in this recess, causing the coating film 4 to peel off. Therefore, the inventors conducted an experiment to investigate a configuration in which the coating film 4 does not peel off.

[0024] Fig. 4 shows the experimental results. In this experiment, when the thickness c of the side monitor electrode 2 is smaller than the thickness a of the coating film 4, the distance between the coating film 4 and the side monitor electrode 2 was set to b [μm], and the length of the side monitor electrode in the extension direction of the dicing line region 12 in a plan view was set to d [mm]. Note that the distance b is shown in Fig. 3, and the length d is shown in Fig. 2.

[0025] 4, when 15[μm]>b>1.15×d+6.88, preferably 10[μm]b>1.15×d+6.88, peeling of the coating film 4 is suppressed. Therefore, the semiconductor structure according to the first embodiment is configured so that 15[μm]>b>1.15×d+6.88 is satisfied. If this formula is satisfied, peeling of the coating film 4 is suppressed even when the length d is greater than 100 μm.

[0026] <Summary of the first embodiment> According to the manufacturing method of the semiconductor device according to the first embodiment as described above, a semiconductor structure in which the side monitor electrode 2 is provided on the dicing line region 12 is used. With this configuration, the ineffective region in the semiconductor substrate 1 can be reduced. In addition, in the first embodiment, the relationship 15>b>1.15×d+6.88 is satisfied between the distance b [μm] between the coating film 4 and the side monitor electrode 2 in a plan view and the length d [mm] of the side monitor electrode 2 in the extending direction of the dicing line region 12 in a plan view. With this configuration, it is possible to prevent the developer from staying in the recess between the side monitor electrode 2 and the coating film 4, and to prevent the coating film 4 from peeling off. As a result, it is possible to prevent the reliability of the semiconductor device from deteriorating and the occurrence of abnormal appearance.

[0027] In addition, when the passivation film 3 is, for example, a glass coating film containing silicon nitride (SiN), the adhesion between the passivation film 3 and the coating film 4 can be improved more than the adhesion between the semiconductor substrate 1 and the coating film 4. Therefore, even if the developer remains in the recesses, it is possible to prevent the coating film 4 from peeling off due to the developer seeping into between the passivation film 3 and the coating film 4.

[0028] Furthermore, when the semiconductor substrate 1 is made of SiC, it is possible to reduce the ineffective region in the expensive semiconductor substrate 1, thereby reducing the cost of the semiconductor device.

[0029] <Embodiment 2> Fig. 5 is a cross-sectional view showing the configuration of a semiconductor structure according to the second embodiment, and corresponds to Fig. 3. In the semiconductor structure according to the second embodiment, a surplus region 13 is defined between the termination region 11b and the dicing line region 12. The surplus region 13 is a region outside the depletion layer at the end of the semiconductor chip 11. The semiconductor substrate 1, the passivation film 3, and the coating film 4 are also provided in the surplus region 13, similarly to the termination region 11b.

[0030] The semiconductor structure includes one or more insulating films 5 in addition to the configuration of FIG. 3. FIG. 6 is a plan view showing the configuration of the excess region 13. The insulating film 5 is provided only in the excess region 13 and between the passivation film 3 and the semiconductor substrate 1. As a result, as shown in FIG. 5, only in the excess region 13 and in the passivation film 3 and the coating film 4, unevenness 6 that fits with each other in a cross-sectional view and corresponds to the shape of the insulating film 5 is provided. The number of unevenness 6 may be one, or multiple unevennesses 6 may be provided at intervals. The insulating film 5 is made of, for example, TEOS (tetra ethoxy silane).

[0031] <Summary of the second embodiment> According to the manufacturing method of the semiconductor device of the second embodiment as described above, the passivation film 3 and the coating film 4 are provided with the irregularities 6 that fit together in a cross-sectional view and correspond to the shape of the insulating film 5. With such a configuration, the surface area of ​​the interface between the passivation film 3 and the coating film 4 can be increased, thereby improving the adhesion between them. As a result, even if the developer remains in the recesses, it is possible to prevent the coating film 4 from peeling off due to the developer seeping into between the passivation film 3 and the coating film 4.

[0032] Moreover, in the second embodiment, the irregularities 6 are provided only in the surplus region 13. With such a configuration, the surplus region 13 can be effectively utilized.

[0033] <Modification> 5 and 6, the insulating films 5 are arranged in a line in the direction from the termination region 11b toward the dicing line region 12, but this is not limited thereto. For example, as shown in FIG. 7, the insulating films 5 may be arranged in both the direction from the termination region 11b toward the dicing line region 12 and the direction perpendicular thereto. Also, for example, the insulating films 5 may be arranged continuously or discontinuously so as to go around the surplus region 13. The number, size, and arrangement of the insulating films 5 are not limited to those described above.

[0034] 5, the side surface of the insulating film 5 is perpendicular to the bottom surface of the insulating film 5. However, as shown in FIG. 8, the taper angle of the insulating film 5 may be less than 90° so that the insulating film 5 has a tapered shape tapering toward the upper side in a cross-sectional view. With such a configuration, the shape of the unevenness 6 between the passivation film 3 and the coating film 4 becomes smooth and air bubbles are less likely to occur between the passivation film 3 and the coating film 4, so that the adhesion between the passivation film 3 and the coating film 4 can be improved.

[0035] In the second embodiment, the irregularities 6 are provided only in the surplus region 13. However, if there is no need to effectively utilize the surplus region 13, the irregularities 6 may be provided in the termination region 11b. As shown in FIG. 9, by providing a surface electrode 11c of the semiconductor chip 11 instead of the insulating film 5, the passivation film 3 and the covering film 4 may be provided with irregularities 6 that fit together in a cross-sectional view and correspond to the shape of the surface electrode 11c. Even in this case, the same effect as in the second embodiment can be obtained.

[0036] It should be noted that the embodiments and modifications may be freely combined, and the embodiments and modifications may be modified or omitted as appropriate.

[0037] Various aspects of the present disclosure are summarized below as appendices.

[0038] (Appendix 1) A preparation step of preparing a semiconductor structure in which a termination region of a semiconductor chip and a dicing line region adjacent to the termination region in a plan view are defined; a dicing step of dicing the dicing line region; Equipped with The semiconductor structure comprises: a semiconductor substrate having the termination region and the dicing line region defined therein; a side monitor electrode provided on the semiconductor substrate in the dicing line region; a passivation film provided from an upper portion of the semiconductor substrate in the termination region to an upper portion of the side monitor electrode; a coating film provided on the passivation film in the termination region; Including, the thickness of the side monitor electrode is smaller than the thickness of the coating film; a distance b [μm] between the covering film and the side monitor electrode and a length d [mm] of the side monitor electrode in an extension direction of the dicing line region in a planar view, the relationship being 15>b>1.15×d+6.88.

[0039] (Appendix 2) A method for manufacturing the semiconductor device according to claim 1, comprising the steps of: A method for manufacturing a semiconductor device, wherein the distance b is 7 μm or more, and the length d is greater than 100 μm.

[0040] (Appendix 3) A method for manufacturing a semiconductor device according to claim 1 or 2, comprising the steps of: the semiconductor structure further includes one or more insulating films disposed between the passivation film and the semiconductor substrate; The method for manufacturing a semiconductor device, wherein the passivation film and the covering film are provided with projections and recesses that fit together in a cross-sectional view and correspond to a shape of the insulating film.

[0041] (Appendix 4) A method for manufacturing a semiconductor device according to claim 1 or 2, comprising the steps of: the semiconductor structure further defines a redundancy region between the termination region and the dicing line region; the semiconductor substrate, the passivation film, and the covering film are provided in the excess region; the semiconductor structure further includes one or more insulating films disposed between the passivation film and the semiconductor substrate; a step of forming a mask pattern on the insulating film by forming a mask only on the excess region and on the passivation film and the covering film;

[0042] (Appendix 5) A method for manufacturing a semiconductor device according to claim 3 or 4, comprising the steps of: The method for manufacturing a semiconductor device, wherein the insulating film has a taper angle of less than 90°.

[0043] (Appendix 6) A method for manufacturing a semiconductor device according to any one of claims 1 to 5, comprising the steps of: the semiconductor structure further includes one or more surface electrodes disposed between the passivation film and the semiconductor substrate; A method for manufacturing a semiconductor device, wherein the passivation film and the covering film in a cross-sectional view are provided with projections and recesses that fit together in a cross-sectional view and correspond to a shape of the surface electrode.

[0044] (Appendix 7) A method for manufacturing a semiconductor device according to any one of claims 1 to 6, comprising the steps of: The semiconductor substrate is made of SiC.

[0045] (Appendix 8) A method for manufacturing a semiconductor device according to any one of claims 1 to 7, comprising the steps of: The method for manufacturing a semiconductor device, wherein the preparation step includes a development step of forming a pattern of the coating film. [Explanation of symbols]

[0046] 1 semiconductor substrate, 2 side monitor electrode, 3 passivation film, 4 coating film, 5 insulating film, 6 unevenness, 11 semiconductor chip, 11b termination region, 11c surface electrode, 12 dicing line region, 13 excess region.

Claims

1. A preparation step of preparing a semiconductor structure in which a termination region of a semiconductor chip and a dicing line region adjacent to the termination region in a plan view are defined; a dicing step of dicing the dicing line region; Equipped with The semiconductor structure comprises: a semiconductor substrate having the termination region and the dicing line region defined therein; a side monitor electrode provided on the semiconductor substrate in the dicing line region; a passivation film provided from an upper portion of the semiconductor substrate in the termination region to an upper portion of the side monitor electrode; a coating film provided on the passivation film in the termination region; Including, the thickness of the side monitor electrode is smaller than the thickness of the coating film; a distance b [μm] between the covering film and the side monitor electrode and a length d [mm] of the side monitor electrode in an extension direction of the dicing line region in a plan view, the relationship being 15>b>1.15×d+6.

88.

2. 2. The method of manufacturing a semiconductor device according to claim 1, The method for manufacturing a semiconductor device, wherein the distance b is 7 μm or more, and the length d is greater than 100 μm.

3. 3. A method for manufacturing a semiconductor device according to claim 1, further comprising the steps of: the semiconductor structure further includes one or more insulating films disposed between the passivation film and the semiconductor substrate; The method for manufacturing a semiconductor device, wherein the passivation film and the covering film are provided with projections and recesses that fit together in a cross-sectional view and correspond to a shape of the insulating film.

4. 3. A method for manufacturing a semiconductor device according to claim 1, further comprising the steps of: the semiconductor structure further defines a redundancy region between the termination region and the dicing line region; the semiconductor substrate, the passivation film, and the covering film are provided in the excess region; the semiconductor structure further includes one or more insulating films disposed between the passivation film and the semiconductor substrate; a step of forming a mask pattern on the insulating film by forming a mask only on the excess region and on the passivation film and the covering film;

5. 4. The method of manufacturing a semiconductor device according to claim 3, The method for manufacturing a semiconductor device, wherein the insulating film has a taper angle of less than 90°.

6. 3. A method for manufacturing a semiconductor device according to claim 1, further comprising the steps of: the semiconductor structure further includes one or more surface electrodes disposed between the passivation film and the semiconductor substrate; A method for manufacturing a semiconductor device, wherein the passivation film and the covering film in a cross-sectional view are provided with projections and recesses that fit together in a cross-sectional view and correspond to a shape of the surface electrode.

7. 3. A method for manufacturing a semiconductor device according to claim 1, further comprising the steps of: The semiconductor substrate is made of SiC.

8. 3. A method for manufacturing a semiconductor device according to claim 1, further comprising the steps of: The method for manufacturing a semiconductor device, wherein the preparation step includes a development step of forming a pattern of the coating film.

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