Printed circuit board

Abstract

To provide a printed circuit board capable of performing die-to-die interconnection in a printed circuit board for mounting electronic components, semiconductor chips, etc., implementing the function of an element in addition to the die-to-die interconnection, and improving reliability.SOLUTION: A printed circuit board includes a substrate portion having a first insulating layer and a first wiring layer disposed on or inside the first insulating layer, and a connecting structure that is disposed on or inside the substrate portion, and includes a plurality of first dielectric layers, a first metal layer and a second metal layer disposed on the plurality of first dielectric layers, a second insulating layer disposed on the plurality of first dielectric layers, and a second wiring layer disposed on the second insulating layer. Each of the plurality of first dielectric layers includes an organic material, and the distance between the first metal layer and the second metal layer is shorter than the distance between the first metal layer and the second wiring layer.SELECTED DRAWING: Figure 3a

Description

[Technical field]

[0001] The present disclosure relates to printed circuit boards. [Background technology]

[0002] Recently, with the development of artificial intelligence (AI) technology, etc., multi-chip packages including memory chips such as HBM (High Bandwidth Memory) and processor chips such as CPU (Central Processing Unit), GPU (Graphics Processing Unit), ASIC (Application Specific Integrated Circuit), FPGA (Field Programmable Gate Array), etc. are being used to process data that has increased exponentially. In particular, as the number of CPU and GPU cores in server products increases rapidly, die split technology that can effectively increase the number of cores has become commonplace, and die-to-die interconnection is being demanded. Research is ongoing to design a substrate to include a connecting structure that performs die-to-die interconnection, to simplify substrate and package structures, and to increase yield while improving the reliability of the connecting structure. Summary of the Invention [Problem to be solved by the invention]

[0003] One of several objects of the present disclosure is to provide a printed circuit board capable of providing die-to-die interconnections on a printed circuit board for mounting electronic components, semiconductor chips, and the like.

[0004] Another of several objects of the present disclosure is to provide a printed circuit board including interconnect structures capable of implementing component functions in addition to die-to-die interconnects.

[0005] Another of several objects of the present disclosure is to provide a printed circuit board that can improve reliability. [Means for solving the problem]

[0006] One of several solutions proposed throughout the present disclosure is to provide a printed circuit board comprising: a substrate portion including a first insulating layer, a first wiring layer disposed on or within the first insulating layer; and a connecting structure disposed on or within the substrate portion, the connecting structure including a plurality of first dielectric layers, first and second metal layers disposed on the plurality of first dielectric layers, a second insulating layer disposed on the plurality of first dielectric layers, and a second wiring layer disposed on the second insulating layer, each of the plurality of first dielectric layers comprising an organic material, and a distance between the first metal layer and the second metal layer being closer than the distance between the first metal layer and the second wiring layer.

[0007] Another of several solutions proposed through the present disclosure is to provide a printed circuit board including a connecting structure including a substrate portion including a first insulating layer, a first wiring layer disposed on or within the first insulating layer, and a capacitor portion disposed on or within the substrate portion and composed of a first dielectric layer and a first metal layer disposed on or within the first dielectric layer, and a wiring portion composed of a second insulating layer and a second wiring layer disposed on the second insulating layer, wherein the first metal layer of the capacitor portion includes a pair of metal plates facing each other, and the first dielectric layer of the capacitor portion includes an organic material. Effect of the Invention

[0008] Among the various advantages of the present disclosure, one advantage is that it provides a printed circuit board capable of performing die-to-die interconnections on a printed circuit board for mounting electronic components, semiconductor chips, and the like.

[0009] Among other advantages of the present disclosure is the provision of a printed circuit board that includes interconnect structures that can provide component functionality in addition to die-to-die interconnects.

[0010] Another advantage of the present disclosure is that it is possible to provide a printed circuit board that can improve reliability. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a block diagram illustrating an example of an electronic device system. [Diagram 2] FIG. 1 is a perspective view illustrating an example of an electronic device. [Figure 3a] FIG. 1 is a cross-sectional view illustrating a schematic diagram of a printed circuit board according to an example. [Figure 3b] FIG. 1 is a cross-sectional view illustrating a schematic diagram of a printed circuit board according to an example. [Figure 4] FIG. 11 is a cross-sectional view illustrating a printed circuit board according to another example. [Diagram 5] FIG. 11 is a cross-sectional view showing a schematic configuration of a printed circuit board according to another embodiment of the present invention. [Figure 6a] 1 is a cross-sectional view showing a schematic diagram of a connection structure of a printed circuit board according to an example. [Figure 6b] 2 is a perspective view showing a schematic diagram of a capacitor part of a connection structure of a printed circuit board according to an example; [Figure 7a] FIG. 11 is a cross-sectional view showing a schematic configuration of a connection structure according to another example. [Figure 7b] FIG. 11 is a perspective view showing a capacitor portion of a connection structure according to another example. [Figure 8a] FIG. 11 is a cross-sectional view showing a schematic diagram of a connection structure according to another example. [Figure 8b] FIG. 11 is a perspective view showing a capacitor portion of a connection structure according to another example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, the present disclosure will be described with reference to the accompanying drawings. The shapes and sizes of elements in the drawings may be scaled (or highlighted or simplified) for a clearer description.

[0013] electronic equipment FIG. 1 is a block diagram illustrating an example of an electronic device system.

[0014] Referring to the drawing, an electronic device 1000 accommodates a main board 1010. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected to the main board 1010. These are also coupled to other electronic components described below to form various signal lines 1090.

[0015] The chip-related components 1020 include, but are not limited to, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processors (e.g., CPU), graphic processors (e.g., GPU), digital signal processors, encryption processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). In addition, these chip-related components 1020 may be combined with each other. The chip-related components 1020 may be in the form of a package including the above-mentioned chips and electronic components.

[0016] The network-related components 1030 may include, but are not limited to, any other wireless and wired protocols designated as Wi-Fi (such as the IEEE 802.11 family), WiMAX (such as the IEEE 802.16 family), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G, and beyond, and may include any of numerous other wireless or wired standards and protocols. The network-related components 1030 may also be combined with the chip-related components 1020 together.

[0017] The other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (low temperature co-firing ceramics), EMI (electromagnetic interference) filters, MLCC (multi-layer ceramic capacitors), etc. However, the other components 1040 are not limited to these, and may include passive elements in the form of chip components used for various other applications. The other components 1040 may also be combined with the chip-related components 1020 and / or the network-related components 1030.

[0018] Depending on the type of electronic device 1000, the electronic device 1000 may include other electronic components that may or may not be physically and / or electrically connected to the main board 1010. Examples of other electronic components include, but are not limited to, a camera module 1050, an antenna module 1060, a display 1070, and a battery 1080. Other electronic components may include, but are not limited to, an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a compact disk (CD), a digital versatile disk (DVD), and the like. In addition, other electronic components used for various purposes may be included depending on the type of electronic device 1000.

[0019] The electronic device 1000 may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, etc. However, the electronic device 1000 is not limited to these, and may be any other electronic device that processes data.

[0020] FIG. 2 is a perspective view that illustrates an example of an electronic device.

[0021] Referring to the drawings, the electronic device may be, for example, a smartphone 1100. A motherboard 1110 is housed inside the smartphone 1100, and various components 1120 are physically and / or electrically connected to the motherboard 1110. In addition, other components, such as a camera module 1130 and / or a speaker 1140, which may or may not be physically and / or electrically connected to the motherboard 1110, are housed inside the smartphone 1100. Some of the components 1120 may be the above-mentioned chip-related components, for example, a component package 1121, but are not limited thereto. The component package 1121 may be in the form of a printed circuit board on which electronic components including active components and / or passive components are mounted on a surface. Alternatively, the component package 1121 may be in the form of a printed circuit board in which active components and / or passive components are built in. Meanwhile, the electronic device is not necessarily limited to the smartphone 1100, and may be other electronic devices as described above.

[0022] Printed Circuit Board 3a and 3b are schematic cross-sectional views of a printed circuit board according to an example.

[0023] 3a, the printed circuit board according to an example includes a substrate part 100 and a connecting structure 200. The substrate part 100 is a part that realizes a signal path of the printed circuit board, and the connecting structure 200 corresponds to a part that connects components such as chips to each other. The connecting structure 200 is a part that realizes a fine signal path corresponding to an electronic component such as a fine chip, and a plurality of electronic components such as chips can be arranged with the connecting structure 200 sandwiched therebetween, and corresponds to a part that interconnects electronic components such as chips and maintains an electrical signal path.

[0024] The substrate unit 100 may include a first insulating layer 110, a first wiring layer 120 disposed on or within the first insulating layer 110, and a cavity penetrating at least a portion of the first insulating layer 110. The substrate unit 100 may include a first via layer 130 penetrating at least a portion of the first insulating layer 110 to connect the first wiring layers 120 to each other.

[0025] The first insulating layer 110 may be composed of a plurality of insulating layers, and each of the first insulating layers 110 may include an insulating material. The insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material including such a resin together with an inorganic filler, an organic filler, and / or glass fiber (glass fiber, glass cloth, and / or glass fabric). The insulating material may be a photosensitive material and / or a non-photosensitive material. For example, the insulating material of the first insulating layer 110 may be, but is not limited to, an insulating material such as PPG (Prepreg) or RCC (Resin Coated Copper), and may be, but is not limited to, ABF (Ajinomoto Build-up Film), PID (Photo Imageable Dielectric), FR-4, BT (Bismaleimide Triazine), and the like. However, the insulating material is not limited to these, and other polymeric materials having excellent rigidity may be used as necessary.

[0026] The first wiring layer 120 may be composed of a plurality of wiring layers, and each of the first wiring layers 120 may include a metal material. The metal material may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The first wiring layers 120 may include, but are not limited to, an electroless plating layer (or chemical copper) as a seed layer and an electrolytic plating layer (or electrolytic copper) as a plating layer. A sputtering layer may be formed as the electroless plating layer instead of chemical copper. If necessary, a copper foil may be further included. The first wiring layers 120 may perform various functions according to the design of the corresponding layers. For example, they may include a ground pattern, a power pattern, a signal pattern, etc. Here, the signal pattern may include various signals other than the ground pattern, the power pattern, etc., such as a data signal. These patterns may include a line pattern, a plane pattern, and / or a pad pattern.

[0027] The first via layer 130 may be composed of a plurality of via layers, and each of the first via layers 130 may include a microvia. The microvia may be a filled via that fills a via hole, or a conformal via that is arranged along the wall surface of the via hole. The microvia may be arranged in a stacked type and / or staggered type. Each of the first via layers 130 may include a metal material. The metal material may include a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. Each of the connection via layers may include, but is not limited to, an electroless plating layer (or chemical copper) as a seed layer and an electrolytic plating layer (or electrolytic copper) as a plating layer. A sputtering layer may be formed instead of chemical copper as the electroless plating layer. The first via layer 130 may perform various functions depending on the design of the layer. For example, the vias may include ground vias, power vias, signal vias, etc. Here, the signal vias may include vias for transmitting various signals, such as data signals, other than the ground vias and power vias.

[0028] Each of the first wiring layers 120 and each of the first via layers 130 may be formed integrally with each other, but is not limited thereto. The first wiring layers 120 and / or the first via layers 130 may be formed by any one of a semi-additive process (SAP), a modified semi-additive process (MSAP), a tenting (TT), or a subtractive process, but is not limited thereto, and any process capable of forming a circuit on a printed circuit board may be used without limitation.

[0029] The fact that the first wiring layer 120 is disposed on or in the first insulating layer 110 means that the first wiring layer 120 can be disposed on the first insulating layer 110 or disposed so as to be embedded in the first insulating layer 110, and may mean that the first wiring layer 120 may have a so-called coreless type substrate structure in which the first wiring layer 120 is embedded in the first insulating layer 110. In particular, referring to FIG. 3, the first wiring layer 120 disposed on the bottom side may have a structure embedded in the first wiring layer 110.

[0030] Meanwhile, in FIG. 3a and FIG. 3b, the first insulating layer 110 is expressed as being composed of four layers, and the first wiring layer 120 and the first via layer 130 are expressed as having a corresponding number, but the present invention is not limited thereto, and the number of layers of the first insulating layer 110, the first wiring layer 120, and the first via layer 130 can be changed according to the design. In particular, the first insulating layer 110 may further include a core insulating layer including a core, the first wiring layer 120 may include a copper foil, and the first via layer 130 may also include a through via penetrating the core insulating layer. In this way, the first insulating layer 110, the first wiring layer 120, and the first via layer 130 of the printed circuit board according to the example may have a configuration that can be used by a person having ordinary knowledge in the technical field of printed circuit boards.

[0031] The cavity may penetrate at least a portion of the first insulating layer 110. The cavity may correspond to a position where the connection structure 200 is mounted. The cavity may penetrate at least a portion of the first insulating layer 110, which may mean penetrating any continuous first insulating layer 110 among the plurality of first insulating layers 110, or may mean penetrating only a portion of any first insulating layer 110, and may mean penetrating any continuous first insulating layer 110 while penetrating a portion of any other first insulating layer 110. Although not shown in FIG. 3a and FIG. 3b, when the cavity penetrates only a portion of any first insulating layer 110, the upper surface of the corresponding first insulating layer 110 may have a step.

[0032] The method for forming the cavity may be any method used in a known cavity forming process without limitation. For example, a mechanical drilling process such as laser processing or a blasting process may be used, but is not limited thereto. In this case, a part of the first wiring layer 120 disposed on the first insulating layer 110 may function as a stopper layer, and another stopper layer may be disposed on the upper surface of the first insulating layer 110 in advance and then removed by etching after the cavity processing. When a stopper layer is formed, the stopper layer may be formed simultaneously with the first insulating layer 120. The wall surface of the cavity penetrating at least a part of the first insulating layer 110 may be formed by the side surface of the first insulating layer 110, and the bottom surface of the cavity may be formed by the top surface of the first insulating layer 110. Meanwhile, although not shown in FIG. 3a and FIG. 3b, the bottom surface of the cavity may be formed by a stopper layer.

[0033] The printed circuit board according to an example includes a connection structure 200. The connection structure 200 may be disposed in a cavity, and may include a wiring portion 201 and a capacitor portion 202.

[0034] The wiring portion 201 of the connecting structure 200 may include a second insulating layer 210, a second wiring layer 220 disposed on or within the second insulating layer 210, and a second via layer 230 penetrating at least a portion of the second insulating layer 210 to connect the second wiring layer 220 to each other.

[0035] The capacitor unit 202 of the connection structure 200 may include a plurality of first dielectric layers 240, a first metal layer 251 and a second metal layer 252 disposed on or within the plurality of first dielectric layers 240. The first metal layer 251 may include a first metal plate 261 and a first connection pad 271 spaced apart from the first metal plate 261, and the second metal layer 252 may include a second metal plate 262 and a second connection pad 272 spaced apart from the second metal plate 262. The capacitor unit 202 may include a first connection via 281 and a second connection via 282. The first connecting via 281 may penetrate at least a part of the plurality of first dielectric layers 240 and / or at least a part of the second insulating layer 210 to connect the second wiring layer 220 and the first metal plate 261, and the second connecting via 282 may penetrate at least a part of the plurality of first dielectric layers 240 and / or at least a part of the second insulating layer 210 to connect the second wiring layer 220 and the second metal plate 262. The second connecting via 282 may connect the second wiring layer 220 and the second metal plate 262 through the first connecting pad 271.

[0036] The wiring unit 201 of the connection structure 200 may have a higher wiring density than the substrate unit 100. Higher wiring density is a relative concept, and may mean, for example, that the average pitch of the wiring included in the second wiring layer 220 may be smaller than the average pitch of the wiring included in the first wiring layer 120. The pitch may be measured by photographing a cross section of the printed circuit board cut with a scanning microscope, and the average pitch may be an average value of the pitch between the wirings measured at any five points. In addition, the average interlayer insulation distance between the second wiring layers 220 may be smaller than the average interlayer insulation distance between the first wiring layers 120. The interlayer insulation distance may also be measured by photographing a cross section of the printed circuit board cut with a scanning microscope, and the average interlayer insulation distance may be an average value of the insulation distance between adjacent wiring layers measured at any five points. In other words, the wiring included in the second wiring layer 220 may be a high-density circuit having a smaller L / S (line / space) than the wiring included in the first wiring layer 120. As a non-limiting example, the wiring included in the second wiring layer 220 may have a line / space of about 2 / 2 μm, but is not limited thereto. The wiring portion 201 of the connection structure 200 has a higher density than the wiring of the substrate portion 100, and thus may be effective in interconnecting electronic components such as semiconductor chips. That is, it may be effective for die-to-die interconnection.

[0037] In this sense, the thickness of the second insulating layer 210 may be thinner than the thickness of the first insulating layer 110, and the thickness of the second wiring layer 220 may be thinner than the thickness of the first wiring layer 120. The thickness of the insulating layer is a concept including a rough one, and may mean the vertical distance between the upper surface and the lower surface of the insulating layer. The thickness of the second insulating layer 210 is thinner than the thickness of the first insulating layer 110, and may mean that the thickness of any one of the second insulating layers 210 among the plurality of second insulating layers 210 is thinner than the thickness of any one of the first insulating layers 110 among the plurality of first insulating layers 110, but is not limited thereto. The thicknesses of the first insulating layer 110 and the second insulating layer 210 may be measured by photographing a cross section of the printed circuit board cut with a scanning microscope, and may be the average value of the thicknesses of the insulating layers measured at any five points. The thickness of the wiring layer may be interpreted in the same sense as the thickness of the insulating layer.

[0038] Other configurations of the connecting structure will be described in detail later.

[0039] The printed circuit board according to an example may further include an adhesive layer 300. The connection structure 200 is disposed in a cavity of the substrate part 100, and the connection structure 200 may be attached to a bottom surface of the cavity via the adhesive layer 300. The adhesive layer 300 may be disposed to cover a lower surface of the connection structure 200. The adhesive layer 300 may be an adhesive film such as a general die attach film (DAF), but is not limited thereto, and may be a known tape, etc., and may be used without limitation as long as it is a means capable of attaching other components, such as electronic components or a connection structure, to the printed circuit board.

[0040] 3b, the printed circuit board according to an example may include a first semiconductor chip 401 disposed on a portion of the substrate unit 100 and a portion of the connecting structure 200, and a second semiconductor chip 402 disposed on a portion of the substrate unit 100 and a portion of the connecting structure 200, and may include a connecting member 500 that connects the first semiconductor chip 401 and the second semiconductor chip 402 to the substrate unit 100 and the connecting structure 200, respectively. The first semiconductor chip 401 may be disposed to be electrically connected to a portion of the substrate unit 100 and a portion of the connecting structure 200, and the second semiconductor chip 402 may be electrically connected to a portion of the substrate unit 100 and a portion of the connecting structure 200, and may be electrically connected to the first semiconductor chip 401 via the connecting structure 200.

[0041] Each of the first semiconductor chip 401 and the second semiconductor chip 402 may include an integrated circuit (IC) die in which hundreds to millions of elements are integrated in one chip. In this case, the integrated circuit may be, for example, a logic chip such as a central processor (e.g., CPU), a graphic processor (e.g., GPU), a field programmable gate array (FPGA), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, an application processor (e.g., AP), an analog-to-digital converter, or an application-specific IC (ASIC), but is not limited thereto, and may be a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), a flash memory, or a High Bandwidth Memory (HBM), or a Power Management IC (PMIC). For example, the first semiconductor chip 401 may include a logic chip such as a GPU, and the second semiconductor chip 402 may include a memory chip such as an HBM. Alternatively, the first semiconductor chip 401 and the second semiconductor chip 402 may be divided logic chips having different cores by being divided by a die split.

[0042] The first semiconductor chip 401 and the second semiconductor chip 402 may each be formed based on an active wafer, and in this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. may be used as a base material forming each body. Various circuits may be formed on the body. Each body may have a connection pad formed thereon, and the connection pad may include a conductive material such as aluminum (Al) or copper (Cu). The first semiconductor chip 401 and the second semiconductor chip 402 may be bare dies, and in this case, metal bumps may be disposed on the connection pads. Alternatively, the first semiconductor chip 401 and the second semiconductor chip 402 may be packaged dies, and in this case, a rewiring layer may be further formed on the connection pads, and metal bumps may be disposed on the rewiring layer.

[0043] The first semiconductor chip 401 and the second semiconductor chip 402 may be connected to the substrate unit 100 of the printed circuit board and the connection structure through the connection member 500. The connection member 500 may be formed of a low melting point metal, for example, a solder such as tin (Sn)-aluminum (Al)-copper (Cu), but is not limited thereto. The connection member 500 may be formed in a multi-layer or single layer. When formed in a multi-layer, it may include a copper pillar and solder, and when formed in a single layer, it may include, but is not limited to, tin-silver solder and copper. In addition, any means that can act as a medium to electrically connect the semiconductor chip or electronic components to the substrate unit 100 and / or the connection structure 200 may be used without limitation. Although FIG. 3b shows two semiconductor chips mounted, the present invention is not limited thereto, and more semiconductor chips may be mounted and electrically connected by the connection structure 200.

[0044] Meanwhile, the printed circuit board according to the embodiment is not limited to the configurations shown in Figures 3a and 3b, and may further include other general configurations of a printed circuit board, that is, may further include configurations that can be utilized by a person having ordinary skill in the art.

[0045] FIG. 4 is a cross-sectional view that illustrates a schematic configuration of a printed circuit board according to another embodiment.

[0046] 4, a connection structure 200 of a printed circuit board according to another example may be disposed on a substrate part 100. That is, the connection structure 200 may be disposed on a first insulating layer 110 of the substrate part 100, and the first insulating layer 110 may not include a cavity.

[0047] Meanwhile, among the configurations other than the arrangement of the connection structure 200, the same configurations as those of the printed circuit board according to one example may also be applied to the printed circuit board according to another example, so duplicated explanations regarding this will be omitted.

[0048] FIG. 5 is a cross-sectional view that illustrates a schematic configuration of a printed circuit board according to another embodiment.

[0049] Referring to FIG. 5, the substrate part 100 of the printed circuit board according to another embodiment may include a core insulating layer 111, and the connection structure 200 may be mounted in a cavity formed in the core insulating layer 111. The core insulating layer 111 may include an insulating material, and examples of the insulating material include, but are not limited to, a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a material in which these insulating resins are mixed with an inorganic filler such as silica, or a resin impregnated in a core material such as glass fiber (glass fiber, glass cloth, glass fabric) together with an inorganic filler, for example, an insulating material such as CCL (Copper Clad Laminate). The core insulating layer 111 may be thicker than each of the first insulating layers 110, but is not limited to this. At this time, a part of the first wiring layer 120 may function as a stopper on the lower surface of the cavity formed in the core insulating layer 111, but is not limited to this.

[0050] Meanwhile, among the configurations other than the contents relating to the core insulating layer 111 of the substrate part 100 and the arrangement of the connecting structure 200, the same configurations as those of the printed circuit board of one example may also be applied to the printed circuit board of another example, and therefore, duplicated explanations regarding this will be omitted.

[0051] FIG. 6a is a cross-sectional view illustrating a connection structure of a printed circuit board according to an example, and FIG. 6b is a perspective view illustrating a capacitor portion of the connection structure of a printed circuit board according to an example.

[0052] Referring to FIG. 6 a , a connection structure 200 may include a wiring portion 201 and a capacitor portion 202 .

[0053] The wiring portion 201 of the connecting structure 200 may include a second insulating layer 210, a second wiring layer 220 disposed on or within the second insulating layer 210, and a second via layer 230 penetrating at least a portion of the second insulating layer 210 to connect the second wiring layer 220 to each other.

[0054] The second insulating layer 210 may be composed of a plurality of insulating layers, and each of the second insulating layers 210 may include an insulating material. The insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material including an inorganic filler, an organic filler, and / or a glass fiber (glass fiber, glass cloth, and / or glass fabric) together with such a resin. The insulating material may be a photosensitive material and / or a non-photosensitive material. For example, the insulating material of the second insulating layer 210 may be, but is not limited to, an insulating material such as PPG (Prepreg) or RCC (Resin Coated Copper), and may be, for example, Ajinomoto Build-up Film (ABF), Photo Imageable Dielectric (PID), FR-4, or Bismaleimide Triazine (BT). However, the insulating material is not limited to these, and other polymer materials having excellent rigidity may be used as necessary. Meanwhile, the second insulating layer 210 may include an insulating material composed of an organic material. That is, the connection structure 200 may be an organic bridge. Therefore, even if the connecting structure 200 is disposed on the upper side of the substrate part 100, unlike the case where the connecting structure 200 is a silicon bridge, there is almost no reliability problem due to a mismatch in coefficient of thermal expansion (CTE). In addition, when the connecting structure 200 includes an organic insulating material, the difficulty and cost of the process for forming the connecting structure 200 can be reduced. The organic insulating material for forming fine circuits can be, but is not limited to, a photosensitive insulating material (Photo Imageable Dielectric (PID)).

[0055] The second wiring layer 220 may be composed of a plurality of wiring layers, and each of the second wiring layers 220 may include a metal material. The metal material may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The second wiring layers 220 may include, but are not limited to, an electroless plating layer (or chemical copper) as a seed layer and an electrolytic plating layer (or electrolytic copper) as a plating layer. A sputtering layer may be formed instead of chemical copper as the electroless plating layer. If necessary, a copper foil may be further included. The second wiring layers 220 may perform various functions according to the design of the corresponding layers. For example, they may include a ground pattern, a power pattern, a signal pattern, etc. Here, the signal pattern may include various signals other than the ground pattern, the power pattern, etc., such as a data signal. These patterns may include a line pattern, a plane pattern, and / or a pad pattern. The second wiring layer 220 disposed on the uppermost side of the second wiring layers 220 may have a structure exposed from the second insulating layer 210, and may further include a surface treatment layer on the exposed surface.

[0056] The second via layer 230 may be composed of a plurality of via layers, and each of the second via layers 230 may include a microvia. The microvia may be a filled via that fills a via hole, or a conformal via that is arranged along the wall surface of the via hole. The microvia may be arranged in a stacked type and / or staggered type. Each of the second via layers 230 may include a metal material. The metal material may include a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The second via layers 230 may include, but are not limited to, an electroless plating layer (or chemical copper) as a seed layer and an electrolytic plating layer (or electrolytic copper) as a plating layer. A sputtering layer may be formed instead of the chemical copper as the electroless plating layer. The second via layer 230 may perform various functions depending on the design of the layer. For example, the signal vias may include ground vias, power vias, signal vias, etc. Here, the signal vias may include vias for transmitting various signals, such as data signals, excluding ground vias, power vias, etc.

[0057] Each second wiring layer 220 and each second via layer 230 may be formed integrally with each other, but is not limited thereto. The second wiring layer 220 and / or the second via layer 230 may be formed by any one of SAP (Semi Additive Process), MSAP (Modified Semi Additive Process), TT (Tenting), or subtractive techniques, but is not limited thereto, and any technique capable of forming a circuit with a printed circuit board or a connection structure, etc., may be used without limitation.

[0058] Meanwhile, in Fig. 6a, the second wiring layer 220 is shown disposed on the second insulating layer 210, but is not limited thereto, and the second wiring layer 220 may be disposed in the second insulating layer 210 and may have a structure in which the second wiring layer 220 is embedded in the second insulating layer 210. In this case, although not shown in Fig. 6a, the wiring portion 201 of the connection structure 200 may have a so-called coreless type wiring portion 201.

[0059] The capacitor unit 202 of the connection structure 200 may include a plurality of first dielectric layers 240, a first metal layer 251 and a second metal layer 252 disposed on or within the plurality of first dielectric layers 240. The first metal layer 251 may include a first metal plate 261 and a first connection pad 271 spaced apart from the first metal plate 261, and the second metal layer 252 may include a second metal plate 262 and a second connection pad 272 spaced apart from the second metal plate 262. The capacitor unit 202 may include a first connection via 281 and a second connection via. The first connecting via 281 may penetrate at least a part of the plurality of first dielectric layers 240 and / or at least a part of the second insulating layer 210 to connect the second wiring layer 220 and the first metal plate 261, and the second connecting via 282 may penetrate at least a part of the plurality of first dielectric layers 240 and / or at least a part of the second insulating layer 210 to connect the second wiring layer 220 and the second metal plate 262. The second connecting via 282 may connect the second wiring layer 220 and the second metal plate 262 through the first connecting pad 271.

[0060] The first dielectric layer 240 may include a dielectric material made of an organic material. The dielectric material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material including such a resin as well as an inorganic filler, an organic filler, and / or glass fiber (glass fiber, glass cloth, and / or glass fabric). The dielectric material may be a photosensitive material and / or a non-photosensitive material. For example, the dielectric material of the first dielectric layer 240 may be an insulating material such as PPG (Prepreg) or RCC (Resin Coated Copper), but may also be ABF (Ajinomoto Build-up Film), PID (Photo Imageable Dielectric), FR-4, BT (Bismaleimide Triazine), etc. However, the dielectric material is not limited thereto, and other polymeric materials having excellent dielectric properties may be used as necessary. It is possible to realize fine circuits and perform fine processing, and a photosensitive dielectric material (Photo Imageable Dielectric, PID), i.e., a photosensitive resin, can be used as an organic insulating material to form the thin first dielectric layer 240, but is not limited thereto, and any material can be used without limitation as long as it is disposed between the first metal layer 251 and the second metal layer 252, which function as electrodes, and can function as a dielectric.

[0061] The first metal layer 251 and the second metal layer 252 may each include a metal material. The metal material may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The second wiring layer 220 may each include, but is not limited to, an electroless plating layer (or chemical copper) as a seed layer and an electrolytic plating layer (or electrolytic copper) as a plating layer. A sputtering layer may be formed as the electroless plating layer instead of chemical copper. If necessary, a copper foil may be further included. The first metal layer 251 and the second metal layer 252 may be formed by any one of a semi-additive process (SAP), a modified semi-additive process (MSAP), a tenting (TT), or a subtractive process, but is not limited to these, and any method for forming a metal layer may be used without limitation. The method for forming the metal layer is not limited, and the metal layer may be formed by printing a conductive paste containing a metal material on the green sheet.

[0062] Among the first metal layer 251 and the second metal layer 252, the first metal plate 261 and the second metal plate 262 can function as internal electrodes of the capacitor unit 202. That is, the first metal layer 251 and the second metal layer 252 can be charged to have opposite polarities to each other and have electrostatic capacitance. The first metal plate 261 and the second metal plate 262 are arranged to correspond to each other as a pair and to face each other with the first dielectric layer 240 in between. By arranging the first metal plate 261 and the second metal plate 262 in this manner, each metal plate can be charged with an electric charge to function as a capacitor. The first metal plate 261 and the second metal plate 262 can have a rectangular plate, i.e., a plate shape, but are not necessarily limited thereto, and can have a polygonal shape or a circular shape. In addition, the metal plate can have a groove or a shape in which many patterns are densely packed. As described above, the first metal plate 261 and the second metal plate 262 may have various designs, such as shapes, depending on the capacitance required in the design of the printed circuit board and the design of the connection structure 200.

[0063] The first connection pad 271 is disposed to be spaced apart from the first metal plate 261, and may be disposed at the same level as the first metal plate 261. The first connection pad 271 may serve as an intermediate body disposed to connect the second wiring layer 220 and the second metal layer 252. That is, the first connection pad 271 may serve as an intermediate body for preventing the second connection via 282 for electrically connecting with the second metal plate 262 disposed under the first metal plate 261 from penetrating the first dielectric layers 240 at once. That is, since the first connection pad 271 is disposed on the first metal layer, it may be more advantageous to form a through hole for forming the second connection via 282. At this time, since the first connection pad 271 is spaced apart from the first metal plate 261, the first metal plate 261 and the second metal plate 262 may not be directly connected to each other. Meanwhile, when a second connection via can be formed penetrating the first dielectric layers 240 at once, the first connection pad 271 may not be disposed.

[0064] The first connection via 281 may penetrate at least a part of the first dielectric layers 240 and / or at least a part of the second insulating layer 210 to connect the second wiring layer 220 and the first metal plate 261 to each other, and the second connection via 282 may penetrate at least a part of the first dielectric layers 240 and / or at least a part of the second insulating layer 210 to connect the second wiring layer 220 and the second metal plate 262 to each other. The second connection via 282 may connect the second wiring layer 220 and the second metal plate 262 to each other through the first connection pad 271. The first connection via 281 and the second connection via 282 may each include a metal material. The metal material may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The second wiring layer 220 may include, but is not limited to, an electroless plating layer (or chemical copper) as a seed layer and an electrolytic plating layer (or electrolytic copper) as a plating layer. A sputtering layer may be formed as the electroless plating layer instead of chemical copper. If necessary, a copper foil may be further included. The first connection via 281 and the second connection via 282 may be formed by any one of a semi-additive process (SAP), a modified semi-additive process (MSAP), a tenting (TT), or a subtractive method, but is not limited thereto, and any method for forming a via may be used without limitation. The second connection via 282 and the first connection pad 271 may be formed integrally, but is not limited thereto.

[0065] The distance d1 between the first metal layer 251 and the second metal layer 252 may be closer than the distance d2 between the first metal layer 251 and the second wiring layer 220. The distance d1 between the first metal layer 251 and the second metal layer 252 may be understood to mean the distance between the lower surface of the first metal layer 251 and the upper surface of the second metal layer 252, and more specifically, may mean the insulation distance between the first metal layer 251 and the second metal layer 252. The distance d1 between the first metal layer 251 and the second metal layer 252 may be measured by photographing a cross section of a printed circuit board or a connection structure with a scanning microscope, and may be the average value of the distances d1 between the first metal layer 251 and the second metal layer 252 measured at any five points. The distance d2 between the first metal layer 251 and the second wiring layer 220 may be interpreted in a similar manner. The distance d2 between the first metal layer 251 and the second wiring layer 220 may refer to the distance between the first metal layer 251 and the closest second wiring layer 220.

[0066] By reducing the distance d1 between the first metal layer 251 and the second metal layer 252, the first metal plate 261 of the first metal layer 251 and the second metal plate 262 of the second metal layer 252 can serve as electrodes of a capacitor. The distance d1 between the first metal layer 251 and the second metal layer 252 can be 1 μm or less, and can be set to have a value of 0.33 μm or less if the first metal layer 251 and the second metal layer 252 can be further reduced in distance. However, the distance between the first metal layer 251 and the second metal layer 252 can be freely designed according to the capacitance required in the capacitor unit 202 of the connection structure 200, but in order to ensure capacitance, they need to be disposed close to each other so as to have a distance shorter than a certain value. However, the distance between the first metal layer 251 and the second metal layer 252 can also have a value greater than 0. This is because, if the first metal layer 251 and the second metal layer 252 come into contact with each other, a short circuit occurs and capacitance cannot be obtained.

[0067] In a similar sense to the distance d1 between the first metal layer 251 and the second metal layer 252 being closer than the distance d2 between the first metal layer 251 and the second wiring layer 220, the thickness of the first dielectric layer 240 may be formed thinner than the thickness of the second insulating layer 210. The fact that the thickness of the first dielectric layer 240 may be formed thinner than the thickness of the second insulating layer 210 may mean that the thickness of any one of the first dielectric layers 240 of the plurality of first dielectric layers 240 may be formed thinner than the thickness of any one of the second insulating layers 210 of the plurality of second insulating layers 210. The thickness of the first dielectric layer 240 is a concept that includes a rough one, and may mean the vertical distance between the upper surface and the lower surface of the first dielectric layer 240. The thickness of the first dielectric layer 240 may be measured by photographing a cross section of a cut printed circuit board with a scanning microscope, and may be an average value of the thicknesses of the insulating layer measured at any five points. The thickness of the second insulating layer 210 can be understood in the same sense as the thickness of the first dielectric layer 240, which can be understood in the same sense as described above with respect to measuring the thickness of the first insulating layer 110.

[0068] Since the first dielectric layer 240 is formed thinner than the second insulating layer 210, the first dielectric layer 240 may be formed by spin coating an insulating material instead of laminating an insulating material formed from a film. When the first dielectric layer 240 is formed by spin coating, the insulating distance, which is the distance d1 between the first metal layer 251 and the second metal layer 252, can be formed closer, and it is also easy to adjust the insulating distance. However, the method or means for forming the first dielectric layer 240 is not limited thereto, and any method that can form an insulating material or a dielectric on a printed circuit board can be used without limitation, and any method that can easily adjust the thickness and form a thin layer can be used without limitation. For example, if an insulating film for use in the first dielectric layer 240 can be formed thinner, it can be formed by a lamination method.

[0069] The first dielectric layer 240 may include the same type of organic material as the second insulating layer 210. As described above, the first dielectric layer 240 may use a photosensitive insulating material (Photo Imageable Dielectric, PID), i.e., a photosensitive resin, to form a thin dielectric layer, and the second insulating layer 210 may use a photosensitive insulating material to realize a fine circuit. However, the materials of the first dielectric layer 240 and the second insulating layer 210 are not limited thereto, and may include various types of organic materials as described above. Even if the first dielectric layer 240 includes an organic material, the capacitor unit 202 may have a capacitance by arranging the first metal layer 251 and the second metal layer 252 close to each other.

[0070] Referring to FIG. 6b, the capacitor unit 202 may include a pair of metal layers facing each other. The first metal plate 261 of the first metal layer 251 and the second metal plate 262 of the second metal layer 252 face each other, and since capacitance may occur in the effective area where the first metal plate 261 and the second metal plate 262 face each other, the first metal plate 261 and the second metal plate may be designed to increase the effective area. In FIG. 6b, protrusions are formed at both ends of the metal plate, and the protrusions are connected to the first connection via 281 or the second connection via 282, but this is an example of one of various designs of the first metal plate 261 and the second metal plate 262. The shape of the protrusions of the metal plate may be changed as necessary, and the position of the first connection pad 271 may also be changed.

[0071] Referring to FIG. 6b, the first metal plate 261 and the second metal plate 262 may include a first hole 291 and a second hole 292 disposed therein. The first hole 291 and the second hole 292 may correspond to degassing holes in a printed circuit board. The first hole 291 and the second hole 292 may be a configuration for degassing, and may be used as a path for ejecting and removing unnecessary moisture, gas, etc. generated in the steps of manufacturing the connection structure 200 and the steps of manufacturing the printed circuit board. In the case of a general printed circuit board or other connection structure, degassing holes are disposed at different positions in each layer to efficiently perform degassing, but in the case of the connection structure 200 of the printed circuit board according to an example, the positions of the first hole 291 formed in the first metal plate 261 and the second hole 292 formed in the second metal plate 262 may correspond to each other. That is, by forming the first hole 291 and the second hole 292 to correspond to each other, the effective area of ​​the overlapping region of the first metal plate 261 and the second metal plate 262 can be easily adjusted. Since the effective areas of the first metal plate 261 and the second metal plate 262 can be easily adjusted, the capacitor unit 202 can be easily designed to have a capacitance as required. Meanwhile, although FIG. 6b illustrates the first hole 291 and the second hole 292 formed one by one, the size, number, and shape of the first hole 291 and the second hole 292 are not limited and can be changed according to the design.

[0072] Meanwhile, although not shown in Figures 6a and 6b, the connecting structure 200 may have a buried pattern structure. For example, the upper surface of the second wiring layer 220 disposed on the uppermost side may be buried in the upper surface of the second insulating layer 210 disposed on the uppermost side and exposed to the upper surface of the second insulating layer 210. When the connecting structure 200 is formed in such a structure, a wiring design with a finer pitch may be possible. In addition, it may be manufactured at a lower cost and in a simpler process than a silicon bridge.

[0073] FIG. 7a is a cross-sectional view that shows a schematic diagram of a connection structure according to another example, and FIG. 7b is a perspective view that shows a schematic diagram of a capacitor portion of the connection structure according to another example.

[0074] 7a and 7b, the connection structure according to another example may include a plurality of first metal layers 251 and a plurality of second metal layers 252. The first metal layers 251 and the second metal layers 252 may be alternately disposed with the first dielectric layer 240 interposed therebetween. That is, a structure may be formed in which the second metal layer is disposed between the first metal layers 251, and the first metal layers 251 may be disposed between the second metal layers 252.

[0075] The first metal layer 251 may include a first metal plate 261 and a first connection pad 271 spaced apart from the first metal plate 261, and the second metal layer 252 may include a second metal plate 262 and a second connection pad 272 spaced apart from the second metal plate 262. The first connection via 281 may connect the second wiring layer 220 and the first metal plate 261 to each other and may also be connected to another first metal plate 261 through the second connection pad 272. The second connection via 282 may connect the second wiring layer 220 and the second metal plate 262 to each other and may also be connected to another second metal plate 262 through the first connection pad 271. The second connection pad 272 is disposed to be spaced apart from the second metal plate 262 and may have the same properties as the first connection pad 271, so a duplicated description will be omitted.

[0076] 7A and 7B, the first metal layer 251 and the second metal layer 252 are each composed of two metal layers, so that a total of four metal layers are arranged, but the number of metal layers is not limited thereto and more metal layers may be arranged. That is, the number of metal layers may be variously designed according to the capacitance of the capacitor unit 202.

[0077] Meanwhile, among the configurations other than the first metal layer 251 and the second metal layer 252, the configuration of the connection structure of one example may also be applied to the connection structure of another example, so duplicated explanations regarding this will be omitted.

[0078] FIG. 8a is a cross-sectional view that shows a schematic diagram of a connection structure according to still another example, and FIG. 8b is a perspective view that shows a schematic diagram of a capacitor portion of a connection structure according to still another example.

[0079] 8a and 8b, in the connection structure according to another example, one first metal layer 251 and one second metal layer 252 may include a plurality of first metal plates 261 and a plurality of second metal plates 262, respectively. In this case, the first metal plates 261 may be arranged to be spaced apart from each other, and the second metal plates 262 may be arranged to be spaced apart from each other. That is, in the connection structure 200 according to another example, the capacitor units 202 may be arranged in parallel. Therefore, the design may be diversified to realize a required capacitance in the capacitor unit 202.

[0080] 8a and 8b, the first metal layer 251 and the second metal layer 252 are each shown as being composed of two metal plates, but the number of metal plates is not limited thereto, and a greater number of metal plates may be arranged in parallel. Meanwhile, the first metal layer 251 and the second metal layer 252 are each shown as being composed of one metal layer, but each may be composed of a plurality of first metal layers 251 and a plurality of second metal layers 252. That is, the number of metal plates and the number of metal layers may be variously designed according to the capacitance of the capacitor unit 202.

[0081] In addition, among the configurations other than the first metal plate 261 and the second metal plate 262, the configuration of the connecting structure of one example can also be applied to the connecting structure of another example, so duplicated explanations regarding this will be omitted.

[0082] In the present disclosure, "cross section" can mean the cross section shape of an object cut vertically or the cross section shape of an object when viewed from the side, and "planar" can mean the shape of an object cut horizontally or the planar shape of an object when viewed from the top or bottom.

[0083] In this disclosure, for convenience, the terms upper side, top, top surface, etc. are used to mean a direction toward a surface on which electronic components can be mounted based on a cross section of a drawing, and the terms lower side, bottom, bottom surface, etc. are used to mean the opposite direction. However, this is a definition of directions for convenience of explanation, and the scope of the claims is not particularly limited by the description of such directions.

[0084] In the present disclosure, the term "connected" refers not only to a direct connection but also to an indirect connection via an adhesive layer or the like. The term "electrically connected" refers to both a physical connection and a non-connection. Furthermore, the terms "first" and "second" are used to distinguish one component from another, and do not limit the order and / or importance of the components. In some cases, the first component may be named the second component, and similarly the second component may be named the first component, without departing from the scope of the right.

[0085] The expression "one example" used in the present disclosure does not mean the same embodiment as the other, but is provided to emphasize and describe the unique features that are different from each other. However, the above-mentioned one example does not exclude being realized in combination with the features of another example. For example, even if the matter described in a particular example is not described in another example, it can be understood as being related to the other example, unless there is a description in the other example that is opposite or contradictory to the matter.

[0086] The terms used in the present disclosure are merely used to describe an example and are not intended to limit the present disclosure. In this case, the singular expression includes the plural expression unless the context clearly indicates otherwise. [Explanation of symbols]

[0087] 100 Substrate 110 First insulating layer 111 Core insulation layer 120 1st wiring layer 130 First via layer 200 linked structure 201 Wiring section 202 Capacitor section 210 Second insulating layer 220 2nd wiring layer 230 2nd via layer 240 First dielectric layer 251 1st metal layer 252 2nd metal layer 261 1st metal plate 262 Second metal plate 271 First connecting pad 272 Second connecting pad 281 1st Connected Via 282 2nd Connected Via 291 Hall 1 292 2nd Hall 300 adhesive layer 401 First semiconductor chip 402 Second semiconductor chip 500 Connecting member 1000 electronic equipment 1010 Mainboard 1020 Chip related parts 1030 Network related parts 1040 Other parts 1050 Camera Module 1060 Antenna Module 1070 display 1080 Battery 1090 Signal Line 1100 Smartphone 1110 Smartphone internal main board 1120 Smartphone internal electronic components 1121 Smartphone Internal Antenna Module 1130 Smartphone internal camera module 1140 Smartphone internal speaker

Claims

1. a substrate portion including a first insulating layer and a first wiring layer disposed on or within the first insulating layer; a connection structure disposed on or within the substrate portion, the connection structure including a plurality of first dielectric layers, a first metal layer and a second metal layer disposed on the plurality of first dielectric layers, a second insulating layer disposed on the plurality of first dielectric layers, and a second wiring layer disposed on the second insulating layer; each of the plurality of first dielectric layers includes an organic material; A printed circuit board, wherein the distance between the first metal layer and the second metal layer is shorter than the distance between the first metal layer and the second wiring layer.

2. the first metal layer includes a first metal plate and a first connection pad spaced apart from the first metal plate, The printed circuit board of claim 1 , wherein the second metal layer comprises a second metal plate.

3. 3. The printed circuit board of claim 2, wherein the connecting structure includes a first connecting via that penetrates at least a portion of the plurality of first dielectric layers and at least a portion of the second insulating layer to connect the second wiring layer and the first metal plate, and a second connecting via that penetrates at least a portion of the plurality of first dielectric layers and at least a portion of the second insulating layer to connect the second wiring layer and the second metal plate.

4. The printed circuit board of claim 3 , wherein the second connection via connects the second wiring layer and the second metal plate through the first connection pad.

5. the first metal layer and the second metal layer are respectively composed of a plurality of first metal layers and a plurality of second metal layers; the second metal layer further includes a second connection pad spaced apart from the second metal plate, The printed circuit board of claim 2 , wherein the first metal layer and the second metal layer are alternately arranged with the first dielectric layer in between.

6. the connection structure includes a first connection via that penetrates at least a portion of the plurality of first dielectric layers and at least a portion of the second insulating layer to connect the second wiring layer and the first metal plate, and a second connection via that penetrates at least a portion of the plurality of first dielectric layers and at least a portion of the second insulating layer to connect the second wiring layer and the second metal plate, the first connection via connects the second wiring layer and the first metal plate through the second connection pad; The printed circuit board of claim 5 , wherein the second connection via connects the second wiring layer and the second metal plate through the first connection pad.

7. the first metal layer includes a plurality of first metal plates spaced apart from one another and a plurality of first connection pads spaced apart from the first metal plates, The printed circuit board of claim 1 , wherein the second metal layer comprises a plurality of spaced apart second metal plates.

8. the connection structure includes a first connection via penetrating at least a portion of the plurality of first dielectric layers and / or at least a portion of the second insulating layer to connect the second wiring layer and the first metal plate, and a second connection via penetrating at least a portion of the plurality of first dielectric layers and / or at least a portion of the second insulating layer to connect the second wiring layer and the second metal plate, The printed circuit board of claim 7 , wherein the second connecting vias connect the second wiring layer and the second metal plates, respectively, through the first connecting pads.

9. The printed circuit board of claim 1 , wherein the first dielectric layer has a thickness less than a thickness of the second insulating layer.

10. The printed circuit board of claim 1 , wherein the first dielectric layer comprises a photosensitive resin.

11. The printed circuit board of claim 1 , wherein the first dielectric layer comprises the same type of organic material as the second insulating layer.

12. The printed circuit board of claim 1 , further comprising an adhesive layer disposed between the substrate portion and the connecting structure.

13. The printed circuit board according to claim 1 , wherein the second wiring layer has a higher wiring density than the first wiring layer.

14. the first metal plate includes a first hole disposed therein; The printed circuit board of claim 2 , wherein the second metal plate includes a second hole therein corresponding to the first hole.

15. a first electronic component connected to a portion of the substrate portion and a portion of the connection structure; The printed circuit board of claim 1 , further comprising: a second electronic component connected to another portion of the substrate portion and another portion of the connection structure.

16. a substrate portion including a first insulating layer and a first wiring layer disposed on or within the first insulating layer; a capacitor portion disposed on or within the substrate portion, the capacitor portion including a dielectric layer and a first metal layer disposed on or within the dielectric layer, and a wiring portion including a second insulating layer and a second wiring layer disposed on the second insulating layer; the first metal layer includes a pair of metal plates facing each other, The printed circuit board, wherein the dielectric layer comprises an organic material.

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