Semiconductor package and manufacturing method thereof

Abstract

To provide a semiconductor package with improved reliability.SOLUTION: The present invention provides a semiconductor package and a manufacturing method thereof, the semiconductor package includes a first substrate, a first semiconductor die including a first bonding film on the first substrate, a second substrate, a second bonding film below the second substrate, a second semiconductor die disposed on the first semiconductor die, and a silicon oxide layer interposed between the first semiconductor die and the second semiconductor die, at least one pore is disposed in the silicon oxide layer, and the height of the pore is 1 Å to 2 nm.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor package and a method for manufacturing the same. [Background technology]

[0002] A semiconductor package is a device that implements an integrated circuit chip in a suitable form for use in electronic products. Typically, a semiconductor package is made by mounting a semiconductor die on a printed circuit board (PCB) and electrically connecting them using bonding wires or bumps. As the electronics industry develops, various research efforts are underway to improve the reliability and durability of semiconductor packages. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 9,522,364 B2 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a semiconductor package having improved reliability.

[0005] An object of the present invention is to provide a method for manufacturing a semiconductor package that can improve yield.

[0006] The problems to be solved by the present invention are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0007] To achieve the above object, a semiconductor package according to an embodiment of the present invention includes a first substrate, a first semiconductor die including a first bonding film on the first substrate, a second substrate, a second bonding film below the second substrate, a second semiconductor die disposed on the first semiconductor die, and a silicon oxide film interposed between the first semiconductor die and the second semiconductor die, at least one pore is disposed in the silicon oxide film, and the height of the pore is 1 Å to 2 nm.

[0008] A semiconductor package according to one embodiment of the present invention includes a first substrate, a first semiconductor die including a first bonding film on the first substrate, a second substrate, a second bonding film below the second substrate, a second semiconductor die disposed on the first semiconductor die, and a silicon oxide film interposed between the first semiconductor die and the second semiconductor die, at least one void is disposed within the silicon oxide film, the first bonding film and the second bonding film include a plurality of SiCN grains, and a height of the void is smaller than an average size of the SiCN grains.

[0009] According to another embodiment of the present invention, a semiconductor package includes a first semiconductor die including a first substrate, a first bonding film on the first substrate, and a first conductive pattern penetrating the first bonding film; a second semiconductor die disposed on the first substrate and partially exposing an upper surface of the first semiconductor die; and a second semiconductor die including a second substrate, a second bonding film under the second substrate, and a second conductive pattern penetrating the second bonding film, the first conductive pattern and the second conductive pattern being interposed between the first bonding film and the second bonding film. a silicon oxide film contacting a side surface of the second semiconductor die, a molding film covering a side surface of the second semiconductor die and an upper surface of the first semiconductor die, and an external connection terminal bonded to a lower surface of the first semiconductor die, the first bonding film and the second bonding film being formed of SiCN, the first bonding film or the second bonding film having a first thickness, the silicon oxide film having a second thickness smaller than the first thickness, at least one void being disposed within the silicon oxide film, and the void being separated from the first conductive pattern and the second conductive pattern.

[0010] In order to achieve the above object, a method for manufacturing a semiconductor package according to the present invention includes the steps of: preparing a first wafer including a first bonding film disposed on a top end thereof; the first bonding film being made of SiCN; grinding the first bonding film; removing CN from a surface of the first bonding film to form dangling bonds on silicon atoms; preparing a second semiconductor die including a second bonding film disposed on a top end thereof; the second bonding film being made of SiCN; removing CN from a surface of the second bonding film to form dangling bonds on silicon atoms. forming a bonding layer on the first wafer; bonding an OH group to the dangling bonds of the silicon atoms on a surface of the first bonding film; bonding an OH group to the dangling bonds of the silicon atoms on a surface of the second bonding film; placing the second semiconductor die upside down on the first wafer so that the second bonding film contacts the first bonding film; and performing a first bonding process to form a silicon oxide film between the second bonding film and the first bonding film, thereby bonding the second bonding film and the first bonding film. Effect of the Invention

[0011] In the semiconductor package according to the present invention, a silicon oxide film is present between a first semiconductor die including a first bonding film and a second semiconductor die including a second bonding film, and ultra-fine voids are formed in the silicon oxide film. During the formation of the voids, water molecules can cause compressive stress in the first bonding film and the second bonding film, thereby improving the adhesive strength between the first bonding film and the second bonding film. Therefore, a semiconductor package with improved reliability can be provided.

[0012] The method for manufacturing a semiconductor package according to the present invention can improve the adhesion between the first semiconductor die and the second semiconductor die, thereby reducing process defects and improving yield. [Brief description of the drawings]

[0013] [Figure 1] 1 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention. [Diagram 2] This is an enlarged view of part 'P1' in FIG. [Figure 3A] This is an enlarged view of part 'P2' in Figure 2. [Figure 3B] This is an enlarged view of part 'P2' in Figure 2. [Figure 4] 3A or 3B. FIG. 3B is an enlarged view of a portion 'P3' of FIG. [Diagram 5] 1 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention. [Figure 6] This is an enlarged view of 'P4' in Figure 5. [Figure 7] 2 is a flow chart illustrating a process for manufacturing a semiconductor package according to an embodiment of the present invention; [Figure 8A] 2A to 2C are cross-sectional views showing a process for manufacturing the semiconductor package of FIG. [Figure 8B] 2A to 2C are cross-sectional views showing a process for manufacturing the semiconductor package of FIG. [Figure 8C] 2A to 2C are cross-sectional views showing a process for manufacturing the semiconductor package of FIG. [Figure 8D] 2A to 2C are cross-sectional views showing a process for manufacturing the semiconductor package of FIG. [Figure 8E] 2A to 2C are cross-sectional views showing a process for manufacturing the semiconductor package of FIG. [Figure 8F] 2A to 2C are cross-sectional views showing a process for manufacturing the semiconductor package of FIG. [Figure 8G] 2A to 2C are cross-sectional views showing a process for manufacturing the semiconductor package of FIG. [Figure 8H] 2A to 2C are cross-sectional views showing a process for manufacturing the semiconductor package of FIG. [Figure 8I] 2A to 2C are cross-sectional views showing a process for manufacturing the semiconductor package of FIG. [Figure 9A] 8B or 8D. FIG. [Figure 9B] This is an enlarged view of part 'P9' of FIG. 9A. [Figure 10] 8C or 8E. FIG. [Figure 11A] This is an enlarged view of part 'P7' of Figure 8F. [Figure 11B] This is an enlarged view of part 'P10' of FIG. 11A. [Figure 12A] This is an enlarged view of part 'P8' in FIG. 8G. [Figure 12B] This is an enlarged view of part 'P11' of FIG. 12A. [Figure 13] This is an enlarged view of part 'P8' in FIG. 8G. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] In order to more specifically explain the present invention, embodiments of the present invention will be described in more detail below with reference to the accompanying drawings.

[0015] Fig. 1 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention. Fig. 2 is an enlarged view of a portion 'P1' in Fig. 1. Figs. 3A and 3B are enlarged views of a portion 'P2' in Fig. 2. Fig. 4 is an enlarged view of a portion 'P3' in Fig. 3A or 3B.

[0016] 1 and 2, a semiconductor package 1000 according to the present embodiment includes a first semiconductor die 10, a second semiconductor die 100, and a molding film MD. In this specification, a 'semiconductor die' may also be referred to as a semiconductor chip. The first semiconductor die 10 may be a logic circuit chip or a memory chip such as a flash memory chip, a DRAM chip, a SRAM chip, an EEPROM chip, a PRAM chip, an MRAM chip, or a ReRAM chip. The first semiconductor die 10 includes a first substrate 1, a first interlayer insulating film IL1, and a first bonding film BNL1, which are sequentially stacked. The first substrate 1 may be a semiconductor substrate made of a semiconductor such as silicon, a silicon on insulator (SOI) substrate, and / or an insulating substrate. The first substrate 1 includes a first surface 1a and a second surface 1b that are opposite to each other. Although not shown, a plurality of transistors may be disposed on the first surface 1a of the first substrate 1.

[0017] A first interlayer insulating film IL1 is disposed on a first surface 1a of the first substrate 1. The first interlayer insulating film IL1 may have a single layer or a multi-layer structure of at least one of silicon oxide, silicon nitride, and silicon oxynitride. A multi-layer first wiring 25 may be disposed in the first interlayer insulating film IL1. The first wiring 25 may be made of polysilicon doped with impurities, or a metal such as aluminum, tungsten, titanium, or copper. The first wiring 25 and the transistors may form various circuits.

[0018] A plurality of first conductive pads 7 may be disposed on the second surface 1b of the first substrate 1. Although not shown, an insulating layer may be interposed between the second surface 1b of the first substrate 1 and the first conductive pads 7. External connection terminals SB may be bonded to the first conductive pads 7. The external connection terminals SB may include at least one of a conductive bump and a solder ball. The external connection terminals SB may include at least one of copper, nickel, tin, and silver.

[0019] The first through via 11 may penetrate the first substrate 1 and a portion of the first interlayer insulating layer IL1 to connect the first conductive pad 7 to the first wiring 25. The first through via 11 may include a metal material such as copper, tungsten, and titanium. A first through insulating layer 13 may be interposed between the first through via 11 and the first substrate 1. The first through insulating layer 13 may be made of, for example, silicon oxide.

[0020] The first bonding layer BNL1 may be made of silicon carbonitride (SiCN). The first bonding layer BNL1 may also be referred to as a 'first SiCN layer'. The first conductive pattern CP1 may penetrate a portion of the insulating layer IL1 between the first bonding layer BNL1 and the first layer. The first conductive pattern CP1 may include, for example, copper.

[0021] The second semiconductor die 100 may be a chip different from the first semiconductor die 10. The second semiconductor die 100 may be a logic circuit chip or a memory chip such as a flash memory chip, a DRAM chip, an SRAM chip, an EEPROM chip, a PRAM chip, an MRAM chip, or a ReRAM chip. The second semiconductor die 100 includes a second substrate 21, a second interlayer insulating film IL2, and a second bonding film BNL2, which are sequentially stacked. The second substrate 21 may be a semiconductor substrate made of a semiconductor such as silicon, a silicon on insulator (SOI) substrate, and / or an insulating substrate. The second substrate 21 includes a first surface 21a and a second surface 21b that are opposite to each other. Although not shown, a plurality of transistors may be disposed on the first surface 21a of the second substrate 21. The first surface 21a of the second substrate 21 faces the first semiconductor die 10.

[0022] A second interlayer insulating film IL2 is disposed on the first surface 21a of the second substrate 21. The second interlayer insulating film IL2 may have a single layer or a multi-layer structure of at least one of silicon oxide, silicon nitride, and silicon oxynitride. A multi-layer second wiring 35 may be disposed in the second interlayer insulating film IL2. The second wiring 35 may be made of polysilicon doped with impurities, or a metal such as aluminum, tungsten, titanium, or copper. The first wiring 25 and the transistors may form various circuits.

[0023] The second bonding layer BNL2 may be made of silicon carbonitride (SiCN). The second bonding layer BNL2 may also be referred to as a 'second SiCN layer'. The second conductive pattern CP2 may penetrate the second bonding layer BNL2 and a portion of the second interlayer insulating layer IL2. The second conductive pattern CP2 may include, for example, copper.

[0024] The first conductive pattern CP1 and the second conductive pattern CP2 may abut against each other. The first conductive pattern CP1 may have a first width WT1. The second conductive pattern CP2 may have a second width WT2 different from the first width WT1. For example, the second width WT2 may be larger than the first width WT1. Conversely, the second width WT2 may be smaller than the first width WT1. Such a width difference may improve the misalignment margin. There is no boundary surface between the first conductive pattern CP1 and the second conductive pattern CP2, and they may be formed integrally with each other.

[0025] Referring to FIG. 2, a silicon oxide layer 31 is interposed between the first semiconductor die 10 and the second semiconductor die 100. The silicon oxide layer 31 is interposed between the first bonding layer BNL1 and the second bonding layer BNL2 and may be in direct contact therewith. The silicon oxide layer 31 may also be referred to as an 'insulation layer' or a 'bonding interface layer'. The silicon oxide layer 31 may be in contact with a side of the first conductive pattern CP1. The silicon oxide layer 31 may be in contact with a side of the second conductive pattern CP2. The silicon oxide layer 31 may have a first thickness T1. The first bonding layer BNL1 may have a second thickness T2. The second bonding layer BNL2 may have a third thickness T3. The first thickness T1 may be smaller than the second thickness T2 and / or the third thickness T3. The second thickness T2 and the third thickness T3 may be the same or different from each other.

[0026] At least one pore PO may be disposed in the silicon oxide film 31. The pore PO may be separated from the first bonding film BNL1 and the second bonding film BNL2. The pore PO may be separated from the first conductive pattern CP1 and the second conductive pattern CP2. The pore PO may have a first height HT1. The first height HT1 may be 1 Å to 2 nm. The pore PO may have a third width WT3. The third width WT3 may be 1 nm to 100 nm. The pore PO may also be referred to as a void' or a vacancy.

[0027] 3A and 3B, the first conductive pattern CP1 and the second conductive pattern CP2 may each have a SiCN grain GRN. The bonding relationship between silicon atoms, carbon atoms, and nitrogen atoms within each of the SiCN grains GRN may have a t-SiCN crystal structure as shown in FIG. 4. Alternatively, the crystal structure of each of the SiCN grains GRN may be c-SiCN, o-SiCN, or h-SiCN. The SiCN grains GRN may have an average size SZ (here, size means diameter, width, or height). A first height HT1 of a void PO of the SiCN grains GRN may be smaller than the average size SZ. A gap VC may exist at the boundary between the SiCN grains GRN. Water molecules WM are contained in the boundary or gap VC between the SiCN grains GRN. 2 O can be present (or trapped).

[0028] The width of the second semiconductor die 100 may be smaller than the width of the first semiconductor die 10, and the top surface of the first semiconductor die 10 may be partially exposed. A molding film MD may cover the top surface and side surfaces of the second semiconductor die 100 and the top surface of the first semiconductor die 10. The molding film MD may include an insulating resin such as an epoxy molding compound EMC. The molding film MD may further include a filler, and the filler may be dispersed in the insulating resin. The filler may be, for example, silicon oxide (SiO 2 ).

[0029] In the semiconductor package 1000 according to the present invention, ultra-fine voids PO are formed in the silicon oxide film 31. While the voids PO are formed, water molecules WM cause compressive stress in the first bonding film BNL1 and the second bonding film BNL2 toward the silicon oxide film 31, thereby improving the adhesive strength and adhesive area between the first bonding film BNL1 and the second bonding film BNL2. Also, as shown in Fig. 4, the silicon oxide film 31 can improve the adhesive strength between the first bonding film BNL1 and the second bonding film BNL2. Therefore, a semiconductor package 1000 with improved reliability can be provided.

[0030] 5 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention, and FIG 6 is an enlarged view of 'P4' in FIG 5.

[0031] 5 and 6, the semiconductor package 1001 according to the present embodiment may include second to fifth semiconductor dies 300a, 300b, 300c, and 300d stacked in sequence on a first semiconductor die 200. The first semiconductor die 10 may be a different type of chip from the second to fifth semiconductor dies 300a, 300b, 300c, and 300d. The first semiconductor die 200 may be, for example, a logic circuit chip or a buffer die. The second to fifth semiconductor dies 300a, 300b, 300c, and 300d may be the same memory chip. The memory chip may be a DRAM, a NAND Flash, an SRAM, an MRAM, a PRAM, or an RRAM. Although a structure in which one logic circuit chip and four memory chips are stacked has been disclosed in the present embodiment, the number of stacked logic circuit chips and memory chips is not limited thereto and may be various. The width of the first semiconductor die 10 may be wider than the width of the second to fifth semiconductor dies 300a, 300b, 300c, and 300d. The semiconductor package 1001 may be a High Bandwidth Memory (HBM) chip.

[0032] A molding film MD may cover an upper surface of the first semiconductor die 200 and side surfaces of the second to fifth semiconductor dies 300a, 300b, 300c, and 300d. An upper surface of the molding film MD may be coplanar with a rear surface of the fifth semiconductor die 300d.

[0033] The first semiconductor die 200 may include a first substrate 1. The first substrate 1 may include a first surface 1a and a second surface 1b facing each other. A first interlayer insulating film IL1 may be disposed on the first surface 1a. A first transistor (not shown) and a first multi-layer wiring 5 may be disposed in the first interlayer insulating film IL1. A first conductive pad 7 may be disposed on the first interlayer insulating film IL1. A first conductive bump 27 may be bonded to each of the first conductive pads 7. The first conductive bump 27 may include, for example, copper. A solder film 43 may be bonded under the first conductive bump 27. The solder film 43 may include, for example, SnAg. The first interlayer insulating film IL1 may be covered with a first passivation film 39. The first passivation film 39 may include, for example, SiN. The second surface 1b of the first substrate 1 may be covered with a first bonding film BNL1. 6, a rear insulating film 115 may be interposed between a first bonding film BNL1 and the second surface 1b of the first substrate 1. The rear insulating film 115 may be formed of, for example, silicon oxide. The first substrate 1 and a portion of the first interlayer insulating film IL1 may be penetrated by a first through via 11. A first through insulating film 13 may be interposed between the first through via 11 and the first substrate 1. A first conductive pattern CP1 may be disposed in the first bonding film BNL1.

[0034] Each of the second to fifth semiconductor dies 300a, 300b, 300c, and 300d may include a second substrate 21. The second substrate 21 may include a first surface 21a and a second surface 21b facing each other. A second interlayer insulating film IL2 may be disposed on the first surface 21a of the second substrate 21. A second transistor (not shown) and a multi-layered second wiring 35 may be disposed in the second interlayer insulating film IL2. A second conductive pattern CP2 may be disposed on the second interlayer insulating film IL2. The second interlayer insulating film IL2 may be covered with a second bonding film BNL2. A first bonding film BNL1 and a first conductive pattern CP1 are disposed on the second surface 21b of the second substrate 21. The first conductive pattern CP1 may penetrate the first bonding film BNL1. As shown in FIG. 6, a rear insulating film 115 may be interposed between the first bonding film BNL1 and the second surface 1b of the second substrate 21. In the second to fourth semiconductor dies 300a, 300b, and 300c, the rear insulating layer 115, the second substrate 21, and a portion of the second interlayer insulating layer IL2 may be penetrated by a second through via 111. A second through insulating layer 113 may be interposed between the second through via 111 and the second substrate 21. The fifth semiconductor die 300d may not include the second through via 111 and the second through insulating layer 113, and may be omitted. The first to fifth semiconductor dies 10, 300a, 300b, 300c, and 300d may contact each other. The first conductive pattern CP1 and the second conductive pattern CP2 may contact each other. The widths of the first conductive pattern CP1 and the second conductive pattern CP2 may be the same. 5 and 6, a silicon oxide layer 31 is interposed between the first to fifth semiconductor dies 200, 300a, 300b, 300c, and 300d. At least one void PO is disposed in the silicon oxide layer 31. The void PO may be separated from the first bonding film BNL1 and the second bonding film BNL2. The void PO may be separated from the first conductive pattern CP1 and the second conductive pattern CP2. As described with reference to FIG. 2, the void PO may have a first height HT1. The first height HT1 may be 1 Å to 2 nm. The void PO may have a third width WT3. The third width WT3 may be 1 nm to 100 nm. Other configurations may be the same / similar to those described with reference to FIGS. 1 to 4.

[0035] 7 is a flow chart showing a process for manufacturing a semiconductor package according to an embodiment of the present invention, and FIGS. 8A to 8I are cross-sectional views showing a process for manufacturing the semiconductor package of FIG.

[0036] 7 and 8A, a first wafer WF1 including a first bonding film BNL1 disposed at the top is prepared (first step, S10). The first wafer WF1 may include a plurality of device regions DR and a separation region SR therebetween. In each device region DR, the first wafer WF1 may have the same / similar structure as the first semiconductor die 10 described with reference to FIGS. 1 and 2. The first wafer WF1 may include a first interlayer insulating film IL1 and a first bonding film BNL1, which are sequentially stacked on a first substrate 1. The first bonding film BNL1 is made of SiCN. The first bonding film BNL1 may include a plurality of SiCN grains GRN as shown in FIG. 3A. A first conductive pad 7 and an external connection terminal SB may be bonded to a lower surface of the first substrate 1. The first wafer WF1 may be attached to a first carrier substrate CR1 via a sacrificial adhesive film AL1. The sacrificial adhesive film AL1 may include a thermosetting resin or a photosetting resin. A trench TRC for forming a first conductive pattern CP1 is formed in a portion of the first bonding layer BNL1 and the first interlayer insulating layer IL1. A plating process is performed on the first bonding layer BNL1 to form a first conductive layer CPL to fill the trench TRC. The first conductive layer CPL may include, for example, copper.

[0037] 7 and 8B, a grinding process is performed on the first conductive layer CPL to form a first conductive pattern CP1 and expose an upper surface of the first bonding layer BNL1, and the first bonding layer BNL1 is also ground (step S20).

[0038] Figure 9A is an enlarged view of a portion 'P5' of Figure 8B or Figure 8D, and Figure 9B is an enlarged view of a portion 'P9' of Figure 9A.

[0039] 7, 8B, 9A and 9B, as the top surface of the first bonding film BNL1 is ground, the top surface of the first bonding film BNL1 appears flat macroscopically as shown in Fig. 8B, but has a surface roughness of several angstroms or several nm microscopically as shown in Fig. 9A. At the surface UEP of the first bonding film BNL1, CN groups may be bonded to silicon (Si) atoms as shown in Fig. 9B.

[0040] FIG. 10 is an enlarged view of the portion 'P6' of FIG. 8C or FIG. 8E.

[0041] 7, 8C, and 10, CN groups are removed from the surface UEP of the first bonding film BNL1 in FIG. 9B, and dangling bonds DB are formed in silicon (Si) atoms (third step, S30). To this end, a first plasma process PL1 is performed on the first bonding film BNL1 in the state of FIG. 8B. The first plasma process PL1 may be performed using at least one of oxygen, nitrogen, and argon. The third step (S30) may also be referred to as a 'step of activating the surface of the first bonding film BNL1'.

[0042] 7 and 8D, a second semiconductor die 100 including a second bonding film BNL2 disposed at the top end is prepared (step 4, S40). The second semiconductor die 100 may have the same / similar structure as that described with reference to FIGS. 1 and 2. The second semiconductor die 100 may include a second interlayer insulating film IL2 and a second bonding film BNL2 sequentially stacked on a second substrate 21. The second bonding film BNL2 is made of SiCN. The second bonding film BNL2 may include a plurality of SiCN grains GRN as shown in FIG. 3A. A second conductive pattern CP2 is disposed in the second bonding film BNL2. A plurality of second semiconductor dies 100 may be provided and attached to a second carrier substrate CR2 via a second sacrificial adhesive film AL2.

[0043] The upper surface of the second bonding layer BNL2 may also be ground in the grinding process for manufacturing the second conductive pattern CP2. Therefore, the upper surface of the second bonding layer BNL2 appears flat macroscopically as shown in Fig. 8D, but has a surface roughness of several angstroms or several nanometers microscopically as shown in Fig. 9A. The surface UEP of the second bonding layer BNL2 may have CN groups bonded to silicon (Si) atoms as shown in Fig. 9B.

[0044] 7 and 8E, as shown in FIG. 10, CN is removed from the surface of the second bonding film BNL2 to form dangling bonds in silicon (Si) atoms (step 5, S50). To this end, a second plasma process PL2 is performed on the second bonding film BNL2. The second plasma process PL2 may be performed using at least one of oxygen, nitrogen, and argon. The fifth step (S50) may also be referred to as a 'step of activating the surface of the second bonding film BNL2'.

[0045] Figure 11A is an enlarged view of the 'P7' portion of Figure 8F, and Figure 11B is an enlarged view of the 'P10' portion of Figure 11A.

[0046] 7, 8F, 11A, and 11B, an OH group is bonded to the dangling bonds DB of the silicon atoms on the surface of the first bonding film BNL1 (step 6, S60). An OH group is bonded to the dangling bonds DB of the silicon atoms on the surface of the second bonding film BNL2 (step 7, S70). The sixth step may be performed by performing a cleaning process using deionized water on the upper surface of the first bonding film BNL1. In the cleaning process, the deionized water WL1 removes particles on the first bonding film BNL1, and at the same time, the OH group of the water molecules of the deionized water WL1 may be bonded to the dangling bonds DB of the silicon atoms. The seventh step may be performed by performing a cleaning process using deionized water on the upper surface of the second bonding film BNL2. In the cleaning process, the deionized water WL1 removes particles on the second bonding film BNL2, and at the same time, OH groups of water molecules of the deionized water WL1 can be bonded to the dangling bonds DB of the silicon atoms.

[0047] Figure 12A is an enlarged view of a portion 'P8' in Figure 8G, and Figure 12B is an enlarged view of a portion 'P11' in Figure 12A.

[0048] 7, 8F, 8G, 12A, and 12B, the second semiconductor die 100 is placed upside down on the first wafer WF1 so that the second bonding film BNL2 contacts the first bonding film BNL1 (step 8, S80). Therefore, deionized water WL1 or water molecules may be present at the interface IF between the second bonding film BNL2 and the first bonding film BNL1 as shown in FIG 12A. Or, OH groups may be adjacent to each other at the interface IF between the second bonding film BNL2 and the first bonding film BNL1 as shown in FIG 12B. In the eighth step (S80), the first conductive pattern CP1 and the second conductive pattern CP2 may contact each other.

[0049] FIG. 13 is an enlarged view of part 'P8' in FIG. 8G.

[0050] 7, 8G, and 13, a first bonding process is performed to form a silicon oxide film 31 between the second bonding film BNL2 and the first bonding film BNL1, and the second bonding film BNL2 and the first bonding film BNL1 are bonded (step S90). The first bonding process may be referred to as a first thermocompression bonding process. The first bonding process may be performed at 100 to 150° C. Through the first bonding process, OH groups on the surface of the second bonding film BNL2 react with OH groups on the surface of the first bonding film BNL1 to form H, which is a water molecule WM. 2 As shown in FIG. 4, the remaining oxygen atoms (O) covalently bond with silicon atoms on the surface of the second bonding film BNL2 and silicon atoms on the surface of the first bonding film BNL1 to form the silicon oxide film 31.

[0051] The water molecule WM formed in the first bonding step is H 2 O may penetrate into the boundary gap VC along the boundary between the SiCN grains GRN (along the first arrow A1) and cause a compressive stress toward the interface IF between the first bonding film BNL1 and the second bonding film BNL2 (in the direction of the second arrow A2). Therefore, the gap between the first bonding film BNL1 and the second bonding film BNL2 may be reduced, the bonding area may be increased, and the adhesive strength may be improved. The compressive stress may increase the covalent bond area between the oxygen atoms and the silicon atoms of the silicon oxide film 31. Therefore, the adhesive strength between the first semiconductor die 10 and the second semiconductor die 100 may be improved in the finally formed semiconductor package 1000. Therefore, the process defects may be reduced and the yield may be improved.

[0052] As the water molecules WM escape during the first bonding process, at least one void PO may be formed in the silicon oxide film 31 as shown in FIG. 3A. As described with reference to FIG. 2, the void PO may have a first height HT1. The first height HT1 may be 1 Å to 2 nm. The void PO may have a third width WT3. The third width WT3 may be 1 nm to 100 nm. The water molecules WM may move along the interface between the first wafer WF1 and the second semiconductor die 100 and escape to the edge of the second semiconductor die 100.

[0053] Some of the water molecules WM may remain trapped in boundary gaps VC between the SiCN grains GRN in the first bonding film BNL1 and the second bonding film BNL2, as shown in FIG. 3B.

[0054] Subsequently, although not shown in FIG. 7, referring to FIG. 8G, a second bonding process may be performed after the first bonding process to bond the first conductive pattern CP1 and the second conductive pattern CP2 to each other. The second bonding process may be referred to as a second thermocompression bonding process. The second bonding process may be performed at a temperature that diffuses or melts a metal (e.g., copper) constituting the first conductive pattern CP1 and the second conductive pattern CP2. The second bonding process may be performed at a temperature of 250 to 350°C.

[0055] Next, referring to Fig. 8H, a mold film MD is formed on the first wafer WF1. Then, as shown in Fig. 8I, a single galling process is performed to cut out the separation region SR of the first wafer WF1 and the mold film MD thereon. Thus, the semiconductor package 1000 of Fig. 1 can be manufactured.

[0056] According to the method for manufacturing a semiconductor package according to the present invention, the adhesive strength between the first semiconductor die 10 and the second semiconductor die 100 can be improved, thereby reducing process defects and improving yields.

[0057] Although the embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention can be embodied in other specific forms without changing the technical concept or essential features of the present invention. Therefore, it should be understood that the embodiments described above are illustrative in all respects and are not limiting. [Explanation of symbols]

[0058] 1 First board 21 Second board 11 First through via 111 2nd Through Via 13 First through insulating film 113 Second through insulating film 25 1st wiring 35 2nd wiring 31 Silicon oxide film 10 First semiconductor die 100 Second semiconductor die 1000 Semiconductor Packages BNL1 First bonding film BNL2 Second bonding film CP1 First conductive pattern CP1 Second conductive pattern IL1 First interlayer insulating film IL2 First interlayer insulating film MD mold film PO void SB external connection terminal PO void

Claims

1. a first semiconductor die including a first substrate and a first bonding film on the first substrate; a second semiconductor die including a second substrate and a second bonding film below the second substrate and disposed on the first semiconductor die; a silicon oxide layer interposed between the first semiconductor die and the second semiconductor die; At least one pore is disposed in the silicon oxide film, The height of the gap is between 1 Å and 2 nm.

2. The semiconductor package according to claim 1 , wherein the width of the gap is between 1 nm and 100 nm.

3. the first bonding film and the second bonding film each include a plurality of SiCN grains; The semiconductor package of claim 1 , wherein an average size of the SiCN grains is greater than a height of the gap.

4. The semiconductor package of claim 3 , wherein the first bonding film or the second bonding film further comprises water molecules trapped between the SiCN grains.

5. the first semiconductor die further includes a first conductive pattern located on the first substrate and passing through the first bonding film; the second semiconductor die further includes a second conductive pattern located under the second substrate, penetrating the second bonding film and contacting the first conductive pattern; The semiconductor package of claim 1 , wherein the gap is spaced apart from the first conductive pattern and the second conductive pattern.

6. The semiconductor package of claim 5 , wherein a width of the first conductive pattern is different from a width of the second conductive pattern.

7. the silicon oxide film has a first thickness; The semiconductor package of claim 1 , wherein the first bonding film or the second bonding film has a second thickness that is greater than the first thickness.

8. The semiconductor package of claim 1 , wherein the gap is spaced apart from the first bonding film or the second bonding film.

9. a first semiconductor die including a first substrate and a first bonding film on the first substrate; a second semiconductor die including a second substrate and a second bonding film below the second substrate and disposed on the first semiconductor die; a silicon oxide layer interposed between the first semiconductor die and the second semiconductor die; At least one void is disposed within the silicon oxide film; the first bonding film and the second bonding film include a plurality of SiCN grains; A semiconductor package, wherein the height of the void is smaller than an average size of the SiCN grains.

10. The semiconductor package of claim 9 , wherein the height of the gap is between 1 Å and 2 nm.

11. 10. The semiconductor package according to claim 9, wherein the width of the gap is between 1 nm and 100 nm.

12. the first semiconductor die further includes a first conductive pattern located on the first substrate and passing through the first bonding film; the second semiconductor die further includes a second conductive pattern located under the second substrate, penetrating the second bonding film and contacting the first conductive pattern; The semiconductor package of claim 9 , wherein the gap is spaced apart from the first conductive pattern and the second conductive pattern.

13. The semiconductor package of claim 12 , wherein a width of the first conductive pattern is different from a width of the second conductive pattern.

14. the silicon oxide film has a first thickness; The semiconductor package of claim 9 , wherein the first bonding film or the second bonding film has a second thickness that is greater than the first thickness.

15. The semiconductor package of claim 9 , wherein the gap is spaced apart from the first bonding film or the second bonding film.

16. a first semiconductor die including a first substrate, a first bonding film on the first substrate, and a first conductive pattern extending through the first bonding film; a second semiconductor die disposed on the first semiconductor die and partially exposing a top surface of the first semiconductor die; the second semiconductor die includes a second substrate, a second bonding film under the second substrate, and a second conductive pattern passing through the second bonding film; a silicon oxide film interposed between the first bonding film and the second bonding film and in contact with side surfaces of the first conductive pattern and the second conductive pattern; a molding film covering a side surface of the second semiconductor die and a top surface of the first semiconductor die; an external connection terminal bonded to a bottom surface of the first semiconductor die; The first bonding film and the second bonding film are formed of SiCN, the first bonding film or the second bonding film has a first thickness; the silicon oxide film has a second thickness less than the first thickness; At least one void is disposed within the silicon oxide film; The gap is spaced apart from the first conductive pattern and the second conductive pattern.

17. 17. The semiconductor package of claim 16, wherein the height of the gap is between 1 Å and 2 nm.

18. 17. The semiconductor package according to claim 16, wherein the width of the gap is from 1 nm to 100 nm.

19. The semiconductor package of claim 16 , wherein a width of the first conductive pattern is different from a width of the second conductive pattern.

20. The semiconductor package of claim 16 , wherein the gap is spaced apart from the first bonding film or the second bonding film.

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