Power semiconductor element and power conversion device including the same, and manufacturing method for power semiconductor element

Abstract

To provide a power semiconductor element, a module, a conversion device, and a manufacturing method for the same.SOLUTION: A power semiconductor element includes a substrate 111, a first conductivity type epitaxial layer 112 disposed on the substrate, a second conductivity type well 113 disposed partially on the first conductivity type epitaxial layer, a second conductivity type ion injection region 114 disposed partially in the second conductivity type well, a source region 115 disposed partially in the second conductivity type well and disposed on the second conductivity type ion injection region, a gate insulating layer 136 disposed on the source region and the second conductivity type well, a gate 134 disposed on the gate insulating layer, an interlayer insulating layer 132 disposed on the gate, and a source electrode 130 disposed on the source region. The gate insulating layer includes a channel gate insulating layer 136a with a first thickness, and a projection type gate insulating layer 136b with a second thickness, which is larger than the first thickness. The concentration in an Rb region, which is a lateral resistance in the second conductivity type ion injection region, is higher than the concentration of the second conductivity type well.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The embodiments relate to a power semiconductor device, a power semiconductor module, a power conversion device, and a manufacturing method thereof. [Background technology]

[0002] Power semiconductors are one of the key elements that determine the efficiency, speed, durability and reliability of power electronic systems.

[0003] Recently, with the development of the power electronics industry, the silicon ((Silicon)Si) power semiconductors that have been used until now have reached their physical limits, and research into WBG (Wide Bandgap) power semiconductors such as silicon carbide ((Silicon Carbide)SiC) and gallium nitride ((Galium Nitride)GaN) as alternatives is being actively conducted.

[0004] WBG power semiconductor elements have a band gap energy approximately three times that of Si power semiconductor elements, which gives them the following characteristics: low intrinsic carrier concentration, high dielectric breakdown field (approximately 4 to 20 times), high thermal conductivity (approximately 3 to 13 times), and large electron saturation velocity (approximately 2 to 2.5 times).

[0005] These characteristics allow them to operate in high-temperature, high-voltage environments and have high switching speeds and low switching losses. Among these, gallium nitride (GaN) power semiconductor devices can be used in low-voltage systems, while silicon carbide (SiC) power semiconductor devices are suitable for high-voltage systems.

[0006] Conventional SiC MOSFETs can be classified according to their structure into trench structure MOSFETs, vertical doubly implanted structure MOSFETs (DIMOSFETs), and lateral diffused structure MOSFETs. DIMOSFETs are also called planar MOSFETs or VDMOSFETs.

[0007] On the other hand, power MOSFETs must have low conduction and switching loss characteristics and must be stable enough to prevent parasitic bipolar elements from operating in high current situations such as unclamped inductive switching (UIS) situations.

[0008] The reason why power MOSFET devices lose stability in UIS situations is that when a high inductive current is generated in the device, a parasitic NPN bipolar transistor is activated, which causes a temperature rise and a voltage drop across Rb (internal base resistance), resulting in serious damage.

[0009] Furthermore, when UIS occurs, abrupt voltage and current spikes occur inside the device, which can lead to the destruction of the power semiconductor device.

[0010] Therefore, UIS is one of the important issues that must be considered in the design and manufacture of power semiconductor devices.

[0011] Research has been conducted into the use of stepped gate insulation layers in internal MOSFET technology to improve switching loss characteristics. The stepped gate insulation layer structure is a structure in which a thick insulation layer is placed in the area excluding the P-well where the channel is formed, which reduces Cgd, the oxide capacitance formed between the gate and drain, improving switching loss characteristics.

[0012] However, in the DIMOSFET technology having the stepped gate insulating layer of the internal technology, the amount of di / dt change increases, resulting in a problem of degraded UIS (Unclamped Inductive Switching) characteristics.

[0013] That is, in the case of internal technology, when a stepped insulating layer structure is adopted to improve switching loss characteristics, the UIS characteristics of the power MOSFET element deteriorate, causing sudden voltage and current spikes, which may result in destruction of the power semiconductor element, creating a technical contradiction. Summary of the Invention [Problem to be solved by the invention]

[0014] A technical problem of the embodiments is to provide a power semiconductor device, a power semiconductor module, a power converter, and a manufacturing method thereof that can substantially solve one or more problems due to the limitations and shortcomings described above.

[0015] Additional features and advantages of the embodiments will be set forth in the description that follows, and in part will be apparent from the description or will be learned by the embodiments. Other advantages of the embodiments will be realized and attained by the structure particularly pointed out in the detailed description and claims hereof, as well as the appended drawings.

[0016] One of the technical objectives of the embodiment is to provide a power semiconductor element and a power conversion device including the same, which can solve the technical contradiction that, when a stepped insulating layer structure is adopted to improve switching loss characteristics, sudden voltage and current spikes occur due to a deterioration in UIS (Unclamped Inductive Switching) characteristics, thereby causing damage to the power semiconductor element.

[0017] The technical problems of the embodiments are not limited to those described in this section, but include those that can be understood from the description of the invention. [Means for solving the problem]

[0018] The power semiconductor device of the embodiment may include a substrate 111, a first conductive type epitaxial layer 112 disposed on the substrate 111, a second conductive type well 113 partially disposed on the first conductive type epitaxial layer 112, a second conductive type ion implantation region 114 partially disposed in the second conductive type well 113, a source region 115 partially disposed in the second conductive type well 113 and disposed on the second conductive type ion implantation region 114, a gate insulating layer 136 disposed on the source region 115 and the second conductive type well 113, a gate 134 disposed on the gate insulating layer 136, an interlayer insulating layer 132 disposed on the gate 134, and a source electrode 130 disposed on the source region 115.

[0019] The gate insulating layer 136 may include a channel gate insulating layer 136a having a first thickness and a protruding gate insulating layer 136b having a second thickness that is thicker than the first thickness.

[0020] The concentration in the Rb region, which is the lateral resistance of the second conductive type ion implantation region 114, is higher than the concentration in the second conductive type well 113.

[0021] The concentration in the Rb region, which is the lateral resistance of the second conductive type ion implantation region 114, is characterized by being 90 to 100 times higher than the concentration of the second conductive type well 113.

[0022] The source electrode 130 may include a protruding source contact electrode 130 p disposed in the source region 115 and in a recessed region of the second conductive type ion implantation region 114 .

[0023] The protruding source contact electrode 130p may contact an upper surface 115T of the source region and a side surface 115S of the source region.

[0024] A power conversion device according to an embodiment may include any one of the power semiconductor devices described above.

[0025] Also, a method for manufacturing a power semiconductor device includes the steps of preparing a substrate 111 including a first conductive type epitaxial layer 112, forming a first hard mask pattern 120M1 on the first conductive type epitaxial layer 112 to form a second conductive type well 113, forming a second hard mask pattern 120M2 on a sidewall of the first hard mask pattern 120M1, implanting ions into the second conductive type well 113 using the first hard mask pattern 120M1 and the second hard mask pattern 120M2 as an ion implantation mask to form a first conductive type source region 115, and forming a first hard mask pattern 120M1 and a second hard mask pattern 120M2 on the sidewall of the first hard mask pattern 120M1. The method may include the steps of forming a third hard mask pattern 120M3 on the hard mask pattern 120M2, implanting ions in a self-aligned manner using the first, second, and third hard mask patterns 120M1, 120M2, and 120M3 as ion implantation masks to form a second conductive type ion implantation region 114 in the second conductive type well 113, removing the first, second, and third hard mask patterns 120M1, 120M2, and 120M3, and sequentially forming a gate insulating layer 136, a gate 134, and an interlayer insulating layer 132 on the source region 115 and the second conductive type well 113.

[0026] In addition, the power semiconductor device of the embodiment may include a first conductive type epitaxial layer disposed on a substrate, a second conductive type well disposed on the first conductive type epitaxial layer, a second conductive type ion implantation region disposed in the second conductive type well, a source region disposed on the second conductive type ion implantation region in the second conductive type well, a recess located between a first gate and a second gate, disposed between two adjacent source regions, and reaching an upper portion of the second conductive type ion implantation region, and a source electrode filled in the recess and in contact with the second conductive type ion implantation region.

[0027] A lateral length of the second conductive type ion implantation region may be equal to a combined length of the two adjacent source regions and the cross section of the recess.

[0028] Also, the embodiment may further include a gate insulating layer disposed on the source region and the second conductive well.

[0029] The first and second gates are disposed on the gate insulating film.

[0030] Also, the embodiment may further include an interlayer insulating film disposed on the first gate and the second gate.

[0031] The gate insulating layer may include a channel gate insulating layer having a first thickness and a protruding gate insulating layer having a second thickness that is thicker than the first thickness.

[0032] The second conductive type ion implantation region may have a higher concentration of Rb than the second conductive type well.

[0033] Also, the embodiment may further include a metal barrier layer on the interlayer insulating film and in the recess.

[0034] The step of forming the second conductive type ion implantation region 114 may involve implanting ions in a self-aligned manner using the first, second, and third hard mask patterns 120M1, 120M2, and 120M3 as ion implantation masks, thereby forming the second conductive type ion implantation region 114 in the second conductive type well 113 through the first conductive type source region 115.

[0035] The second conductive type ion implantation region 114 is disposed to cover a lower region of the source region 115 .

[0036] The concentration of the Rb region, which is a side resistance of the second conductive type ion implantation region, may be higher than the concentration of the second conductive type well.

[0037] The concentration in the Rb region, which is the lateral resistance of the second conductive type ion implantation region 114, is characterized by being 90 to 100 times higher than the concentration of the second conductive type well 113.

[0038] The gate insulating layer 136 may include a channel gate insulating layer 136a having a first thickness and a protruding gate insulating layer 136b having a second thickness that is thicker than the first thickness.

[0039] The embodiment may further include forming a source electrode 130 on the source region 115 after patterning the layer disposed above the source region 115 .

[0040] The source electrode 130 may include a protruding source contact electrode 130 p disposed in the source region 115 and in a recessed region of the second conductive type ion implantation region 114 .

[0041] The protruding source contact electrode 130p may contact an upper surface 115T of the source region and a side surface 115S of the source region. Effect of the Invention

[0042] According to the power semiconductor device and the power semiconductor module and power conversion device including the same according to the embodiments, when a stepped insulating layer structure is adopted to improve switching loss characteristics, a technical contradiction occurs in which a sudden voltage and current spike occurs due to a deterioration in UIS (Unclamped Inductive Switching) characteristics, thereby causing damage to the power semiconductor device. This has a technical effect of solving the technical contradiction.

[0043] For example, the gate insulating layer 136 of the embodiment includes a channel gate insulating layer 136a and a protruding gate insulating layer 136b. By disposing the thick protruding gate insulating layer 136b in an area other than the P-well where the channel is formed, the oxide capacitance Cgd formed between the gate and drain is reduced, and the Miller Capacitance (Cgd) value associated with the switching speed is reduced, thereby improving the switching loss characteristics of the element.

[0044] At the same time, the embodiment has a special technical effect of significantly improving the alignment accuracy of the second conductive type ion implantation region 114 disposed under the source region 115 and reducing the Rb resistance, thereby resolving the technical contradiction of degraded UIS (Unclamped Inductive Switching) characteristics.

[0045] For example, in the embodiment, in a self-aligned structure for the source region 115, a CVD film of a certain thickness may be deposited, and then the second conductive type ion implantation region 114 may be ion-implanted in a self-aligned manner.

[0046] For example, in the embodiment, instead of using a photo method, a second conductive type ion implantation region 114 can be formed under the source region 115 using a self-alignment method by depositing an insulating layer of a certain thickness and then strongly implanting ions. This makes it possible to form the second conductive type ion implantation region 114 that thinly covers the source region 115 while ensuring the thickness of the second conductive type well 113, which is a P body, to withstand internal pressure.

[0047] As a result, in the embodiment, compared to the existing photo align method, the second conductive type ion implantation region 114 can be controlled to finely cover the lower region of the source region 115, and the Rb (internal base resistance) resistance related to the operation of the parasitic NPN BJT (bipolar junction transistor) can be dramatically reduced.

[0048] For example, in the conventional internal technology, the Rb concentration is similar to the concentration of the second conductivity type well 113, which is the second conductivity type body. However, when the embodiment is applied, the Rb concentration is similar to the concentration of the second conductivity type ion implantation region 114, and thus has a higher concentration than before, dramatically reducing the Rb (internal base resistance) resistance, thereby suppressing the operation of the parasitic NPN BJT and improving the UIS characteristics.

[0049] For example, when the embodiment is applied, the Rb concentration has a similar concentration to that of the second conductivity type ion implantation region 114, so that the Rb resistance can be dramatically reduced by providing a concentration 10 times or more higher than the conventional one.

[0050] Furthermore, for example, when the embodiment is applied, the Rb concentration has a similar concentration to that of the second conductivity type ion implantation region 114, and thus the Rb resistance can be dramatically reduced by providing a concentration 30 times or more higher than in the past.

[0051] Furthermore, for example, when the embodiment is applied, the Rb concentration has a similar concentration to that of the second conductivity type ion implantation region 114, and thus the Rb resistance can be dramatically reduced by providing a concentration 50 times higher than in the past.

[0052] For example, when the embodiment is applied, the Rb concentration is similar to the concentration of the second conductive type ion implantation region 114, and thus the Rb (internal base resistance) resistance is dramatically reduced with a concentration 90 to 100 times higher than conventionally, resulting in a special technical effect of suppressing the operation of the parasitic NPN BJT and improving UIS characteristics.

[0053] In addition, in the embodiment, in a self-aligned structure for the source region 115 in the conventional internal technology, ion implantation can be performed in a self-aligned manner up to the second conductive type ion implantation region 114, which increases the degree of freedom of the contact align process in the subsequent process. This has the effect of significantly increasing cell density, thereby providing the technical effect of improving Ron characteristics.

[0054] The source electrode 130 of the embodiment may include a protruding source contact electrode 130p having a body contact shape and disposed in the source region 115 and the recess region of the second conductive type ion implantation region 114. The protruding source contact electrode 130p contacts the top surface 115T of the source region and the side surface 115S of the source region, thereby increasing the contact area and improving the Ron characteristics.

[0055] The technical effects of the embodiments are not limited to those described in this section, but include those that can be understood from the description of the invention.

[0056] The foregoing general description and the following detailed description are exemplary and are intended to provide further explanation of the subject matter recited in the claims. [Brief description of the drawings]

[0057] The accompanying drawings, which are included to provide an understanding of the embodiments and constitute a part of the invention, illustrate one aspect of the invention and, together with the description, explain the principles of the invention. [Figure 1] FIG. 1 is a diagram illustrating an example of a configuration of a power conversion device 1000 according to an embodiment. [Diagram 2] FIG. 2 is a cross-sectional view of a power semiconductor device 100 according to an embodiment. [Figure 3a] FIG. 3a is a cross-sectional view of a power semiconductor device 100 according to an embodiment. [Figure 3b] FIG. 3b is a detailed partial cross-sectional view of the power semiconductor device 100 of FIG. 3a. [Figure 4] FIG. 4 is a detailed view of region D of the cross-sectional view of the power semiconductor device 100 shown in FIG. 3b. [Figure 5a] FIG. 5a is a cross-sectional view of a manufacturing process of the power semiconductor device 100 according to the embodiment. [Figure 5b] FIG. 5b is a cross-sectional view of a manufacturing process of the power semiconductor device 100 according to the embodiment. [Figure 5c] FIG. 5c is a cross-sectional view of a manufacturing process of the power semiconductor device 100 according to the embodiment. [Figure 5d] FIG. 5d is a cross-sectional view of a manufacturing process of the power semiconductor device 100 according to the embodiment. [Figure 5e] FIG. 5e is a cross-sectional view of a manufacturing process of the power semiconductor device 100 according to the embodiment. [Figure 5f] FIG. 5f is a cross-sectional view of a manufacturing process of the power semiconductor device 100 according to the embodiment. [Figure 5g]FIG. 5g is a cross-sectional view of a manufacturing process of the power semiconductor device 100 according to the embodiment. [Figure 5h] FIG. 5h is a cross-sectional view of a manufacturing process of the power semiconductor device 100 according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0058] Hereinafter, the invention according to the embodiment for solving the above problems will be described in more detail with reference to the drawings.

[0059] The suffixes "module" and "section" for components used in the following description are merely given to facilitate the writing of the specification and do not impart any particular significance or role to the components themselves. Therefore, the terms "module" and "section" can be used interchangeably.

[0060] Terms including ordinal numbers such as first, second, etc. may be used to describe various components, but the components are not limited by the terms. The terms are used only to distinguish one component from another.

[0061] A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0062] In this application, the terms "including," "having," or "comprising" are intended to specify the presence of any feature, number, step, operation, component, part, or combination thereof set forth in the specification, but are not to be understood as precluding the presence or additional possibility of one or more other features, number, steps, operations, components, parts, or combinations thereof.

[0063] (Example) FIG. 1 is a diagram illustrating an example of a configuration of a power conversion device 1000 according to an embodiment.

[0064] The power conversion device 1000 according to the embodiment can receive DC power from a battery or a fuel cell, convert it into AC power, and supply the AC power to a predetermined load. For example, the power conversion device 1000 according to the embodiment can include an inverter, receive DC power from a battery, convert it into three-phase AC power, and supply it to a motor M, and the motor M can provide power to an electric vehicle, a fuel cell vehicle, etc.

[0065] The power converter 1000 according to the embodiment may include a power semiconductor device 100. The power semiconductor device 100 may be, but is not limited to, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and may include an Insulated Gate Bipolar Transistor (IGBT).

[0066] For example, the power converter 1000 may include a plurality of power semiconductor devices 100a, 100b, 100c, 100d, 100e, and 100f, and may include a plurality of diodes (not shown). Each of the plurality of diodes may be included in the power semiconductor devices 100a, 100b, 100c, 100d, 100e, and 100f in the form of an internal diode, but is not limited thereto, and may be disposed separately.

[0067] The embodiment can convert DC power into AC power by controlling the on / off of the multiple power semiconductor elements 100a-100f. For example, the power conversion device 1000 according to the embodiment can supply positive power to the motor M by turning on the first power semiconductor element 100a and turning off the second power semiconductor element 100b in a first time interval of one cycle, and supply negative power to the motor M by turning off the first power semiconductor element 100a and turning on the second power semiconductor element 100b in a second time interval of one cycle.

[0068] In the embodiment, a group of power semiconductor devices arranged in series on the high voltage line and low voltage line on the input side may be called an arm. For example, the first power semiconductor device 100a and the second power semiconductor device 100b may form the first arm 12a, the third power semiconductor device 100c and the fourth power semiconductor device 100d may form the second arm 12b, and the fifth power semiconductor device 100e and the sixth power semiconductor device 100f may form the third arm 12c.

[0069] The upper and lower power semiconductor devices in each arm are controlled so as not to be turned on at the same time. For example, the first and second power semiconductor devices 100a and 100b in the first arm are not turned on at the same time but can be turned on and off alternately.

[0070] A high voltage is applied to each of the power semiconductor elements 100a-100f when the element is off. For example, when the first power semiconductor element 100a is on and the second power semiconductor element 100b is off, the input voltage is applied to the second power semiconductor element 100b as is. The voltage input to the second power semiconductor element 100b is a relatively high voltage, and the withstand voltage of each of the power semiconductor elements 100a-100f is designed to be at a high level so that the power semiconductor elements 100a-100f can withstand such a high voltage.

[0071] Each of the power semiconductor elements 100a to 100f can conduct a high current when it is turned on. The motor M is driven by a relatively high current, and this high current is supplied to the motor M through the power semiconductors that are turned on.

[0072] A high voltage applied to each of the power semiconductor elements 100a-100f may induce high switching loss. A high current passing through the power semiconductor elements 100a-100f may induce high conduction loss. In order to dissipate heat generated by such losses, the power semiconductor elements 100a-100f may be packaged in a power semiconductor module including a heat dissipation means.

[0073] The power semiconductor device 100 of the embodiment may be a silicon carbide (SiC) power semiconductor device, which is capable of operating in a high temperature, high voltage environment, and has a high switching speed and low switching loss.

[0074] Meanwhile, the power conversion device 1000 according to the embodiment may include a plurality of power semiconductor modules.

[0075] For example, the multiple power semiconductor devices 100a to 100f shown in FIG. 1 may be packaged in one power semiconductor module, or the power semiconductor devices constituting each arm may be packaged in one power semiconductor module.

[0076] For example, the first power semiconductor device 100a, the second power semiconductor device 100b, the third power semiconductor device 100c, the fourth power semiconductor device 100d, the fifth power semiconductor device 100e, and the sixth power semiconductor device 100f shown in FIG. 1 may be packaged into one power semiconductor module.

[0077] In addition, there may be additional power semiconductor devices arranged in parallel with each of the power semiconductor devices 100a to 100f in order to increase the current capacity. In this case, the number of power semiconductor devices included in the power semiconductor module may be more than six.

[0078] The power converter 1000 according to the embodiment may include a diode-type power semiconductor element in addition to the transistor-type power semiconductor elements 100a to 100f. For example, a first diode (not shown) may be arranged in parallel with the first power semiconductor element 100a, and a second diode (not shown) may be arranged in parallel with the second power semiconductor element 100b. Such diodes may also be packaged together in one power semiconductor module. The diodes may also be arranged in the form of internal diodes in each power semiconductor element.

[0079] Next, the power semiconductor elements that make up each arm may be packaged into one power semiconductor module.

[0080] For example, the first power semiconductor element 100a and the second power semiconductor element 100b constituting the first arm may be packaged in a first power semiconductor module, the third power semiconductor element 100c and the fourth power semiconductor element 100d constituting the second arm may be packaged in a second power semiconductor module, and the fifth power semiconductor element 100e and the sixth power semiconductor element 100f constituting the third arm may be packaged in a third power semiconductor module.

[0081] In addition, there may be additional power semiconductor devices arranged in parallel with each of the power semiconductor devices 100a-100f to increase the current capacity, in which case the number of power semiconductor devices included in each power semiconductor module may be more than two. Each arm may also include a diode-type power semiconductor device (not shown) in addition to the transistor-type power semiconductor devices 100a-100f, and such a diode may also be packaged together in one power semiconductor module. The diode may also be arranged in the form of an internal diode in each power semiconductor device.

[0082] Next, FIG. 2 is a cross-sectional view of one of the power semiconductor devices 100 according to the embodiment.

[0083] The power semiconductor device 100 according to the embodiment may include a source electrode 130 and a gate electrode 175 disposed on a given semiconductor epitaxial layer 120 , and a drain electrode 105 disposed on a lower side of the semiconductor epitaxial layer 120 .

[0084] In the form of a MOSFET, the source electrode 130 or the gate electrode 175 may include an Al-based metal, and the drain electrode 105 may include, but is not limited to, Ti / Ni / Ag metal including a Ti layer, a Ni layer, and an Ag layer, NiV / Ag, V(vanadium) / Ni / Ag, etc.

[0085] One of the technical objectives of the embodiment is to provide a power semiconductor element and a power conversion device including the same, which can solve the technical contradiction that, when a stepped insulating layer structure is adopted to improve switching loss characteristics, sudden voltage and current spikes occur due to a deterioration in UIS (Unclamped Inductive Switching) characteristics, thereby causing damage to the power semiconductor element.

[0086] First, the power semiconductor device according to the internal technology will be described.

[0087] In internal MOSFET technology, research is being conducted on adopting a stepped gate insulation layer in which a thick insulation layer is placed in the area other than the P-well where the channel is formed in order to improve switching loss characteristics. This reduces Cgd, which is the oxide capacitance formed between the gate and drain, and improves switching loss characteristics.

[0088] However, in the DIMOSFET technology having the stepped gate insulating layer of the internal technology, the di / dt change amount increases and the UIS (Unclamped Inductive Switching) characteristics deteriorate, which causes a sudden voltage and current spike, resulting in the destruction of the power semiconductor device.

[0089] Specifically, in a DIMOSFET technology having a stepped gate insulating layer of an internal technology, a P-type region of the opposite polarity is formed under an N+ contact region, which is a source region, by a photo process.

[0090] However, a problem was investigated in which the Rb (internal base resistance) resistance related to the operation of the parasitic NPN BJT increases due to the difficulty in aligning the P-type region directly under the N+ contact region. Rb is the lateral resistance of the P-type region of opposite polarity directly under the N+ contact.

[0091] As a result, in the DIMOSFET technology with the internal stepped gate insulation layer, the internal base resistance (Rb) increases, which increases the di / dt change amount and degrades the Unclamped Inductive Switching (UIS) characteristics, resulting in a sudden voltage and current spike, which can cause the breakdown of the power semiconductor device.

[0092] Hereinafter, a power semiconductor device 100 according to an embodiment for solving the above technical problem will be described.

[0093] FIG. 3a is a cross-sectional view of a power semiconductor device 100 according to an embodiment, and FIG. 3b is a detailed view of a portion of the cross-sectional view of the power semiconductor device 100 according to the embodiment shown in FIG. 3a.

[0094] First, referring to FIG. 3a, the power semiconductor device 100 of the embodiment may include at least one of a drain electrode 110, a substrate 111, a first conductive type epitaxial layer 112, a second conductive type well 113, a second conductive type ion implantation region 114, a first conductive type source region 115, a gate insulating layer 136, a gate 134, an interlayer insulating layer 132, and a source electrode 130.

[0095] The first conductivity type may be, but is not limited to, an n-type and the second conductivity type may be, but is not limited to, a p-type. The substrate 111 and the first conductivity type epitaxial layer 112 may include, but is not limited to, SiC (Silicon Carbide).

[0096] Specifically, the power semiconductor device 100 of the embodiment may include a substrate 111, a first conductive type epitaxial layer 112 disposed on the substrate 111, a second conductive type well 113 partially disposed on the first conductive type epitaxial layer 112, a second conductive type ion implantation region 114 partially disposed in the second conductive type well 113, and a source region 115 partially disposed in the second conductive type well 113 and disposed on the second conductive type ion implantation region 114.

[0097] Also, the power semiconductor device 100 according to the embodiment may include a gate insulating layer 136 disposed on the source region 115 and the second conductive type well 113, a gate 134 disposed on the gate insulating layer 136, an interlayer insulating layer 132 disposed on the gate 134, and a source electrode 130 disposed on the source region 115. A predetermined channel C is defined between the gate 134 and the source region 115.

[0098] Hereinafter, technical features of the power semiconductor device 100 according to the embodiment will be described in detail with reference to FIG. 3b and FIG.

[0099] FIG. 3b is a partial drawing of a cross-sectional view of the power semiconductor device 100 according to the embodiment shown in FIG. 3a, and FIG. 4 is a detailed view of region D of the cross-sectional view of the power semiconductor device 100 according to the embodiment shown in FIG. 3b.

[0100] According to the power semiconductor device and the power semiconductor module and power conversion device including the same according to the embodiments, when a stepped insulating layer structure is adopted to improve switching loss characteristics, a technical contradiction occurs in which a sudden voltage and current spike occurs due to a deterioration in UIS (Unclamped Inductive Switching) characteristics, thereby causing damage to the power semiconductor device. This has a technical effect of solving the technical contradiction.

[0101] For example, referring to FIG. 4, (1) the gate insulating layer 136 of the embodiment includes a channel gate insulating layer 136a and a protruding gate insulating layer 136b. By disposing the thick protruding gate insulating layer 136b in an area other than the P-well where the channel is formed, the oxide capacitance Cgd formed between the gate and drain is reduced, and the Miller Capacitance (Cgd) value associated with the switching speed is reduced, thereby improving the switching loss characteristics of the element.

[0102] At the same time, (2) the embodiment has a special technical effect of significantly improving the alignment accuracy of the second conductive type ion implantation region 114 disposed under the source region 115, and reducing the Rb resistance (region A), thereby resolving the technical contradiction of degraded UIS (Unclamped Inductive Switching) characteristics.

[0103] For example, in the embodiment, in a self-aligned structure for the source region 115, a CVD film of a certain thickness may be deposited, and then the second conductive type ion implantation region 114 may be ion-implanted in a self-aligned manner.

[0104] For example, in the embodiment, instead of using a photo method, a second conductive type ion implantation region 114 can be formed under the source region 115 using a self-alignment method in which an insulating layer of a certain thickness is deposited and then ions are implanted. This makes it possible to form the second conductive type ion implantation region 114 that thinly covers the source region 115 while ensuring the thickness of the second conductive type well 113, which is a P body, to withstand internal pressure.

[0105] As a result, in the embodiment, compared to the existing photo align method, the second conductive type ion implantation region 114 can be controlled to finely cover the region below the source region 115, and the Rb (internal base resistance) resistance related to the operation of the parasitic NPN BJT can be dramatically reduced.

[0106] In the conventional internal technology, the Rb concentration is similar to the concentration of the second conductive type well 113, which is the second conductive type body. However, when the embodiment is applied, the Rb concentration is similar to the concentration of the second conductive type ion implantation region 114, which is 90 to 100 times higher than before, dramatically reducing the Rb (internal base resistance) resistance, thereby suppressing the operation of the parasitic NPN BJT and improving the UIS characteristics. This provides a special technical effect.

[0107] In addition, in the embodiment, in a self-aligned structure for the source region 115 in the conventional internal technology, ion implantation can be performed in a self-aligned manner up to the second conductive type ion implantation region 114, which increases the degree of freedom of the contact align process in the subsequent process. This has the effect of significantly increasing cell density, thereby providing the technical effect of improving Ron characteristics.

[0108] In addition, in an embodiment, the source electrode 130 may include a barrier metal layer 130b and a protruding source contact electrode 130p.

[0109] The source electrode 130 of the embodiment may include a protruding source contact electrode 130p having a body contact shape and disposed in the source region 115 and the recess region of the second conductive type ion implantation region 114. The protruding source contact electrode 130p contacts the top surface 115T of the source region and the side surface 115S of the source region, thereby increasing the contact area and improving the Ron characteristics.

[0110] Next, a manufacturing process of the power semiconductor device 100 according to the embodiment will be described with reference to FIGS. 5a to 5h.

[0111] Referring to FIG. 5a, a substrate 111 including a first conductivity type epilayer 112 is provided.

[0112] The first conductive type epitaxial layer 112 may include a first conductive type buffer layer 112a and a first conductive type drift layer 112b.

[0113] The substrate 111 and the first conductive type epitaxial layer 112 may include, but are not limited to, a 4H-SiC material, for example, the substrate 111 and the first conductive type epitaxial layer 112 may include 3C-SiC or 6H-SiC.

[0114] Next, a second conductivity type well 113 may be formed in the first conductivity type epitaxial layer 112 .

[0115] For example, a first hard mask pattern 120M1 may be formed on the first conductive type epitaxial layer 112, and ions may be implanted using the first hard mask pattern 120M1 as a mask to form the second conductive type well 113. The second conductive type well 113 may be, but is not limited to, a P-type body.

[0116] The first hard mask pattern 120M1 may include, but is not limited to, a polysilicon pattern 125 and an oxide pattern 126.

[0117] The second conductive well 113 is doped with a P-type dopant at about 1×10 16 cm -3 ~Approx. 2×10 19 cm -3 For example, Al, boron, or the like may be implanted, but the present invention is not limited to this.

[0118] Next, referring to FIG. 5b, a second hard mask preliminary layer 127 may be formed on the first hard mask pattern 120M1 and etched back to form a second hard mask pattern 120M2 on the sidewalls of the first hard mask pattern 120M1 as shown in FIG. 5c.

[0119] The second hard mask preliminary layer 127 may include, but is not limited to, polysilicon.

[0120] 5d, ions may be implanted into the second conductive well 113 using the first hard mask pattern 120M1 and the second hard mask pattern 120M2 as an ion implantation mask to form a first conductive source region 115. For example, an n-type dopant such as nitrogen or phosphorus may be implanted at about 1×10 18 cm -3 ~Approx. 7×10 19 cm -3 The first conductive type source region 115 can be formed by implanting ions at a concentration of 1000 .mu.m or more in a self-aligned manner.

[0121] Next, referring to FIG. 5e, a third hard mask pattern 120M3 may be formed on the first and second hard mask patterns 120M1 and 120M2.

[0122] For example, the third hard mask pattern 120M3 may be formed on the top surface of the first hard mask pattern 120M1, the sidewalls of the second hard mask pattern 120M2, and the first conductive type source region 115 using oxide, but is not limited thereto.

[0123] Next, a second conductive type ion implantation region 114 may be formed in the second conductive type well 113 by implanting ions in a self-aligned manner using the first, second and third hard mask patterns 120M1, 120M2 and 120M3 as ion implantation masks.

[0124] For example, Al, boron or the like is implanted into the second conductivity type well 113 at a deeper position through the first conductivity type source region 115 to form a second conductivity type ion implantation region 114 .

[0125] In this embodiment, instead of using a photo method, an insulating layer of a certain thickness is deposited using a third hard mask pattern 120M3, and then ions are strongly implanted to form a second conductive type ion implantation region 114 under the source region 115 using a self-alignment method.

[0126] As a result, in the embodiment, the second conductivity type ion implantation region 114 can be controlled to finely cover the region below the source region 115, compared to the existing photo-alignment method, and the Rb (internal base resistance) resistance related to the operation of the parasitic NPN BJT can be dramatically reduced.

[0127] For example, in the conventional internal technology, the Rb concentration is similar to the concentration of the second conductive type well 113, which is the second conductive type body. However, when the embodiment is applied, the Rb concentration is similar to the concentration of the second conductive type ion implantation region 114, which is 90 to 100 times higher than before, dramatically reducing the Rb (internal base resistance) resistance, thereby suppressing the operation of the parasitic NPN BJT and improving the UIS characteristics. This provides a special technical effect.

[0128] In addition, since ions can be implanted in a self-aligned manner not only in the source region 115 but also in the second conductive type ion implantation region 114, the degree of freedom of contact align, which is a post-process, is increased, resulting in a significant increase in cell density and an improvement in Ron characteristics.

[0129] Next, referring to FIG. 5f, the first, second, and third hard mask patterns 120M1, 120M2, and 120M3 may be removed by CMP, etching, or the like.

[0130] Next, referring to FIG. 5g, a gate insulating layer 136 may be formed on the source region 115 and the second conductive well 113, a gate 134 may be formed on the gate insulating layer 136, and an interlayer insulating layer 132 may be formed on the gate 134.

[0131] The gate insulating layer 136 may be, but is not limited to, a thermal oxide film or a vapor-deposited oxide film. The gate 134 may be, but is not limited to, polysilicon. The interlayer insulating layer 132 may be, but is not limited to, an oxide film or a nitride film.

[0132] The gate insulating layer 136 may include a channel gate insulating layer 136a and a protruding gate insulating layer 136b. In the embodiment, by disposing a thick protruding gate insulating layer 136b in an area other than the P-well where a channel is formed, Cgd, which is an oxide capacitance formed between the gate and the drain, is reduced, and a Miller Capacitance (Cgd) value associated with a switching speed is reduced, thereby improving the switching loss characteristic of the device.

[0133] Next, referring to FIG. 5h, a source electrode 130 may be formed on the source region 115 after patterning the layers disposed above the source region 115. As shown in FIG.

[0134] The source electrode 130 may be made of, but is not limited to, Al, etc. Also, the source electrode 130 may further include a barrier metal layer 130b (see FIGS. 3a, 3b, and 4).

[0135] The source electrode 130 of the embodiment may include a protruding source contact electrode 130p having a body contact shape and disposed in the source region 115 and the recess region of the second conductive type ion implantation region 114.

[0136] In the embodiment, the protruding source contact electrode 130p contacts the top surface 115T of the source region and the side surface 115S of the source region, thereby increasing the contact area and providing a composite technical effect of improving the Ron characteristics.

[0137] According to the power semiconductor device and the power semiconductor module and power conversion device including the same according to the embodiments, when a stepped insulating layer structure is adopted to improve switching loss characteristics, a technical contradiction occurs in which a sudden voltage and current spike occurs due to a deterioration in UIS (Unclamped Inductive Switching) characteristics, thereby causing damage to the power semiconductor device. This has a technical effect of solving the technical contradiction.

[0138] For example, the gate insulating layer 136 of the embodiment includes a channel gate insulating layer 136a and a protruding gate insulating layer 136b. By disposing the thick protruding gate insulating layer 136b in an area other than the P-well where the channel is formed, the oxide capacitance Cgd formed between the gate and drain is reduced, and the Miller Capacitance (Cgd) value associated with the switching speed is reduced, thereby improving the switching loss characteristics of the element.

[0139] At the same time, the embodiment has a special technical effect of significantly improving the alignment accuracy of the second conductive type ion implantation region 114 disposed under the source region 115, and reducing the Rb resistance (region A), thereby resolving the technical contradiction of degraded UIS (Unclamped Inductive Switching) characteristics.

[0140] For example, in the embodiment, compared to the existing photo align method, the second conductive type ion implantation region 114 can be controlled to finely cover the area under the source region 115, and the Rb (internal base resistance) resistance related to the operation of the parasitic NPN BJT can be dramatically reduced.

[0141] For example, in the conventional internal technology, the Rb concentration is similar to the concentration of the second conductive type well 113, which is the second conductive type body. However, when the embodiment is applied, the Rb concentration is similar to the concentration of the second conductive type ion implantation region 114, which is 90 to 100 times higher than before, dramatically reducing the Rb (internal base resistance) resistance, thereby suppressing the operation of the parasitic NPN BJT and improving the UIS characteristics. This provides a special technical effect.

[0142] In addition, in the embodiment, in a self-aligned structure for the source region 115, which is a conventional internal technology, ion implantation can be performed in a self-aligned manner up to the second conductive type ion implantation region 114, which increases the degree of freedom of the contact align process, which has the effect of significantly increasing cell density, thereby improving Ron characteristics.

[0143] Also, the source electrode 130 of the embodiment may include a protruding source contact electrode 130p having a body contact shape and disposed in the source region 115 and the recess region of the second conductive type ion implantation region 114. The protruding source contact electrode 130p contacts the top surface 115T of the source region and the side surface 115S of the source region, thereby increasing the contact area and improving the Ron characteristics.

[0144] Although the present invention has been described above with reference to an embodiment, it should be readily apparent to those skilled in the art that the present invention can be modified and changed in various ways without departing from the spirit and scope of the present invention as set forth in the claims below.

[0145] In addition, it will be apparent to those skilled in the art that various modifications and variations are possible without departing from the power semiconductor device, power semiconductor module, power converter, and manufacturing method thereof according to the embodiments. Therefore, the present disclosure is intended to include modifications and variations of features provided within the scope of the appended claims and their equivalents.

Claims

1. A substrate; a first conductivity type epitaxial layer disposed on the substrate; a second conductivity type well disposed partially on the first conductivity type epitaxial layer; a second conductivity type ion implantation region partially disposed in the second conductivity type well; a source region disposed partially in the second conductivity type well and over the second conductivity type ion implanted region; a gate insulating layer disposed on the source region and the second conductivity type well; a gate disposed on the gate insulating layer; an interlayer insulating layer disposed on the gate; a source electrode disposed on the source region; the gate insulating layer includes a channel gate insulating layer having a first thickness and a protruding gate insulating layer having a second thickness greater than the first thickness; a concentration of the second conductive type ion implantation region in an Rb region is higher than a concentration of the second conductive type well.

2. 2. The power semiconductor device according to claim 1, wherein the concentration of the second conductive type ion implantation region in the Rb region is 90 to 100 times higher than the concentration of the second conductive type well.

3. 2 . The power semiconductor device according to claim 1 , wherein the source electrode comprises a protruding source contact electrode disposed in a recessed region of the source region and the second conductive type ion implantation region.

4. The power semiconductor device according to claim 3 , wherein the protruding source contact electrode contacts an upper surface of the source region and a side surface of the source region.

5. A power conversion device comprising the power semiconductor device according to claim 1 .

6. providing a substrate including a first conductivity type epilayer; forming a first hard mask pattern on the first conductivity type epitaxial layer to form a second conductivity type well; forming a second hard mask pattern on a sidewall of the first hard mask pattern; implanting ions into a second conductivity type well using the first hard mask pattern and the second hard mask pattern as an ion implantation mask to form a first conductivity type source region; forming a third hard mask pattern on the first hard mask pattern and the second hard mask pattern; implanting ions in a self-aligned manner using the first, second, and third hard mask patterns as an ion implantation mask to form a second conductive type ion implantation region in the second conductive type well; removing the first, second and third hard mask patterns; and sequentially forming a gate insulating layer, a gate, and an interlayer insulating layer on the source region and the second conductive type well.

7. The step of forming the second conductivity type ion implantation region includes:

7. The method of claim 6, further comprising: implanting ions in a self-aligned manner using the first, second, and third hard mask patterns as ion implantation masks to form the second conductive type ion implantation region in the second conductive type well through the first conductive type source region.

8. The method for manufacturing a power semiconductor device according to claim 7 , wherein the second conductivity type ion implantation region is disposed so as to cover an area below the source region.

9. 9. The method of claim 8, wherein the concentration of the Rb region of the second conductive type ion implantation region is higher than the concentration of the second conductive type well.

10. 10. The method of claim 9, wherein the concentration of the Rb region of the second conductive type ion implantation region is 90 to 100 times higher than the concentration of the second conductive type well.

11. 7. The method of claim 6, wherein the gate insulating layer comprises a channel gate insulating layer having a first thickness and a protruding gate insulating layer having a second thickness that is thicker than the first thickness.

12. forming a source electrode on the source region after patterning the layer disposed above the source region; 7. The method of claim 6, wherein the source electrode comprises a protruding source contact electrode disposed in a recessed region of the source region and the second conductive type ion implantation region.

13. The method for manufacturing a power semiconductor device according to claim 12 , wherein the protruding source contact electrode contacts an upper surface of the source region and a side surface of the source region.

14. a first conductivity type epitaxial layer disposed on a substrate; a second conductivity type well disposed on the first conductivity type epitaxial layer; a second conductivity type ion implantation region disposed in the second conductivity type well; a source region disposed on the second conductivity type ion implantation region in the second conductivity type well; a recess located between the first gate and the second gate, the recess being disposed between two adjacent source regions and reaching an upper portion of the second conductivity type ion implantation region; a source electrode filling the recess and contacting the second conductivity type ion implantation region; 4. A power semiconductor device, comprising: a first conductive type ion implantation region having a width equal to a width of the first conductive type ion implantation region; a second conductive type ion implantation region having a width equal to a width of the first conductive type ion implantation region;

15. The power semiconductor device of claim 14 , further comprising a gate insulating film disposed on the source region and the second conductive type well.

16. The power semiconductor device according to claim 15 , wherein the first and second gates are disposed on the gate insulating film.

17. The power semiconductor device according to claim 15 , further comprising an interlayer insulating film disposed on the first gate and the second gate.

18. 17. The power semiconductor device of claim 16, wherein the gate insulating layer comprises a channel gate insulating layer having a first thickness and a protruding gate insulating layer having a second thickness that is thicker than the first thickness.

19. 15. The power semiconductor device according to claim 14, wherein the second conductive type ion implantation region has a higher concentration of Rb than the second conductive type well.

20. 20. The power semiconductor device according to claim 17, further comprising a metal barrier layer on the interlayer insulating film and in the recess.

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