Display panel and method of repairing the same

Abstract

To allow for expanding emission regions of pixels and increasing the aperture ratio.SOLUTION: A display panel of the present invention comprises: a plurality of pixel circuits, each having an emission region defined thereon to release light from a light-emitting element; a power line configured to apply a pixel driving voltage to the pixel circuits; a reference voltage line designed to have a reference voltage lower than the pixel driving voltage applied thereto; and a branch line connected to the reference voltage line to apply the reference voltage to one or more of the pixel circuits. At least a portion of the branch line includes a partially metalized semiconductor layer.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The present invention relates to a display device. More specifically, the present invention relates to a display panel of a display device and a repair method thereof. [Background technology]

[0002] Most electronic devices use liquid crystal displays (LCDs) and organic light emitting displays (OLEDs) as display devices. Active matrix type OLEDs use light emitting elements such as organic light emitting diodes (OLEDs) to display images. Such OLEDs have a fast response speed, high luminous efficiency, brightness and viewing angle, and excellent contrast ratio and color reproduction rate as they can display black gradations as perfect black. In addition, OLEDs are advantageous for realizing flexible display devices as elements can be formed on flexible substrates such as plastic.

[0003] Various methods for increasing the aperture ratio have been researched in response to the high resolution of organic display devices. However, it is difficult to design an increased aperture ratio due to pixel circuits and wiring connected to the pixel circuits. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2020-98775 A Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention is directed to solving the above-mentioned needs and / or problems.

[0006] In particular, the present invention provides a display panel having an improved aperture ratio of a pixel, and a repair method for darkening a defective pixel of the display panel.

[0007] The objects of the present invention are not limited to the objects mentioned above, and other objects not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0008] A display panel according to the present invention includes a plurality of pixel circuits each having a light-emitting region defined therein, the light-emitting region defining a region in which light is emitted from a light-emitting element, a power line for applying a pixel driving voltage to the pixel circuits, a reference voltage line for applying a reference voltage lower than the pixel driving voltage, and a branch line connected to the reference voltage line for applying the reference voltage to one or more of the pixel circuits, at least a portion of the branch line including a conductive semiconductor layer.

[0009] The display panel repair method disconnects the branch line and the anode electrode of the light emitting element by irradiating the branch line and the anode electrode of the light emitting element with a laser beam without changing the wavelength of the laser beam. Effect of the Invention

[0010] In the present invention, the light-emitting area of ​​a pixel can be enlarged and the aperture ratio can be improved by forming a transparent semiconductor layer at a portion of a branch line that distributes a reference voltage to a pixel circuit and crosses the light-emitting area of ​​a subpixel.

[0011] The present invention uses a double capacitor structure to increase the capacitance of the storage capacitor of the pixel circuit, thereby reducing the area occupied by the pixel circuit, enlarging the light emitting area, and further improving the aperture ratio.

[0012] The present invention reduces the resistance of the contact hole by connecting an electrode of a transistor to a conductive semiconductor layer or a metal layer formed on a semiconductor layer in the contact hole, thereby reducing the size of the contact hole and the number of contact holes, thereby further reducing the area occupied by the pixel circuit, expanding the light emitting area, and further improving the aperture ratio.

[0013] The repair method of the present invention is a display device in which at least a portion of the branch line overlaps with the light emitting region of a subpixel to enlarge the light emitting region and opening of the subpixel, and can simultaneously disconnect the anode electrode and branch line connected to a defective subpixel by irradiating a laser beam once, without changing the wavelength, at an overlapping portion between the anode electrode of the light emitting element and the metal layer of the branch line.

[0014] The effects of the present invention are not limited to those mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims. [Brief description of the drawings]

[0015] [Figure 1] 1 is a block diagram illustrating a display device according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a circuit diagram showing an example of a pixel circuit. [Diagram 3] FIG. 2 is a plan view showing a pixel of the display panel according to the first embodiment of the present invention. [Figure 4] 4 is a cross-sectional view of the display panel taken along line A-A' in FIG. 3. [Diagram 5] 4 is a cross-sectional view of the display panel taken along line B-B' in FIG. 3. [Figure 6a] 6A to 6C are cross-sectional views showing a process for forming the semiconductor pattern shown in FIGS. 4 and 5. [Figure 6b] 6A to 6C are cross-sectional views showing a process for forming the semiconductor pattern shown in FIGS. 4 and 5. [Figure 6c] 6A to 6C are cross-sectional views showing a process for forming the semiconductor pattern shown in FIGS. 4 and 5. [Figure 7a] FIG. 4 is a plan view showing a contact hole structure of the pixel circuit shown in FIG. [Figure 7b] FIG. 4 is a plan view showing a contact hole structure of the pixel circuit shown in FIG. [Figure 7c] FIG. 4 is a plan view showing a contact hole structure of the pixel circuit shown in FIG. [Figure 7d] FIG. 4 is a plan view showing a contact hole structure of the pixel circuit shown in FIG. [Figure 8] FIG. 11 is a plan view showing a pixel of a display panel according to a second embodiment of the present invention. [Figure 9] 9 is a cross-sectional view of the display panel taken along CC' in FIG. 8. [Figure 10] 9 is a cross-sectional view of the display panel taken along line D-D' in FIG. 8. [Figure 11a] 13 is a diagram showing a photo process for simultaneously forming a pattern of a third metal layer on a semiconductor layer using a half-tone mask and partially converting the semiconductor layer into a conductive layer. [Figure 11b] 13 is a diagram showing a photo process for simultaneously forming a pattern of a third metal layer on a semiconductor layer using a half-tone mask and partially converting the semiconductor layer into a conductive layer. [Figure 11c] 13 is a diagram showing a photo process for simultaneously forming a pattern of a third metal layer on a semiconductor layer using a half-tone mask and partially converting the semiconductor layer into a conductive layer. [Figure 11d] 13 is a diagram showing a photo process for simultaneously forming a pattern of a third metal layer on a semiconductor layer using a half-tone mask and partially converting the semiconductor layer into a conductive layer. [Figure 11e] 13 is a diagram showing a photo process for simultaneously forming a pattern of a third metal layer on a semiconductor layer using a half-tone mask and partially converting the semiconductor layer into a conductive layer. [Figure 12a] 9 is a plan view showing a contact hole structure of the pixel circuit shown in FIG. 8; [Figure 12b] 9 is a plan view showing a contact hole structure of the pixel circuit shown in FIG. 8; [Figure 12c]9 is a plan view showing a contact hole structure of the pixel circuit shown in FIG. 8; [Figure 13] An enlarged plan view of area E in Figure 3. [Figure 14] An enlarged plan view of region F in Figure 8. [Figure 15] 1 is a cross-sectional view illustrating a schematic cross-sectional structure of a display panel according to various embodiments of the present invention; [Figure 16] 1 is a cross-sectional view illustrating a schematic cross-sectional structure of a display panel according to various embodiments of the present invention; [Figure 17] 1 is a cross-sectional view illustrating a schematic cross-sectional structure of a display panel according to various embodiments of the present invention; [Figure 18] 2 is a cross-sectional view showing a stack of semiconductor and metal layers connected to an electrode of a transistor and an electrode of a storage capacitor; [Figure 19] 9 is a detailed plan view showing a first metal layer pattern and a semiconductor layer pattern of the display panel shown in FIG. 8. [Figure 20] FIG. 13 is a plan view showing an example in which a reference voltage line and a branch pattern are directly connected by a conductive semiconductor pattern. [Figure 21a] FIG. 11 is a circuit diagram showing the presence or absence of resistance in a contact hole between a reference voltage line and a branch line. [Figure 21b] FIG. 11 is a circuit diagram showing the presence or absence of resistance in a contact hole between a reference voltage line and a branch line. [Figure 22] FIG. 11 is an enlarged plan view of a part of a sub-pixel to be darkened in a display panel according to a third embodiment of the present invention. [Figure 23] 23 is a cross-sectional view taken along cutting line II' in FIG. 22. [Figure 24] FIG. 13 is an enlarged plan view of a part of a sub-pixel to be darkened in a display panel according to a fourth embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] The advantages and features of the present invention, and the methods for achieving them, will become apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but may be embodied in various different forms, but each embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art of the invention of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0017] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are merely examples, and the present invention is not limited to the matters shown in the drawings. The same reference numerals refer to substantially the same components throughout the specification. In addition, in the description of the present invention, if it is determined that a detailed description of related publicly known technology may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

[0018] When the terms "comprise," "include," "have," "consist," and the like are used herein, other parts may be added unless "only" is used. When an element is expressed in the singular, it may be interpreted as being plural unless otherwise expressly stated.

[0019] In interpreting elements, they are interpreted as including a margin of error even if there is no explicit mention otherwise.

[0020] In the case of describing a positional relationship, for example, when a positional relationship is described between two elements using "on," "at the top," "below," "next to," etc., one or more other elements may be interposed between those elements if "immediately" or "directly" is not used.

[0021] Although the terms "first", "second", etc. may be used to distinguish between components, the functions and structures of these components are not limited by the ordinal numbers preceding the components or the names of the components.

[0022] The following embodiments may be combined or combined with each other in part or in whole, and may be technically linked and driven in various ways. Each embodiment may be implemented independently of each other, or may be implemented together in a linked relationship.

[0023] Hereinafter, a display device according to an embodiment of the present specification will be described with reference to the accompanying drawings. The same reference numbers refer to substantially the same components throughout the specification. In the following description, if it is determined that a detailed description of a known function or configuration related to the present specification may unnecessarily obscure the gist of the present specification, the detailed description will be omitted or will be described briefly.

[0024] FIG. 1 is a block diagram for explaining a schematic configuration of a display device according to an embodiment of the present invention.

[0025] Referring to FIG. 1, the display device of the present invention is configured to include at least a display panel 10, a timing controller 11, a source driver 12, and a gate driver 13.

[0026] The display panel 10 has a plurality of pixels P, a plurality of data lines DL, a plurality of reference voltage lines RL, and a plurality of gate lines GL arranged therein.

[0027] The pixels P are arranged in a matrix on the screen of the display panel 10 to form a pixel array. Each pixel P may be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel to realize colors. Each pixel may further include a white sub-pixel. Each sub-pixel may include the pixel circuit shown in FIG.

[0028] Each of the sub-pixels is connected to one of the data lines DL to which a data voltage is supplied, one of the reference voltage lines RL to which a reference voltage is supplied, and one of the gate lines GL. Each pixel P is configured to receive a high potential driving power supply and a low potential driving power supply from a power supply generating unit. For example, the power supply generating unit can supply the high potential driving power supply through a high potential driving power supply wiring or a pad unit, and can supply the low potential driving power supply through a low potential driving power supply wiring or a pad unit.

[0029] The display device includes at least one external compensation circuit. The external compensation circuit technique means a technique for sensing electrical characteristics of a driving element provided in a pixel P and correcting input video data DATA according to the sensed value. For example, the sensing unit is configured to compensate for brightness deviation between pixels P due to the threshold voltage and electron mobility of the driving element as electrical characteristics of the driving element.

[0030] The display panel 10 may be configured to further include a switch array 40. However, the present invention is not limited thereto. The switch circuit 40 may include a demultiplexer (DEMUX) connected between an output pin of the source driver 12 and a data line DL. The demultiplexer distributes the data voltage output from one channel of the source driver 12 to two or more data lines DL in a time-division manner, thereby reducing the number of channels of the source driver 12.

[0031] The source driver 12 includes a data voltage supply unit 20 that supplies a data voltage to the display panel 10 .

[0032] The data voltage supply unit 20 of the source driver 12 includes a plurality of digital-to-analog converters (hereinafter, DACs). The data voltage supply unit 20 converts the digital data DATA of the corrected input image input from the timing controller 11 into a data voltage for the display through the DAC when driving the display.

[0033] During sensing driving, the data voltage supplier 20 of the source driver 12 generates a data voltage for sensing through a DAC under the control of the timing controller 11. The data voltage for sensing is a voltage applied to a gate electrode of a driving element provided in each pixel P during sensing driving.

[0034] The source driver 12 may be configured to further include a sensing unit 30, but is not limited thereto.

[0035] The timing controller 11 is configured to receive timing signals such as video data DATA, a vertical sync signal Vsync, a horizontal sync signal Hsync, a dot clock signal DCLK, and a data enable signal DE input from a host system, but is not limited to these.

[0036] The timing controller 11 is configured to generate a data control signal DDC for controlling the operation timing of the source driver 12 and a gate control signal GDC for controlling the operation timing of the gate driver 13 based on the input signal.

[0037] The data control signal DDC includes a source start pulse, a source sampling clock, and a source output enable signal. The source start pulse controls the data sampling start timing of the source driver 12. The source sampling clock is a clock signal that controls the data sampling timing based on a rising or falling edge. The source output enable signal controls the output timing of the source driver 12.

[0038] The gate control signal GDC includes a gate start pulse, a gate shift clock, etc. The gate start pulse is applied to a gate stage of the gate driver 13 that generates the first output to control the gate stage. The gate shift clock is a clock signal commonly input to the gate stages, and is a clock signal for shifting the gate start pulse.

[0039] For example, the timing controller 11 may generate the control signals DDC and GDC for driving the display and the control signals DDC and GDC for driving the sensing, but is not limited thereto.

[0040] The timing controller 11 is configured to control a sensing drive for sensing an electrical characteristic of a driving TFT in each pixel P and updating a compensation value according to the sensing drive, and a display drive for displaying an input image reflecting the compensation value.

[0041] The timing controller 11 may be configured to separate the sensing drive and the display drive according to a predetermined control sequence, but is not limited thereto. For example, under the control of the timing controller 11, the sensing drive may be performed in a vertical blank period during the display drive, or in a power-on sequence period before the display drive starts, or in a power-off sequence period after the display drive ends, but is not limited thereto. The sensing drive may be performed during the display drive.

[0042] The vertical blanking period is a period during which input image data DATA is not written, and is disposed between vertical active periods during which one frame's worth of input image data DATA is written. The power-on sequence period refers to a transitional period from when the driving power source is turned on until the input image is displayed. The power-off sequence period refers to a transitional period from when the display of the input image ends until the driving power source is turned off. However, the sensing driving is not limited to the above-mentioned periods.

[0043] For example, the timing controller 11 can detect a standby mode, a slip mode, a low power mode, etc. according to a predetermined detection process and control various operations for the sensing drive. That is, the sensing drive may be performed in a state where only the screen of the display device is turned off while the system power is being applied, for example, in a standby mode, a slip mode, a low power mode, etc., but is not limited thereto.

[0044] The timing controller 11 is configured to calculate compensation parameters capable of compensating for changes in the electrical characteristics of the driving element of the pixel P based on the digital sensing value input from the source driver 12 during sensing driving.

[0045] For example, the organic light emitting display device may include a memory 17 or may be configured to communicate with the memory 17. Then, compensation parameters may be stored in the memory 17. The compensation parameters stored in the memory 17 may be updated every time sensing is driven, so that time-varying characteristics of the driving elements may be easily compensated for, but are not limited to this.

[0046] The timing controller 11 reads the compensation parameters from the memory 17 when driving the display, corrects the digital data DATA of the input image based on the compensation parameters, and supplies the corrected data to the source driver 12 .

[0047] The gate driver 13 may be implemented as a GIP (Gate in Panel) circuit formed directly on the display panel 10 together with circuit components and wiring of the pixel array. The GIP circuit may be disposed on a bezel region, which is a non-display region of the display panel 10, or may be distributed within the pixel array. The gate driver 13 sequentially outputs scan signals synchronized with data voltages to the gate lines GL under the control of the timing controller 11. The gate driver 13 can sequentially supply the scan signals to the gate lines GL by shifting the scan signals using a shift register.

[0048] The host system may be any one of a TV (Television) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, a wearable device, and a vehicle system.

[0049] FIG. 2 is a circuit diagram showing an example of a pixel circuit.

[0050] 2, the pixel circuit is connected to a data line DL to which a data voltage Vdata is supplied, a reference voltage line RL to which a reference voltage Vref is supplied, and a gate line GL to which a scan signal Vscan is supplied. The scan signal Vscan is a signal that swings between a gate high voltage VGH and a gate low voltage VGL.

[0051] The pixel P includes a light emitting element OLED, a driving element DT, a first switching element ST1, a second switching element ST2, and a storage capacitor Cst. The driving element DT and the switching elements ST1 and ST2 may each be implemented as a transistor.

[0052] The light emitting element OLED may be realized as an OLED including an organic compound layer formed between an anode and a cathode. The organic compound layer may include, but is not limited to, a hole injection layer HIL, a hole transport layer HTL, an emission layer EML, an electron transport layer ETL, and an electron injection layer EIL. The light emitting element OLED is a light emitting element connected between a third node Ns connected to a source electrode of the driving element DT and a low potential driving power source EVSS, and emits light by a driving current. The light emitting element OLED may be configured to display red, green, blue, or white.

[0053] The driving element DT includes a gate electrode connected to a first node Ng, a drain electrode connected to a second node Nd, and a source electrode connected to a third node Ns. The driving element DTR controls the amount of current applied to the light emitting element OLED according to a gate-source voltage Vgs to drive the light emitting element OLED. A pixel driving voltage VDD may be applied to the drain electrode of the driving element DT.

[0054] The first switch element ST1 includes a gate electrode connected to the gate line GL, a drain electrode connected to the data line DL, and a source electrode connected to a first node Ng. The first switch element ST1 is turned on in response to a scan signal Vscan from the gate line GL. When the first switch element ST1 is turned on, the data line DL to which the data voltage Vdata is applied is electrically connected to the first node Ng, and the data voltage Vdata is applied to the gate electrode of the driving element DT and the storage capacitor Cst.

[0055] The second switch element ST2 includes a gate electrode connected to the gate line GL, a drain electrode connected to the reference voltage line RL, and a source electrode connected to a third node Ns. The second switch element ST2 is turned on in response to a scan signal Vscan from the gate line GL, and applies a reference voltage Vref to the third node Ns by electrically connecting the reference voltage line RL and the third node Ns. The reference voltage Vref is set to a voltage lower than the pixel driving voltage EVDD. Meanwhile, the second switch element ST2 may be turned on when sensing of the electrical characteristics of the driving element DT is required. In this case, a sensing signal from the gate driver 13 may be applied to the gate electrode of the second switch element ST2. Since the sensing signal may be generated independently of the scan signal Vscan, it is possible to control the on / off timing of the second switch element ST2 at a desired sensing time.

[0056] The storage capacitor Cst is connected between the first node Ng and the third node Ns, and maintains the gate-source voltage Vgs of the driving element DT during the light emission period. The larger the gate-source voltage Vgs, the larger the driving current, and therefore the more light is emitted from the pixel P. In other words, the brightness of the pixel P increases in proportion to the voltage applied to the first node Ng, i.e., the magnitude of the data voltage Vdata.

[0057] Adjacent pixel circuits are configured to be connected to at least one reference voltage line RL. For example, although not shown in FIG. 2, four pixel circuits may be configured to share one reference voltage line RL. According to the above-described configuration, the number of reference voltage lines RL can be reduced, which is advantageous in that the aperture ratio can be increased. That is, since the number of reference voltage lines RL is reduced, more sub-pixels can be arranged. Therefore, the resolution can be increased. However, the number of reference voltage lines RL and the number and type of shared pixels P can be modified in various ways without being limited thereto.

[0058] FIG. 3 is a plan view showing a pixel P of a display panel 10 according to a first embodiment of the present invention.

[0059] Referring to FIG. 3, each pixel P includes sub-pixels SP1 to SP4 having a light-emitting portion EA and a circuit portion CA.

[0060] The sub-pixels SP1 to SP4 are arranged along a first direction (e.g., the x-axis direction). For example, the first sub-pixel SP1 may be a red sub-pixel R, the second sub-pixel SP2 may be a green sub-pixel G, the third sub-pixel SP3 may be a blue sub-pixel B, and the fourth sub-pixel SP4 may be a white sub-pixel W, but is not limited thereto. The green and white sub-pixels G and W have relatively high light efficiency and luminance contribution rate, and therefore may be smaller in size than the red and blue sub-pixels R and B.

[0061] The light emitting unit EA includes a light emitting element OLED. The circuit unit CA includes a driving element DT for driving the light emitting element OLED, a first switch element ST1, a second switch element ST2, a storage capacitor Cst, and the like.

[0062] In the first embodiment, the light emitting unit EA and the circuit unit CA are arranged along a second direction (y-axis direction) intersecting with the first direction x. In each of the sub-pixels SP1 to SP4, the light emitting element OLED is driven by a pixel circuit implemented in the circuit unit CA to emit light.

[0063] The light-emitting region of each of the sub-pixels SP1 to SP4 is defined by a bank BNK formed on the anode electrode AND of the light-emitting element OLED and exposing a part of the anode electrode AND. That is, the anode electrode AND exposed by the bank BNK can be said to be the light-emitting region of each of the sub-pixels SP1 to SP4.

[0064] The wiring of the pixel array includes horizontal and vertical lines for applying driving signals to the sub-pixels SP1 to SP4. The pixels P can share the horizontal and vertical lines. The vertical lines are disposed between the adjacent sub-pixels SP1 to SP4.

[0065] The vertical lines may include a vertical power supply line VDDV, a reference voltage line RL, and data lines DL1 to DL4. The vertical lines are long lines that extend in the second direction y across the sub-pixels SP1 to SP4 adjacent to each other in the first direction x.

[0066] The horizontal lines may include the gate lines GL and the horizontal power supply lines VDDH. The horizontal lines intersect with the vertical lines. The horizontal lines are wirings that extend in the first direction x.

[0067] The wiring connected to the pixel and the electrodes constituting the transistor may be disposed on the same layer or on different layers with one or more insulating layers interposed therebetween, and may be connected to each other through contact holes penetrating the insulating layers for electrical connection.

[0068] The first to fourth data lines DL1 to DL4 may be connected to the first switch elements ST1 of the corresponding sub-pixels SP. The gate lines GL may be connected to the first switch elements ST1 of the sub-pixels SP1 to SP4. The gate lines GL may be connected to the second switch elements ST2 of the sub-pixels SP1 to SP4.

[0069] The pixel driving voltage EVDD is commonly applied to the pixel circuits of the sub-pixels SP1 to SP4 through the vertical power line VDDV and the horizontal power line VDDH. The vertical power line VDDV may be connected to the driving elements DT of the sub-pixels SP1 to SP4 through the horizontal power line VDDH. The horizontal power line VDDH is disposed in the circuit unit CA. The horizontal power line VDDH extends in a first direction and transmits signals from the vertical power line VDDV extending in a second direction to the sub-pixels SP1 to SP4 arranged along the first direction. The horizontal power line VDDH is disposed in a layer different from the vertical power line VDDV and is electrically connected to the sub-pixels SP1 to SP4 through a first power contact hole SEH1. The horizontal power line VDDH is disposed in a layer different from the drain electrodes of the driving elements DT and is electrically connected to the drain electrodes through a second power contact hole EH2.

[0070] A reference voltage Vref applied to the reference voltage line RL is applied to one or more sub-pixels SP1 to SP4 through (or via) the branch line RBL. The branch line RBL may be connected to the second switch element ST2 of each of the sub-pixels SP1 to SP4. The branch line RBL is disposed in the circuit unit CA. The branch line RBL extends in a first direction and transmits a signal from the reference voltage line RL extending in a second direction to the sub-pixels SP1 to SP4 arranged along the first direction. More specifically, the first branch line BLa connects the reference voltage line RL to two sub-pixels SP1 and SP4 at both ends, and the second branch line BLb connects the reference voltage line RL to two sub-pixels SP2 and SP3 in the middle. The branch line RBL is disposed in a layer different from the reference voltage line RL and is electrically connected to the reference voltage line RL through a first reference contact hole RH1. The first branch line BLa is longer than the second branch line BLb since it is connected to the first and fourth sub-pixels spaced apart from each other by sandwiching the two sub-pixels SP2 and SP3 therebetween. The first branch line BLa is bent so as to have a recessed center portion so as not to interfere with the second branch line BLb. The second branch line BLb is disposed under the recessed center portion of the first branch line BLa and is connected to the adjacent second and third sub-pixels SP2 and SP3. The first branch line BLa is patterned so as to have a recessed center portion and passes under the bank BNK, thereby reducing loss of the light-emitting area of ​​the sub-pixels SP1 to SP4 due to the branch line RBL and increasing the aperture ratio.

[0071] The branch line RBL is disposed in the same layer as the drain electrode of the second switch element ST2, and the branch line RBL is electrically connected to the active layer of the second switch element ST2 through a contact hole RH2. The drain electrode D2 of the second switch element ST2 may be integrated with the branch line RBL.

[0072] The gate electrode of the first switch element ST1 of the present invention is formed as a part of the gate line GL or is branched off therefrom. The drain electrode of the first switch element ST1 is formed as a part of the data line DL or is branched off therefrom. The active layer of the first switch element ST1 is connected to the drain electrode through a contact hole STH1 penetrating the buffer layer BUF (see FIG. 14). The source electrode of the first switch element ST1, which is positioned to face the drain electrode across the gate electrode, is connected to the gate electrode of the driving element DT.

[0073] In each of the sub-pixels SP1 to SP4, the anode electrode AND of the light emitting element OLED disposed in the light emitting unit EA extends in the second direction and is electrically connected to the corresponding driving element DT and storage capacitor Cst in the circuit unit CA.

[0074] Next, a cross-sectional structure of the display panel according to the first embodiment of the present invention will be described with reference to FIG. 4 and FIG.

[0075] Fig. 4 is a cross-sectional view taken along line A-A' in the first sub-pixel SP1 in Fig. 3 to show cross-sectional structures of the second switch element ST2 and the branch line RBL shown in Fig. 3. Fig. 5 is a cross-sectional view taken along line B-B' in the first sub-pixel SP1 in Fig. 3 to show cross-sectional structures of the driving element DT, the storage capacitor Cst, and the horizontal power line VDDH.

[0076] Referring to FIG. 4, the display panel 10 includes a first metal layer, a buffer layer BUF, a semiconductor layer, a first insulating layer GI, a second metal layer, a second insulating layer PAS, a third insulating layer OC, an anode electrode AND, an organic compound layer EL, a cathode electrode CAT, a color filter CF, and a bank BNK, which are disposed on a substrate SUBS. The first metal layer includes at least a data line DL1 and a light blocking pattern LS. The second metal layer includes an electrode of the second switch element ST2. Although not visible in the cross section of line A-A', the electrodes of all the transistors DT, ST1, and ST2 constituting the pixel circuit are also formed by the pattern of the second metal layer. Each of the first and second metal layers may be realized as a single metal layer or a double metal layer in which different metal layers are stacked. The semiconductor layer includes at least an active layer ACT2 of the second switch element ST2.

[0077] A data line DL1 and a light-blocking pattern LS are disposed on a substrate SUBS. The data line DL1 may be formed of the same first metal in the same layer as the light-blocking pattern LS. The light-blocking pattern LS may be disposed only under the channel region (or active layer) of the driving element DT, or may be disposed not only under the channel region of the driving element DT but also under the channel regions of the first and second switch elements ST1 and ST2. The light-blocking pattern LS may be used to block external light, or may be connected to other electrodes or wiring to be used as an electrode of a capacitor.

[0078] A buffer layer BUF may be disposed on the substrate SUBS on which the data line DL1 and the light blocking pattern LS are disposed. The buffer layer BUF may include one or more inorganic insulating material layers and serve to block ions or impurities diffusing from the substrate SUBS and to block the penetration of external moisture.

[0079] A second switch element ST2 and a first branch line BLa are formed on the buffer layer BUF. Although not visible along line A-A' in FIG. 3, a second branch line BLb may also be formed on the buffer layer BUF.

[0080] The second switch element ST2 includes an active layer ACT2, a gate electrode G2, a source electrode S2, and a drain electrode D2. The active layer ACT2 is disposed on the buffer layer BUF. The active layer ACT2 is made of a semiconductor. The semiconductor may be any one of an oxide semiconductor, polysilicon, and amorphous silicon.

[0081] The active layer ACT2 may be divided into a channel region, a source region provided on one side of the channel region, and a drain region provided on the other side of the channel region. When ions are doped into the source region and the drain region of the active layer ACT2, the gate electrode G2 formed of the second metal layer acts as a mask, so that the channel region under the gate electrode G2 is not doped with ions.

[0082] The gate electrode G2 is disposed on the channel region of the active layer ACT2 with a first insulating layer GI sandwiched therebetween. The first insulating layer GI may be made of, but is not limited to, a silicon oxide film (SiOx) or a silicon nitride film (SiNx). The first insulating layer GI may be a gate insulating layer. The gate electrode G2 may be a part of the gate line GL or a part branched off from the gate line GL. That is, the gate electrode G2 and the gate line GL may be formed of the same second metal disposed in the same layer.

[0083] The source electrode S2 and the drain electrode D2 are disposed on the buffer layer BUF, spaced apart from each other with the gate electrode G2 in between. The source electrode S2 and the drain electrode D2 may be formed of the same second metal disposed in the same layer as the gate electrode G2. A first insulating layer GI is disposed between the source electrode S2 and the buffer layer BUF. A first insulating layer GI is also disposed between the drain electrode D2 and the buffer layer BUF.

[0084] The source electrode S2 is connected to the source region of the active layer ACT2 through a second source contact hole STH1 penetrating the first insulating layer GI. The source electrode S2 is connected to the light-blocking pattern LS through a second source contact hole STH2 penetrating the buffer layer BUF. Although not shown in FIG. 4, as described above, the light-blocking pattern LS may be used to connect to other electrodes or lines, and therefore the light-blocking pattern LS may be a part of a node electrically connecting the source electrode S2 to the source electrode of the driving element DT or the anode electrode AND of the light-emitting element OLED.

[0085] The drain electrode D2 is connected to the drain region of the active layer ACT2 through a second drain contact hole RH2 penetrating the first insulating layer GI.

[0086] The branch line BLa formed on the buffer layer BUF may be made of the same metal as the gate electrode, source electrode, and drain electrode of the second switch element ST2, and the drain electrode D2 may be a part of the branch line BLa or a part branched off from the branch line BLa.

[0087] A second insulating layer PAS is disposed on the second switch element ST2 and the branch line BLa. The second insulating layer PAS may be a passivation layer. The passivation layer is an insulating layer that protects the underlying elements and may be a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a multilayer having two or more of these layers stacked together.

[0088] A third insulating layer OC may be disposed on the second insulating layer PAS. The third insulating layer OC may be a planarization layer for reducing steps in the lower structure, and may be made of an organic material such as polyimide, benzocyclobutene series resin, or acrylate. If necessary, either the passivation layer or the planarization layer may be omitted. A color filter CF may be disposed between the second insulating layer PAS and the third insulating layer OC.

[0089] The light emitting element OLED is disposed on the third insulating layer OC. The light emitting element OLED includes an anode electrode AND and a cathode electrode CAT facing each other with the organic compound layer EL interposed therebetween.

[0090] Since the display device according to the present invention is implemented in a bottom emission mode, the anode electrode AND may function as a transparent electrode. For example, the anode electrode AND may be made of a transparent electrode material such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or ZnO (Zinc Oxide).

[0091] A bank BNK is disposed on the substrate SUBS on which the anode electrodes AND are formed. The bank BNK may be made of an organic material such as polyimide, benzocyclobutene series resin, or acrylate.

[0092] An organic compound layer EL is disposed on the substrate SUBS on which the bank BNK is formed. The organic compound layer EL includes an emission layer (EML) in which electrons and holes combine to emit light. The organic compound layer EL may further include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0093] The cathode electrode CAT is disposed on the organic compound layer EL. The cathode electrode CAT may be widely formed on the front surface of the substrate SUBS. The display device of the present invention may be realized in a bottom emission mode. In this case, the cathode electrode CAT may function as a reflective electrode. For example, the cathode electrode CAT may be made of a reflective material having a low work function, such as magnesium (Mg), calcium (Ca), aluminum (Al), silver (Ag), or an alloy thereof.

[0094] 5, the display panel 10 includes a first metal layer, a buffer layer BUF, a semiconductor layer, a first insulating layer GI, a second metal layer, a second insulating layer PAS, a third insulating layer OC, a driving element DT, a light-emitting element OLED, and a bank BNK, which are disposed on a substrate SUBS. The first metal layer includes a light-blocking pattern LS. The second metal layer includes an electrode of the driving element DT. Each of the first and second metal layers may be realized as a single metal layer or a double metal layer in which different metal layers are stacked. The semiconductor layer includes at least an active layer ACT0 of the driving element DT.

[0095] A light-blocking pattern LS is disposed on a substrate SUBS. The light-blocking pattern LS may be disposed only under a channel region (or active layer) of the driving element DT, or may be disposed not only under the channel region of the driving element DT but also under the channel regions of the first and second switch elements ST1 and ST2. The light-blocking pattern LS may be used simply to block external light, or may be connected to other electrodes or lines and used as an electrode for constituting a capacitor, etc.

[0096] A buffer layer BUF may be disposed on the substrate SUBS on which the light blocking pattern LS is disposed. The buffer layer BUF may function to block ions or impurities diffusing from the substrate SUBS and to block the penetration of external moisture.

[0097] A driving element DT and a horizontal power supply line VDDH are formed on the buffer layer BUF. The driving element DT includes an active layer ACT0, a gate electrode G0, a source electrode S0, and a drain electrode D0.

[0098] The active layer ACT0 is disposed on the buffer layer BUF. The active layer ACT0 may be divided into a channel region, a source region provided on one side of the channel region, and a drain region provided on the other side of the channel region. The active layer ACT0 is made of a non-metallized semiconductor. The semiconductor may be any one of an oxide semiconductor, polysilicon, and amorphous silicon.

[0099] The gate electrode G0 is disposed on the channel region of the active layer ACT0 with a first insulating layer GI sandwiched therebetween. The first insulating layer GI may be made of, but is not limited to, a silicon oxide film (SiOx) or a silicon nitride film (SiNx). Here, the first insulating layer GI may be a gate insulating layer GI. The gate electrode G0 may be disposed between the source electrode S0 and the drain electrode D0 and spaced apart from the source electrode S0 and the drain electrode D0. The gate electrode G0 may be formed of the same metal disposed in the same layer as the source electrode S0 and the drain electrode D0.

[0100] The source electrode S0 and the drain electrode D0 are spaced apart from each other on the buffer layer BUF with the gate electrode G0 in between. The source electrode S0 and the drain electrode D0 may be formed of the same metal in the same layer as the gate electrode G0. A first insulating layer GI is disposed between the source electrode S0 and the buffer layer BUF. A first insulating layer GI is disposed between the drain electrode D0 and the buffer layer BUF.

[0101] The source electrode S0 is connected to the source region of the active layer ACT0 through a source contact hole EH3 penetrating the first insulating layer GI. The source electrode S0 is electrically connected to the anode electrode AND of the light emitting element OLED through a pixel contact hole CH1 as shown in FIG.

[0102] The drain electrode D0 is connected to a drain region of the active layer ACT0 through a drain contact hole EH2 penetrating the first insulating layer GI. The drain electrode D0 may be a part of the horizontal power supply line VDDH or a part branched off from the horizontal power supply line VDDH.

[0103] The display panel 10 may further include an electrode of a capacitor Cst disposed on the buffer layer BUF and spaced apart from the active layer ACT0 of the driving element DT. The electrode of the storage capacitor Cst may include a semiconductor integrated with the active layer ACT0 of the driving element DT. The semiconductor used as the electrode of the storage capacitor Cst may be conductive.

[0104] The storage capacitor Cst includes an electrode formed of a conductive semiconductor pattern, a buffer layer BUF, and a light-blocking pattern LS overlapping the semiconductor pattern with the buffer layer BUF interposed therebetween. Thus, a portion of the light-blocking pattern LS also serves as the other electrode of the storage capacitor Cst. As described above, the storage capacitor Cst may be connected between the first node Ng and the third node Ns of the driving element DT.

[0105] A second insulating layer PAS is disposed on the driving element DT and the horizontal power line VDDH. The second insulating layer PAS may be a passivation film. The passivation film is an insulating layer that protects the underlying elements and may be a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multi-layer structure in which these are stacked.

[0106] A third insulating layer OC may be disposed on the second insulating layer PAS. The third insulating layer OC may be a planarization layer for reducing steps in the lower structure, and may be made of an organic material such as polyimide, benzocyclobutene series resin, acrylate, etc. If necessary, either the passivation layer or the planarization layer may be omitted.

[0107] The light-emitting element OLED is disposed on the third insulating layer OC. The light-emitting element OLED includes an anode electrode AND, an organic compound layer EL, and a cathode electrode CAT. The anode electrode AND is not shown in FIG. 4 because it is not visible in the cross section taken along line B-B'.

[0108] The anode electrode AND is connected to the source electrode S0 of the driving element DT through a pixel contact hole CH1 penetrating the second and third insulating layers PAS and OC as shown in Fig. 3. The display device of the present invention may be embodied in a bottom emission mode. For this purpose, the anode electrode of the light emitting element may function as a transparent electrode. For example, the anode electrode may be made of a transparent electrode material such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide) or ZnO (Zinc Oxide).

[0109] A bank BNK is disposed on the third insulating layer OC. The bank BNK may be made of an organic material such as polyimide, benzocyclobutene series resin, or acrylate.

[0110] The bank BNK exposes the anode electrode at the opening of the subpixel but covers the edge of the anode electrode AND. The bank BNK defines the light-emitting area of ​​the subpixel where light from the light-emitting element OLED is emitted to the outside. The light-emitting area includes the anode electrode exposed area of ​​the opening defined by the bank BNK within the light-emitting portion EA of each of the subpixels SP1 to SP4. Most of the anode electrode AND of the light-emitting element OLED is exposed in the light-emitting area defined by the bank BNK. The light-emitting area is substantially the same as the opening APT in FIG. 3 where the anode electrode AND is exposed without metal.

[0111] All thin film layers within the light emitting region may consist of 90% or more of the medium.

[0112] An organic compound layer EL is disposed on the substrate SUBS on which the bank BNK is formed. The organic compound layer EL is a layer in which electrons and holes are combined to emit light, and includes an emission layer EML and may further include at least one of a hole injection layer HIL, a hole transport layer HTL, an electron transport layer ETL, and an electron injection layer EIL.

[0113] The cathode electrode CAT is disposed on the organic compound layer EL. The cathode electrode CAT may be widely formed on the front surface of the substrate SUBS. In the bottom emission mode, the cathode electrode CAT may function as a reflective electrode. For example, the cathode electrode CAT may be made of a reflective material having a low work function, such as magnesium (Mg), calcium (Ca), aluminum (Al), silver (Ag), or an alloy thereof.

[0114] In the display panel 10 shown in Figures 3 to 5, the active layers of the transistors DT, ST1, and ST2 may be realized as semiconductor patterns patterned into a desired shape using a photolithography process (hereinafter referred to as a "photo process"). This will be explained in conjunction with Figures 6a to 6c. In Figures 6a to 6c, "PAD" is a pad portion in the display panel 10 to which the data line DL and the output pin of the source driver 12 are connected. "APT" is an aperture of a sub-pixel. "TFT" is a driving element portion of the display panel 10. "Cst" is a storage capacitor portion of the display panel 10. "DATA" is a data line portion of the display panel 10.

[0115] In the photolithography process, as shown in FIG. 6a, a semiconductor material is deposited on the buffer layer BUF to form a semiconductor layer SEM on the buffer layer BUF. The semiconductor material may be an oxide semiconductor, for example, indium-gallium-zinc oxide (IGZO). In the following, the semiconductor material will be exemplified as amorphous indium-gallium-zinc oxide (IGZO), but is not limited thereto.

[0116] As shown in Figure 6b, the photolithography process involves coating a photosensitive material layer on the semiconductor layer SEM, aligning a photomask with the desired pattern on the photosensitive material layer, and exposing the photosensitive material through the photomask. The photolithography process then sprays a developer onto the photosensitive material layer to dissolve and remove only the exposed portions of the photosensitive material layer. As a result, a semiconductor pattern SEM' of the desired shape remains under the photoresist pattern PR.

[0117] In the photolithography process, an etchant is sprayed onto the photoresist pattern PR and the semiconductor pattern SEM'. By this wet etching process, the exposed portions of the semiconductor pattern SEM' that are not covered by the photoresist pattern PR are removed, as shown in Figure 6c.

[0118] Figures 7a to 7d are plan views showing contact hole structures connecting the semiconductor pattern SEM' and the transistors DT, ST1, and ST2 in the pixel circuit shown in Figure 3. In Figures 7a to 7d, "GM" indicates a partial pattern of the second metal layer used as an electrode of the transistors DT, ST1, and ST2. The contact hole structure shown in Figures 7a to 7d may be any one of the contact holes CH1, STH1, and STH2 connecting the semiconductor layer and the second metal layer in Figure 3.

[0119] A first insulating layer GI is covered on the passivated semiconductor pattern SEM' as shown in Figure 7a, and a portion of the first insulating layer GI is removed by a photo process. As a result, a portion of the semiconductor pattern SEM' is exposed through the contact hole [CH(GI)] where the first insulating layer GI has been removed as shown in Figure 7b. Here, the semiconductor pattern SEM' is a semiconductor layer that is not made conductive.

[0120] A portion CA1 of the semiconductor pattern SEM' exposed by the contact hole [CH(GI)] becomes conductive. The conductive properties of oxide semiconductor (IGZO) change depending on the oxygen content. As the oxygen content decreases, the conductivity of oxide semiconductor (IGZO) increases and it becomes conductive and is metalized. Plasma treatment can be used to reduce the oxygen content of oxide semiconductor (IGZO). For example, when oxide semiconductor is exposed to plasma, oxygen contained inside the oxide semiconductor is removed and the resistance of oxide semiconductor (IGZO) decreases and it can be metalized. Plasma treatment is a method of generating plasma discharge in helium (He), hydrogen (H2) or argon (Ar) gas.

[0121] A second metal layer pattern GM is formed on the first insulating layer GI to cover a portion of the contact hole [CH(GI)]. The second metal layer pattern GM may be a source electrode or a drain electrode of the transistors DT, ST1, and ST2. The second metal layer pattern GM covers a portion of the non-conductive semiconductor pattern SEM' and a portion of the contact hole [CH(GI)], and contacts the semiconductor pattern SEM' and a portion of the contact hole [CH(GI)], as shown in FIG. 7c.

[0122] As shown in Fig. 7d, the remaining portion CA2 of the semiconductor pattern SEM' that is not covered by the second metal layer pattern GM is made conductive. At this time, the portion NA that is covered by the second metal layer pattern GM is not exposed to the plasma and is therefore not made conductive.

[0123] In the display device according to the first embodiment of the present invention, the aperture ratio of the pixel P can be improved due to the fact that one reference voltage line RL is shared by a number of sub-pixels SP1, SP2, SP3, and SP4 and due to the double branch line RBL structure.

[0124] FIG. 8 is a plan view showing a pixel of a display panel 10 according to a second embodiment of the present invention.

[0125] 8, the wiring shared by the pixel P includes horizontal lines and vertical lines. The vertical lines are disposed between adjacent sub-pixels SP1 to SP4. The vertical lines may include a vertical power supply line VDDV, a reference voltage line RL, and fourth data lines DL1 to DL4.

[0126] The horizontal lines may include gate lines GL, horizontal power supply lines VDDH, etc. The horizontal lines intersect with the vertical lines. The horizontal lines may refer to lines extending in a first direction x.

[0127] The wiring connected to the pixel and the electrodes constituting the transistor may be disposed on the same layer or on different layers with one or more insulating layers interposed therebetween, and may be connected to each other through contact holes penetrating the insulating layers for electrical connection.

[0128] The first to fourth data lines DL1 to DL4 may be connected to the first switch elements ST1 of the corresponding sub-pixels SP. The gate line GL may be connected to the first switch elements ST1 of the sub-pixels SP1 to SP4. The gate line GL may also be connected to the second switch elements ST2 of the sub-pixels SP1 to SP4.

[0129] The vertical power line VDDV may be connected to the driving elements DT of each of the sub-pixels SP1 to SP4 through the horizontal power line VDDH. The horizontal power line VDDH is disposed in the circuit unit CA. The horizontal power line VDDH extends in a first direction x and transmits signals from the vertical power line VDDV extending in a second direction y to the sub-pixels SP1 to SP4 arranged along the first direction x. The horizontal power line VDDH is disposed in a layer different from the vertical power line VDDV and is electrically connected through a first power contact hole EH4.

[0130] The horizontal power supply line VDDH may be disposed in the same layer as the drain electrode of the driving element DT. The horizontal power supply line VDDH may be realized by a conductive semiconductor layer. In this case, since the conductive semiconductor layer is transparent, the horizontal power supply line VDDH may overlap the light emitting area of ​​the sub-pixel, and therefore the aperture and light emitting area of ​​the sub-pixel may be further enlarged.

[0131] The horizontal power supply line VDDH may be realized as a multi-layer structure including at least a portion of a semiconductor layer and a third metal layer formed on the semiconductor layer. The third metal layer may be one of copper (Cu) and molybdenum titanium (MoTi), or a dual metal layer in which these metals are stacked. The third metal layer is in direct contact with the semiconductor layer at the active layer of the transistor and the capacitor electrode, etc., and is not present on the semiconductor layer in the light-emitting region of the subpixel. The third metal layer is stacked on the semiconductor layer and disposed between the first metal layer and the second metal layer.

[0132] The reference voltage line RL may be connected to the second switch elements ST2 of the sub-pixels SP1 to SP4 through (or via) the branch lines RBL.

[0133] The branch lines RBL extend in a horizontal direction, i.e., a first direction x, and transmit signals from the reference voltage line RL to the sub-pixels SP1 to SP4 arranged along the first direction. The branch lines RBL are disposed in a layer different from the reference voltage line RL and are electrically connected to the reference voltage line RL through a first reference contact hole RH3. Unlike the first embodiment described above, the branch lines RBL are not separated into two. At least a portion of the branch lines RBL may be formed of a semiconductor layer alone. The branch lines RBL may include a multi-layer structure including a semiconductor layer and a third metal layer formed on the semiconductor layer. The third metal layer may be any one of copper (Cu) and molybdenum titanium (MoTi), or a dual metal layer in which these metals are stacked. The semiconductor layer has a much higher light transmittance than metal. The third metal layer is formed on the semiconductor layer between the first metal layer and the second metal layer.

[0134] A multi-layer portion of the branch line RBL in which a semiconductor layer and a third metal layer are stacked (hereinafter referred to as a "multi-layered branch line") may be disposed in a non-light-emitting region between adjacent sub-pixels SP1, SP2, SP3, and SP4. The multi-layered branch line crosses vertical lines such as the data lines DL1 to DL4.

[0135] In the branch line RBL, the portion where only the semiconductor layer exists without the metal layer (hereinafter referred to as the "single-layer branch line") appears transparent. Oxide semiconductor (IGZO) has an optical transmittance of 90% or more. The semiconductor layer of the single-layer branch line can be made conductive so that current can flow. In the branch line with a multi-layer structure, the semiconductor layer under the metal may not be made conductive, but it can be an amorphous semiconductor that is not made conductive.

[0136] The single layer branch line is connected to a pixel circuit across a light emitting region in at least one of the sub-pixels SP1 to SP4. The single layer branch line may overlap an anode electrode AND of the light emitting region. A portion of the semiconductor layer of the single layer branch line may be bent in an “L” shape along the first and second directions in an area overlapping with the anode electrode and connected to at least one of the pixel circuits.

[0137] The transparent single-layer branch line can improve the aperture ratio of the subpixel and expand the light-emitting area. The aperture ratio of the subpixel increases by the area OA where the transparent single-layer branch line overlaps with the light-emitting area of ​​the subpixel SP. The light-emitting area of ​​the subpixel includes the exposed area of ​​the anode electrode AND defined by the bank BNK.

[0138] The gate electrode of the first switch element ST1 of the present invention is formed as a part of the gate line GL or is branched therefrom. The drain electrode of the first switch element ST1 is formed as a part of the data line DL or is branched therefrom. The active layer of the first switch element ST1 is connected to the drain electrode through a contact hole STH3 penetrating the buffer layer BUF. The source electrode of the first switch element ST1 may be implemented as a second metal layer formed on a semiconductor layer. The first switch element ST1 may include an extension extending from the source electrode. One side of the extension may be connected to the source electrode of the first switch element ST1 and the other side may be connected to the gate electrode of the driving element DT. The extension may connect the source electrode of the first switch element ST1 to the gate electrode of the driving element DT as shown in FIG. 2. Since the extension is continuous with the source electrode of the first switch element ST1, it may have a multi-layer structure including a semiconductor layer and a second metal layer formed thereon, like the source electrode.

[0139] The anode electrodes AND of the light emitting devices OLED disposed in the light emitting units EA of the sub-pixels SP1 to SP4 extend in the second direction and are electrically connected to the corresponding driving devices DT and storage capacitors Cst in the circuit unit CA.

[0140] Fig. 9 is a cross-sectional view taken along line CC' in the first sub-pixel SP1 in Fig. 8 to show cross-sectional structures of the second switch element ST2 and the branch line RBL shown in Fig. 8. Fig. 10 is a cross-sectional view taken along line D-D' in the first sub-pixel SP1 in Fig. 8 to show cross-sectional structures of the driving element DT, the storage capacitor Cst, and the horizontal power line VDDH shown in Fig. 8.

[0141] 9, the display panel 10 includes a first metal layer, a buffer layer BUF, a semiconductor layer, a first insulating layer GI, a second metal layer, a second insulating layer PAS, a third insulating layer OC, an anode electrode AND, an organic compound layer EL, a cathode electrode CAT, a color filter CF, and a bank BNK disposed on a substrate SUBS. The first metal layer includes at least a data line DL1 and a light blocking pattern LS. The second metal layer may include an electrode of a second switch element ST2. Each of the first and second metal layers may be realized as a single metal layer or a double metal layer in which different metal layers are stacked. The semiconductor layer includes at least an active layer ACT2 and a branch line RBL of the second switch element ST2. A third metal layer is partially stacked on the semiconductor layer. The third metal layer is formed on the semiconductor layer intersecting the data line DL1 and configured as a branch line of a multi-layer structure, and may be used as a source and drain electrode of the second switch element ST2.

[0142] The data line DL1 and the light-blocking pattern LS are disposed on the substrate SUBS. The data line DL1 may be formed of the same first metal disposed in the same layer as the light-blocking pattern LS. The light-blocking pattern LS may be disposed only under the channel region (or active layer) of the driving element DT, or may be disposed not only under the channel region of the driving element DT but also under the channel regions of the first and second switch elements 232 and 233. The light-blocking pattern LS may be used to block external light, or may be connected to an electrode or wiring of another transistor and used as an electrode of a capacitor.

[0143] A buffer layer BUF may be disposed on the substrate SUBS on which the data line DL1 and the light blocking pattern LS are disposed. The buffer layer BUF blocks ions and impurities diffusing from the substrate SUBS and blocks the penetration of external moisture.

[0144] An electrode of the second switch element ST2 and the branch line RBL are disposed on the buffer layer BUF. The branch line RBL includes a branch line with a single-layer structure overlapping the light-emitting region and a branch line with a multi-layer structure overlapping the data line DL1. The semiconductor layer of the branch line with a single-layer structure overlapping the light-emitting regions of the sub-pixels SP1 to SP4 in the branch line RBL is made conductive to apply the reference voltage Vref applied to the reference voltage line RL to the pixel circuits of the sub-pixels SP1 to SP4.

[0145] The source and drain electrodes S2, D2 of the second switch element ST2 may include a third metal layer formed on the semiconductor layer and a second metal layer on the third metal layer and in contact with the third metal layer. The gate electrode of the second switch element ST2 may be formed of the second metal layer.

[0146] The second switch element ST2 includes an active layer ACT2, a gate electrode G2, a source electrode S2, and a drain electrode D2.

[0147] The active layer ACT2 is disposed on the buffer layer BUF. The active layer ACT2 may be divided into a channel region, a source region provided on one side of the channel region, and a drain region provided on the other side of the channel region.

[0148] The gate electrode G2 may be formed of a second metal layer disposed on the channel region of the active layer ACT2 with a first insulating layer GI sandwiched therebetween. The first insulating layer GI may be made of, but is not limited to, a silicon oxide film (SiOx) or a silicon nitride film (SiNx). The first insulating layer GI may be a gate insulating layer. The gate electrode G2 may be a part of the gate line GL or a part branched off from the gate line GL. That is, the gate electrode G2 and the gate line GL may be formed in the same layer and made of the same material.

[0149] The source electrode S2 and the drain electrode D2 are disposed on the buffer layer BUF with the gate electrode G2 interposed therebetween. Therefore, the electrodes G2, S2, and D2 of the second switch element ST2 can be disposed on substantially the same plane on the buffer layer BUF.

[0150] The source electrode S2 includes a third metal layer formed on a source region of the semiconductor layer, and a second metal layer on the third metal layer in contact with the third metal layer. Since the source electrode S2 is formed of the third metal layer, it is connected to the active layer ACT2 made of a semiconductor layer. A first insulating layer GI may be disposed between the source electrode S2 and the source region of the active layer ACT2. The second metal layer of the source electrode S2 contacts the third metal layer and the source region of the active layer ACT2 of the semiconductor layer through a contact hole STH4 penetrating the first insulating layer GI. The second metal layer of the source electrode S2 is connected to the light-blocking pattern LS through a contact hole STH5 penetrating the first insulating layer GI, the semiconductor layer, and the buffer layer BUF. Although not shown in FIG. 9, as described above, the light-blocking pattern LS may be connected to electrodes or lines of other transistors. The light-blocking pattern LS connected to the source electrode S2 may connect the source electrode S2 to a source electrode of the driving element DT or an anode electrode AND of the light-emitting element OLED.

[0151] The drain electrode D2 includes a third metal layer formed on the semiconductor layer including the active layer ACT2. The drain electrode D2 may further include a second metal layer on the third metal layer in contact with the third metal layer. The branch line RBL is formed of the third metal layer formed on the semiconductor layer and is connected to the drain electrode D2 as shown in FIG 2. Therefore, the branch line of the multi-layer structure of the branch line RBL and the drain electrode D2 are integrated by the third metal layer.

[0152] The second insulating layer PAS covers the second switch element ST2 and the branch line RBL. The second insulating layer PAS may be a passivation layer. The passivation layer is an insulating layer that protects the underlying elements and may be a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a multi-layer structure in which these are stacked.

[0153] A third insulating layer OC may be disposed on the second insulating layer PAS. The third insulating layer OC may be a planarization layer for reducing steps in the lower structure, and may be made of an organic material such as polyimide, benzocyclobutene series resin, acrylate, etc. If necessary, either the passivation layer or the planarization layer may be omitted.

[0154] A color filter CF may be disposed between the second insulating layer PAS and the third insulating layer OC.

[0155] An organic light emitting diode OLED is disposed on the third insulating layer OC. The organic light emitting diode OLED includes an anode electrode AND, an organic compound layer EL, and a cathode electrode CAT, which face each other.

[0156] The display device may be implemented as a bottom emission type. In this case, the anode electrode AND may function as a transparent electrode. For example, the anode electrode AND may be made of a transparent electrode material such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or ZnO (Zinc Oxide).

[0157] A bank BNK is disposed on the substrate SUBS on which the anode electrodes AND are formed. The bank BNK may be made of an organic material such as polyimide, benzocyclobutene series resin, or acrylate.

[0158] An organic compound layer EL of the light emitting element OLED is disposed on the substrate SUBS on which the bank BNK is formed. The organic compound layer EL is a layer in which electrons and holes are combined to emit light, and includes an emission layer EML, and may further include at least one of a hole injection layer HIL, a hole transport layer HTL, an electron transport layer ETL, and an electron injection layer EIL.

[0159] The cathode electrode CAT is disposed on the organic compound layer EL. The cathode electrode CAT may be widely formed on the front surface of the substrate SUBS. Since the display device according to the second embodiment of the present invention is implemented in a bottom emission mode, the cathode electrode CAT may function as a reflective electrode. For example, the cathode electrode CAT may be made of a reflective material having a low work function, such as magnesium (Mg), calcium (Ca), aluminum (Al), silver (Ag), or an alloy thereof.

[0160] 9, the branch lines of the branch line RBL having a transparent single-layer structure overlap with the light-emitting areas of the sub-pixels SP1 to SP2. As a result, the present invention can further widen the light-emitting areas of the sub-pixels SP1 to SP4, thereby increasing the brightness and reducing the power consumption.

[0161] Referring to FIG. 10, the display panel 10 includes a first metal layer, a buffer layer BUF, a semiconductor layer, a first insulating layer GI, a second metal layer, a second insulating layer PAS, a third insulating layer OC, an anode electrode AND, an organic compound layer EL, a cathode electrode CAT, a color filter CF, and a bank BNK disposed on a substrate SUBS. The first metal layer includes a light blocking pattern LS. The second metal layer may be used as a gate electrode of the driving element DT and an upper electrode CE1 of the storage capacitor Cst. Each of the first and second metal layers may be realized as a single metal layer or a double metal layer in which different metal layers are stacked. The semiconductor layer includes at least an active layer ACT0 of the driving element DT. A third metal layer is partially stacked on the semiconductor layer. The third metal layer is formed on the semiconductor layer and patterned as a horizontal power line VDDH, and may be used as a source and drain electrode of the driving element DT. The source and drain electrodes of the driving element DT may further include a second metal layer on the third metal layer in contact with the third metal layer.

[0162] A light blocking pattern LS is disposed on a substrate SUBS. A buffer layer BUF may be disposed on the substrate SUBS on which the light blocking pattern LS is disposed. A driving element DT and a horizontal power supply line VDDH are formed on the buffer layer BUF.

[0163] The driving element DT includes an active layer ACT0, a gate electrode G0, a source electrode S0, and a drain electrode D0.

[0164] The active layer ACT0 is formed of a passivated semiconductor layer disposed on the buffer layer BUF. The active layer ACT0 may be divided into a channel region, a source region provided on one side of the channel region, and a drain region provided on the other side of the channel region.

[0165] The gate electrode G0 is disposed on the channel region of the active layer ACT0 with a first insulating layer GI sandwiched therebetween. The first insulating layer GI may be made of, but is not limited to, a silicon oxide film (SiOx) or a silicon nitride film (SiNx). Here, the first insulating layer GI may be a gate insulating layer. The gate electrode G0 may be disposed between the source electrode S0 and the drain electrode D0.

[0166] The source electrode S0 and the drain electrode D0 can be disposed on the buffer layer BUF with the gate electrode G0 sandwiched therebetween.

[0167] A first insulating layer GI may be disposed between the source electrode S0 and the buffer layer BUF. The source electrode S0 may include the same second metal layer as the gate electrode G0. The second metal layer of the source electrode S0 may be connected to a third metal layer formed in a source region of the active layer ACT0 through a source contact hole EH5 penetrating the first insulating layer GI. The source electrode S0 may be connected to an anode electrode AND of the light emitting element OLED through a contact hole CH2 as shown in FIG. 8.

[0168] The drain electrode D0 may include a semiconductor layer formed in the drain region of the active layer ACT and a third metal layer formed on the semiconductor layer. The drain electrode D0 may further include a second metal layer formed on the third metal layer and in contact with the third metal layer. The drain electrode D0 may be a part of the horizontal power supply line VDDH or a part branched off from the horizontal power supply line VDDH. Thus, the horizontal power supply line VDDH may be integrated with the drain electrode D0. Thus, the drain electrode D0 and the horizontal power supply line VDDH may share the semiconductor layer and the third metal layer formed thereon.

[0169] 10, the storage capacitor Cst1 includes first and second capacitors Cst1 and Cst2 and has a larger capacitance than that of the first embodiment described above. The storage capacitor Cst is connected between the gate electrode G0 and the source electrode S0 of the driving element DT as shown in FIG.

[0170] The first capacitor Cst includes a light-blocking pattern LS and an intermediate electrode CE2 that face each other with a buffer layer BUF interposed therebetween. The light-blocking pattern LS is integrated with a lower electrode of the storage capacitor Cst1. The intermediate electrode CE2 includes a conductive semiconductor layer connected to the active layer ACT0. The intermediate electrode CE2 may further include a third metal layer formed on the semiconductor layer.

[0171] The second capacitor Cst includes an intermediate electrode CE2 and an upper electrode CE1 that face each other with a first insulating layer GI sandwiched therebetween. The upper electrode CE1 may be formed on the first insulating layer GI using the same second metal layer as the gate electrode G0.

[0172] 10, the present invention can secure sufficient capacitance by forming a double capacitor in the pixel circuit of each of the sub-pixels SP1 to SP4. As a result, the size of the storage capacitor Cst can be reduced, so that the light-emitting area of ​​the sub-pixels SP1 to SP4 can be expanded and the aperture ratio can be improved.

[0173] The second insulating layer PAS covers the driving element DT, the horizontal power line VDDH, and the storage capacitor Cst. The second insulating layer PAS may be a passivation film. The passivation film is an insulating layer that protects the underlying elements and may be a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multi-layer structure in which these are stacked.

[0174] A third insulating layer OC may be disposed on the second insulating layer PAS. The third insulating layer OC may be a planarization layer for reducing steps in the lower structure, and may be made of an organic material such as polyimide, benzocyclobutene series resin, acrylate, etc. If necessary, one of the passivation layer and the planarization layer may be omitted.

[0175] A light-emitting element OLED is disposed on the third insulating layer OC. The light-emitting element OLED includes an anode electrode AND, an organic compound layer EL, and a cathode electrode CAT. The anode electrode AND is obscured by the line "DD."

[0176] In one photo process, a third metal layer is partially stacked on the semiconductor layer in the display panel shown in Figures 8 to 10, so that the semiconductor layer can be partially conductive. This photo process uses a half-tone mask after continuously depositing the semiconductor layer and the third metal layer on the buffer layer BUF. This photo process will be described in conjunction with Figures 11a to 11e.

[0177] 11a to 11e are diagrams showing a photo process for simultaneously forming a pattern of a third metal layer on a semiconductor layer using a half-tone mask and partially converting the semiconductor layer into a conductive layer.

[0178] Referring to FIG. 11a, a photo process involves front-side deposition of a semiconductor layer SEM on a buffer layer BUF, and then deposition of a metal layer MM thereon. The semiconductor layer SEM may be selected from an oxide semiconductor that is easy to metallize, such as indium-gallium-zinc oxide (IGZO). The metal layer MM may be one of copper (Cu) and molybdenum-titanium (MoTi), or a dual metal layer in which these metals are stacked. The metal layer MM is used as the third metal layer described above.

[0179] A photosensitive material is coated on the metal layer MM to form a photosensitive material layer on the metal layer MM. In the photo process, a half-tone mask with a desired pattern engraved on the photosensitive material layer is aligned, and the photosensitive material layer is exposed through the half-tone mask and developed to pattern the photosensitive material layer. As a result, photoresist patterns PRa and PRb remain on the metal layer MM.

[0180] The halftone mask may include a transparent portion, a semi-transparent portion, and a blocking portion. In the halftone mask, the photosensitive material exposed to the light incident through the transparent portion is completely removed by the developer, and the photosensitive material exposed to the light incident through the semi-transparent portion may have a part of the upper end removed by the developer. The first photoresist pattern PRa is a portion that is not exposed and is relatively thick. The second photoresist pattern PRb is a photosensitive material exposed through the semi-transparent portion of the halftone mask. The second photoresist pattern PRb is thinner than the first photoresist pattern PRb. The first photoresist pattern PRa is a structure in which a semiconductor layer and a third metal layer are stacked, and is located on the remaining portion. The second photoresist pattern PRb is located on the portion where only the semiconductor layer remains without the third metal layer. The semiconductor layer and the third metal layer are all removed in the portion where the photoresist patterns PRa and PRb are not present by the etching process.

[0181] Subsequently, a photolithography process sprays an etchant onto the metal layer MM to perform wet etching. As a result, as shown in Fig. 11b, a portion of the metal layer MM blocked by the first and second photoresist patterns PRa, PRb remains on the semiconductor layer SEM, and the semiconductor layer SEM exposed to the etchant is removed. The width of the metal pattern MM' remaining on the semiconductor layer SEM may be smaller than the width of the photoresist patterns PRa, PRa because the metal layer is over-etched.

[0182] Next, the photolithography process adjusts the thickness of the photoresist patterns PRa and PRb through an ashing process. The first photoresist pattern PRa is reduced in thickness by the ashing process, and the second photoresist pattern PRb is completely etched and removed. As a result, as shown in FIG. 11c, the first photoresist pattern PRa', which has been reduced in thickness after the ashing process, remains on the semiconductor layer SEM.

[0183] Subsequently, a photolithography process is performed to wet-etch the semiconductor layer SEM, so that the semiconductor layer SEM under the first photoresist pattern PRa remains on the buffer layer BUF, and the semiconductor layer SEM exposed to the etchant is removed.

[0184] Subsequently, a plasma treatment is performed to conductiveize the semiconductor pattern SEM' exposed without being blocked by the photoresist pattern PRa'. As a result, as shown in FIG. 11d, a conductive semiconductor pattern SEM' to be used as the intermediate electrode CE2 of the store capacitor Cst may be formed on the buffer layer BUF.

[0185] Although not shown in the drawings, the semiconductor pattern may be conductive at a contact hole where the semiconductor pattern is connected to an electrode or wiring of a transistor. After the semiconductor pattern is conductive, the photoresist pattern PRa' is removed as shown in FIG 11e.

[0186] Figures 12a to 12c are plan views showing contact hole structures of the pixel circuit shown in Figure 8. In Figures 12a to 12c, "GM" indicates a pattern of a portion of the second metal layer used as electrodes of transistors DT, ST1, and ST2. The contact hole structure shown in Figures 12a to 12c may be any one of contact holes CH2, STH3, and STH4 in Figure 8 that connect the semiconductor layer and the second metal layer.

[0187] For example, the source electrode S0 of the driving element DT is connected to the branch line RBL through a contact hole STH4 penetrating the first insulating layer GI. In the contact hole STH, the conductive semiconductor layer of the branch line RBL may be connected to the second metal layer connected to the source electrode S0. As another example, the third metal layer of the branch line RBL may be connected to the source electrode S0 of the driving element DT through the contact hole STH4.

[0188] After a first insulating layer GI is formed on the conductive semiconductor pattern CSEM / MM', the first insulating layer GI is etched, so that a part of the semiconductor pattern CSEM' / MM' is exposed through the contact hole [CH(GI)] where the first insulating layer GI has been removed, as shown in Figures 12a and 12b.

[0189] The second metal layer GM may be contacted to a metal pattern MM' formed on the non-conductive semiconductor layer SEM in the contact hole [CH(GI)]. In this case, the first insulating layer GI is etched to expose the metal pattern MM' on the semiconductor layer SEM in the contact hole [CH(GI)].

[0190] Subsequently, as shown in FIG. 12c, a second metal layer GM is formed on the first insulating layer GI so as to completely cover the contact hole [CH(GI)]. The second metal layer GM may be a source electrode, a drain electrode, or a gate electrode of the transistors DT, ST1, and ST2. The second metal layer GM contacts the conductive semiconductor pattern CSEM or the metal pattern MM' at the contact hole [CH(GI)] as shown in FIG. 12c.

[0191] In the contact hole structure shown in Fig. 12c, a separate semiconductor conductor process is not required because the second metal layer GM contacts the metal layer MM' having low resistance or the conductorized semiconductor layer CSEM. In the contact hole structure shown in Fig. 7d, the semiconductor layer overlapping with the second metal layer cannot be conductorized, resulting in high electrical resistance. To reduce this resistance, the contact holes exposing the semiconductor layer in Figs. 7a to 7d can be enlarged to increase the exposed area of ​​the semiconductor layer, thereby conductorizing the semiconductor layer, but only a portion of the contact hole can be used as the actual contact area.

[0192] In the contact hole structure shown in FIG. 12c, the conductive semiconductor pattern CSEM or the third metal pattern MM' on the semiconductor layer contacts the second metal layer GM, so that the resistance of the contact hole can be reduced without having to consider the difficulty of conductiveizing the semiconductor layer overlapping with the second metal layer GM. Therefore, the present invention can reduce the size of the contact hole [CH(GI)] by using the contact hole structure shown in FIG. 12c to reduce the pixel circuit area in the sub-pixels SP1 to SP4. As a result, the present invention can increase the light emitting area in the sub-pixels SP1 to SP4 and improve the aperture ratio. Furthermore, as can be seen from FIG. 8, the present invention can further reduce the pixel circuit area, further expand the light emitting area, and further improve the aperture ratio by reducing the number of contact holes STH4 connecting the branch line RBL and the switch element ST2 to one.

[0193] 13 and 14 are diagrams showing an example of darkening a defective sub-pixel by laser cutting in a repair process.

[0194] Fig. 13 is an enlarged plan view of region E in Fig. 3. Fig. 14 is an enlarged plan view of region F in Fig. 8.

[0195] After the pixel array of the display panel is completed, an inspection process is performed. A defective subpixel may be found on the screen of the display panel. In this case, the repair process may be performed by irradiating a laser beam onto a wiring or electrode of a cut node of the pixel circuit of the defective subpixel to cut off the current path, thereby darkening the defective subpixel. The darkening of the defective subpixel may be minimized from being visible to the user. The examples of FIGS. 13 and 14 show a case where the first subpixel is an example of a defective subpixel.

[0196] Referring to FIG. 13, the repair process includes irradiating a laser beam to metals of the branch line RBL and horizontal power line VDDH, which supply power Vref and EVDD to the pixel circuit, in order to darken the defective subpixel. The metal wiring can be melted and disconnected by a laser beam with a wavelength of 1,064 (nm) generated by general laser equipment. If the horizontal power line VDDH has a multi-layer structure in which a semiconductor layer and a third metal layer are stacked, the third metal layer of the horizontal power line VDDH can be melted and the horizontal power line VDDH can be disconnected without changing the wavelength of the laser beam. Since the semiconductor layer under the third metal layer is not conductive, if the third metal layer is disconnected, the horizontal power line VDDH can be disconnected.

[0197] The repair process may further include disconnecting the gate electrode of the first switch element ST1 with a laser beam without changing the wavelength of the laser beam.

[0198] In the display panel shown in FIG. 8, the branch line RBL includes a semiconductor layer and a metal layer partially formed on the semiconductor layer. The semiconductor layer is not melted by a laser beam with a wavelength of 1,064 (nm), so a separate laser device is required. For example, an oxide semiconductor (IGZO) can be melted by a laser beam with a wavelength of 266 (nm). Therefore, in the case of the display panel shown in FIG. 8, in order to reduce the cost of the repair process, it is preferable to cut off the branch line RBL by irradiating a laser beam with a wavelength of 1,064 (nm) to the third metal layer formed on the semiconductor layer in the multi-layered branch line as shown in FIG. 14.

[0199] In the multi-layered branch line, the semiconductor layer below the third metal layer includes a non-conductive portion and can cross the data line between adjacent pixel circuits. Therefore, if the third metal layer of the multi-layered branch line is disconnected, the current path through which the reference voltage Vref is applied can be interrupted.

[0200] 15 to 17 are cross-sectional views that roughly show cross-sectional structures of display panels 10 according to various embodiments of the present invention.

[0201] As can be seen from Figures 15 to 17, the cross-sectional structure of the pixel circuit of the present invention includes a first metal layer ML1 formed on a substrate, a buffer layer BUF covering the first metal layer; an insulating layer GI formed on the buffer layer BUF and covering the semiconductor layer SEML of the transistor TFT; and a second metal layer ML2 formed on the insulating layer GI.

[0202] The first metal layer ML includes a light blocking layer LS of the transistor TFT and a lower electrode of a capacitor Cst. The second metal layer ML2 includes a gate electrode G, a source electrode S, and a drain electrode D of the transistor, which are arranged substantially on the same plane. The semiconductor layer SEML includes an active layer ACT that forms a channel of the transistor TFT. The transistor TFT may be a driving element DT or a switching element ST1, ST2, or may be all transistors of a pixel circuit.

[0203] At least a portion of the branch line RBL may include a conductive semiconductor layer disposed substantially in the same plane as the semiconductor layer SEML, as illustrated in FIGS.

[0204] The cross-sectional structures of the transistor TFT, the storage capacitor Cst, and the branch line RBL in the display panel 10 shown in Fig. 3 can be simply expressed as shown in Fig. 15. The transistor TFT shown in Fig. 15 is a driving element DT. The switching elements ST1 and ST2 have substantially the same structure as the driving element DT, except that they do not have a light blocking pattern LS.

[0205] Referring to FIG. 15, the gate electrode G, source electrode S, and drain electrode D of the transistor TFT of the pixel circuit may be formed of a metal pattern separated from a second metal layer ML2 disposed on a first insulating layer GI. The transistor TFT may be all the transistors constituting the pixel circuit, i.e., the driving element and the switching element. The transistor TFT includes an active layer ACT formed on a buffer layer BUF. The active layer ACT may be formed of a semiconductor pattern separated from a semiconductor layer SEML between the buffer layer BUF and the first insulating layer GI. Each of the buffer layer BUF and the first insulating layer GI may be an inorganic insulating film.

[0206] A light-blocking pattern LS separated from a first metal layer ML1 may be disposed under the transistor TFT. The light-blocking pattern LS may be patterned from a first metal layer covered by a buffer layer BUF. The storage capacitor Cst includes an upper electrode CE made of a conductive semiconductor pattern and a lower electrode made of the first metal layer ML1. The light-blocking pattern LS and the lower electrode of the storage capacitor Cst may be integrated into a single pattern of the first metal layer ML1. The branch line RBL includes first and second branch lines BLa, BLb patterned from a second metal layer ML2.

[0207] 15, the first metal layer ML1 includes at least the light blocking pattern LS of the transistor TFT and the lower electrode of the storage capacitor Cst. The semiconductor layer SEML includes at least the active layer ACT of the transistor TFT and the upper electrode CE of the storage capacitor Cst. The second metal layer ML2 includes at least the electrodes of the transistor TFT and the branch lines BLa, BLb (i.e., RBL shown in FIG. 15).

[0208] In the display panel 10 shown in FIG 8, the cross-sectional structures of the transistor TFT, the storage capacitor Cst, and the branch line RBL can be simply expressed as shown in FIG 16. The storage capacitor Cst can be realized by the structure shown in FIG 17.

[0209] 16 and 17, the first metal layer ML1 includes at least a light blocking pattern LS of the transistor TFT. The first metal layer ML1 may further include a lower electrode of the storage capacitor Cst. The semiconductor layer SEML includes at least an active layer ACT of the transistor TFT, an intermediate electrode CE2 of the storage capacitor Cst, and a branch line RBL. The second metal layer ML2 includes at least an electrode of the transistor TFT and an upper electrode CE1 of the storage capacitor Cst.

[0210] The intermediate electrode CE2 of the storage capacitor Cst shown in Fig. 16 is implemented as a conductive semiconductor layer. The storage capacitor Cst may include a first capacitor Cst1 between the first metal layer ML1 and the semiconductor layer SEML, and a second capacitor Cst2 between the semiconductor layer SEML and the second metal layer ML2, as shown in Fig. 16. As another example, the storage capacitor Cst may be implemented as a capacitor between the semiconductor layer SEML and the second metal layer ML2, as shown in Fig. 17.

[0211] When the semiconductor layer SEML is a single semiconductor layer, it may be partially conductive. A third metal layer (not shown in the drawing) may be formed on the semiconductor layer SEML. The third metal layer is disposed on the semiconductor layer SEML between the first metal layer ML1 and the second metal layer ML2.

[0212] The branch line RBL includes a single-layer branch line overlapping the light-emitting region of the aperture APT. The single-layer branch line is formed of a transparent conductive semiconductor layer, so that it overlaps with the light-emitting region and can expand the aperture.

[0213] In the display panel shown in FIG. 8, the electrodes of the transistors and the electrodes of the storage capacitors may be connected to a stacked structure of semiconductor layers and metal layers as shown in FIG.

[0214] 18, the active layer ACT of the transistor TFT may be a multi-layer structure in which a semiconductor layer SEML and a third metal layer ML3 are stacked. The source and drain electrodes S and D of the transistor TFT contact the third metal layer ML3 on the semiconductor layer SEML through contact holes penetrating the first insulating layer GI.

[0215] The intermediate electrode CE2 of the storage capacitor Cst may have a multi-layer structure in which a semiconductor layer SEML and a third metal layer ML3 are stacked. In this case, the semiconductor layer SEML of the intermediate electrode CE2 does not need to be conductive.

[0216] The pad PAD includes a first electrode PE1 formed of a first metal layer ML1, a second electrode PE2 formed of a second metal layer ML2, and a third electrode PE3 formed on the second electrode PE2. The second electrode PE2 contacts the first electrode PE1 through a contact hole penetrating the buffer layer BUF. The third electrode PE3 is formed of a transparent electrode material at the same time as the anode electrode AND of the light emitting element OLED. An output pin of the source driver 12 is connected to the third electrode PE3 of the pad PAD through an anisotropic conductive film (ACF).

[0217] In the display panel 10 shown in FIG. 8, the first metal layer pattern and the semiconductor pattern are the same as those in FIG.

[0218] Referring to FIG. 19, the pattern of the first metal layer ML includes at least a vertical power supply line VDDV, a reference voltage line RL, data lines DL1 to DL4, and a light blocking pattern LS.

[0219] The semiconductor pattern includes at least first to sixth semiconductor patterns SEM1 to SEM6. The first semiconductor pattern SEM1 includes a branch line connected to the reference voltage line RL through a contact hole RH3.

[0220] The semiconductor pattern of the branch line RBL includes a conductive line portion SEM1-1 that crosses at least one light emitting region of the subpixel along a first direction x, and a branch portion SEM1-2 that bends from the line portion SEM1-1 along a second direction y that intersects the first direction x and is connected to the pixel circuit.

[0221] The line portion SEM1-1 of the branch line RBL may cross and overlap the light emitting region of one or more sub-pixels. A plurality of branch portions SEM1-2 are connected to one line portion SEM1-1 so that a reference voltage Vref may be applied to one or more sub-pixels through the branch line RBL. The branch portion SEM1-2 may include an active layer that is not conductive in the second switch element ST2 and at least one of the electrodes of the second switch element ST2. The branch portion SEM1-2 may include a conductive electrode portion that contacts the source and drain electrodes of the second switch element ST2.

[0222] The second to fifth semiconductor patterns SEM2 to SEM5 may be conductive at portions in contact with the electrode of the storage capacitor Cs1 and the source and drain electrodes of the first switch element ST1. The third semiconductor pattern SEM2 may be conductive at portions in contact with the electrode of the storage capacitor Cs1 and the source and drain electrodes of the first switch element ST1. The sixth semiconductor pattern SEM6 may be conductive at the source and drain electrodes of the driving element DT.

[0223] The reference voltage line RL may be implemented as a conductive semiconductor pattern. In this case, as shown in FIG. 20, the first semiconductor pattern SEM1 and the reference voltage line RL are connected on the same plane, so no contact hole is required. The reference voltage line RL is connected to the second switch element ST2 of the pixel circuit. When the reference voltage line RL and the drain electrode of the second switch element ST2 and the reference voltage line RL are connected through a contact hole, as shown in FIG. 21a, there is a resistance Rcnt of the contact hole and a wiring resistance Rr of the reference voltage line RL. In contrast, when the reference voltage line RL and the drain electrode of the second switch element ST2 and the reference voltage line RL are directly connected without a contact hole, there is only a wiring resistance Rr of the reference voltage line RL between them, as shown in FIG. 21b.

[0224] When the reference voltage line RL is embodied as a conductorized semiconductor pattern, in order to prevent a short circuit between the reference voltage line and the horizontal power supply line VDDH, the horizontal power supply line VDDH may be formed of a first metal layer ML1 or a second metal layer ML2 separated from the semiconductor layer by an insulating layer.

[0225] In the repair process, when a defective sub-pixel is darkened, it is necessary to disconnect the node, i.e., the wiring between the driving element DT and the anode electrode AND of the light-emitting element OLED. The wavelength of the laser beam capable of melting the anode electrode may be different from the wavelength of the laser beam capable of melting the metal and semiconductor layers. For example, ITO used as the anode electrode can be melted by a laser beam with a wavelength of 266 (nm). In contrast, the semiconductor layer of the branch line can be melted by a laser beam with a wavelength of 1,064 (nm). In this case, a laser device for disconnecting the anode electrode and a laser device for disconnecting the branch line are required separately, which increases the repair process time. In the third embodiment of the present invention, the branch line can be embodied in a structure as shown in FIG. 22 and FIG. 23 in order to simultaneously disconnect the anode electrode and the branch line using one laser device in the laser process.

[0226] FIG 22 is a plan view of a display device according to a third embodiment of the present invention. FIG 23 is a cross-sectional view taken along cutting line I-I' in FIG 22. In this embodiment, the anode electrode of the light emitting device OLED and the branch line RBL can be simultaneously cut by a laser beam of the same wavelength in a repair process. FIG 22 and FIG 23 are enlarged views of a part of the branch line modified into a pixel circuit of the display panel shown in FIG 8. In this embodiment, the same components as those in FIG 8 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0227] 22 and 23, the branch line RBL includes a line portion RBL-1 that is long along a first direction x, and a branch portion RBL-2 that is bent from the line portion RBL-1 along a second direction y that intersects with the first direction x and is connected to a pixel circuit. The line portion RBL-1 is connected to the reference voltage line RL and intersects with the data lines DL1 and DL2.

[0228] The line portion RBL-1 of the branch line RBL has a length that crosses one or more subpixels between the light emitting area of ​​the subpixel and the pixel circuit. At least a portion of the line portion RBL-1 overlaps the anode electrode AND of the light emitting element OLED between the light emitting area of ​​the subpixel and the gate line GL. At least a portion of the line portion RBL-1 may overlap the bank BNK.

[0229] A plurality of branch portions RBL-2 are connected to one line portion RBL-1 so that a reference voltage Vref can be applied to one or more subpixels through the branch line RBL. The branch portion RBL-2 includes a non-conductive active layer of the second switch element ST2 in the corresponding subpixel and a conductive electrode portion that contacts the source and drain electrodes of the second switch element ST2. At least a portion of the branch portion RBL-2 overlaps with the anode electrode AND of the light emitting element OLED. At least a portion of the branch portion RBL-2 may overlap with the bank BNK.

[0230] At least a portion of the line portion RBL-1 and at least a portion of the branch portion RBL-2 have a multi-layer structure in which a semiconductor layer SEM and a third metal layer ML3 are stacked, as shown in FIG. 23. The third metal layer ML3 may be any one of copper (Cu) and molybdenum titanium (MoTi), or a dual metal layer in which these metals are stacked. The third metal layer ML3 of the line portion RBL-1 allows the line portion RBL-1 to be disposed along a path that avoids the light-emitting region of the opening. For example, the portion of the line portion RBL-1 where the third metal layer ML3 exists may be disposed between the light-emitting region of the subpixel and the gate line GL.

[0231] When a defective subpixel is detected in the display panel 10 having the pixel structure shown in FIG. 22 and FIG. 23, a repair process is performed. In the repair process, a laser beam is irradiated onto the power supply wiring that supplies the power supply Vref and EVDD to the pixel circuit in order to darken the defective subpixel. The metal wiring can be cut with a laser beam having a wavelength of 1,064 (nm) generated by a general laser device. In the repair process, the branch line RBL can be disconnected by irradiating the laser beam once along the overlapping portion of the third metal layer ML3 and the anode electrode AND in the branch line RBL, for example, along the cutting line I-I' in FIG. 22 and FIG. 23, without changing the wavelength of the laser beam. At this time, the semiconductor layer SEM under the third metal layer ML3 is not disconnected, but since this semiconductor layer SEM is not made conductive, a disconnection effect is achieved.

[0232] The repair process may further include disconnecting the horizontal power supply line VDDH and the gate electrode of the first switch element ST1 with a laser beam.

[0233] As shown in FIG. 24, the line portion RBL-1 and the branch portion RBL-2 of the branch line RBL may be embodied as a single layer structure including a semiconductor layer at least partially conductive. For example, at least a portion of the branch portion RBL-2 may be a multi-layer structure in which a semiconductor layer SEM and a third metal layer ML3 are stacked. Since the conductive semiconductor layer is transparent, it may overlap with the light emitting region of the subpixel to enlarge the opening including the light emitting region. In the repair process, a laser beam is irradiated to a position where the anode electrode AND and the third metal layer ML3 of the branch line RBL overlap in the line portion RBL-1 or the branch portion RBL-2 as shown in FIG. 23 and FIG. 24, thereby simultaneously disconnecting the anode electrode AND and the branch line RBL connected to the defective subpixel.

[0234] The contents of the specification, which describe the problem to be solved, the means for solving the problem, and the effects described above, do not specify essential features of the claims, and therefore the scope of the claims is not limited by the matters described in the specification.

[0235] Although the embodiments of the present invention have been described in detail above with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications can be made within the scope of the technical idea of ​​the present invention. Therefore, the embodiments disclosed in the present invention are for illustration purposes, not for limiting the technical idea of ​​the present invention, and the scope of the technical idea of ​​the present invention is not limited by these embodiments. Therefore, the embodiments described above should be understood to be illustrative in all respects, and not restrictive. The scope of protection of the present invention should be interpreted by the scope of the claims, and all technical ideas within the scope equivalent thereto should be interpreted as being included in the scope of the present invention. [Explanation of symbols]

[0236] 10: Display panel SP1, SP2, SP3, SP4: Subpixel EA: Light emitting part CA:Circuit section GL: Gate line DL: Data line RL: Reference voltage line Cst: storage capacitor VDDH: Horizontal power supply line VDDV: Vertical power line DT: Drive element ST1: First switch element ST2: second switch element RBL: Branch Line

Claims

1. A substrate; an anode including a light-emitting region disposed on the substrate; a reference voltage line adjacent to the anode; a branch line connected to the reference voltage line and applying a reference voltage from the reference voltage line to the anode via a switch element; the branch line includes a semiconductor layer; The branch line is provided between the reference voltage line and the anode.

2. further comprising a bank disposed on the anode; the bank exposes a portion of the anode and defines an opening that includes the light emitting region; The display panel according to claim 1 , wherein at least a portion of the semiconductor layer of the branch line overlaps with the anode within the opening.

3. The display panel of claim 1 , wherein the branch lines further include a metal layer partially disposed on the semiconductor layer.

4. a pixel circuit for driving a light emitting element including the anode; a power supply line for applying a pixel driving voltage to the pixel circuit; a data line for supplying a data voltage to the pixel circuit; 2. The display panel of claim 1, further comprising: a gate line for supplying a gate voltage to the pixel circuit.

5. The power supply line is a first power line connected to the pixel circuit in a first direction to apply the pixel driving voltage to the pixel circuit; a second power supply line arranged in a second direction intersecting the first direction and connected to the first power supply line; The display panel according to claim 4 , wherein at least a portion of the first power supply line has a multi-layer structure in which a semiconductor layer and a metal layer are laminated.

6. The display panel according to claim 1 , wherein the branch lines are arranged in a layer different from that of the reference voltage line and are connected to the reference voltage line through contact holes.

7. The display panel according to claim 3 , wherein the semiconductor layer of the branch line is disposed to cross the light emitting region, and the metal layer of the branch line is disposed to cross the data line.

8. The branch line is a line portion arranged along a first direction so as to intersect with the light emitting region; The display panel of claim 3 , further comprising at least one branch portion bent from the line portion in a second direction intersecting the first direction and connected to the pixel circuit.

9. The display panel of claim 1 , wherein the branch lines and the reference voltage lines are arranged to be connected to each other in the same layer.

10. The display panel of claim 9 , wherein the reference voltage line includes the semiconductor layer.

11. A substrate; a first voltage line provided on the substrate in a first direction; a second voltage line connected to the first voltage line and provided in a second direction intersecting the first direction, the second voltage line includes a semiconductor layer; The second voltage line is provided between the substrate and the first voltage line.

12. A transparent anode; a bank disposed on the transparent anode; the bank exposes a portion of the transparent anode and defines an opening including a light emitting region; The display panel of claim 11 , wherein at least a portion of the semiconductor layer of the second voltage line overlaps the transparent anode in the opening.

13. The display panel of claim 12 , wherein the second voltage line further comprises a metal layer partially disposed on the semiconductor layer.

14. a pixel circuit for driving a light emitting element including the transparent anode; a power supply line for applying a pixel driving voltage to the pixel circuit; a data line for supplying a data voltage to the pixel circuit; The display panel of claim 12 , further comprising: a gate line for supplying a gate voltage to the pixel circuit.

15. The second voltage line is a line portion arranged along a first direction so as to intersect with the transparent anode; The display panel of claim 13 , further comprising at least a branch portion bent from the line portion in a second direction intersecting the first direction to be connected to the pixel circuit.

16. The display panel of claim 15 , wherein at least a portion of the line portion overlaps the transparent anode between the light emitting region and the gate line.

17. The display panel of claim 15 , wherein at least a portion of the branch portion overlaps the transparent anode.

18. The display panel according to claim 15 , wherein at least a portion of the branch portion overlaps with the bank.

19. The display panel according to claim 15 , wherein at least a portion of the line portion has a multi-layer structure including the semiconductor layer and a metal layer laminated on the semiconductor layer.

20. The display panel according to claim 15 , wherein at least a part of the line portion and at least a part of the branch portion have a single-layer structure including the semiconductor layer.

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