Manufacturing method of semiconductor device

Abstract

To provide a manufacturing method of a semiconductor device capable of efficiently consuming a semiconductor wafer.SOLUTION: A method includes: a step for preparing a semiconductor wafer source comprising SiC (silicon carbide); a step for forming an epitaxial layer comprising SiC on a first principal surface of the semiconductor wafer source; an element forming step for forming the semiconductor wafer in the epitaxial layer; a bonding step for bonding a first principal surface side supporting member to a first principal surface side of the semiconductor wafer source in which the semiconductor element is formed in the epitaxial layer; a step for forming an alterated layer on the semiconductor wafer source along a horizontal direction parallel to the first principal surface from an intermediate section in a depth direction of the semiconductor wafer source in a state where the semiconductor wafer source is supported on the first principal surface side supporting member; and a wafer source separation step for separating the semiconductor wafer source into an element formed wafer and an element non-formed wafer along the alterated layer.SELECTED DRAWING: Figure 6A

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a method for manufacturing a semiconductor device, including a step of thinning a semiconductor wafer by grinding, and a step of cutting out a plurality of semiconductor chips (semiconductor devices) from the thinned semiconductor wafer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2010-016188 A Summary of the Invention [Problem to be solved by the invention]

[0004] In recent years, with the development of semiconductor device manufacturing technology, semiconductor devices have become thinner. On the other hand, with the development of semiconductor wafer manufacturing technology, the diameter of semiconductor wafers has become larger. The thickness of semiconductor wafers has become larger in proportion to the diameter in order to suppress bending due to their own weight. In other words, semiconductor wafer manufacturing technology is moving in the direction of thickening semiconductor wafers, contrary to the semiconductor device manufacturing technology that aims to thin semiconductor devices.

[0005] For example, in the conventional manufacturing method disclosed in Patent Document 1, a thick semiconductor wafer is thinned by grinding, and then a plurality of semiconductor devices are cut out. With this manufacturing method, it is possible to manufacture semiconductor devices having a desired thickness regardless of the thickness of the semiconductor wafer.

[0006] However, in the conventional manufacturing method, as the thickness of the semiconductor wafer increases, the portion of the semiconductor wafer that needs to be removed by grinding increases. In other words, in the conventional manufacturing method, in the case of a large-diameter and thick semiconductor wafer, the grinding time required to thin the semiconductor device increases and the number of semiconductor devices that can be obtained per unit volume relatively decreases compared to the case of a small-diameter and thin semiconductor wafer. Therefore, the semiconductor wafer cannot be consumed efficiently.

[0007] An embodiment of the present invention provides a method for manufacturing a semiconductor device that can efficiently consume semiconductor wafers. [Means for solving the problem]

[0008] One embodiment of the present invention includes a step of preparing a semiconductor wafer source made of SiC (silicon carbide) including a first main surface on one side, a second main surface on the other side, and a sidewall connecting the first main surface and the second main surface; a step of forming an epitaxial layer made of SiC on the first main surface of the semiconductor wafer source; an element forming step of setting a plurality of element formation regions in the epitaxial layer and fabricating semiconductor elements in each of the plurality of element formation regions; and a step of forming a semiconductor wafer of the first semiconductor wafer source having semiconductor elements formed in the element formation regions of the epitaxial layer. The present invention provides a method for manufacturing a semiconductor device, the method including: a bonding step of bonding a first main surface side support member to a main surface side; a step of forming an altered layer in the semiconductor wafer source from a middle part in the thickness direction of the semiconductor wafer source along a horizontal direction parallel to the first main surface while the semiconductor wafer source is supported by the first main surface side support member; and a wafer source separation step of separating the semiconductor wafer source along the altered layer formed in the semiconductor wafer source into an element-formed wafer on which the semiconductor elements are formed and an element-unformed wafer supported by the first main surface side support member.

[0009] According to this manufacturing method for a semiconductor device, a plurality of semiconductor devices can be cut out from a wafer with elements formed thereon (a wafer with elements formed thereon), while the wafer without elements formed thereon can be reused as a new semiconductor wafer source. This makes it possible to suppress delays in manufacturing and at the same time to suppress excessive consumption of the semiconductor wafer source. Therefore, it is possible to provide a manufacturing method for a semiconductor device that can efficiently consume the semiconductor wafer source.

[0010] The above and other objects, features and advantages of the present invention will become apparent from the following detailed description of the embodiments with reference to the accompanying drawings. [Brief description of the drawings]

[0011] [Figure 1A] FIG. 1A is a perspective view for explaining one example of a semiconductor wafer source that can be applied to a method for manufacturing a semiconductor device according to a first embodiment of the present invention. FIG. [Figure 1B] FIG. 1B is a perspective view for explaining one embodiment of a wafer bonding structure that can be applied to the method for manufacturing a semiconductor device according to the first embodiment of the present invention. FIG. [Figure 2A] FIG. 2A is a process diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention. [Figure 2B] FIG. 2B is a process diagram for explaining a process carried out on the element formed wafer obtained from the process shown in FIG. 2A. [Figure 3A] FIG. 3A is a schematic cross-sectional view for explaining the manufacturing method shown in FIGS. 2A and 2B. [Figure 3B] FIG. 3B is a cross-sectional view for explaining a step subsequent to FIG. 3A. [Figure 3C] FIG. 3C is a cross-sectional view for explaining a step subsequent to FIG. 3B. [Figure 3D] FIG. 3D is a cross-sectional view for explaining a step subsequent to FIG. 3C. [Figure 3E] FIG. 3E is a cross-sectional view for explaining a step subsequent to FIG. 3D. [Figure 3F] FIG. 3F is a cross-sectional view for explaining a step subsequent to FIG. 3E. [Figure 3G] FIG. 3G is a cross-sectional view for explaining a step subsequent to FIG. 3F. [Figure 3H] FIG. 3H is a cross-sectional view for explaining a step subsequent to FIG. 3G. [Figure 3I] FIG. 3I is a cross-sectional view for explaining a step subsequent to FIG. 3H. [Figure 3J] FIG. 3J is a cross-sectional view for explaining a step subsequent to FIG. 3I. [Figure 3K] FIG. 3K is a cross-sectional view for explaining a step subsequent to FIG. 3J. [Figure 4] FIG. 4 is a process diagram illustrating a method for manufacturing a semiconductor device according to the second embodiment of the present invention. [Diagram 5] FIG. 5 is a process diagram illustrating a method for manufacturing a semiconductor device according to the third embodiment of the present invention. [Figure 6A] FIG. 6A is a process diagram illustrating a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention. [Figure 6B] FIG. 6B is a process diagram for explaining a process carried out on the element formed wafer obtained from the process shown in FIG. 6A. [Figure 7A] FIG. 7A is a schematic cross-sectional view for explaining the manufacturing method shown in FIGS. 6A and 6B. [Figure 7B] FIG. 7B is a cross-sectional view for explaining a step subsequent to FIG. 7A. [Figure 7C] FIG. 7C is a cross-sectional view for explaining a step subsequent to FIG. 7B. [Figure 7D] FIG. 7D is a cross-sectional view for explaining a step subsequent to FIG. 7C. [Figure 7E] FIG. 7E is a cross-sectional view for explaining a step subsequent to FIG. 7D. [Figure 7F] FIG. 7F is a cross-sectional view for explaining a step subsequent to FIG. 7E. [Figure 7G] FIG. 7G is a cross-sectional view for explaining a step subsequent to FIG. 7F. [Figure 8A]FIG. 8A is a process diagram illustrating a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention. [Figure 8B] FIG. 8B is a process diagram for explaining a process carried out on the element formed wafer obtained from the process shown in FIG. 8A. [Figure 9A] FIG. 9A is a schematic cross-sectional view for explaining the manufacturing method shown in FIGS. 8A and 8B. [Figure 9B] FIG. 9B is a cross-sectional view for explaining a step subsequent to FIG. 9A. [Figure 9C] FIG. 9C is a cross-sectional view for explaining a step subsequent to FIG. 9B. [Figure 9D] FIG. 9D is a cross-sectional view for explaining a step subsequent to FIG. 9C. [Figure 9E] FIG. 9E is a cross-sectional view for explaining a step subsequent to FIG. 9D. [Figure 9F] FIG. 9F is a cross-sectional view for explaining a step subsequent to FIG. 9E. [Figure 9G] FIG. 9G is a cross-sectional view for explaining a step subsequent to FIG. 9F. [Figure 9H] FIG. 9H is a cross-sectional view for explaining a step subsequent to FIG. 9G. [Figure 9I] FIG. 9I is a cross-sectional view for explaining a step subsequent to FIG. 9H. [Figure 9J] FIG. 9J is a cross-sectional view for explaining a step subsequent to FIG. 9I. [Figure 9K] FIG. 9K is a cross-sectional view for explaining a step subsequent to FIG. 9J. [Figure 9L] FIG. 9L is a cross-sectional view for explaining a step subsequent to FIG. 9K. [Figure 9M] FIG. 9M is a cross-sectional view for explaining a step subsequent to FIG. 9L. [Figure 10] FIG. 10 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention. [Figure 11A] FIG. 11A is a process diagram illustrating a method for manufacturing a semiconductor device according to a sixth embodiment of the present invention. [Figure 11B]FIG. 11B is a process diagram for explaining a process carried out on the element formed wafer obtained from the process shown in FIG. 11A. [Figure 12A] FIG. 12A is a schematic cross-sectional view for illustrating the manufacturing method shown in FIGS. 11A and 11B by applying the manufacturing method shown in FIGS. 11A and 11B to a manufacturing method of the semiconductor device shown in FIG. [Figure 12B] FIG. 12B is a cross-sectional view for explaining a step subsequent to FIG. 12A. [Figure 12C] FIG. 12C is a cross-sectional view for explaining a step subsequent to FIG. 12B. [Figure 12D] FIG. 12D is a cross-sectional view for explaining a step subsequent to FIG. 12C. [Figure 12E] FIG. 12E is a cross-sectional view for explaining a step subsequent to FIG. 12D. [Figure 12F] FIG. 12F is a cross-sectional view for explaining a step subsequent to FIG. 12E. [Figure 12G] FIG. 12G is a cross-sectional view for explaining a step subsequent to FIG. 12F. [Figure 12H] FIG. 12H is a cross-sectional view for explaining a step subsequent to FIG. 12G. [Figure 12I] FIG. 12I is a cross-sectional view for explaining the step subsequent to FIG. 12H. [Figure 13] FIG. 13 is a cross-sectional view showing a first modified example of the wafer bonding structure. [Figure 14] FIG. 14 is a perspective view showing a second modified example of the wafer bonding structure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] FIG. 1A is a perspective view for explaining one embodiment of a semiconductor wafer source 1 that can be applied to a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

[0013] 1A, a disk-shaped semiconductor wafer source 1 may be applied to the manufacture of a semiconductor device. In this embodiment, the semiconductor wafer source 1 includes SiC (silicon carbide). More specifically, the semiconductor wafer source 1 is made of a semiconductor wafer made of a single crystal SiC.

[0014] The semiconductor wafer source 1 has a first main surface 2 on one side, a second main surface 3 on the other side, and a sidewall 4 connecting the first main surface 2 and the second main surface 3. The first main surface 2 of the semiconductor wafer source 1 is an element formation surface on which semiconductor elements are formed.

[0015] The semiconductor wafer source 1 has a thickness T1 that allows cutting from a middle portion in the thickness direction along a horizontal direction parallel to the first main surface 2. The thickness T1 of the semiconductor wafer source 1 exceeds the thickness of a semiconductor substrate of a semiconductor device (semiconductor chip) to be obtained. The thickness T1 of the semiconductor wafer source 1 may be 100 μm or more and 1000 μm or less. The thickness T1 of the semiconductor wafer source 1 may be 250 μm or more and 500 μm or less.

[0016] The semiconductor wafer source 1 includes a first wafer edge 5 and a second wafer edge 6. The first wafer edge 5 connects the first main surface 2 and the sidewall 4. More specifically, the first wafer edge 5 connects the first main surface 2 and the sidewall 4 at a right angle. That is, the first wafer edge 5 is not chamfered.

[0017] The second wafer edge 6 connects the second main surface 3 and the side wall 4. More specifically, the second wafer edge 6 connects the second main surface 3 and the side wall 4 at a right angle. That is, the second wafer edge 6 is not chamfered. In the semiconductor wafer source 1, it is preferable that at least the second wafer edge 6 is not chamfered.

[0018] A first orientation flat 7 (first mark) indicating a crystal orientation or the like is formed on the semiconductor wafer source 1. The first orientation flat 7 includes a notch formed on the periphery of the semiconductor wafer source 1. The first orientation flat 7 extends linearly on the periphery of the semiconductor wafer source 1.

[0019] A plurality of element formation regions 10 (chip formation regions) are set on the first main surface 2 of the semiconductor wafer source 1. A semiconductor element 11 is formed in each of the element formation regions 10. The element formation regions 10 may be set in a matrix with gaps between them. Each element formation region 10 may be set in a quadrangular shape in a plan view seen from the normal direction of the first main surface 2.

[0020] The semiconductor element 11 may include various functional elements formed by utilizing a semiconductor material, properties of the semiconductor material, etc. The semiconductor element 11 may include at least one of a semiconductor rectifying element, a semiconductor switching element, and a semiconductor passive element.

[0021] The semiconductor rectifying element may include various diode elements such as a pn junction diode, a Zener diode, a Schottky barrier diode, a fast recovery diode, etc. The semiconductor switching element may include various transistor elements such as a bipolar transistor, a MISFET (Metal Insulator Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), etc. The semiconductor passive element may include various passive elements such as a capacitor, a resistor, an inductor, etc.

[0022] The semiconductor device 11 may include a circuit network in which any two or more elements selected from a semiconductor rectifying element, a semiconductor switching element, and a semiconductor passive element are selectively combined. The circuit network may form a part or the whole of an integrated circuit.

[0023] The integrated circuit may include Small Scale Integration (SSI), Large Scale Integration (LSI), Medium Scale Integration (MSI), Very Large Scale Integration (VLSI) or Ultra-Very Large Scale Integration (ULSI).

[0024] Dicing lines 12 are defined in boundary regions between the plurality of element forming regions 10. The semiconductor wafer source 1 is cut along the dicing lines 12 to cut out a plurality of semiconductor devices.

[0025] FIG. 1B is a perspective view for explaining one embodiment of a wafer bonding structure 101 that can be applied to the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

[0026] 1B, a disk-shaped wafer bonding structure 101 may be applied to the manufacture of a semiconductor device. The wafer bonding structure 101 has a laminated structure including a semiconductor wafer source 1 and a first support member 21. The semiconductor wafer source 1 is bonded to the first support member 21.

[0027] According to the wafer bonding structure 101, the semiconductor wafer source 1 and the first support member 21 are handled as a single unit. This increases the convenience of handling the semiconductor wafer source 1. In this specification, the term "handling" includes not only carrying in and out of a manufacturing device for manufacturing a semiconductor device, but also distribution in the market. In other words, the wafer bonding structure 101 can be a trading object in the market.

[0028] The first support member 21 is made of a disk-shaped substrate (wafer) and supports the semiconductor wafer source 1 from the second main surface 3. The first support member 21 has a first support main surface 22 on one side, a second support main surface 23 on the other side, and a support sidewall 24 connecting the first support main surface 22 and the second support main surface 23.

[0029] The first support member 21 includes a first support edge 25 and a second support edge 26. The first support edge 25 connects the first support main surface 22 and the support side wall 24. The first support edge 25 includes a chamfered portion. The first support edge 25 may be C-chamfered. The first support edge 25 may be R-chamfered. In this case, the first support edge 25 may include a chamfered portion that is chamfered into a convex curved shape or a shape close to a convex curved shape.

[0030] The first support edge 25 may be chamfered by at least one of a wire saw processing method, a dicing blade processing method, and an etching processing method. The chamfering of the first support edge 25 can improve the convenience of handling the wafer bonding structure 101.

[0031] The second support edge 26 connects the second support main surface 23 and the support side wall 24. The second support edge 26 includes a chamfered portion. The second support edge 26 may be C-chamfered. The second support edge 26 may be R-chamfered. In this case, the second support edge 26 may include a chamfered portion that is chamfered into a convex curved shape or a shape close to a convex curved shape.

[0032] The second support edge 26 may be chamfered by at least one of a wire saw processing method, a dicing blade processing method, and an etching processing method. The chamfering of the second support edge 26 can improve the convenience of handling the wafer bonding structure 101.

[0033] The first support member 21 supports the semiconductor wafer source 1 from the side of the second main surface 3. In other words, the semiconductor wafer source 1 is disposed on the first main support surface 22 of the first support member 21 with the second main surface 3 facing the first main support surface 22 of the first support member 21. The first main support surface 22 of the first support member 21 is adhered to the second main surface 3 of the semiconductor wafer source 1.

[0034] In this embodiment, the planar area of ​​the first support member 21 is formed to be equal to or larger than the planar area of ​​the semiconductor wafer source 1. This can improve the convenience of handling the wafer bonding structure 101. In a state in which the semiconductor wafer source 1 is supported at the center of the first support member 21, the distance D between the periphery of the semiconductor wafer source 1 and the periphery of the first support member 21 may be 0 mm or more and 10 mm or less.

[0035] Various materials can be used as the material of the first support member 21 as long as they can fixedly support the semiconductor wafer source 1. For the convenience of supporting the semiconductor wafer source 1, the first support member 21 preferably has physical properties relatively close to those of the semiconductor wafer source 1. The physical properties include, for example, the thermal expansion coefficient and the melting point.

[0036] The ratio of the thermal expansion coefficient of the first support member 21 to the thermal expansion coefficient of the semiconductor wafer source 1 may be 0.5 or more and 1.5 or less. The thermal expansion coefficient ratio is preferably 0.8 or more and 1.2 or less. The melting point of the first support member 21 may be equal to or higher than the melting point of the semiconductor wafer source 1. The melting point of the first support member 21 may be 1600°C or more.

[0037] The first support member 21 preferably contains the same material type as the semiconductor wafer source 1. That is, the first support member 21 preferably contains SiC (silicon carbide). The first support member 21 is more preferably made of a semiconductor wafer made of single crystal SiC. This makes the physical properties of the first support member 21 approximately equal to the physical properties of the semiconductor wafer source 1.

[0038] The thickness T2 of the first support member 21 may be 100 μm or more and 1000 μm or less. The thickness T2 of the first support member 21 may be 250 μm or more and 500 μm or less. The thickness T2 of the first support member 21 may be equal to the thickness T1 of the semiconductor wafer source 1.

[0039] In the method for manufacturing a semiconductor device, the semiconductor wafer source 1 may be irradiated with laser light via the first support member 21. In this case, the first support member 21 is preferably optically transparent. The first support member 21 is preferably an optically transparent wafer that suppresses attenuation of the laser light irradiated to the semiconductor wafer source 1. The optically transparent wafer may include a light-transmitting wafer and a transparent wafer.

[0040] The first support member 21 is preferably a single crystal semiconductor wafer (a semiconductor wafer made of single crystal SiC) with no or a low impurity concentration added thereto. In this case, absorption (attenuation) of the laser light by the first support member 21 is suppressed.

[0041] When the first support member 21 contains impurities, the impurity concentration of the first support member 21 is preferably 1.0×1018 cm-3 or less. It should be noted that laser light having a wavelength of 390 μm or less tends to be absorbed (attenuated) by the first support member 21 made of a semiconductor wafer made of single crystal SiC, regardless of whether or not impurities are added.

[0042] The first support member 21 may be a single crystal semiconductor wafer (a semiconductor wafer made of single crystal SiC) doped with vanadium. The first support member 21 may be a single crystal semiconductor wafer (a semiconductor wafer made of single crystal SiC) doped with p-type impurities. The first support member 21 may be a single crystal semiconductor wafer (a semiconductor wafer made of single crystal SiC) doped with n-type impurities.

[0043] The first support member 21 may be a single crystal semiconductor wafer (a semiconductor wafer made of single crystal SiC) doped with p-type impurities and n-type impurities. The p-type impurity concentration and the n-type impurity concentration may be approximately the same. In addition, the first support member 21 made of various types of materials may be adopted based on the physical properties of the semiconductor wafer source 1 and the wavelength of the laser light.

[0044] A second orientation flat 27 (second mark) indicating a crystal orientation or the like is formed on the first support member 21. The second orientation flat 27 includes a notch formed on the periphery of the first support member 21. The second orientation flat 27 extends linearly on the periphery of the first support member 21.

[0045] The second orientation flat 27 of the first support member 21 may have the same crystal orientation as the first orientation flat 7 of the semiconductor wafer source 1. This allows the semiconductor wafer source 1 to be attached to the first support member 21 while knowing the crystal orientation.

[0046] The second orientation flat 27 of the first support member 21 may be aligned with the first orientation flat 7 of the semiconductor wafer source 1. That is, the second orientation flat 27 may extend parallel to and adjacent the first orientation flat 7.

[0047] As a result, the crystal orientation of the semiconductor wafer source 1 and the crystal orientation of the first support member 21 coincide with each other, so that the crystal orientation of the semiconductor wafer source 1 can be easily determined. This makes it possible to improve the convenience of handling the wafer bonding structure 101.

[0048] Fig. 2A is a process diagram for explaining the method for manufacturing a semiconductor device according to the first embodiment of the present invention. Fig. 2B is a process diagram for explaining a process performed on an element-formed wafer 41 (a new semiconductor wafer source 51, a wafer with elements formed thereon) obtained from the process shown in Fig. 2A.

[0049] Figures 3A to 3K are schematic cross-sectional views for explaining the manufacturing method shown in Figures 2A and 2B. For convenience of explanation, Figures 3A to 3K show a simplified structure of the semiconductor wafer source 1 and the first support member 21.

[0050] First, referring to Fig. 3A, a semiconductor wafer source 1 is prepared (step S1 in Fig. 2A). Also, a first support member 21 is prepared.

[0051] Next, referring to Fig. 3B, the semiconductor wafer source 1 is attached to the first support member 21 (step S2 in Fig. 2A). The semiconductor wafer source 1 is attached to the first support member 21 in a position in which the second main surface 3 faces the first support main surface 22 of the first support member 21. In this way, a wafer-attached structure 101 is formed.

[0052] The semiconductor wafer source 1 may be attached to the first support member 21 by an adhesive. If the semiconductor wafer source 1 and the first support member 21 are made of the same material type (SiC), the semiconductor wafer source 1 may be bonded to the first support member 21 by a direct wafer bonding method. The direct wafer bonding method may include a room temperature bonding method, a hydroxyl bonding method, or a plasma bonding method.

[0053] In the room temperature bonding method, first, the second main surface 3 of the semiconductor wafer source 1 and the first main supporting surface 22 of the first supporting member 21 are irradiated with an ion beam. As a result, atoms having bonds are formed on the second main surface 3 of the semiconductor wafer source 1 and the first main supporting surface 22 of the first supporting member 21. Thereafter, the second main surface 3 of the semiconductor wafer source 1 is attached to the first main supporting surface 22 of the first supporting member 21.

[0054] In the hydroxyl bonding method, first, a hydrophilic treatment is performed on the second main surface 3 of the semiconductor wafer source 1 and the first main supporting surface 22 of the first supporting member 21. An oxidizing chemical such as sulfuric acid or hydrogen peroxide may be used for the hydrophilic treatment. As a result, hydroxyl groups are introduced into the second main surface 3 of the semiconductor wafer source 1 and the first main supporting surface 22 of the first supporting member 21. Then, the second main surface 3 of the semiconductor wafer source 1 is attached to the first main supporting surface 22 of the first supporting member 21.

[0055] In the plasma bonding method, first, the second main surface 3 of the semiconductor wafer source 1 and the first main supporting surface 22 of the first supporting member 21 are each subjected to an oxygen plasma treatment. As a result, active regions are formed on the second main surface 3 of the semiconductor wafer source 1 and the first main supporting surface 22 of the first supporting member 21, respectively. The active regions may contain atoms having hydroxyl groups and / or bonds. Thereafter, the second main surface 3 of the semiconductor wafer source 1 is attached to the first main supporting surface 22 of the first supporting member 21.

[0056] In the direct wafer bonding method, a heat treatment step or a pressure application step for increasing the bonding strength between the semiconductor wafer source 1 and the first support member 21 may be carried out as necessary.

[0057] The wafer bonding structure 101 may include a bonding layer 28 that bonds the semiconductor wafer source 1 and the first support member 21 at an interface region between the semiconductor wafer source 1 and the first support member 21. When the semiconductor wafer source 1 and the first support member 21 are bonded by an adhesive, the bonding layer 28 may include the adhesive.

[0058] When the semiconductor wafer source 1 and the first support member 21 are attached by a wafer direct bonding method, the bonding layer 28 may include a semiconductor bonding layer. The semiconductor bonding layer may have a crystal state different from a crystal state of the semiconductor wafer source 1 and / or a crystal state of the first support member 21. The semiconductor bonding layer may include an amorphous layer. The amorphous layer may have a material of the semiconductor wafer source 1 and / or a material of the first support member 21.

[0059] Next, referring to FIG. 3C, semiconductor elements 11 are fabricated in each of the element formation regions 10 defined on the first main surface 2 of the semiconductor wafer source 1 (Step S3 in FIG. 2A).

[0060] The step of forming the semiconductor element 11 may include a step of polishing the first main surface 2 of the semiconductor wafer source 1. The step of forming the semiconductor element 11 may include a step of forming an epitaxial layer 29 on the first main surface 2 of the semiconductor wafer source 1.

[0061] The step of forming the semiconductor element 11 may include a step of selectively introducing n-type impurities and / or p-type impurities into the epitaxial layer 29 depending on the properties of the semiconductor element 11. The step of forming the semiconductor element 11 may include a step of forming a first main surface electrode 30 on the epitaxial layer 29.

[0062] In the polishing step, the first main surface 2 of the semiconductor wafer source 1 may be polished until the arithmetic mean roughness Ra becomes 1 nm or less. The polishing step may be performed by a CMP (Chemical Mechanical Polishing) method.

[0063] In the step of forming the epitaxial layer 29, SiC is epitaxially grown on the first main surface 2 of the semiconductor wafer source 1. After the polishing step, the epitaxial layer 29 can be appropriately formed on the first main surface 2 of the semiconductor wafer source 1. This allows the semiconductor element 11 to be appropriately fabricated on the first main surface 2 of the semiconductor wafer source 1.

[0064] In the step of forming the first principal surface electrodes 30, the first principal surface electrodes 30 electrically connected to the element formation regions 10 are formed in each of the element formation regions 10.

[0065] Next, referring to Fig. 3D, the second support member 31 is attached to the semiconductor wafer source 1 (step S4 in Fig. 2A). The wafer attachment structure 101 may be handled in a state in which the second support member 31 is attached.

[0066] The second support member 31 supports the semiconductor wafer source 1 from the first main surface 2 side of the semiconductor wafer source 1. The second support member 31 may be attached to the semiconductor wafer source 1 via a double-sided adhesive tape 32.

[0067] Various materials may be applied to the second support member 31 as long as they are capable of supporting the semiconductor wafer source 1. For example, a member having a structure similar to that of the first support member 21 may be adopted as the second support member 31. In this case, the description of the first support member 21 applies mutatis mutandis to the description of the second support member 31.

[0068] The second support member 31 may be a disk-shaped glass plate. The glass plate may have an outer shape similar to that of the first support member 21. The second support member 31 may be directly attached to the semiconductor wafer source 1 without using the tape 32. In this case, the second support member 31 may be a single-sided adhesive tape.

[0069] For convenience of handling, the planar area of ​​the second support member 31 may be set to be equal to or larger than the planar area of ​​the semiconductor wafer source 1. In this case, the wafer bonding structure 101 has a structure in which the semiconductor wafer source 1 is accommodated in the facing area where the first support member 21 and the second support member 31 face each other.

[0070] As a result, the semiconductor wafer source 1 can be appropriately protected from external forces by the first support member 21 and the second support member 31. Of course, the planar area of ​​the second support member 31 may be equal to or smaller than the planar area of ​​the semiconductor wafer source 1.

[0071] Next, referring to Fig. 3E, laser light is irradiated from laser light irradiating device 33 toward semiconductor wafer source 1 (step S5 in Fig. 2A). The laser light is irradiated toward semiconductor wafer source 1 in a state in which semiconductor wafer source 1 is supported by second support member 31. The laser light is irradiated toward semiconductor wafer source 1 from the second main surface 3 side of semiconductor wafer source 1 via first support member 21.

[0072] The focusing point (focus) of the laser light is set midway in the thickness direction of the semiconductor wafer source 1. The distance W1 from the first main surface 2 of the semiconductor wafer source 1 to the focusing point of the laser light is set according to the thickness of the semiconductor device to be obtained. The distance W1 may be 50 μm or more and 100 μm or less.

[0073] The irradiation position of the laser light on the semiconductor wafer source 1 is moved along a horizontal direction parallel to the first main surface 2 of the semiconductor wafer source 1. As a result, a first affected layer 34, whose crystalline state has been affected to have properties different from those of other regions, is formed in the middle of the semiconductor wafer source 1 in the thickness direction.

[0074] The first deteriorated layer 34 is formed along the horizontal direction at a midpoint in the thickness direction of the semiconductor wafer source 1. The first deteriorated layer 34 is a laser processing mark formed by irradiation with laser light. The first deteriorated layer 34 is also a layer whose density, refractive index, mechanical strength (crystal strength), or other physical properties are different from those of other regions due to deterioration.

[0075] The first affected layer 34 may include at least one of a melt-rehardened layer, a defect layer, a dielectric breakdown layer, and a refractive index change layer. The melt-rehardened layer is a layer that is rehardened after a part of the semiconductor wafer source 1 melts. The defect layer is a layer that includes voids, cracks, etc. The dielectric breakdown layer is a layer that is generated by dielectric breakdown. The refractive index change layer is a layer that has a refractive index different from other regions.

[0076] 3F, the semiconductor wafer source 1 is cut from the middle of the thickness direction of the semiconductor wafer source 1 along a horizontal direction parallel to the first main surface 2 (step S6 in FIG. 2A). More specifically, the semiconductor wafer source 1 is cleaved along the horizontal direction starting from the first affected layer 34. The cleavage of the semiconductor wafer source 1 is performed in a state in which the semiconductor wafer source 1 is supported (clamped) by the first support member 21 and the second support member 31.

[0077] As a result, the semiconductor wafer source 1 is separated into an element-formed wafer 41 having semiconductor elements 11, and an element-unformed wafer 42 not having semiconductor elements 11. The element-formed wafer 41 includes a first main surface 2 on one side and a first cut surface 43 on the other side. The element-formed wafer 41 has a thickness Ta. The element-unformed wafer 42 includes a second cut surface 44 on one side and a second main surface 3 on the other side. The element-unformed wafer 42 has a thickness Tb.

[0078] 3G, after the separation process of the semiconductor wafer source 1, the first cut surface 43 of the device formed wafer 41 is ground (step S11 in FIG. 2B). The grinding process of the first cut surface 43 may be performed by a CMP method.

[0079] The grinding step of the first cut surface 43 may be performed until the element formed wafer 41 has a desired thickness. In other words, the grinding step of the first cut surface 43 may include a step of thinning the element formed wafer 41.

[0080] After the grinding step of the first cut surface 43, the second principal surface electrode 45 is formed on the first cut surface 43 of the element formed wafer 41 (step S12 in FIG. 2B). Of course, the grinding step of the first cut surface 43 may be omitted. In other words, the second principal surface electrode 45 may be formed directly on the first cut surface 43 immediately after the separation step of the semiconductor wafer source 1.

[0081] Thereafter, the element-formed wafer 41 is cut along the dicing lines 12 (see also FIGS. 1A and 1B) (step S13 in FIG. 2B). As a result, a plurality of semiconductor devices are cut out from the element-formed wafer 41.

[0082] The cutting step of the element-formed wafer 41 may be performed in a state where the element-formed wafer 41 is supported by the second support member 31. In this case, the second support member 31 is removed after the cutting step of the element-formed wafer 41. The cutting step of the element-formed wafer 41 may be performed after the second support member 31 is removed.

[0083] After the separation process of the semiconductor wafer source 1, it is determined whether or not the device-free wafer 42 can be reused as a new semiconductor wafer source (step S7 in FIG. 2A).

[0084] The determination of whether the non-element-formed wafer 42 can be reused may be performed based on the thickness Ta of the element-formed wafer 41 and the thickness Tb of the non-element-formed wafer 42. When the thickness Tb of the non-element-formed wafer 42 is equal to or less than the thickness Ta of the element-formed wafer 41 (Tb≦Ta), it may be determined that the non-element-formed wafer 42 cannot be reused. The non-reusable condition is Tb <Taであってもよい。

[0085] The determination of whether the unformed-element wafer 42 can be reused may be performed based on the thickness Tch1 of the semiconductor device to be obtained from the unformed-element wafer 42. When the thickness Tch1 of the semiconductor device to be obtained is equal to or greater than the thickness Tb of the unformed-element wafer 42 (Tch1 ≧ Tb), it may be determined that reuse is not possible. The non-reusable condition may be Tch1 > Tb.

[0086] The non-reusable conditions for the unformed-element wafer 42 may include cases where, while the unformed-element wafer 42 has a sufficient thickness Tb (for example, Tch1 < Tb), circumstances where reuse is not possible occur.

[0087] When the unformed-element wafer 42 cannot be reused (step S7 in FIG. 2A: NO), the method for manufacturing a semiconductor device using one semiconductor wafer source 1 ends.

[0088] When the unformed-element wafer 42 cannot be reused, a step of removing the unformed-element wafer 42 from the first support member 21 may be performed. The non-reusable unformed-element wafer 42 may be removed by a polishing process. The polishing process may be performed by the CMP method. After the removal step, a step of reusing the first support member 21 as a support member for supporting another semiconductor wafer source may be performed.

[0089] Referring to FIG. 3H, when the unformed-element wafer 42 can be reused as a new semiconductor wafer source (step S7 in FIG. 2A: YES), a new semiconductor element 52 is formed on the unformed-element wafer 42 (step S8 in FIG. 2A).

[0090] Hereinafter, the unformed-element wafer 42 is referred to as the "new semiconductor wafer source 51". The second cut surface 44 of the new semiconductor wafer source 51 corresponds to the first main surface 2 of the semiconductor wafer source 1. The new semiconductor element 52 may be formed on the second cut surface 44 of the new semiconductor wafer source 51 in a state where the new semiconductor wafer source 51 is supported by the first support member 21.

[0091] The new semiconductor element 52 may be of the same type as or a different type from the above-mentioned semiconductor element 11. Fig. 3H shows an example in which the new semiconductor element 52 is of the same type as the semiconductor element 11. The new semiconductor elements 52 are fabricated in each of the multiple element formation regions 10 set on the second cut surface 44 of the new semiconductor source wafer 51.

[0092] The step of forming the new semiconductor device 52 may include a step of polishing the second cut surface 44 of the new semiconductor wafer source 51. The step of forming the new semiconductor device 52 may include a step of forming an epitaxial layer 29 on the second cut surface 44 of the new semiconductor wafer source 51.

[0093] The step of forming the new semiconductor element 52 may include a step of selectively introducing n-type impurities and / or p-type impurities into the epitaxial layer 29 depending on the properties of the new semiconductor element 52. The step of forming the new semiconductor element 52 may include a step of forming a first main surface electrode 30 on the epitaxial layer 29.

[0094] In the polishing step, the second cut surface 44 of the new semiconductor source wafer 51 may be polished until the arithmetic mean roughness Ra becomes 1 nm or less. The polishing step may be performed by a CMP method.

[0095] In the step of forming the epitaxial layer 29, SiC is epitaxially grown from the second cut surface 44 of the new semiconductor wafer source 51. After the polishing step, the epitaxial layer 29 can be appropriately formed on the second cut surface 44 of the new semiconductor wafer source 51. This allows a new semiconductor element 52 to be appropriately fabricated on the second cut surface 44 of the new semiconductor wafer source 51.

[0096] In the step of forming the first principal surface electrodes 30, the first principal surface electrodes 30 electrically connected to the element formation regions 10 are formed in each of the element formation regions 10.

[0097] Next, referring to Fig. 3I, the second support member 31 is attached to the new semiconductor wafer source 51 (step S4 in Fig. 2A). The second support member 31 supports the semiconductor wafer source 1 from the second cut surface 44 side of the new semiconductor wafer source 51. The second support member 31 may be attached to the semiconductor wafer source 1 via a double-sided adhesive tape 32.

[0098] Next, referring to Fig. 3J, laser light is irradiated from the laser light irradiating device 33 toward the new semiconductor wafer source 51 (step S5 in Fig. 2A). The laser light is irradiated toward the new semiconductor wafer source 51 while the new semiconductor wafer source 51 is supported by the second support member 31. The laser light is irradiated toward the new semiconductor wafer source 51 from the second main surface 3 side of the new semiconductor wafer source 51 via the first support member 21.

[0099] The focusing point (focus) of the laser light is set at a midpoint in the thickness direction of the new semiconductor wafer source 51. A distance W2 from the second cut surface 44 of the new semiconductor wafer source 51 to the focusing point of the laser light is set according to a thickness Tch1 of the semiconductor device to be obtained. The distance W2 may be 50 μm or more and 100 μm or less.

[0100] The irradiation position of the laser light on the new semiconductor wafer source 51 is moved along a horizontal direction parallel to the second cut surface 44 of the new semiconductor wafer source 51. As a result, a second affected layer 55, whose crystalline state has been affected to have properties different from those of the other regions, is formed in the middle of the new semiconductor wafer source 51 in the thickness direction.

[0101] The second damaged layer 55 is formed along the horizontal direction in the middle of the thickness direction of the new semiconductor wafer source 51. The second damaged layer 55 has a configuration substantially similar to the configuration of the above-mentioned first damaged layer 34. A detailed description of the second damaged layer 55 will be omitted.

[0102] Next, referring to FIG. 3K, the new semiconductor wafer source 51 is cut from the middle of the thickness direction of the new semiconductor wafer source 51 along a horizontal direction parallel to the second cut surface 44 (Step S6 in FIG. 2A).

[0103] More specifically, the new semiconductor wafer source 51 is cleaved in a horizontal direction starting from the second affected layer 55. The cleavage of the new semiconductor wafer source 51 is performed in a state in which the new semiconductor wafer source 51 is supported (sandwiched) by the first support member 21 and the second support member 31.

[0104] This separates the new semiconductor wafer source 51 into a second element-formed wafer 61 (element-formed wafer) on which new semiconductor elements 52 are formed, and a second element-unformed wafer 62 on which new semiconductor elements 52 are not formed.

[0105] The second element-formed wafer 61 includes a second cut surface 44 on one side and a third cut surface 63 on the other side. The second element-formed wafer 61 has a thickness Tc. The second element-unformed wafer 62 includes a fourth cut surface 64 on one side and a second main surface 3 on the other side. The second element-unformed wafer 62 has a thickness Td.

[0106] After the separation process of the new semiconductor wafer source 51, the third cut surface 63 of the second device formed wafer 61 is ground (step S11 in FIG. 2B). The grinding process of the third cut surface 63 may be performed by a CMP method.

[0107] The grinding step of the third cut surface 63 may be performed until the second element formed wafer 61 has a desired thickness. In other words, the grinding step of the third cut surface 63 may include a step of thinning the second element formed wafer 61.

[0108] After the grinding step of the third cut surface 63, the second principal surface electrode 45 is formed on the third cut surface 63 of the second element formed wafer 61 (step S12 in FIG. 2B). Of course, the grinding step of the third cut surface 63 may be omitted. In other words, the second principal surface electrode 45 may be formed directly on the third cut surface 63 immediately after the separation step of the new semiconductor wafer source 51.

[0109] Thereafter, the second element formation wafer 61 is cut along the dicing line 12 (see also FIGS. 1A and 1B) (step S13 in FIG. 2B). As a result, a plurality of semiconductor devices are cut out from the second element formation wafer 61.

[0110] The cutting process of the second element formation wafer 61 may be performed while being supported by the second support member 31. In this case, after the cutting process of the second element formation wafer 61, the second support member 31 is removed. The cutting process of the second element formation wafer 61 may be performed after the second support member 31 is removed.

[0111] After the separation process of the new semiconductor wafer source 51, it is determined whether the second element-unformed wafer 62 can be reused as a new semiconductor wafer source (step S7 in FIG. 2A).

[0112] The determination of whether the second element-unformed wafer 62 can be reused may be performed based on the thickness Tc of the second element formation wafer 61 and the thickness Td of the second element-unformed wafer 62. When the thickness Td of the second element-unformed wafer 62 is less than or equal to the thickness Tc of the second element formation wafer 61 (Td ≦ Tc), it may be determined that it cannot be reused. The non-reusable condition may also be Td < Tc.

[0113] The determination of whether the second element-unformed wafer 62 can be reused may be performed based on the thickness Tch2 of the semiconductor device to be obtained from the second element-unformed wafer 62. When the thickness Tch2 of the semiconductor device to be obtained is greater than or equal to the thickness Td of the second element-unformed wafer 62 (Tch2 ≧ Td), it may be determined that it cannot be reused. The non-reusable condition may also be Tch2 > Td.

[0114] The non-reusable conditions for the second element-unformed wafer 62 may include a case where the second element-unformed wafer 62 has a sufficient thickness Td (for example, Tch2 < Td), but a non-reusable situation occurs.

[0115] If the second device-free wafer 62 cannot be reused as a new semiconductor wafer source (step S7 in FIG. 2A: NO), the method for manufacturing a semiconductor device using one semiconductor wafer source 1 is completed.

[0116] If the second wafer 62 without elements formed thereon is not reusable, a step of removing the second wafer 62 without elements formed thereon from the first support member 21 may be performed. The second wafer 62 without elements formed thereon that is not reusable may be removed by a polishing step. The polishing step may be performed by a CMP method. After the removing step, a step of reusing the first support member 21 as a support member for supporting another semiconductor wafer source may be performed.

[0117] If the second non-device-formed wafer 62 is reusable as a new semiconductor wafer source (step S7 in FIG. 2A: YES), step S8 is performed. Thus, in this embodiment, steps S4 to S7 are repeated until the non-device-formed wafer becomes unreusable as a new semiconductor wafer source.

[0118] As described above, in this embodiment, after the step of forming the semiconductor element 11 (step S3 in FIG. 2A), the step of separating the semiconductor wafer source 1 (steps S5 and S6 in FIG. 2A) is performed. The step of separating the semiconductor wafer source 1 is performed on the wafer bonding structure 101 in which the semiconductor wafer source 1 is bonded to the first support member 21.

[0119] The semiconductor wafer source 1 is separated by cleavage into an element-formed wafer 41 and an element-unformed wafer 42. In this case, the element-unformed wafer 42 is in a state of being adhered to the first support member 21. Therefore, a plurality of semiconductor devices can be cut out from the element-formed wafer 41, while the element-unformed wafer 42 supported by the first support member 21 can be reused as a new semiconductor wafer source 51.

[0120] This makes it possible to suppress delays in the manufacturing process and at the same time suppress excessive consumption of the semiconductor wafer source 1. Therefore, it is possible to provide the wafer bonding structure 101 that can efficiently consume the semiconductor wafer source 1.

[0121] In this embodiment, new semiconductor elements 52 are fabricated in the new reused semiconductor wafer source 51 (step S8 in FIG. 2A). In this embodiment, a wafer source reuse repeat process (steps S5 to S7 in FIG. 2A) is performed in which a separation process of the semiconductor wafer source 1 and a reuse process of the semiconductor wafer source 1 are alternately repeated. This makes it possible to increase the number of semiconductor devices that can be obtained from one semiconductor wafer source 1.

[0122] In this embodiment, a cleavage process of the semiconductor wafer source 1 using a laser light irradiation method is performed in the separation process of the semiconductor wafer source 1 (steps S5 and S6 in FIG. 2A). This eliminates the need to adjust the thickness of the semiconductor device by grinding the semiconductor wafer source 1. This makes it possible to suppress an increase in costs due to grinding.

[0123] In particular, the laser light irradiation method can be applied to the semiconductor wafer source 1 made of a relatively hard SiC single crystal. Also, the semiconductor wafer source 1 made of a SiC single crystal can be appropriately separated into the device formed wafer 41 and the device unformed wafer .

[0124] Moreover, the laser light irradiation method has an advantage in that even if the initial device-free wafer 42 cannot be reused (step S7 in FIG. 2A: NO), the increase in cost due to grinding can be suppressed. The laser light irradiation method is particularly useful for the semiconductor wafer source 1 made of SiC single crystal, which has a relatively high hardness.

[0125] In this embodiment, in the separation process of the semiconductor wafer source 1 (steps S5 and S6 in FIG. 2A), a laser beam is irradiated onto a middle portion of the semiconductor wafer source 1 in the thickness direction from the second main surface 3 side of the semiconductor wafer source 1.

[0126] No semiconductor element 11 is formed on the second main surface 3 of the semiconductor wafer source 1. Therefore, the laser light can be irradiated toward the inside of the semiconductor wafer source 1 from the second main surface 3 side of the semiconductor wafer source 1 where there are fewer obstacles. This allows the first affected layer 34 and the second affected layer 55 to be properly formed in the semiconductor wafer source 1, and therefore the semiconductor wafer source 1 can be properly separated (cleaved).

[0127] When the second wafer edge 6 of the semiconductor wafer source 1 has a chamfered portion, a gap is formed in the region between the second wafer edge 6 of the semiconductor wafer source 1 and the first main support surface 22 of the first support member 21. Errors occurring in the focused portion (focus) of the laser light include those caused by this gap.

[0128] Therefore, in this embodiment, the second wafer edge 6 that does not have a chamfered portion is formed in the semiconductor wafer source 1. This makes it possible to suppress the formation of a gap in the region between the second wafer edge 6 of the semiconductor wafer source 1 and the first main supporting surface 22 of the first supporting member 21.

[0129] This makes it possible to suppress errors in the focused portion (focus) of the laser light, thereby enabling the first deteriorated layer 34 to be properly formed inside the semiconductor wafer source 1. As a result, the semiconductor wafer source 1 can be properly separated (cleaved) into the element-formed wafer 41 and the element-unformed wafer 42.

[0130] Moreover, since it is possible to suppress the occurrence of an error in the focusing portion (focus) of the laser light, it is possible to properly form the second deteriorated layer 55 inside the new semiconductor wafer source 51. As a result, it is possible to properly separate (cleave) the new semiconductor wafer source 51 into the second element-formed wafer 61 and the second element-unformed wafer 62.

[0131] When the first support member 21 is made of a single crystal semiconductor wafer or the like with no or low impurity concentration, absorption (attenuation) of the laser light can be suppressed. Therefore, by devising the material of the first support member 21, the quality of the first affected layer 34 formed on the semiconductor wafer source 1 and the quality of the second affected layer 55 formed on the new semiconductor wafer source 51 can be improved.

[0132] In this embodiment, the melting point of the first support member 21 is equal to or higher than the melting point of the semiconductor wafer source 1. This makes it possible to prevent the first support member 21 from melting or deforming during the manufacturing process.

[0133] In this embodiment, the ratio of the thermal expansion coefficient of the support member to the thermal expansion coefficient of the semiconductor wafer source 1 is 0.5 or more and 1.5 or less. This reduces the stress difference between the thermal stress generated on the semiconductor wafer source 1 (new semiconductor wafer source 51) side and the thermal stress generated on the first support member 21 side during the manufacturing process. This makes it possible to suppress warping of the semiconductor wafer source 1 (new semiconductor wafer source 51).

[0134] When the first support member 21 is made of the same material (SiC) as the semiconductor wafer source 1, the melting point and thermal expansion coefficient are almost the same, so that warping of the semiconductor wafer source 1 (new semiconductor wafer source 51) can be reliably suppressed. Also, melting and deformation of the first support member 21 can be reliably suppressed.

[0135] 4 is a process diagram for explaining the method for manufacturing a semiconductor device according to the second embodiment of the present invention. In the following, explanations of steps corresponding to the steps described in the first embodiment will be omitted.

[0136] In this embodiment, steps S21 and S22 are performed instead of steps S1 to S3 (see FIG. 2A) in the first embodiment. More specifically, first, a semiconductor wafer source 1 having semiconductor elements 11 formed in each of a plurality of element formation regions 10 is prepared (step S21 in FIG. 4).

[0137] Next, the semiconductor wafer 1 on which the semiconductor elements 11 are formed is attached to the first support member 21 (step S22 in FIG. 4). This forms the wafer-attached structure 101. Thereafter, steps S4 to S8 are carried out.

[0138] As described above, in this embodiment, the semiconductor elements 11 are formed on the semiconductor wafer source 1 (step S21 in FIG. 4) prior to the step of attaching the semiconductor wafer source 1 to the first support member 21 (step S22 in FIG. 4). With this manufacturing method as well, it is possible to achieve the same effects as those described in the first embodiment.

[0139] 5 is a process diagram for explaining the method for manufacturing a semiconductor device according to the third embodiment of the present invention. In the following, explanations of steps corresponding to the steps described in the first embodiment will be omitted.

[0140] In this embodiment, step S31 is performed instead of steps S1 to S3 (see FIG. 2A) in the first embodiment. More specifically, first, a wafer bonding structure 101 is prepared (step S31). The preparation process of the wafer bonding structure 101 may include a process of acquiring a wafer bonding structure 101 available on the market.

[0141] The wafer-bonded structure 101 may be manufactured through the same steps as steps S1 to S3 in the first embodiment (see also FIG. 2A). Then, steps S4 to S8 are performed. This manufacturing method can also achieve the same effects as those described in the first embodiment.

[0142] Fig. 6A is a process diagram for explaining a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention. Fig. 6B is a process diagram for explaining a process performed on an element-formed wafer 41 (a new semiconductor wafer source 51) obtained from the process shown in Fig. 6A.

[0143] Figures 7A to 7G are schematic cross-sectional views for explaining the manufacturing method shown in Figures 6A and 6B. In the following, explanations of steps corresponding to those described in the first embodiment will be omitted.

[0144] In this embodiment, step S41 is performed instead of steps S1 to S3 (see FIG. 2A) in the first embodiment. Also, in this embodiment, step S42 is performed after step S5 in the first embodiment and before step S6. Also, in this embodiment, step S43 is performed after step S8.

[0145] More specifically, referring to Fig. 7A, a semiconductor wafer source 1 having a semiconductor element 11 formed on a first main surface 2 is prepared (step S41 in Fig. 6A). In this embodiment, a second main surface 3 of the semiconductor wafer source 1 is exposed to the outside. That is, a second main surface electrode 45 is not formed on the second main surface 3 of the semiconductor wafer source 1.

[0146] 7B, the second support member 31 is attached to the first main surface 2 side of the semiconductor wafer source 1 (step S4 in FIG. 6A). The second support member 31 may be attached to the semiconductor wafer source 1 via a double-sided adhesive tape 32.

[0147] 7C, laser light is emitted from laser light irradiation device 33 toward semiconductor wafer source 1 (step S5 in FIG. 6A). The laser light is emitted toward second main surface 3 of semiconductor wafer source 1 in a state where semiconductor wafer source 1 is supported by second support member 31.

[0148] In this embodiment, the laser light is directly irradiated from the second main surface 3 side of the semiconductor wafer source 1 to the middle part in the thickness direction of the semiconductor wafer source 1. The distance W1 from the first main surface 2 of the semiconductor wafer source 1 to the focusing part of the laser light is set according to the thickness of the semiconductor device to be obtained. The distance W1 may be 50 μm or more and 100 μm or less.

[0149] The position of the laser beam irradiated on the semiconductor wafer source 1 is moved along a horizontal direction parallel to the first main surface 2 of the semiconductor wafer source 1. As a result, a first affected layer 34, whose crystalline state has been affected to a different property from that of other regions, is formed in the middle of the thickness direction of the semiconductor wafer source 1. +In the case of a SiC semiconductor substrate of the type mentioned above, the first affected layer 34 may be formed in the middle of the SiC semiconductor substrate.

[0150] If the semiconductor wafer source 1 has a chamfered portion at its edge, an error occurs in the focused portion (focus) of the laser light, and there is a risk that the first affected layer 34 will not be formed parallel to the first main surface 2. Therefore, in this embodiment, a semiconductor wafer source 1 including a second wafer edge 6 that is not chamfered is prepared.

[0151] This makes it possible to suppress errors in the focusing portion (focus) of the laser light. As a result, the first deteriorated layer 34 can be formed inside the semiconductor wafer source 1 across the entire thickness direction of the semiconductor wafer source 1, parallel to the first main surface 2. This makes it possible to properly separate (cleave) the semiconductor wafer source 1 into an element-formed wafer 41 and an element-unformed wafer 42.

[0152] Next, referring to Fig. 7D, the semiconductor wafer source 1 having the first deteriorated layer 34 is attached to the first support member 21 (step S42 in Fig. 6A). The semiconductor wafer source 1 is attached to the first support member 21 in a position in which the second main surface 3 faces the first support main surface 22 of the first support member 21. In this way, a wafer-attached structure 101 is formed. The method of attaching the semiconductor wafer source 1 to the first support member 21 is the same as that described in the first embodiment, and therefore the description will be omitted.

[0153] 7E, the semiconductor wafer source 1 is cut from the middle of the thickness direction of the semiconductor wafer source 1 along a horizontal direction parallel to the first main surface 2 (Step S6 in FIG. 6A). More specifically, the semiconductor wafer source 1 is cleaved along the horizontal direction starting from the first deteriorated layer 34.

[0154] The cleavage of the semiconductor wafer source 1 is performed in a state in which the semiconductor wafer source 1 is supported (clamped) by the first support member 21 and the second support member 31. As a result, the semiconductor wafer source 1 is separated into an element-formed wafer 41 having semiconductor elements 11 and an element-unformed wafer 42 not having the semiconductor elements 11.

[0155] In the cutting step of the semiconductor wafer source 1 (step S6 in FIG. 6A), the semiconductor wafer source 1 may be separated into an element-formed wafer 41 having semiconductor elements 11 and an element-unformed wafer 42 not having semiconductor elements 11. In addition to the above-described cleavage, the semiconductor wafer source 1 may be spontaneously separated into the element-formed wafer 41 and the element-unformed wafer 42 by adjusting, for example, the formation position and formation conditions of the first affected layer 34.

[0156] 7F, after the separation process of the semiconductor wafer source 1, the first cut surface 43 of the element formed wafer 41 is ground (Step S44 in FIG. 6B). The grinding process of the first cut surface 43 may be performed by a CMP method.

[0157] The grinding step of the first cut surface 43 may be performed until the element formed wafer 41 has a desired thickness. In other words, the grinding step of the first cut surface 43 may include a step of thinning the element formed wafer 41.

[0158] Next, referring to Fig. 7G, second principal surface electrodes 45 are formed on the first cut surface 43 of the element formed wafer 41 (step S45 in Fig. 6B). Of course, the grinding step of the first cut surface 43 may be omitted. In other words, the second principal surface electrodes 45 may be formed directly on the first cut surface 43 immediately after the separation step of the semiconductor wafer source 1.

[0159] After the grinding step of the element formed wafer 41 (step S44 in FIG. 6B) and prior to the forming step of the second principal surface electrode 45 (step S45 in FIG. 6B), an annealing treatment may be performed on the first cut surface 43 (ground surface) of the element formed wafer 41. The annealing treatment may be performed by a laser light irradiation method. In this case, the ohmic property of the second principal surface electrode 45 with respect to the first cut surface 43 of the element formed wafer 41 can be improved.

[0160] Thereafter, the element-formed wafer 41 is cut along the dicing lines 12 (see also FIGS. 1A and 1B) (step S46 in FIG. 6B). As a result, a plurality of semiconductor devices are cut out from the element-formed wafer 41.

[0161] The cutting step of the element-formed wafer 41 may be performed in a state where the element-formed wafer 41 is supported by the second support member 31. In this case, the second support member 31 is removed after the cutting step of the element-formed wafer 41. The cutting step of the element-formed wafer 41 may be performed after the second support member 31 is removed.

[0162] After the separation process of the semiconductor wafer source 1, it is determined whether or not the non-device-formed wafer 42 can be reused as a new semiconductor wafer source 51 (step S7 in FIG. 6A). The method of determining whether or not the non-device-formed wafer 42 can be reused is the same as that described in the first embodiment, and therefore the description thereof will be omitted.

[0163] If the device-free wafer 42 cannot be reused (step S7 in FIG. 6A: NO), the method for manufacturing a semiconductor device using one semiconductor wafer source 1 is completed.

[0164] If the device-free wafer 42 can be reused as a new semiconductor wafer source 51 (step S7 in FIG. 6A: YES), new semiconductor devices 52 are formed on the device-free wafer 42 (step S8 in FIG. 6A).

[0165] Next, the first support member 21 is removed from the new semiconductor wafer source 51 (step S43 in FIG. 6A). This causes the second main surface 3 of the new semiconductor wafer source 51 to be exposed to the outside. If the bonding layer 28 is attached to the second main surface 3 of the new semiconductor wafer source 51, the bonding layer 28 is removed from the semiconductor wafer source 51.

[0166] The first support member 21 may be removed by a polishing process. The polishing process may be performed by a CMP method. The first support member 21 may be removed by an etching method. The first support member 21 may be removed by peeling. If the first support member 21 is reusable, the first support member 21 may be utilized as a support member for supporting another semiconductor wafer source. Then, step S4 is performed.

[0167] Then, similarly to the first embodiment, steps S4 to S7 are repeated until the element-free wafer becomes unreusable as a new semiconductor wafer source. This manufacturing method also has the same effects as those described in the first embodiment.

[0168] In this embodiment, an example has been described in which the step of removing first supporting member 21 (step S43 in FIG. 6A) is performed after the step of forming new semiconductor elements 52 (step S8 in FIG. 6A). However, the step of removing first supporting member 21 (step S43 in FIG. 6A) may be performed before the step of forming new semiconductor elements 52 (step S8 in FIG. 6A) after determining whether or not element-free wafer 42 can be reused (step S7 in FIG. 6A).

[0169] Fig. 8A is a process diagram for explaining a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention. Fig. 8B is a process diagram for explaining a process performed on an element-formed wafer 41 (a new semiconductor wafer source 51) obtained from the process shown in Fig. 8A.

[0170] Figures 9A to 9M are schematic cross-sectional views for explaining the manufacturing method shown in Figures 8A and 8B. In the following, explanations of steps corresponding to those described in the first embodiment will be omitted.

[0171] In this embodiment, step S51 is performed instead of steps S1 to S3 (see FIG. 2A) according to the first embodiment. Also, in this embodiment, step S52 is performed after step S5 according to the first embodiment and before step S6. Furthermore, in this embodiment, steps S53 to S56 or steps S53, S57, and S58 are performed after step S7 according to the first embodiment.

[0172] More specifically, referring to FIG. 9A, a semiconductor wafer source 1 having semiconductor elements 11 formed on a first main surface 2 is prepared (Step S51 in FIG. 8A).

[0173] 9B, the second support member 31 is attached to the first main surface 2 side of the semiconductor wafer source 1 (step S4 in FIG. 8A). The second support member 31 may be attached to the semiconductor wafer source 1 via a double-sided adhesive tape 32.

[0174] 9C, laser light is emitted from laser light irradiation device 33 toward semiconductor wafer source 1 (step S5 in FIG. 8A). The laser light is emitted toward second main surface 3 of semiconductor wafer source 1 in a state where semiconductor wafer source 1 is supported by second support member 31.

[0175] In this embodiment, the laser light is directly irradiated from the second main surface 3 side of the semiconductor wafer source 1 to the middle part in the thickness direction of the semiconductor wafer source 1. The distance W1 from the first main surface 2 of the semiconductor wafer source 1 to the focusing part of the laser light is set according to the thickness of the semiconductor device to be obtained. The distance W1 may be 50 μm or more and 100 μm or less.

[0176] The position of the laser beam irradiated on the semiconductor wafer source 1 is moved along a horizontal direction parallel to the first main surface 2 of the semiconductor wafer source 1. As a result, a first affected layer 34, whose crystalline state has been affected to a different property from that of other regions, is formed in the middle of the thickness direction of the semiconductor wafer source 1. + In the case of a SiC semiconductor substrate of the type mentioned above, the first affected layer 34 may be formed in the middle of the SiC semiconductor substrate.

[0177] If the semiconductor wafer source 1 has a chamfered portion at its edge, an error occurs in the focused portion (focus) of the laser light, and there is a risk that the first affected layer 34 will not be formed parallel to the first main surface 2. Therefore, in this embodiment, a semiconductor wafer source 1 including a second wafer edge 6 that is not chamfered is prepared.

[0178] This makes it possible to suppress errors in the focusing portion (focus) of the laser light. As a result, the first deteriorated layer 34 can be formed inside the semiconductor wafer source 1 across the entire thickness direction of the semiconductor wafer source 1, parallel to the first main surface 2. This makes it possible to properly separate (cleave) the semiconductor wafer source 1 into an element-formed wafer 41 and an element-unformed wafer 42.

[0179] Next, referring to Fig. 9D, the semiconductor wafer source 1 having the first deteriorated layer 34 is attached to the first support member 21 (step S52 in Fig. 8A). The semiconductor wafer source 1 is attached to the first support member 21 in a position in which the second main surface 3 faces the first support main surface 22 of the first support member 21. In this way, a wafer-attached structure 101 is formed. The method of attaching the semiconductor wafer source 1 to the first support member 21 is the same as that described in the first embodiment, and therefore the description will be omitted.

[0180] 9E, the semiconductor wafer source 1 is cut from the middle of the thickness direction of the semiconductor wafer source 1 along a horizontal direction parallel to the first main surface 2 (Step S6 in FIG. 8A). More specifically, the semiconductor wafer source 1 is cleaved along the horizontal direction starting from the first deteriorated layer 34.

[0181] The cleavage of the semiconductor wafer source 1 is performed in a state in which the semiconductor wafer source 1 is supported (clamped) by the first support member 21 and the second support member 31. As a result, the semiconductor wafer source 1 is separated into an element-formed wafer 41 having semiconductor elements 11 and an element-unformed wafer 42 not having the semiconductor elements 11.

[0182] In the cutting step of the semiconductor wafer source 1 (step S6 in FIG. 6A), the semiconductor wafer source 1 may be separated into an element-formed wafer 41 having semiconductor elements 11 and an element-unformed wafer 42 not having semiconductor elements 11. In addition to the above-described cleavage, the semiconductor wafer source 1 may be spontaneously separated into the element-formed wafer 41 and the element-unformed wafer 42 by adjusting, for example, the formation position and formation conditions of the first affected layer 34.

[0183] 9F, after the separation process of the semiconductor wafer source 1, the first cut surface 43 of the element formed wafer 41 is ground (Step S59 in FIG. 8B). The grinding process of the first cut surface 43 may be performed by a CMP method.

[0184] The grinding step of the first cut surface 43 may be performed until the element formed wafer 41 has a desired thickness. In other words, the grinding step of the first cut surface 43 may include a step of thinning the element formed wafer 41.

[0185] Next, referring to Fig. 9G, second principal surface electrodes 45 are formed on the first cut surface 43 of the element formed wafer 41 (step S60 in Fig. 8B). Of course, the grinding step of the first cut surface 43 may be omitted. In other words, the second principal surface electrodes 45 may be formed directly on the first cut surface 43 immediately after the separation step of the semiconductor wafer source 1.

[0186] After the grinding step of the element formed wafer 41 (step S44 in FIG. 6B) and prior to the forming step of the second principal surface electrode 45 (step S45 in FIG. 6B), an annealing treatment may be performed on the first cut surface 43 (ground surface) of the element formed wafer 41. The annealing treatment may be performed by a laser light irradiation method. In this case, the ohmic property of the second principal surface electrode 45 with respect to the first cut surface 43 of the element formed wafer 41 can be improved.

[0187] Thereafter, the element-formed wafer 41 is cut along the dicing lines 12 (see also FIGS. 1A and 1B) (step S61 in FIG. 8B). As a result, a plurality of semiconductor devices are cut out from the element-formed wafer 41.

[0188] The cutting step of the element-formed wafer 41 may be performed in a state where the element-formed wafer 41 is supported by the second support member 31. In this case, the second support member 31 is removed after the cutting step of the element-formed wafer 41. The cutting step of the element-formed wafer 41 may be performed after the second support member 31 is removed.

[0189] After the separation process of the semiconductor wafer source 1, it is determined whether or not the non-device-formed wafer 42 can be reused as a new semiconductor wafer source 51 (step S7 in FIG. 8A). If the non-device-formed wafer 42 cannot be reused (step S7 in FIG. 8A: NO), the method for manufacturing a semiconductor device using one semiconductor wafer source 1 is completed. The method for determining whether or not the non-device-formed wafer 42 can be reused is the same as that described in the first embodiment, and therefore will not be described here.

[0190] If the unformed wafer 42 can be reused as a new semiconductor wafer source 51 (step S7 in FIG. 8A: YES), it is determined whether the unformed wafer 42 cannot be divided again and will be the last semiconductor wafer source (step S53 in FIG. 8A). The determination of whether the unformed wafer 42 can be divided again may be made based on the thickness of the semiconductor device to be obtained.

[0191] The wafer 42 without elements formed thereon may be determined to be the last semiconductor wafer source if it is indivisible and has a thickness that can be adjusted to the thickness of the semiconductor device by grinding for a short time. Also, the wafer 42 without elements formed thereon may be determined to be the last semiconductor wafer source if it is indivisible and has a thickness approximately equal to the thickness of the semiconductor device to be obtained.

[0192] 9H, when the non-device-formed wafer 42 cannot be divided and is to be the last semiconductor wafer source (step S53 in FIG. 8A: YES), the non-device-formed wafer 42 is reused as the last semiconductor wafer source 81.

[0193] Then, the first support member 21 is removed from the last semiconductor wafer source 81 (step S54 in FIG. 8A), whereby the second main surface 3 of the last semiconductor wafer source 81 is exposed to the outside.

[0194] The first support member 21 may be removed by a polishing process. The polishing process may be performed by a CMP method. The first support member 21 may be removed by an etching method. The first support member 21 may be removed by peeling. If the first support member 21 is reusable, the first support member 21 may be utilized as a support member for supporting another semiconductor wafer source.

[0195] Next, referring to FIG. 9I, in the case where the bonding layer 28 is attached to the second main surface 3 of the last semiconductor wafer source 81, the bonding layer 28 is removed from the last semiconductor wafer source 81.

[0196] Next, referring to Fig. 9J, a new semiconductor element 52 is formed on the second cut surface 44 of the final semiconductor wafer source 81 (step S55 in Fig. 8A). The new semiconductor element 52 may be of the same type as the semiconductor element 11 described above or of a different type.

[0197] 9J shows an example in which the new semiconductor element 52 is the same type as the semiconductor element 11. The new semiconductor elements 52 are fabricated in each of the element formation regions 10 set on the second cut surface 44 of the last semiconductor wafer source 81. The process of forming the new semiconductor elements 52 is the same as that described in the first embodiment, and therefore will not be described here. Then, a second principal surface electrode 45 is formed on the second principal surface 3 of the last semiconductor wafer source 81.

[0198] Prior to the step of forming the second principal surface electrode 45, an annealing treatment may be performed on the second principal surface 3 (ground surface) of the final semiconductor wafer source 81. The annealing treatment may be performed by a laser light irradiation method. In this case, the ohmic property of the second principal surface electrode 45 with respect to the second principal surface 3 of the final semiconductor wafer source 81 can be improved.

[0199] Thereafter, the last semiconductor wafer source 81 is cut along the dicing lines 12 (see also FIGS. 1A and 1B) (step S13 in FIG. 2B). As a result, a plurality of semiconductor devices are cut out from the last semiconductor wafer source 81.

[0200] On the other hand, referring to FIG. 9K, if the non-device-formed wafer 42 can be divided again and will not become the final semiconductor wafer source (step S53 in FIG. 8A: NO), the non-device-formed wafer 42 is reused as a new semiconductor wafer source 51.

[0201] Then, the first support member 21 is removed from the new semiconductor wafer source 51 (step S57 in FIG. 8A), whereby the second main surface 3 of the new semiconductor wafer source 51 is exposed to the outside.

[0202] The first support member 21 may be removed by a polishing process. The polishing process may be performed by a CMP method. The first support member 21 may be removed by an etching method. The first support member 21 may be removed by peeling. If the first support member 21 is reusable, the first support member 21 may be utilized as a support member for supporting another semiconductor wafer source.

[0203] Next, referring to FIG. 9L, if the bonding layer 28 is attached to the second main surface 3 of the new semiconductor wafer source 51, the bonding layer 28 is removed from the new semiconductor wafer source 51.

[0204] Next, referring to FIG. 9M, a new semiconductor element 52 is formed on the second cut surface 44 of the new semiconductor wafer source 51 (step S58 in FIG. 8A). The new semiconductor element 52 may be of the same type as the aforementioned semiconductor element 11 or of a different type.

[0205] 9M shows an example in which the new semiconductor elements 52 are the same type as the semiconductor elements 11. The new semiconductor elements 52 are fabricated in each of a plurality of element formation regions 10 set on the second cut surface 44 of the new semiconductor wafer source 51. The process of forming the new semiconductor elements 52 is the same as that described in the first embodiment, and therefore will not be described here.

[0206] In this manner, in this embodiment, steps S4 to S7 are repeated until the non-device-formed wafer becomes unusable as a new semiconductor wafer source. Also, in this embodiment, steps S4 to S53 are repeated until the non-device-formed wafer becomes the last semiconductor wafer source.

[0207] This manufacturing method can also achieve the same effects as those described in the first embodiment. In particular, in this embodiment, the element-free wafer 42 can be reused as the final semiconductor wafer source 81 (steps S53 to S56). This allows the initial semiconductor wafer source 1 to be consumed without waste.

[0208] In this step, an example has been described in which the step of forming new semiconductor elements 52 for the final semiconductor wafer source 81 (step S55 in FIG. 8A) is performed after the step of removing first support member 21 (step S54 in FIG. 8A). However, the step of forming new semiconductor elements 52 (step S55 in FIG. 8A) may be performed prior to the step of removing first support member 21 (step S54 in FIG. 8A).

[0209] In this step, an example has been described in which the step of forming new semiconductor elements 52 on the new semiconductor wafer source 51 (step S58 in FIG. 8A) is performed after the step of removing the first support member 21 (step S57 in FIG. 8A). However, the step of forming new semiconductor elements 52 (step S58 in FIG. 8A) may be performed prior to the step of removing the first support member 21 (step S57 in FIG. 8A).

[0210] FIG. 10 is a cross-sectional view showing a semiconductor device 111 according to an embodiment of the present invention.

[0211] 10, the semiconductor device 111 includes a Schottky barrier diode as an example of the semiconductor element 11. The semiconductor device 111 includes a chip-shaped SiC semiconductor layer 112. The SiC semiconductor layer 112 has a first main surface 113 on one side, a second main surface 114 on the other side, and a side surface 115 connecting the first main surface 113 and the second main surface 114.

[0212] In this embodiment, the SiC semiconductor layer 112 is + The SiC epitaxial layer 117 has an n-type impurity concentration lower than that of the SiC semiconductor substrate 116.

[0213] The SiC semiconductor substrate 116 forms a second main surface 114 of the SiC semiconductor layer 112. The SiC epitaxial layer 117 forms a first main surface 113 of the SiC semiconductor layer 112. The SiC semiconductor substrate 116 and the SiC epitaxial layer 117 form a side surface 115 of the SiC semiconductor layer 112.

[0214] An n-type diode region 118 is formed in a surface layer portion of first main surface 113 of SiC semiconductor layer 112. In this embodiment, diode region 118 is formed in a central portion of first main surface 113 of SiC semiconductor layer 112 in a plan view seen from the normal direction of first main surface 113 of SiC semiconductor layer 112 (hereinafter simply referred to as "plan view"). In this embodiment, diode region 118 is formed by utilizing a part of SiC epitaxial layer 117.

[0215] The surface layer portion of the first main surface 113 of the SiC semiconductor layer 112 is + A guard region 119 of a mold is formed. Guard region 119 is formed in a band shape extending along diode region 118 in plan view. More specifically, guard region 119 is formed in an endless shape (for example, a square ring shape, a square ring shape with chamfered corners, or a circular ring shape) surrounding diode region 118 in plan view. Thus, guard region 119 is formed as a guard ring region.

[0216] The p-type impurity in guard region 119 does not have to be activated. In this case, guard region 119 is formed as a non-semiconductor region. The p-type impurity in guard region 119 may be activated. In this case, guard region 119 is formed as a p-type semiconductor region.

[0217] An insulating layer 120 is formed on the first main surface 113 of the SiC semiconductor layer 112. An opening 121 that exposes the diode region 118 is formed in the insulating layer 120. In this embodiment, the inner periphery of the guard region 119 is also exposed from the opening 121 in addition to the diode region 118.

[0218] A first principal surface electrode 30 is formed on the insulating layer 120. The first principal surface electrode 30 extends into the opening 121 from above the insulating layer 120. The first principal surface electrode 30 is electrically connected to the diode region 118 within the opening 121.

[0219] The first principal surface electrode 30 forms a Schottky junction with the diode region 118. This forms a Schottky barrier diode with the first principal surface electrode 30 serving as an anode and the diode region 118 serving as a cathode.

[0220] A second principal surface electrode 45 is formed on the second principal surface 114 of the SiC semiconductor layer 112. The second principal surface electrode 45 forms an ohmic contact with the second principal surface 114 of the SiC semiconductor layer 112.

[0221] Fig. 11A is a process diagram for explaining a method for manufacturing a semiconductor device according to a sixth embodiment of the present invention. Fig. 11B is a process diagram for explaining a process performed on an element formed wafer 41 obtained from the process shown in Fig. 11A.

[0222] 12A to 12I are schematic cross-sectional views for illustrating the manufacturing method shown in FIGS. 11A and 11B by applying the manufacturing method shown in FIGS. 11A and 11B to a manufacturing method of semiconductor device 111 shown in FIG.

[0223] In the following, the description of the steps corresponding to the steps described in the first embodiment will be omitted. For convenience of description, in Fig. 12A to Fig. 12I, only the region where one semiconductor device 111 is formed is shown, and the regions of other semiconductor devices and the edge region of the semiconductor wafer source 1 are omitted.

[0224] In this embodiment, steps S71 to S74 are performed instead of steps S1 to S5 (see FIG. 2A) according to the first embodiment. Also, in this embodiment, step S75 is performed after step S7 according to the first embodiment.

[0225] More specifically, first, referring to FIG. 12A, + A semiconductor wafer source 1 made of a type of SiC single crystal is prepared. Next, a part of a semiconductor element 11 is formed on a first main surface 2 of the semiconductor wafer source 1 (Step S71 in FIG. 11A).

[0226] In this embodiment, the step of forming a part of the semiconductor device 11 includes a step of forming an n-type SiC epitaxial layer 117 on the first main surface 2 of the semiconductor wafer source 1. The step of forming a part of the semiconductor device 11 also includes a step of forming an n-type diode region 118 and a p-type diode region 119 on the surface layer of the SiC epitaxial layer 117. + This includes forming guard regions 119 in the mold.

[0227] In the step of forming the SiC epitaxial layer 117, SiC is epitaxially grown from the first main surface 2 of the semiconductor wafer source 1. The diode region 118 is formed by utilizing a portion of the SiC epitaxial layer 117.

[0228] 12B, the semiconductor wafer source 1 on which a part of the semiconductor element 11 is formed is attached to the first support member 21 (step S72 in FIG. 11A). The semiconductor wafer source 1 is attached to the first support member 21 in a position in which the second main surface 3 faces the first support main surface 22 of the first support member 21. In this way, a wafer-attached structure 101 is formed. The method of attaching the semiconductor wafer source 1 to the first support member 21 is the same as that described in the first embodiment, and therefore the description will be omitted.

[0229] 12C, laser light is emitted from the laser light emitting device 33 toward the semiconductor wafer source 1 (step S73 in FIG. 11A). In this embodiment, the laser light is emitted from the first main surface 2 side of the semiconductor wafer source 1 to a middle portion in the thickness direction of the semiconductor wafer source 1.

[0230] In this process, no electrode layer is formed on the surface of the SiC epitaxial layer 117 on the first main surface 2 side of the semiconductor wafer source 1. Also, no insulating layer is formed on the surface of the SiC epitaxial layer 117 on the first main surface 2 side of the semiconductor wafer source 1. Therefore, the laser light can be irradiated toward the inside of the semiconductor wafer source 1 from the first main surface 2 side of the semiconductor wafer source 1 where there are fewer obstacles.

[0231] The distance W1 from the first main surface 2 of the semiconductor wafer source 1 to the focusing portion of the laser light is set according to the thickness of the semiconductor device to be obtained. The distance W1 may be 50 μm or more and 100 μm or less.

[0232] The position of the laser beam irradiated on the semiconductor wafer source 1 is moved along a horizontal direction parallel to the first main surface 2 of the semiconductor wafer source 1. As a result, a first deteriorated layer 34, whose crystalline state has been altered to have properties different from those of other regions, is formed in the middle of the thickness direction of the semiconductor wafer source 1. The first deteriorated layer 34 is n + The mold may be formed in the middle of the semiconductor wafer source 1 .

[0233] If the semiconductor wafer source 1 has a chamfered portion at its edge, an error occurs in the focused portion (focus) of the laser light, and there is a risk that the first affected layer 34 will not be formed parallel to the first main surface 2. Therefore, in this embodiment, a semiconductor wafer source 1 including a second wafer edge 6 that is not chamfered is prepared.

[0234] This makes it possible to suppress errors in the focusing portion (focus) of the laser light. As a result, the first deteriorated layer 34 can be formed inside the semiconductor wafer source 1 across the entire thickness direction of the semiconductor wafer source 1, parallel to the first main surface 2. This makes it possible to properly separate (cleave) the semiconductor wafer source 1 into an element-formed wafer 41 and an element-unformed wafer 42.

[0235] 12D, the second support member 31 is attached to the first main surface 2 of the semiconductor wafer source 1 (step S74 in FIG. 11A). The second support member 31 may be attached to the semiconductor wafer source 1 via a double-sided adhesive tape 32.

[0236] 12E, the semiconductor wafer source 1 is cut from the middle of the thickness direction of the semiconductor wafer source 1 along a horizontal direction parallel to the first main surface 2 (Step S6 in FIG. 11A). More specifically, the semiconductor wafer source 1 is cleaved along the horizontal direction starting from the first deteriorated layer 34.

[0237] The cleavage of the semiconductor wafer source 1 is performed in a state in which the semiconductor wafer source 1 is supported (clamped) by the first support member 21 and the second support member 31. As a result, the semiconductor wafer source 1 is separated into an element-formed wafer 41 having a part of the semiconductor element 11, and an element-unformed wafer 42 having no semiconductor element 11.

[0238] In the cutting step of the semiconductor wafer source 1 (step S6 in FIG. 11A), the semiconductor wafer source 1 may be separated into an element-formed wafer 41 having semiconductor elements 11 and an element-unformed wafer 42 not having semiconductor elements 11. In addition to the above-described cleavage, the semiconductor wafer source 1 may be spontaneously separated into the element-formed wafer 41 and the element-unformed wafer 42 by adjusting, for example, the formation position and formation conditions of the first affected layer 34.

[0239] 12F, after the separation process of the semiconductor wafer source 1, the first cut surface 43 of the element formed wafer 41 is ground (Step S76 in FIG. 11B). The grinding process of the first cut surface 43 may be performed by a CMP method.

[0240] The grinding step of the first cut surface 43 may be performed until the element formed wafer 41 has a desired thickness. In other words, the grinding step of the first cut surface 43 may include a step of thinning the element formed wafer 41.

[0241] 12G, second principal surface electrodes 45 are formed on the first cut surface 43 of the element formed wafer 41 (step S77 in FIG. 11B). Of course, the grinding step of the first cut surface 43 may be omitted. In other words, the second principal surface electrodes 45 may be formed directly on the first cut surface 43 immediately after the separation step of the semiconductor wafer source 1.

[0242] After the grinding step of the element formed wafer 41 (step S76 in FIG. 11B) and prior to the forming step of the second main surface electrode 45 (step S77 in FIG. 11B), an annealing treatment may be performed on the first cut surface 43 (ground surface) of the element formed wafer 41. The annealing treatment may be performed by a laser light irradiation method. In this case, the ohmic property of the second main surface electrode 45 with respect to the first cut surface 43 of the element formed wafer 41 can be improved.

[0243] 12H, the second support member 31 is removed from the first main surface 2 of the semiconductor wafer source 1 (step S78 in FIG. 11B). The step of removing the second support member 31 may be performed prior to the step of grinding the first cut surface 43 or the step of forming the second main surface electrode 45.

[0244] 12I, the remaining portion of the semiconductor element 11 is formed on the first main surface 2 of the semiconductor wafer source 1 (step S79 in FIG. 11B). In this embodiment, an insulating layer 120 and a first main surface electrode 30 are formed on the first main surface 2 of the semiconductor wafer source 1 as the remaining portion of the semiconductor element 11.

[0245] Thereafter, the element-formed wafer 41 is cut along the dicing lines 12 (see also FIGS. 1A and 1B) (step S80 in FIG. 11B). As a result, a plurality of semiconductor devices 111 are cut out from the element-formed wafer 41.

[0246] After the separation process of the semiconductor wafer source 1, it is determined whether or not the non-device-formed wafer 42 can be reused as a new semiconductor wafer source 51 (step S7 in FIG. 11A). The method of determining whether or not the non-device-formed wafer 42 can be reused is the same as that described in the first embodiment, and therefore the description thereof will be omitted.

[0247] If the element-free wafer 42 cannot be reused (step S7 in FIG. 11A: NO), the method for manufacturing a semiconductor device using one semiconductor wafer source 1 is completed.

[0248] If the unformed wafer 42 can be reused as a new semiconductor wafer source 51 (step S7 in FIG. 11A: YES), a portion of the new semiconductor element 52 is formed on the unformed wafer 42 (new semiconductor wafer source 51) (step S75 in FIG. 11A), similar to step S71.

[0249] The step of forming a part of the new semiconductor element 52 (step S75 in FIG. 11A) may be performed in a state where the new semiconductor wafer source 51 is attached to the support member 21. Of course, prior to the step of forming a part of the new semiconductor element 52 (step S75 in FIG. 11A), the first support member 21 may be removed. In this case, the support member 21 may be attached again to the new semiconductor wafer source 51 after the step of forming a part of the new semiconductor element 52 (step S75 in FIG. 11A).

[0250] Thereafter, step S73 is carried out. Thus, in this embodiment, steps S73 to S7 are repeated until the wafer without elements formed thereon cannot be reused as a new semiconductor wafer source. This manufacturing method can also achieve the same effects as those described in the first embodiment.

[0251] In this embodiment, a Schottky barrier diode has been described as an example of the semiconductor element 11. However, the semiconductor element 11 may include a functional element other than the Schottky barrier diode. As described in the first embodiment, the semiconductor element 11 may include at least one of a semiconductor rectifier element, a semiconductor switching element, and a semiconductor passive element.

[0252] Although the embodiment of the present invention has been described, the present invention can be embodied in other forms.

[0253] In each of the above-mentioned embodiments, a wafer bonding structure 101 shown in Fig. 13 may be adopted. Fig. 13 is a cross-sectional view showing a first modified example of the wafer bonding structure 101. In the following, the description of the configuration corresponding to the configuration described in the first embodiment will be omitted.

[0254] 13, in the wafer bonding structure 101 according to this modification, the first wafer edge 5 of the semiconductor wafer source 1 has a chamfered portion. The first wafer edge 5 may have a C-chamfered C-chamfered portion. The first wafer edge 5 may have a R-chamfered R-chamfered portion.

[0255] On the other hand, the second wafer edge 6 of the semiconductor wafer source 1 does not have a chamfered portion. This makes it possible to suppress the formation of a gap in the region between the second wafer edge 6 of the semiconductor wafer source 1 and the first supporting main surface 22 of the first supporting member 21 when the semiconductor wafer source 1 is supported by the first supporting member 21.

[0256] As a result, it is possible to suppress the occurrence of an error in the condensed part (focus) of the laser light irradiated inside the semiconductor wafer source 1. As described above, the wafer bonding structure 101 according to this modification can also achieve the same effects as those described in the first embodiment.

[0257] In each of the above-mentioned embodiments, the wafer bonding structure 101 shown in Fig. 14 may be adopted. Fig. 14 is a cross-sectional view showing a second modified example of the wafer bonding structure 101. In the following, the description of the configuration corresponding to the configuration described in the first embodiment will be omitted.

[0258] 14, in a wafer bonding structure 101 according to this modification, a first orientation notch 71 (first mark) indicating a crystal orientation or the like is formed in the semiconductor wafer source 1 instead of the first orientation flat 7.

[0259] The first orientation notch 71 includes a cutout portion formed on the periphery of the semiconductor wafer source 1. The first orientation notch 71 includes a recess recessed on the periphery of the semiconductor wafer source 1 toward the center of the semiconductor wafer source 1.

[0260] Moreover, in the wafer bonding structure 101 according to this modification, a second orientation notch 72 (second mark) indicating a crystal orientation or the like is formed in the first support member 21 instead of the second orientation flat 27.

[0261] The second orientation notch 72 includes a cutout portion formed on the periphery of the first support member 21. The second orientation notch 72 includes a recess that is recessed on the periphery of the first support member 21 toward the center of the first support member 21.

[0262] The second orientation notch 72 of the first support member 21 may indicate the same crystal orientation as the first orientation notch 71 of the semiconductor wafer source 1. This allows the semiconductor wafer source 1 to be attached to the first support member 21 while knowing the crystal orientation.

[0263] The second orientation notch 72 of the first support member 21 may be aligned with the first orientation notch 71 of the semiconductor wafer source 1. That is, the second orientation notch 72 may face the first orientation notch 71 at a position proximate to the first orientation notch 71.

[0264] As a result, the crystal orientation of the semiconductor wafer source 1 and the crystal orientation of the first support member 21 coincide with each other, so that it is possible to easily determine the crystal orientation of the semiconductor wafer source 1. This makes it possible to improve the convenience of handling the semiconductor wafer source 1.

[0265] As described above, the wafer bonding structure 101 according to this modified example can also achieve the same effects as those described in the first embodiment.

[0266] Of course, the semiconductor wafer source 1 may have the first orientation flat 7 while the first support member 21 may have the second orientation notch 72. Also, the semiconductor wafer source 1 may have the first orientation notch 71 while the first support member 21 may have the second orientation flat 27.

[0267] In each of the above-described embodiments, a semiconductor wafer source 1 made of single crystal Si (silicon) may be used instead of the semiconductor wafer source 1 made of single crystal SiC. In this case, the thickness T1 of the semiconductor wafer source 1 may be 100 μm or more and 1000 μm or less. The thickness T1 of the semiconductor wafer source 1 may be 500 μm or more and 800 μm or less.

[0268] When a single crystal Si semiconductor wafer source 1 is employed, the first support member 21 preferably includes a single crystal Si semiconductor wafer, so that the physical properties of the first support member 21 are approximately equal to those of the semiconductor wafer source 1.

[0269] The thickness T2 of the first support member 21 may be 100 μm or more and 1000 μm or less. Specifically, the thickness T2 of the first support member 21 is 500 μm or more and 800 μm or less. The thickness T2 of the first support member 21 may be equal to the thickness T1 of the semiconductor wafer source 1.

[0270] Additionally, the above description of the configuration of the first support member 21 according to the first embodiment also applies to the case where the first support member 21 is made of a semiconductor wafer made of single crystal Si.

[0271] The hardness of Si is lower than that of SiC. Therefore, the difficulty of processing the semiconductor wafer source 1 made of single crystal Si is lower than the difficulty of processing the semiconductor wafer source 1 made of single crystal SiC. Therefore, the semiconductor wafer source 1 made of single crystal Si can achieve the same effects as those described in the first embodiment.

[0272] Of course, in each of the above-described embodiments, the first support member 21 may include a substrate (wafer) made of a material other than a semiconductor wafer. For example, the first support member 21 may include an insulating substrate having optical transparency. The insulating substrate may include a glass substrate or a resin substrate.

[0273] In each of the above-described embodiments, the separation process of the semiconductor wafer source 1 using the laser light irradiation method (steps S5 and S6 in FIG. 2A) has been described. However, the cutting method used in the separation process is not limited to the laser light irradiation method as long as the semiconductor wafer source 1 can be efficiently consumed.

[0274] The separation process of the semiconductor wafer source 1 may include at least one of a wire saw process, a dicing blade process, and an etching process instead of or in addition to the laser light irradiation method. Among these, the separation process of the semiconductor wafer source 1 preferably includes the laser light irradiation method.

[0275] In each of the above-described embodiments, after the non-device-formed wafer 42 is detached from the first support member 21, new semiconductor elements 52 may be formed on the non-device-formed wafer 42.

[0276] In this case, the non-element wafer 42 on which the new semiconductor elements 52 are formed may be re-bonded to the first support member 21 in order to carry out steps S4 to S8. The non-element wafer 42 on which the new semiconductor elements 52 are formed may be re-bonded to a support member different from the first support member 21 in order to carry out steps S4 to S8.

[0277] In each of the above-described embodiments, after the second wafer 62 without elements formed thereon is detached from the first support member 21, new semiconductor elements may be formed on the second wafer 62 without elements formed thereon.

[0278] In this case, the second non-element wafer 62 on which new semiconductor elements are formed may be re-bonded to the first support member 21 in order to carry out steps S4 to S8. The second non-element wafer 62 on which new semiconductor elements are formed may be re-bonded to a support member different from the first support member 21 in order to carry out steps S4 to S8.

[0279] In each of the above-described embodiments, the wafer 42 without devices formed thereon may be used for purposes other than forming new semiconductor devices 52. The wafer 42 without devices formed thereon may be reused as a support member for supporting another semiconductor wafer source. The other semiconductor wafer source may be a semiconductor wafer source having a smaller diameter and a thinner thickness than the wafer 42 without devices formed thereon.

[0280] In each of the above-described embodiments, an example has been shown in which a vertical semiconductor device including the first principal surface electrode 30 and the second principal surface electrode 45 is manufactured. However, a horizontal semiconductor device including only the first principal surface electrode 30 may also be manufactured. In this case, the process of forming the second principal surface electrode 45 is omitted.

[0281] In each of the above-described embodiments, the step of forming the epitaxial layer 29 may be omitted. That is, a semiconductor device without the epitaxial layer 29 may be manufactured.

[0282] This specification does not limit any combination of the features shown in the first to sixth embodiments. The first to sixth embodiments can be combined in any manner and in any form. In other words, any combination of the features shown in the first to sixth embodiments in any manner and in any form is included in the examples of the present invention.

[0283] This application corresponds to Patent Application No. 2017-119704 filed with the Japan Patent Office on June 19, 2017, the entire disclosure of which is incorporated herein by reference.

[0284] Although the embodiments of the present invention have been described in detail, these are merely examples used to clarify the technical content of the present invention, and the present invention should not be interpreted as being limited to these examples, and the scope of the present invention is limited only by the appended claims. [Explanation of symbols]

[0285] 1. Semiconductor Wafer Source 2. First main surface of semiconductor wafer source 3. Second main surface of semiconductor wafer source 4. Sidewall of semiconductor wafer source 5. First wafer edge of semiconductor wafer source 6 Second wafer edge of semiconductor wafer source 10. Device formation area 11 Semiconductor elements 21 First support member 22 First supporting surface of first supporting member 23 Second main support surface of first support member 24 Support side wall of first support member 25 First support edge of first support member 26 Second support edge of first support member 34 First altered layer 41 Device formation wafer 42 Unformed wafer 51 New semiconductor wafer sources 52 New semiconductor elements 55 Second altered layer 61 Second device formation wafer 62 Second wafer without device formation

Claims

1. A first main surface on one side, a second main surface on the other side, and the first main surface and the second main surface Providing a semiconductor wafer source comprised of SiC (silicon carbide) including a connecting sidewall; forming an epitaxial layer of SiC on the first main surface of the semiconductor wafer source; and, A plurality of element formation regions are defined in the epitaxial layer, and semiconductor an element formation process for fabricating each of the body elements; The semiconductor wafer having a semiconductor element formed in the element forming region of the epitaxial layer. a bonding step of bonding a first main surface side support member to the first main surface side of the source; The semiconductor wafer is supported by the first main surface side support member. The semiconductor wafer source is transformed from a middle portion of the source in the thickness direction along a horizontal direction parallel to the first main surface. forming a porous layer; The semiconductor wafer source is supported by the first main surface side support member. The device-formed wafer and the device-unformed wafer are subjected to a process of forming a pre-formed semiconductor wafer on the semiconductor wafer source. a wafer source separation step of separating the wafer along the deterioration layer; After the wafer separation step, the element-forming Forming a second principal surface electrode on the separation surface of the wafer (the lower surface of the element-formed wafer) and a step of manufacturing a semiconductor device.

2. 2. The method according to claim 1, wherein the altered layer is formed by irradiating the semiconductor wafer source with a laser beam. A method for manufacturing a semiconductor device.

3. The step of forming the deteriorated layer includes:

2. The method for manufacturing a semiconductor device according to claim 1, wherein the method is carried out by irradiating a laser beam onto an emission source.

4. The step of forming the affected layer includes: A laser beam is irradiated onto the semiconductor wafer source at a middle position in the thickness direction of the semiconductor wafer source. a laser beam irradiation position of the semiconductor substrate being moved in a horizontal direction parallel to the first main surface of the semiconductor substrate; The method for manufacturing a semiconductor device according to claim 1 , wherein the method is carried out by

5. After the step of forming the deteriorated layer, the semiconductor wafer source on which the deteriorated layer is formed is The semiconductor device according to claim 1 , further comprising a second adhering step of adhering a second-surface side support member to the second main surface. A method for manufacturing the device.

6. The element forming step includes a step of forming a first main surface electrode on the epitaxial layer. The method for manufacturing a semiconductor device according to claim 1 .

7. After the wafer separation step, the element-forming a grinding step of grinding a separation surface of the wafer (a lower surface of the element-formed wafer); The second principal surface electrode forming step includes forming a second principal surface electrode on the lower surface of the element formed wafer after the grinding step. The method for manufacturing a semiconductor device according to claim 1 , further comprising the step of forming a second principal surface electrode.

8. If the device-free wafer is reusable after the wafer separation step, The unformed wafer is reused as a new semiconductor wafer source, and a first main surface of the unformed wafer is forming an epitaxial layer of SiC on the silicon carbide substrate; A plurality of element formation regions are defined in the epitaxial layer, and semiconductor an element formation process for fabricating each of the body elements; The method for manufacturing a semiconductor device according to any one of claims 1 to 7, further comprising the steps of:

9. forming an epitaxial layer made of SiC on a first main surface of the wafer without elements formed thereon; A plurality of element formation regions are set in the epitaxial layer, and the plurality of element formation regions In the element forming process, a semiconductor element is formed on the first main surface of the element-free wafer. The method for manufacturing a semiconductor device according to claim 8, wherein the method is carried out in a state where the semiconductor device is supported by two main surface side support members. Law.

10. After the wafer separation step, and prior to the step of fabricating the new semiconductor device, 10. The semiconductor device of claim 9, further comprising a polishing step of polishing the separation surface of a new semiconductor wafer source. A method for manufacturing a semiconductor device.

11. In the polishing step, the separation surface of the new semiconductor wafer source has an arithmetic mean roughness Ra The method for manufacturing a semiconductor device according to claim 10, wherein the surface roughness is polished to 1 nm or less.

12. forming an epitaxial layer on the first main surface of the wafer having no elements formed thereon; After the element forming step, before attaching the first main surface side supporting member, the second main surface side supporting member is attached.

10. The method of claim 9, further comprising removing a support member from the source semiconductor wafer to be recycled. Construction method.

13. A first main surface on one side, a second main surface on the other side, and the first main surface and the second main surface Providing a semiconductor wafer source comprised of SiC (silicon carbide) including a connecting sidewall; forming an epitaxial layer of SiC on the first main surface of the semiconductor wafer source; and, A plurality of element formation regions are defined in the epitaxial layer, and semiconductor an element formation process for fabricating each of the body elements; The semiconductor wafer having a semiconductor element formed in the element forming region of the epitaxial layer. a bonding step of bonding a first main surface side support member to the first main surface side of the source; The semiconductor wafer is supported by the first main surface side support member. The semiconductor wafer source is transformed from a middle portion of the source in the thickness direction along a horizontal direction parallel to the first main surface. forming a porous layer; The semiconductor wafer source is supported by the first main surface side support member. The device-formed wafer and the device-unformed wafer are subjected to a process of forming a pre-formed semiconductor wafer on the semiconductor wafer source. A wafer source separation step of separating the wafer along the deterioration layer, After the step of forming the deteriorated layer, the semiconductor wafer source on which the deteriorated layer is formed is A method for manufacturing a semiconductor device, comprising a second adhering step of adhering a second main surface side support member to the second main surface.

14. A first main surface on one side, a second main surface on the other side, and the first main surface and the second main surface Providing a semiconductor wafer source comprised of SiC (silicon carbide) including a connecting sidewall; forming an epitaxial layer of SiC on the first main surface of the semiconductor wafer source; and, A plurality of element formation regions are defined in the epitaxial layer, and semiconductor an element formation process for fabricating each of the body elements; The semiconductor wafer having a semiconductor element formed in the element forming region of the epitaxial layer. a bonding step of bonding a first main surface side support member to the first main surface side of the source; The semiconductor wafer is supported by the first main surface side support member. The semiconductor wafer source is transformed from a middle portion of the source in the thickness direction along a horizontal direction parallel to the first main surface. forming a porous layer; The semiconductor wafer source is supported by the first main surface side support member. The device-formed wafer and the device-unformed wafer are subjected to a process of forming a pre-formed semiconductor wafer on the semiconductor wafer source. a wafer source separation step of separating the wafer along the deterioration layer; If the device-free wafer is reusable after the wafer separation step, The unformed wafer is reused as a new semiconductor wafer source, and a first main surface of the unformed wafer is forming an epitaxial layer made of SiC on the substrate; A plurality of element formation regions are defined in the epitaxial layer, and semiconductor and an element forming step of forming each of the semiconductor elements, forming an epitaxial layer made of SiC on a first main surface of the wafer without elements formed thereon; A plurality of element formation regions are set in the epitaxial layer, and the plurality of element formation regions In the element forming process, a semiconductor element is formed on the first main surface of the element-free wafer. A method for manufacturing a semiconductor device, the method being performed in a state in which the semiconductor device is supported by two main surface side support members.

15. After the wafer separation step, and prior to the step of fabricating the new semiconductor device, 15. The method of claim 14, further comprising the step of polishing the separation surface of a new semiconductor source wafer. A method for manufacturing a semiconductor device.

16. In the polishing step, the separation surface of the new semiconductor wafer source has an arithmetic mean roughness Ra 16. The method for manufacturing a semiconductor device according to claim 15, wherein the surface roughness is polished to 1 nm or less.

17. The step of reusing the wafer without any device formed thereon as a new semiconductor wafer source comprises:

15. The method according to claim 14, wherein the thickness of the device-formed wafer is equal to or greater than the thickness of the device-formed wafer.

17. A method for manufacturing a semiconductor device according to any one of claims 1 to 16.

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