Display device

Abstract

To provide a logic circuit using a resistor element and a thin film transistor manufactured using an oxide semiconductor layer with the electric characteristics controlled, and a semiconductor device using the logic circuit.SOLUTION: In a semiconductor device, on an oxide semiconductor layer 905 used for a resistor element 354, a silicon nitride layer 910 is provided in direct contact by a plasma CVD method using gas containing a hydrogen compound such as SiH4 and NH3. In an oxide semiconductor layer 906 used for a thin film transistor 355, a silicon nitride layer 910 is provided through a silicon oxide layer 909 functioning as a barrier layer. Therefore, in the oxide semiconductor layer 905, hydrogen is introduced at higher concentration than in the oxide semiconductor layer 906. As a result, a resistance value of the oxide semiconductor layer 905 used for the resistor element 354 is lower than that of the oxide semiconductor layer 906 used for the thin film transistor 355.SELECTED DRAWING: Figure 11

Description

[Technical field]

[0001] The present invention relates to a driving circuit that is composed of elements formed using a metal oxide that exhibits semiconductor properties, The present invention also relates to a semiconductor device using the driving circuit. This refers to all devices that can function by performing operations on the semiconductor device. Display devices, semiconductor circuits, and electronic devices are all semiconductor devices. It is a body device. [Background technology]

[0002] Metal oxides exist in a wide variety of forms and are used for a variety of purposes. Indium oxide is well known. It is a material that has been used as a transparent electrode material for liquid crystal displays and other devices. There are.

[0003] Some metal oxides exhibit semiconducting properties. A compound semiconductor is a type of semiconductor in which two or more types of atoms are bonded together by ionic bonds. Generally, metal oxides are insulators. However, It is known that some combinations of elements have weak electrostatic attraction and become semiconductors.

[0004] For example, metal oxides such as tungsten oxide, tin oxide, indium oxide, and zinc oxide It is known that transparent semiconductors made of such metal oxides exhibit semiconducting properties. Thin film transistors in which a dielectric layer is used as a channel forming region have been disclosed (Patent Documents 1 to 4, Non-patent literature 1).

[0005] By the way, metal oxides are not only single-component oxides, but also multi-component oxides. For example, , InGaO3(ZnO) with homologous phase m (m: natural number) is a known material ( Non-patent documents 2 to 4).

[0006] The In-Ga-Zn oxide is used as the channel forming region of a thin film transistor. It has been confirmed that the above-mentioned method can be applied to the following areas (Patent Document 5, Non-Patent Documents 5 and 6). [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Publication No. 1988-1986 [Patent Document 2] Japanese Patent Application Publication No. 8-264794 [Patent Document 3] Special Publication No. 11-505377 [Patent Document 4] JP 2000-150900 A [Patent Document 5] JP 2004-103957 A [Non-patent literature]

[0008] [Non-Patent Document 1] MW Prins, KO Grosse-Holz, G. Muller, JFM Cillessen, JB Giesbers, RP Weening, and RM Wolf, “A ferroelectric transparent thin-film transistor”, Appl. Phys. Lett., 17 June 1996, Vol.68 p.3650-3652 [Non-Patent Document 2] M. Nakamura, N. Kimizuka, and T. Mohri, "The Phase Relations in the In2O3-Ga2ZnO4-ZnO System at 1350℃", J. Solid State Chem., 1991, Vol.93, p.298-315 [Non-Patent Document 3] N. Kimizuka, M. Isobe, and M. Nakamura, “Syntheses and Single-Crystal Data of Homologous Compounds, In2O3(ZnO)m(m=3,4, and 5), InGaO3(ZnO)3, and Ga2O3(ZnO)m(m=7,8,9, and 16) in the In2O3-ZnGa2O4-ZnO System”, J. Solid State Chem., 1995, Vol.116, p.170-178 [Non-Patent Document 4] Masaki Nakamura, Noboru Kimizuka, Takahiko Mouri, Mitsumasa Isobe, "Synthesis and crystal structure of homologous phase, InFeO3(ZnO)m (m: natural number) and its isomorphic compounds", Solid State Physics, 1993, Vol.28, No.5, pp.317-327 [Non-Patent Document 5] K. Nomura, H. Ohta, K. Ueda, T. Kamiya, M. Hirano, and H. Hosono, "Thin-film transistor fabricated in single-crystalline transparent oxide semiconductor", SCIENCE, 2003, Vol.300, p.1269-1272 [Non-Patent Document 6] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, "Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors", NATURE, 2004, Vol.432 p.488-492 Summary of the Invention [Problem to be solved by the invention]

[0009] Thin-film transistors using metal oxides (hereinafter referred to as oxide semiconductors) that exhibit semiconductor properties The star is an active matrix display device (liquid crystal display, electroluminescence Applications to active matrix displays, electronic paper, etc. are being considered. A trix display device has hundreds of thousands to millions of pixels arranged in a matrix, and each pixel is individually and a drive circuit for inputting a pulse signal.

[0010] In an active matrix display device, a thin film transistor is provided for each pixel. A switch that switches on and off when a pulse signal is input from a drive circuit. The thin-film transistor also functions as a driving circuit. It is also used as an element that constitutes a path.

[0011] The driver circuit for driving the pixel section is made up of thin film transistors, capacitance elements, and resistance elements. It is configured to include an element.

[0012] One embodiment of the present invention is a semiconductor device including active elements and passive elements formed using an oxide semiconductor. It is an object of the present invention to provide a logic circuit and a semiconductor device having the logic circuit. . [Means for solving the problem]

[0013] One embodiment of the present invention includes an enhancement type thin film transistor and a resistor element. The transistor and the resistor are formed using an oxide semiconductor layer. The hydrogen concentration of the oxide semiconductor layer applied to the resistor is As a result, the resistance value of the oxide semiconductor layer applied to the resistor element is is lower than the resistance value of an oxide semiconductor layer applied to a thin film transistor. do.

[0014] One embodiment of the present invention is a thin film transistor and a resistor formed using an oxide semiconductor layer. The oxide semiconductor layer used for the resistor element is provided with silane (SiH4) and ammonia. The material was formed by the plasma CVD method using gases containing hydrogen compounds such as NH3. An oxide layer is provided directly adjacent to a silicon nitride layer and is applied to a thin film transistor. On the semiconductor layer, the silicon nitride layer is formed via a silicon oxide layer that functions as a barrier layer. Therefore, in the oxide semiconductor layer used for the resistor element, a thin film transistor is provided. Hydrogen is introduced at a higher concentration than in the oxide semiconductor layer applied to the resistor. The resistance value of the oxide semiconductor layer applied to the element is set to be equal to that of the oxide semiconductor layer applied to the thin film transistor. The resistance of the insulating layer is lower than that of the insulating layer.

[0015] That is, one embodiment of the present invention is a resistor element in which a first oxide semiconductor layer is used as a resistance component. The second oxide semiconductor layer, which has a lower hydrogen concentration than the first oxide semiconductor layer, is formed as a channel formation region. a thin film transistor applied to the first embodiment, a silicon oxide layer provided on the second oxide semiconductor layer, a first oxide semiconductor layer and a silicon nitride layer provided on the silicon oxide layer. It is a logic circuit that

[0016] Furthermore, the resistive component of the resistive element and the oxide applied to the channel forming region of the thin film transistor are A low-resistance oxide semiconductor layer is provided between the oxide semiconductor layer and the wiring, which is a conductor. is also an aspect of the present invention.

[0017] That is, one embodiment of the present invention is a method for manufacturing a semiconductor device having the above-described structure, a third oxide semiconductor layer in contact with a terminal and the first oxide semiconductor layer; and a thin film transistor. a fourth oxide semiconductor layer in contact with the first terminal and the second oxide semiconductor layer; and a fifth oxide semiconductor layer in contact with the second terminal of the third oxide semiconductor layer and the second oxide semiconductor layer; The first to fifth oxide semiconductor layers have a lower resistance than the second oxide semiconductor layer. It is a simple logic circuit.

[0018] In addition, one embodiment of the present invention is a semiconductor device formed using an oxide semiconductor layer containing nitrogen at a high concentration. The thin film transistor includes a resistor element and a barrier layer. At this stage, a layer of silicon oxide is applied to act as a source of hydrogen atoms. Heat treatment at 200℃ to 600℃ in an atmosphere containing The nitrogen in the oxide semiconductor layer is generated when atoms constituting the oxide semiconductor layer are densely packed in the film. This has the effect of preventing hydrogen from being filled in the film and promoting the diffusion and dissolution of hydrogen into the film. By the heat treatment, a thin film of a nitrogen-containing oxide semiconductor layer that is applied to a resistor element is formed. Hydrogen is introduced at a higher concentration than in an oxide semiconductor layer applied to a transistor. The resistance value of the oxide semiconductor layer containing nitrogen at a high concentration and applied to the resistor element is The resistance value of the oxide semiconductor layer containing nitrogen at a high concentration and used as a GaN LED is lower than that of the oxide semiconductor layer containing nitrogen at a high concentration.

[0019] That is, in one embodiment of the present invention, a first oxide semiconductor layer containing nitrogen at a high concentration is used as a resistance component. and a resistor element having a lower hydrogen concentration than the first oxide semiconductor layer and a high nitrogen concentration. a thin film transistor having a channel formation region formed of a second oxide semiconductor layer containing the It is a logic circuit that

[0020] Note that the oxide semiconductor layer containing nitrogen at a high concentration is an oxide semiconductor layer containing nitrogen (N) at a high concentration relative to oxygen (O). The ratio (N / O) is in the range of 0.05 to 0.8, preferably 0.1 to 0.5. The term "oxide semiconductor layer" refers to an oxide semiconductor layer formed in a thin film.

[0021] Furthermore, silane ( Plasma CV using gases containing hydrogen compounds such as SiH4 and ammonia (NH3) The present invention also provides a structure in which a silicon nitride layer formed by the D method is provided so as to be in direct contact with the substrate. It is an attitude.

[0022] That is, in one embodiment of the present invention, in the above structure, a silicon oxide layer formed on the first oxide semiconductor layer and a silicon nitride layer formed on the first oxide semiconductor layer and the silicon oxide layer; and a reconfiguration layer.

[0023] In this document (specification, claims, drawings, etc.), the term "film" refers to the entire substrate. The surface is then processed into the desired shape by a photolithography process or the like. The object to be processed is in its pre-processed state. And the word "layer" refers to the difference between "film" and "photo". Those processed and formed into the desired shape by lithography processes, etc., and those formed on the entire surface of a substrate It refers to something that is intended to do so.

[0024] In addition, in this document (specification, claims, drawings, etc.), A and B are connected. "A and B are directly connected" refers to those where A and B are electrically connected in addition to those where A and B are directly connected. Here, "A and B being electrically connected" means that there is no electrical connection between A and B. When an object having an electrical effect exists, A and B are approximately at the same node through the object. This represents the case where

[0025] Specifically, A and B are connected via a switching element such as a transistor, and the When the switching element is turned on, A and B may be at roughly the same potential, or they may be connected via a resistor. A and B are connected by this resistor, and the potential difference generated across the resistor element determines the behavior of the circuit including A and B. When considering circuit operation, for example, when A and B are the same node, This indicates a situation where it is acceptable to interpret the situation as normal.

[0026] The source terminal and the drain terminal of the thin film transistor are determined according to the structure of the thin film transistor. Since it changes depending on the operating conditions, it is not possible to specify which is the source terminal or the drain terminal. Therefore, in this document (specification, claims, drawings, etc.), one of the source terminal and the drain terminal is a first terminal, and the other of the source terminal and the drain terminal is a second terminal. will be referred to as the second terminal to distinguish it from the first terminal. Effect of the Invention

[0027] According to one embodiment of the present invention, the hydrogen concentration of the oxide semiconductor layer applied to the resistance component of the resistor element is higher than the hydrogen concentration in the oxide semiconductor layer applied to the channel formation region of the thin film transistor. Therefore, the resistance value of the oxide semiconductor layer can be selectively reduced. This makes it possible to provide a manufacturing process for the thin film transistor and a manufacturing process for the resistor element separately. A logic circuit that does not require a semiconductor device and can be fabricated in a reduced number of processes, and a semiconductor device having the logic circuit Locations can be provided. [Brief description of the drawings]

[0028] [Figure 1] FIG. 1 is a diagram illustrating a configuration example of a semiconductor device. [Diagram 2] FIG. 2 is a block diagram showing a configuration example of a drive circuit. [Diagram 3] 1A and 1B are circuit diagrams showing an example of a configuration of a drive circuit. [Figure 4] FIG. 4 is a diagram illustrating an example of a timing chart of a drive circuit. [Diagram 5] FIG. 2 is a circuit diagram showing a configuration example of a drive circuit. [Figure 6] FIG. 2 is a circuit diagram showing a configuration example of a drive circuit. [Figure 7] FIG. 2 is a block diagram showing a configuration example of a drive circuit. [Figure 8] FIG. 2 is a layout diagram showing a configuration example of a drive circuit. [Figure 9] FIG. 2 is a layout diagram showing a configuration example of a drive circuit. [Figure 10] FIG. 2 is a layout diagram showing a configuration example of a drive circuit. [Figure 11] 3A to 3C are diagrams illustrating an example of a configuration of a drive circuit. [Figure 12] 1A and 1B are diagrams illustrating an example of a configuration of a drive circuit. [Figure 13] 1A and 1B are diagrams illustrating an example of a configuration of a drive circuit. [Figure 14] 1A and 1B are diagrams illustrating an example of a configuration of a drive circuit. [Figure 15] 5A to 5C are diagrams illustrating an example of a process for producing a drive circuit. [Figure 16] 5A to 5C are diagrams illustrating an example of a process for producing a drive circuit. [Figure 17] FIG. 2 is a diagram illustrating a configuration example of a drive circuit. [Figure 18] 5A to 5C are diagrams illustrating an example of a process for producing a drive circuit. [Figure 19]1A and 1B are diagrams illustrating an example of a process for producing a drive circuit. [Figure 20] 1A and 1B are circuit diagrams showing an example of a configuration of a drive circuit, and FIG. 1C is a diagram showing an example of a timing chart of the drive circuit. [Figure 21] FIG. 1 is a diagram illustrating a configuration example of a semiconductor device. [Figure 22] FIG. 2 is a circuit diagram showing a configuration example of a protection circuit. [Diagram 23] FIG. 1 is a circuit diagram showing a configuration example of a pixel of a semiconductor device. [Figure 24] FIG. 1 is a diagram illustrating a configuration example of a semiconductor device. [Diagram 25] FIG. 1 is a diagram illustrating a configuration example of a semiconductor device. [Figure 26] FIG. 1 is a diagram illustrating a configuration example of a semiconductor device. [Figure 27] FIG. 1 illustrates an example of a semiconductor device. [Figure 28] FIG. 1 illustrates an example of a semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] The following embodiments of the present invention will be described with reference to the accompanying drawings. The present invention is not limited to the following embodiments, and the present invention is not limited to the embodiments described below without departing from the spirit and scope of the present invention. It will be easily understood by those skilled in the art that various changes can be made in form and detail. Therefore, the disclosed invention should be construed as being limited to the description of the following embodiment modes. In the following exemplary embodiments, the same reference numerals are used in different drawings. It may be used throughout.

[0030] (Embodiment 1) In this embodiment, a driver circuit manufactured using an oxide semiconductor will be described with reference to FIGS. An example of a display device having the above-mentioned structure will be described. As an example of a source line driver circuit and a gate line driver circuit, which are driver circuits for An inverter formed by combining an ER thin-film transistor and a resistor element In this embodiment, a driver circuit having a unipolar transistor (referred to as a MOS circuit) will be described. N-channel thin-film transistors are used as the thin-film transistors that make up the driver circuits of the An example of this is shown below.

[0031] Note that the display device refers to a device having a display element such as a light-emitting element or a liquid crystal element. The display device may include a peripheral driving circuit for driving the plurality of pixels. The peripheral driving circuit for driving the pixels is formed on the same substrate as the pixels. The device is a flexible printed circuit board (F The display device may further include a flexible printed circuit board (FPC) or the like. They are connected via a resistor, a capacitor, an inductor, a transistor, etc. The display device may further include a printed wiring board (PWB) attached thereto. Optical sheets such as polarizing plates or retardation plates, lighting devices, housings, audio input / output devices, or optical sensors It may also include s, etc.

[0032] 1 shows an overall view of a display device. A source line driver circuit is provided on a substrate 100. 101, a first gate line driving circuit 102A, a second gate line driving circuit 102B, and a pixel The pixel portion 103 is integrally formed. The portion surrounded by the dotted line frame 110 in the pixel portion 103 is In the example of FIG. 1, the first gate line driving circuit 102 is used as the gate line driving circuit. Although the first gate line driving circuit 102A and the second gate line driving circuit 102B are shown, only one of them may be used. In addition, in the pixels of the display device, the display element is controlled by a thin film transistor. A first gate line driving circuit 101, a first gate line driving circuit 102A, and a second gate line driving circuit 102 The signals that drive B (clock signals, start pulses, etc.) are sent to the flexible printed circuit board ( Flexible Print Circuit (FPC) 104A, 104B , is input from the outside.

[0033] The source line driving circuit and the gate line driving circuit for driving the pixel portion are made of thin film transistors, It has a logic circuit such as an inverter circuit that is composed of capacitance elements, resistance elements, etc. When forming an inverter circuit using thin film transistors of the same polarity, Combination of enhancement type thin film transistor and depletion type thin film transistor (hereinafter referred to as EDMOS circuit) and enhancement type thin film transistor There are two types of circuits: an EEMOS circuit formed by a single transistor (hereinafter referred to as an EEMOS circuit) and an ERMOS circuit. In addition, when the threshold voltage of an n-channel thin film transistor is positive, it is called an enhancement type. A negative threshold voltage for an n-channel thin-film transistor is called a de- This definition is used throughout the specification to refer to a pressure-type transistor.

[0034] The thin film transistor provided in the pixel area is an enhancement type with a positive threshold voltage. When a transistor is applied, a current flows between the gate and source terminals. The current can be made smaller than that of depletion type transistors, which reduces power consumption. In addition, the thin film transistor can be used in a driver circuit for driving a pixel portion. It is preferable to use the same enhancement type thin film transistor as the pixel portion. The thin film transistor of the inverter circuit is an enhancement type thin film transistor. As a result, the number of transistors required to manufacture the pixel portion and the driver circuit is one. The manufacturing process can be reduced. The electrical characteristics of the device are as follows: on-off switching at gate voltages from -20V to 20V. The ratio is 10 9 Therefore, the leakage current between the source terminal and the drain terminal is small and low It is possible to realize low power consumption driving.

[0035] In addition, the oxide semiconductor used in this document (specification, claims, drawings, etc.) is I nMO3(ZnO) m (m>0) is formed, and the thin film is used to form a semiconductor. The element is fabricated. M is gallium (Ga), iron (Fe), nickel (Ni), manganese (Mn), and Indicates one or more metal elements selected from manganese (Mn) and cobalt (Co). For example, M can be gallium (Ga), or it can be gallium (Ga) and nickel. Ni (Ni) or gallium (Ga) and iron (Fe), etc., other than gallium (Ga), In the oxide semiconductor, the metal element contained as M may be In addition, impurities such as iron (Fe), nickel (Ni), and other transition metal elements, or In addition, the oxide of a transition metal is contained in the oxide semiconductor. Thorium (Na) is 5×10 18 (atoms / cm 3 ) or less, preferably 1×10 1 8 (atoms / cm 3) This document (specification, claims or In the drawings, etc., this thin film is also called an In-Ga-Zn-O type non-single crystal film.

[0036] Inductively Coupled Plasma Mass Spectrometry A typical measurement example using ICP-MS (Ion-coupled Plasma Mass Spectrometry) The molar ratio of the target was In2O3:Ga2O3:ZnO=1:1:1. The ZnO (In:Ga:Zn=1:1:0.5) was used, and the pressure was 0.4 Pa and the DC power supply was 5 The acid obtained under condition 1 with 00 W, argon gas flow rate of 10 sccm, and oxygen flow rate of 5 sccm The compound semiconductor film is InGa 0.94 Zinc 0.40 O 3.31 In addition, from the above conditions, The deposition atmosphere conditions were changed to argon gas flow rate of 40 sccm and oxygen flow rate of 0 sccm. The oxide semiconductor film obtained in Example 2 is InGa 0.95 Zinc 0.41 O 3.33 It is.

[0037] [Table 1]

[0038] The measurement method was the Rutherford Backscattering Analysis. Quantification results after changing to RBS analysis is shown in Table 2.

[0039] [Table 2]

[0040] The sample under condition 1 was measured by RBS analysis. As a result, the oxide semiconductor film was InGa0.92 Zinc 0.45 O 3.86 In addition, the RBS analysis of the sample under condition 2 showed that the oxide semiconductor The conductive film is InGa 0.93 Zinc 0.44 O 3.49 It is.

[0041] The crystal structure of the In-Ga-Zn-O non-single crystal film is determined by sputtering and then heating at 200°C. Even if heat treatment is performed at temperatures between 300 and 400°C for 10 to 100 minutes, The rufus structure was observed in the XRD (X-ray diffraction) analysis. The on / off ratio of the transistor is 10 when the gate voltage is from -20V to 20V. 9 As above, the mobility is 10 or more can be fabricated. The thin-film transistors fabricated using this method are thin-film transistors fabricated using amorphous silicon. It has higher mobility than a transistor, enabling high-speed operation of a driver circuit composed of a shift register. It is possible.

[0042] Next, regarding the circuit diagram of the gate line driver circuit and the source line driver circuit using the ERMOS circuit, An example will be given and explained.

[0043] First, the configuration of the source line driver circuit using an ERMOS circuit as the inverter circuit Provide an explanation.

[0044] FIG. 2 is a diagram showing a configuration of the source line driving circuit 101 in the display device shown in FIG. The source line driver circuit includes a clock signal level shifter 201, a start pulse level shifter 202, and a A shifter 202, a pulse output circuit 203 constituting a shift register 251, a NAND circuit 2 04, a buffer 205, and a sampling switch 206. The signals are the first clock signal (CLK1), the second clock signal (CLK2), and the start The first is the clock signal. The first clock signal (CLK1), the second clock signal (CLK2), and the start pulse (SP) Immediately after a low-voltage amplitude signal is input from the outside, the level shifter 201 or 2 The amplitude is converted by 02 and input to the drive circuit as a high-voltage amplitude signal.

[0045] In addition, the source line driving circuit in the display device of the present embodiment is a shift register. The sampling pulse output from the pulse output circuit switches the sampling switch 206 By driving this, analog video signals from 12 source signal lines can be sampled simultaneously. In addition, there is also a scanning direction switching signal for switching the scanning direction. In this embodiment, the first clock signal is input as a clock signal. The clock signal (CLK1) and the second clock signal (CLK2) are two-phase clock signals. An example of driving the driver circuit using a clock signal other than two phases is shown below. This is also fine.

[0046] 3A and 3B show a plurality of pulse output circuits 203 included in a shift register 251. The pulse output circuit 300 is connected to a terminal to which a start pulse SP is input. and a first switch 301 that inverts the signal input through the first switch 301 and outputs the inverted signal. A first inverter circuit 302 inputs a signal a second inverter circuit 303 and a third inverter circuit 305 which invert and output the A second switch connected to a terminal to which a signal output from the second inverter circuit 303 is input and switch 304.

[0047] In the circuit diagram shown in FIG. 3(A), the block indicated by the dotted line is a sampling The shift register in FIG. 3A has N stages (N The pulse output circuit is composed of N stages (N stages is a natural number). The output signals out1 to outN are output from the output terminals of the third inverter circuits 305. In the pulse output circuit next to the first stage described above, the first switch 3 Between the first clock signal and the second clock signal 301 and the second switch 304, The wiring that inputs the signal is switched and connected. From the third stage onwards, the first clock is alternately connected. The wiring for inputting the first clock signal and the second clock signal is connected to the first switch 301 and the second switch The connection is switched between the switch 304 and the switch 305 in an alternating manner.

[0048] FIG. 3B shows the detailed circuit configuration of the pulse output circuit. The main body includes thin film transistors 351, 353, 355, 356, 358, and a resistive element 35 2, 354, and 357. Also, the odd-numbered pulse output circuits 331 and the even-numbered pulse The signal output circuit 332 includes a wiring 359 for supplying a first clock signal (CLK1), and and a wiring 360 for supplying a second clock signal (CLK2). Next, the specific connection relationship of the semiconductor elements will be described using the first stage pulse output circuit 331 as an example. State.

[0049] A first terminal of the thin film transistor 351 is connected to a terminal to which a start pulse SP is input. The gate terminal is connected to a wiring 359 .

[0050] One terminal of the resistor element 352 is connected to a wiring through which a high power supply potential VDD is supplied (a high power supply potential line). (also called a "connector").

[0051] A first terminal of the thin film transistor 353 is connected to the other terminal of the resistor element 352. The second terminal is connected to the low power supply potential VS This is connected to the wiring that supplies S (also called the low power supply potential line).

[0052] One terminal of the resistor element 354 is connected to the high power supply potential line.

[0053] A first terminal of the thin film transistor 355 is connected to the other terminal of the resistor element 354. The first terminal is connected to the other terminal of the resistor element 352 and a first terminal of the thin film transistor 353. , the second terminal is connected to the low power supply potential line.

[0054] The first terminal of the thin film transistor 356 is connected to the other terminal of the resistor element 354 and the thin film transistor The first terminal of the transistor 355 is connected to the gate terminal of the transistor 355, the gate terminal of the transistor 355 is connected to the wiring 360, and the second terminal of the transistor 355 is connected to the wiring 360. A second terminal of the thin film transistor 351 and a gate terminal of the thin film transistor 353 are connected to each other. do.

[0055] One terminal of the resistor element 357 is connected to the high power supply potential line, and the other terminal is connected to the second stage power supply potential line. The first terminal of the thin film transistor 351 in the pulse output circuit 332 is connected to the first terminal of the thin film transistor 351 in the pulse output circuit 332.

[0056] The first terminal of the thin film transistor 358 is connected to the other terminal of the resistor element 357 and the second-stage pulse The gate terminal of the thin film transistor 351 in the output circuit 332 is connected to the first terminal of the thin film transistor 351. , the other terminal of the resistor element 352, the first terminal of the thin film transistor 353, and the The first terminal is connected to the gate terminal of the transistor 355, and the second terminal is connected to the low power supply potential line.

[0057] The second stage pulse output circuit is also connected to the first stage pulse output circuit via wiring 359 and wiring 360. The configuration is the same except that the pulse output circuits 331 and 332 in the odd-numbered stages from the third stage onwards are the same. The even-numbered pulse output circuits 332 are connected in sequence in a similar manner.

[0058] In FIG. 3B, a thin film transistor 351 corresponds to the first switch shown in FIG. The resistor element 352 and the thin film transistor 353 correspond to the resistor element 352 and the thin film transistor 353 shown in FIG. This corresponds to the first inverter circuit 302, which is an ERMOS circuit. The resistor element 354 and the thin film transistor 355 are the same as those in the second inverter shown in FIG. The first inverter circuit 303 corresponds to an ERMOS circuit. The transistor 356 corresponds to the second switch 304 shown in FIG. 57 and a thin film transistor 358 are connected to the third inverter circuit 305 shown in FIG. Correspondingly, the third inverter circuit 305 is an ERMOS circuit.

[0059] The thin film transistors 351 and 356 are the same as the thin film transistors 353, 355, and 358. As in the case of the switch, it is preferable to use an enhancement type transistor. By using an enhancement type transistor, the off-state current of the transistor can be reduced. This allows for low power consumption and reduces the number of manufacturing steps. do.

[0060] Here, referring to the timing chart shown in FIG. 4, the circuits shown in FIG. 3(A) and (B) The circuit operation will be described. For the sake of explanation, FIG. 4 shows the circuit shown in FIG. In the first stage pulse output circuit, the second terminal of the thin film transistor 351 is connected to a node A (indicated as A in FIG. 3B and FIG. 4), and the other terminal of the resistor element 352 is connected to a node B (indicated as A in FIG. 3B and FIG. 4). 3B and 4B), and the other terminal of the resistor element 354 is connected to a node C (FIG. 3B and 3B and C in FIG. 4), and the other terminal of the resistor element 357 is connected to a node out1 (FIG. 3B and In FIG. 4, this is shown as out1.

[0061] In addition, in the second stage pulse output circuit as a node in the circuit shown in FIG. The second terminal of the transistor 351 is connected to a node D (shown as D in FIG. 3B and FIG. 4), and the resistor The other terminal of the resistor 352 is connected to a node E (indicated as E in FIG. 3B and FIG. 4), and the other terminal of the resistor 354 is connected to a node E (indicated as E in FIG. 3B and FIG. 4). The other terminal of the resistor element 357 is connected to a node F (indicated as F in FIG. 3B and FIG. 4). The terminal is the node out2 (indicated as out2 in FIG. 3(B) and FIG. 4). In the third stage pulse output circuit, a thin film transistor 35 The second terminal of No. 1 is designated as node G (indicated as G in FIG. 3B and FIG. 4).

[0062] In FIG. 4, during a period T1, the start pulse SP is at H level, and the first clock signal (CLK1 ) is at H level and the second clock signal (CLK2) is at L level. .

[0063] When the first clock signal (CLK1) goes high, the first stage pulse output circuit The thin film transistor 351 is turned on.

[0064] And the voltage level of the start pulse, which is H level, makes the voltage level of node A H level. Rise to the bell.

[0065] Then, the voltage level of node A rises to the H level, causing the first stage pulse output The thin film transistor 353 in the circuit is turned on.

[0066] The voltage level of the low power supply potential, L level, makes the voltage level of node B L level. Lower it to.

[0067] Then, the voltage level of node B drops to the L level, causing the first stage pulse output The thin film transistor 355 and the thin film transistor 358 in the circuit are turned off.

[0068] Then, the thin film transistor 355 of the first stage pulse output circuit is turned off. As a result, the voltage level of the high power supply potential, H level, rises to the H level at node C. In addition, the thin film transistor 358 of the first stage pulse output circuit is turned off. As a result, the voltage level of the high power supply potential, H level, rises to the H level at the node out1. Rise to the bell.

[0069] In addition, since the second clock signal (CLK2) is at the L level, the first stage pulse output The thin film transistor 356 of the circuit and the thin film transistor 351 of the second stage pulse output circuit are The switch is turned off.

[0070] Next, in the period T2 in FIG. 4, the start pulse SP is at the L level, and the first clock signal (CL This section explains the operation when the first clock signal K1) is at the L level and the second clock signal K2 is at the H level.

[0071] When the first clock signal goes low, the thin-film transistor of the first-stage pulse output circuit On the other hand, the second clock signal (CLK2) is at H level. Therefore, the thin film transistor 356 of the first stage pulse output circuit is turned on. During the period T1, the voltage level of node C is at H level, so the voltage level of node A becomes H. The level will be maintained.

[0072] And each node of the first stage pulse output circuit is kept at the same level as during the period T1. It becomes.

[0073] On the other hand, when the second clock signal (CLK2) goes to H level, the second stage pulse output The thin film transistor 351 in the circuit is turned on.

[0074] And the voltage level of the node out1, which is the H level, makes the voltage level of the node D, Rise to the bell.

[0075] Then, the voltage level of node D rises to the H level, causing the second stage pulse output The thin film transistor 353 in the circuit is turned on.

[0076] The voltage level of the low power supply potential, L level, causes the voltage level of node E to become L level. Lower it to.

[0077] Then, the voltage level of node E drops to the L level, causing the second stage pulse output The thin film transistor 355 of the circuit and the thin film transistor 358 of the second stage pulse output circuit are The switch is turned off.

[0078] Then, the thin film transistor 355 of the second stage pulse output circuit is turned off. As a result, the voltage level of the high power supply potential, H level, rises to the H level at node F. In addition, the thin film transistor 358 of the second stage pulse output circuit is turned off. As a result, the voltage level of the high power supply potential, that is, the H level, is set to the H level. Rise to the bell.

[0079] In addition, since the first clock signal (CLK1) is at the L level, the second stage pulse output The thin film transistor 356 of the circuit and the thin film transistor 351 of the third stage pulse output circuit are The switch is turned off.

[0080] Next, in the period T3 in FIG. 4, the start pulse SP is at the L level, and the first clock signal (CL This section describes the operation when the first clock signal K1) is at H level and the second clock signal K2 is at L level.

[0081] When the first clock signal goes high, the thin-film transistor of the first-stage pulse output circuit On the other hand, the second clock signal (CLK2) is at the L level. Therefore, the thin film transistor 356 of the first stage pulse output circuit is turned off. , the voltage level of node A drops to the L level.

[0082] Then, the voltage level of node A drops to the L level, causing the first stage pulse output The thin film transistor 353 in the circuit is turned off.

[0083] The voltage level of the high power supply potential, H level, makes the voltage level of node B H level. to rise.

[0084] Then, the voltage level of node B rises to the H level, causing the first stage pulse output The thin film transistor 355 of the first stage pulse output circuit and the thin film transistor 358 of the second stage pulse output circuit are The switch is turned on.

[0085] Then, the thin film transistor 355 of the first stage pulse output circuit is turned on. As a result, the voltage level of the low power supply potential, L level, drops the voltage level of node C to L level. The thin film transistor 358 of the first stage pulse output circuit is turned on, The low level, which is the voltage level of the low power supply potential, drops the voltage level of node out1 to the low level. To bring down.

[0086] In addition, since the second clock signal (CLK2) is at the L level, the first stage pulse output The thin film transistor 356 in the circuit is turned off.

[0087] Similarly to the first-stage pulse output circuit during period T2, the second clock signal is at the L level. As a result, the thin film transistor 351 of the second stage pulse output circuit is turned off. On the other hand, since the first clock signal (CLK1) is at the H level, the second-stage pulse output circuit The thin film transistor 356 is turned on. Due to the voltage level of node F, the voltage level of node D is maintained at the H level.

[0088] And each node of the second stage pulse output circuit is kept at the same level as during the period T2. It becomes.

[0089] On the other hand, when the first clock signal (CLK1) becomes H level, the third stage pulse output The thin film transistor 351 in the circuit is turned on.

[0090] And the voltage level of the node out2, which is the H level, sets the voltage level of the node G to the H level. Rise to the bell.

[0091] Then, the voltage level of node G rises to the H level, and the third stage pulse output The thin film transistor 353 in the circuit is turned on.

[0092] The transistors are then turned on and off in sequence, forming a shift register. It can be driven.

[0093] In the pulse output circuit described with reference to FIGS. 3(A) and 3(B), the nodes A and C are 3 shows a configuration in which a thin film transistor 356 (second switch 304) is provided between the This is because the voltage level of the node C is changed from the high voltage potential VDD to the low voltage potential VDD by the resistor element 354. This is because the thin film transistor 356 (second switch 304) ) by disconnecting and driving the connection between node A and node C. This is preferable because the driving capability of the thin film transistor 353 can be improved by the potential of the thin film transistor 353 . The present embodiment can be implemented without the thin film transistor 356 (second switch 304). The circuit of the embodiment can be driven.

[0094] In addition, in the configuration of the source line driving circuit, the negation logic of the signals output from each pulse output circuit is The products (NAND) are used to generate signals to drive each source line. In the source line driver circuit, a number of pulse output circuits is provided that is greater than the number of source lines. It is preferable that the signal generating circuit 100 generates a signal to be output to the base line.

[0095] Fig. 5(A) shows a configuration example of the clock signal level shifter 201 shown in Fig. 2. . Since the configurations of the level shifter for the first clock signal (CLK1) and the level shifter for the second clock signal (CLK2) are the same in Fig. 5(A), only the level shifter for the first clock signal (C LK1) is shown. In Fig. 5(A), the first clock signal (CL K1) is amplitude-converted by the ERMOS circuit (Stage1), and buffer stages (S tage2, Stage3) are provided thereafter.

[0096] The operation of the circuit shown in Fig. 5(A) will be described. Here, the potential of the power supply used is three potentials of VSS, VDD0, and VDD, and VSS < VDD0 < VDD. By configuring to level-shift the amplitude of the first clock signal (CLK1) at the source line driving circuit input section, low power consumption and noise reduction can be achieved.

[0097] From the signal input section (CLK in1), the first input clock signal (CLK1) having an amplitude of L level / H level = VSS / VDD0 is input.

[0098] When the first input clock signal is at the H level, the thin film transistor 602 is turned on. . Here, the on-resistance of the thin film transistor 602 is designed to be sufficiently lower than the resistance value of the resistance element 601. Therefore, the node α becomes the L level.

[0099] When the node α is at the L level, the thin film transistor 604 is turned off. Here, the off-resistance of the thin film transistor 604 is designed to be sufficiently higher than the resistance value of the resistance element 603. Therefore, the node β becomes the H level, and the H level becomes approximately the same as VDD. As described above, Thus, the amplitude conversion is completed.

[0100] The level shifter described in FIG. 5(A) takes into consideration the load on the pulse after amplitude conversion, A buffer stage (Stage 2, S Stage 3) The same operation is performed in Stage 2 and Stage 3, and the signal is finally A pulse is output to the signal output section.

[0101] FIG. 5A shows a level shifter for the first clock signal (CLK1). However, the level shifter for the start pulse (SP) has the same configuration.

[0102] Figure 5(B) shows how the amplitude of the clock signal is converted. The amplitude of the input signal is , L level / H level = VSS / VDD0, and the amplitude of the output signal is L level / H level. The input voltage is VSS / VDD.

[0103] Figure 5(C) shows the amplitude conversion of the start pulse (SP). The amplitude of the output signal is the same as that of the clock signal, L level / H level = VSS / VDD0. The amplitude is L level / H level = VSS / VDD.

[0104] FIG. 6A shows the two-input NAND circuit 204 shown in FIG. The configuration of the circuit 204 is similar to that of an ERMOS circuit. The signal input section has two inputs, and thin film transistors 702 and 703 are arranged in series. The differences are different.

[0105] When a high level is input to both the signal input section (In1) and the signal input section (In2), Since the thin film transistors 702 and 703 are turned on, the signal output section (Out) is The level appears.

[0106] On the other hand, either or both of the signal input section (In1) and the signal input section (In2) When an L level is input to the terminal VDD, an H level of the potential VDD appears at the signal output section (Out).

[0107] Fig. 6B shows the buffer 205 shown in Fig. 2. The buffer 205 is an ERMO It is composed of S circuits (Stage 1 to 4). The operation of the ERMOS circuit is as follows: Since this has been explained in the section on the level shifter circuit, the above explanation is incorporated herein.

[0108] FIG. 6C shows the sampling switch 206 shown in FIG. The switch 206 receives a sampling pulse from the signal input unit (25) and The 12 thin film transistors 731 connected to the 12 thin film transistors 731 are controlled simultaneously. An analog video signal is input to the input electrodes (1) to (12) of the 731, and a sampling pulse It serves to write the potential of the video signal when the source is input to the source signal line.

[0109] FIG. 7 is a diagram showing a circuit configuration of a gate line driving circuit in the display device shown in FIG. A clock signal level shifter 751, a start pulse level shifter 752, a shift register The pulse output circuit 753, the NAND circuit 754, and the buffer 755 that constitute the register 781 are Yes.

[0110] The gate line driving circuit is supplied with a first clock signal (CLK1) and a second clock signal (CL These input signals are low voltage amplitude signals from the outside. Immediately after it is input as a signal of width, the level shifter 751 for the clock signal and the level shifter 752 for the start pulse The signal undergoes amplitude conversion by the level shifter 752 and is input to the driving circuit as a high voltage amplitude signal. can be.

[0111] In addition, the clock signal level shifter 751, the start pulse level shifter 752, Regarding the configurations and operations of the pulse output circuit 753, the NAND circuit 754, and the buffer 755, Since the above description is the same as that used in the source line driver circuit, the above description is used here. .

[0112] Next, examples of layout diagrams of the pulse output circuit shown in FIG. 3B are shown in FIGS. 8 to 10. 8 to 10, the first stage of the pulse output circuit is shown. 1 shows a pulse output circuit.

[0113] The pulse output circuit of FIG. 8 to FIG. 10 includes a power supply line 801, a power supply line 802, a control signal line 803, and a power supply line 804. , control signal line 804, control signal line 805, thin film transistors 351, 353, 355, 3 56, 358, and resistive elements 352, 354, 357.

[0114] 8 to 10, an oxide semiconductor layer 806, a first wiring layer 807, a second wiring layer 808, and a 8 and the contact hole 809. The first wiring layer 807 is a thin film The second wiring layer 808 is a layer including a gate terminal of a thin film transistor. This layer includes a source terminal and a drain terminal (a first terminal and a second terminal).

[0115] The connections of the circuit elements in FIGS. 8 to 10 are the same as those in FIG. 3(B). That is, the power supply line 801 is a wiring to which a high power supply potential VDD is supplied (also called a high power supply potential line). ), and the power supply line 802 is a wiring to which a low power supply potential VSS is supplied (also called a low power supply potential line). ), and the control signal line 803 is a line through which a start pulse (SP) is supplied, The signal line 804 is a wiring to which a first clock signal is supplied, and the control signal line 805 is a wiring to which a second clock signal is supplied. This is the wiring through which the clock signal 2 is supplied.

[0116] The resistor elements 352, 354, and 357 of the ERMOS circuit shown in FIG. Therefore, the resistance elements 352, 354, and 357 shown in FIG. is a resistor element that has a wide current path and exhibits high current driving capability. The resistor elements 352, 354, and 357 of the ERMOS circuit are meander-shaped. The oxide semiconductor layer is applied. It is possible to increase the resistance of 54,357.

[0117] In the layout diagrams of the pulse output circuit in FIG. 8 to FIG. 10, the thin film transistor 3 The channel regions of 51, 353, 355, 356, and 358 may be U-shaped. In addition, in FIG. 8, the sizes of the thin-film transistors are shown as being the same, but The size of the thin film transistor may be appropriately changed depending on the size of the thin film transistor.

[0118] Next, the resistor element 354 and the thin film transistor in the layout diagrams described with reference to FIGS. The structure of the inverter circuit formed by the resistor 355 is shown in Figs. 11(A) to (C). The resistor element 354 and the thin film transistor shown in FIGS. The resistor 355 is a cross-sectional view corresponding to the dotted lines AB and CD in FIGS. This shows the following.

[0119] FIG. 11(A) is a cross-sectional view corresponding to dotted lines AB and CD in FIG. In A), the resistor 354 uses the first oxide semiconductor layer 905 as a resistor component. In addition, one end of the first oxide semiconductor layer 905 is connected to a first wiring layer 807. The wiring 901 is connected to the insulating layer 903 via a contact hole 904. The end is connected to a second wiring 907 included in the second wiring layer 808 .

[0120] In FIG. 11A, a thin film transistor 355 includes a gate terminal 902 on a substrate, a gate An insulating layer 903 on a gate terminal 902 which functions as an insulating layer, an insulating layer which becomes a channel forming region, A second oxide semiconductor layer 906 on the layer 903, a source terminal and a drain terminal (first terminal and A second wiring 907 and a third wiring 908 over the second oxide semiconductor layer 906 functioning as a second terminal It has wiring 908.

[0121] The first wiring 901 is one terminal of the resistor element 354. The wiring 907 is the other terminal of the resistor element 354 and the thin film transistor 355. For the first wiring 90, it is the first terminal and also the wiring that connects the two. 8 is a second terminal for the thin film transistor 355 and is supplied with a low power supply potential VSS. In other words, the connection wiring and the low (high) voltage A part of the power supply line is used as the first terminal or the second terminal of each thin film transistor. .

[0122] In addition, in FIG. 11A, the first oxide semiconductor layer 905 and the second oxide semiconductor layer The thickness of the wiring 906 is not uniform. The first oxide semiconductor layer 905 and the second oxide semiconductor layer 906 correspond to the overlapping region. The thicknesses of the first oxide semiconductor layer 905 and the second oxide semiconductor layer 906 not corresponding to the region are This is because the thickness of the second wiring 907 and the third wiring 908 is larger than that of the first wiring 909. In the same manner, the first oxide semiconductor layer 905 and the second oxide semiconductor layer 906 are also partially This is because it is etched.

[0123] FIG. 11(B) is a cross-sectional view corresponding to dotted lines AB and CD in FIG. In B), the resistor element 354 is formed in a meandering shape by the first oxide semiconductor layer 90 5 is used as a resistance component. The line 901 is connected to the insulating layer 903 via a contact hole 904, and the other end The second wiring 907 is connected to the thin film transistor. Since the thin film transistor is the same as that described above, the above description is incorporated herein.

[0124] FIG. 11C is a cross-sectional view corresponding to dotted lines AB and CD in FIG. In (C), the resistor element 354 is a first oxide semiconductor layer 9 formed in a meandering shape. The first oxide semiconductor layer 905 is used as a resistor component. The other end is connected to a fourth wiring 912 included in the wiring layer 808 and is included in the second wiring layer 808. The thin film transistor has a structure similar to that described in FIG. Since this is the same as the thin film transistor described above, the above description is incorporated herein. In the resistor element 354, a fourth wiring 912 is formed directly on the first oxide semiconductor layer 905. Therefore, a good bond can be formed between the first oxide semiconductor layer and the fourth wiring.

[0125] Next, the specific material composition of the ERMOS circuit shown in Figures 11(A) to (C) will be explained. do.

[0126] In FIG. 11(A) to (C), the substrate 900 is made of barium borosilicate glass or alumina. A glass substrate such as a borosilicate glass substrate can be used. The material of the terminal 902 is a low-resistance conductive material such as aluminum (Al) or copper (Cu). It is also possible to form a ceramic capacitor by combining aluminum (Al) with a heat-resistant conductive material. Heat-resistant conductive materials include titanium (Ti), tantalum (Ta), Tungsten (W), Molybdenum (Mo), Chromium (Cr), Neodymium (Nd), Scan Sc, or an alloy containing the above elements, or The present invention can be applied to a film of an alloy of the above elements or a film of a nitride of the above elements. do.

[0127] The insulating layer 903 is a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, or a silicon oxynitride film. The insulating film can be formed of an insulating film such as a silicon film, an aluminum oxide film, or a tantalum oxide film. Alternatively, the insulating film may be formed as a laminated structure of these insulating films. The film is a composition that contains more oxygen than nitrogen, and the concentration range is 55-65 atomic % of nitrogen, 1-20 atomic % of nitrogen, 25-35 atomic % of silicon, 0 atomic % of hydrogen Each element is added at any concentration within the range of 1 to 10 atomic percent so that the total is 100 atomic percent. The silicon nitride oxide film is a film containing more nitrogen than oxygen. The concentration range is 15-30 atomic % for oxygen and 20-35 atomic % for nitrogen. %, Si is 25 to 35 atomic %, and hydrogen is 15 to 25 atomic %, for a total of 100 atoms. % of each element.

[0128] The first oxide semiconductor layer 905 and the second oxide semiconductor layer 906 are made of InMO3 (ZnO ) m The thin film is formed from a material represented by (m>0). Note that M is gallium (Ga), iron (F e), nickel (Ni), manganese (Mn), or cobalt (Co); It indicates a metal element or elements. For example, M may be gallium (Ga). In addition to gallium (Ga) and nickel (Ni), gallium (Ga) and iron ( In some cases, the above metal elements other than gallium (Ga), such as gallium (Ga), may be included. In the nitride semiconductor layer, in addition to the metal element M, iron (Fe) is also included as an impurity element. , nickel (Ni) or other transition metal elements, or oxides of said transition metals In addition, the amount of sodium (Na) contained in the oxide semiconductor layer is 5×10 18 ( atoms / cm 3 ) or less, preferably 1×10 18 (atoms / cm 3 ) or less It shall be so.

[0129] The second wiring 907 and the third wiring 908 are made of aluminum (Al), chromium (Cr), or the like. (Cr), Tantalum (Ta), Titanium (Ti), Molybdenum (Mo), Tungsten ( W), or an alloy containing the above elements or a combination of the above elements Also, it may be formed as a laminated structure made of these materials. stomach.

[0130] The silicon oxide layer 909 is formed from a silicon oxide film formed by sputtering. The silicon nitride layer 910 formed on the entire surface of the substrate is formed by silane (SiH4) and ammonia ( It is formed by the plasma CVD method using gases containing hydrogen compounds such as NH3. Therefore, the silicon nitride layer 910 contains a high concentration of hydrogen.

[0131] As shown in FIG. 12A, the first oxide semiconductor layer 905 and the second oxide semiconductor layer Buffer layers 911a to 911b are provided between the dielectric layer 906 and the second and third wirings 907 and 908. 11c may also be provided.

[0132] Note that the above-described buffer layers 911a to 911c are the first oxide semiconductor layer 905 and The In- It is a low-resistance oxide semiconductor layer formed based on a Ga-Zn-O-based non-single crystal film. In the following description, for convenience, the first oxide semiconductor layer 905 and the second oxide semiconductor layer 906 will be referred to as “first oxide semiconductor layer 905” and “second oxide semiconductor layer 906” later. The oxide semiconductor film on which the buffer layer 911a is formed is referred to as a first oxide semiconductor film. The oxide semiconductor film in which 911c is formed is referred to as a second oxide semiconductor film.

[0133] For example, when an oxide semiconductor film is formed by sputtering, the sputtering The resistance value of the oxide semiconductor film can be changed by changing the oxygen concentration of the deposition gas. Specifically, by increasing the oxygen concentration in the sputtering gas, it is possible to form an oxide semiconductor. The first oxide semiconductor film and the second oxide semiconductor film are formed by sputtering. One of the conditions for forming the oxide semiconductor film is a sputtering temperature used for forming the first oxide semiconductor film. The gas flow rate of argon gas was 10 sccm and the oxygen gas flow rate was 5 sccm. The sputtering gas used for depositing the semiconductor film is argon gas with a flow rate of 40 sccm. The buffer layers 911a to 911c have n-type conductivity and are activated. The energy (ΔE) is 0.1 eV or less. Note that the In-Ga-Zn-O system non-single crystal film The buffer layers 911a to 911c formed based on the above contain at least an amorphous component. The buffer layers 911a to 911c have an amorphous structure with crystal grains (nanocrystals). The crystal grains (nanocrystals) in the buffer layers 911a to 911c may be included. The diameter of the nanoparticles is 1 nm to 10 nm, typically about 2 nm to 4 nm.

[0134] A buffer layer having a lower resistance than the first oxide semiconductor layer 905 and the second oxide semiconductor layer 906 By providing the layers 911a to 911c, the second wiring 907, which is a conductor, and the first oxide A semiconductor layer 905, a second wiring 907 and a third wiring 908 which are conductors, and a second oxide A better junction is formed between the semiconductor layer 906 and the semiconductor layer 906 than a Schottky junction, and the junction is also thermally stable. In addition, in the thin film transistor 355, the buffer layers 911b and 91 By providing 1c, good mobility can be maintained even at a high drain voltage.

[0135] As shown in FIG. 12B, the first oxide semiconductor layer 905 and the second oxide semiconductor layer Buffer layers 911a, 911b, 911c, 911d, and 911e are provided above and below the substrate layer 906. It is also possible to do so.

[0136] By providing the buffer layer 911d, the first wiring 901, which is a conductor, and the first oxide A better junction is formed between the semiconductor layer 905 and the semiconductor layer 905 than a Schottky junction, and the junction is also thermally stable. It is possible to perform constant operation.

[0137] Next, a thin film transistor different from those shown in FIGS. 11(A) to (C) and 12(A) and (B) will be described. A thin film transistor having such a structure is shown and described in Figs. 13(A) and (B). In A) and B), the resistor element and the thin-film transistor corresponding to the lines AB and CD in FIG. The cross-sectional structure of the capacitor is shown in Fig. 11(A), (B), and (C) with the same reference numerals. It is attached.

[0138] In FIG. 13A, a silicon oxide layer is formed over the second oxide semiconductor layer 906. A channel protection layer 1001 is provided. The channel protection layer 1001 and the second oxide semiconductor layer 9 9, a second wiring 907 and a third wiring 908 are provided on the substrate 906. , the second wiring 907, the third wiring 908, and the channel protection layer 1001. 13B, the first oxide semiconductor layer 9 9, the second oxide semiconductor layer 905, the second wiring 907, and the third wiring 908. It is also possible to provide buffer layers 911a, 911b, and 911c between them.

[0139] In Figs. 11(A)-(C), 12(A) and (B), and 13(A) and (B), the reverse stagger The thin film transistor of the present embodiment has a reversed structure. The present invention is not limited to the staggered type. For example, the same can be applied to a coplanar type thin film transistor. An example of the cross-sectional structure is shown in FIG. 14(A) and (B), and will be described. In addition, in FIGS. 14(A) and 14(B), the resistance elements corresponding to the lines AB and CD in FIG. 11(A), (B), and (C) show cross-sectional structures of the thin film transistors. The same reference numerals are used for the above.

[0140] In FIG. 14A, one end of a first oxide semiconductor layer 905 is connected to a first wiring 901. The other end of the first oxide semiconductor layer 905 and one end of the second oxide semiconductor layer 906 are The other end of the second oxide semiconductor layer 906 is connected to the third wiring 907. Further, an oxide semiconductor layer 906 is provided on the second oxide semiconductor layer 908. A first oxide semiconductor layer 909 and a second silicon nitride layer 910 are stacked. Only a silicon nitride layer 910 is provided on the 905. Also, as shown in FIG. In this manner, a buffer layer 1 is provided between the second wiring 907 and the third wiring 908 and the insulating layer 903. It is also possible to provide a configuration in which 010a and 1010b are provided.

[0141] Figures 11(A)-(C), 12(A), (B), 13(A), (B), and 14(A) In FIG. 9B, silane (SiH4) and The plasma CVD method uses gases containing hydrogen compounds such as ammonia (NH3) and A silicon nitride layer 910 is provided.

[0142] The ERMOS circuit having the above-mentioned structure has a first oxide layer 910 in direct contact with the silicon nitride layer 910. A resistive element having a resistive component of a nitride semiconductor layer 905 and a silicon oxide layer 909 (channel protection The second oxide semiconductor layer 906 on which the silicon nitride layer 910 is provided is formed through the layer 1001. A thin film transistor having a channel formation region is provided. Hydrogen can be introduced into the layer 905 at a higher concentration than into the second oxide semiconductor layer 906. As a result, the resistance value of the first oxide semiconductor layer 905 is reduced by the resistance value of the second oxide semiconductor layer 906. can be lower than the value.

[0143] Next, the manufacturing process of the ERMOS circuit will be explained using the cross-sectional views of Figures 15(A) to (C). Here, a manufacturing process of the ERMOS circuit shown in FIG.

[0144] A first conductive film is formed on a substrate 900. The first conductive film is formed by a sputtering method, a pure film, or the like. Thin film deposition methods such as air vapor deposition, pulsed laser deposition, and ion plating are used. The material of the first conductive film is a low-resistance conductive material such as aluminum (Al) or copper (Cu). It can be made of aluminum (Al) and a heat-resistant conductive material. The heat-resistant conductive material can be titanium (Ti), tantalum (T a), Tungsten (W), Molybdenum (Mo), Chromium (Cr), Neodymium (Nd), An element selected from scandium (Sc), or an alloy containing the above elements, or Applying an alloy film combining the above elements or a nitride containing the above elements as components. Next, a first photolithography process is performed to apply a resist to the first conductive film. Further, the first conductive film is selectively etched using the resist as a mask; A first wiring 901 and a gate terminal 902 are formed.

[0145] Next, an insulating film is formed to cover the first wiring 901 and the gate terminal 902. The film is formed by sputtering, vacuum deposition, pulsed laser deposition, ion plating, and plating. Thin film deposition methods such as the Zuma CVD method are used. Silicon oxide film, nitrogen film, etc. are used as insulating films. silicon oxide film, silicon oxynitride film, silicon nitride oxide film, aluminum oxide film, tungsten oxide film In addition, a laminated structure of these insulating films can be used. Next, a second photolithography process is performed to form a resist on the insulating film. Furthermore, the insulating film is selectively etched using the resist as a mask to form a first wiring. An insulating layer 903 is formed in which a contact hole 904 is provided to reach the wiring. The cross-sectional view at the end of this process is shown in FIG.

[0146] Next, a second oxide semiconductor film is formed. method, vacuum deposition method, pulsed laser deposition method, ion plating method, plasma CVD method, etc. When forming a film by sputtering, In2O3, G It is preferable to use targets made of sintered Al2O3 and ZnO. The deposition conditions for the sputtering method are In2O3:Ga A sintered target of 2O3:ZnO=1:1:1 was used, and the pressure was 0.4 Pa and the direct current was The (DC) power supply was 500 W and the argon gas flow rate was 40 sccm.

[0147] Next, the second conductive film is formed. The second conductive film can be formed by a sputtering method, a vacuum deposition method, or the like. A thin film deposition method such as pulsed laser deposition or ion plating is used. The material of the second conductive film is aluminum (Al), chromium (Cr), tantalum (T a), titanium (Ti), molybdenum (Mo), tungsten (W), or or an alloy film containing the above elements or a combination of the above elements. Moreover, it may be formed as a laminated structure made of these materials.

[0148] Next, a third photolithography process is performed to form a resist on the second conductive film. Further, the second oxide semiconductor film and the second conductive film are selectively formed using the resist as a mask. The second wiring 907, the third wiring 908, and the buffer layer 1010a are etched. The etching method used here may be wet etching or dry etching. Etching is used. For example, the second conductive film is an aluminum (Al) film, or When using an aluminum alloy film, wet etching is performed using a solution of phosphoric acid, acetic acid, and nitric acid. Similarly, a titanium (Ti) film or a titanium alloy film can be used as the second conductive film. When using a membrane, use ammonia peroxide water (hydrogen peroxide:ammonia:water = 5:2:2). In this case, wet etching can be performed.

[0149] Next, a first oxide semiconductor film is formed. Thin film deposition methods such as the ion plating method, vacuum deposition method, pulsed laser deposition method, etc. The first oxide semiconductor film is deposited using a deposition method. One of the conditions for sputtering is to form the film under conditions where the oxygen concentration in the film is high. 3: Ga2O3:ZnO = 1:1:1 mixed and sintered target was used, and the pressure was 0.4P a, DC power supply 500 W, argon gas flow rate 10 sccm, oxygen gas flow rate 5 s It is ccm.

[0150] In addition, before the first oxide semiconductor film is formed, argon gas is introduced to generate plasma. A reverse sputtering process is performed to form an insulating layer 903, a first wiring 901, a second wiring 907, and It is preferable to remove dust adhering to the third wiring 908. The treatment is performed in an atmosphere of argon to which oxygen has been added, so that the first wiring 90, which is a conductor, The surfaces of the first, second wiring 907, and third wiring 908 are oxidized to form a second oxide semiconductor film. This allows the contact interface between the thin-film transistor and the semiconductor substrate to have a high resistance. The reverse sputtering process is a process in which the target is turned on and off. The substrate was heated by applying a voltage to the substrate side using an RF power supply in an argon atmosphere without applying a voltage to the substrate side. This is a treatment method in which plasma is formed on a plate to modify its surface.

[0151] Next, a fourth photolithography step is performed to apply a resist to the first oxide semiconductor film. Furthermore, the first oxide semiconductor film is selectively etched using the resist as a mask. A first oxide semiconductor layer 905 and a second oxide semiconductor layer 906 are formed. The cross-sectional view at the stage where the steps up to this point have been completed corresponds to FIG.

[0152] Next, a silicon oxide film is formed by sputtering. The film is formed using a silicon target and a sputtering gas containing argon and oxygen. It is also possible to use silicon oxide as a target and argon as a sputtering gas. A silicon oxide film can also be formed. Next, a fifth photolithography step is performed. A resist is formed on the silicon oxide film. Then, the silicon oxide film is patterned by using the resist as a mask. The silicon film is selectively etched to form a silicon oxide layer 90 on the second oxide semiconductor layer 906. Form 9.

[0153] Next, a silicon nitride layer 910 having a function as a passivation film is formed on the entire surface of the substrate. The silicon nitride layer 910 is formed using a gas such as silane (SiH4) and ammonia (NH3). It is formed by the plasma CVD method using gases containing hydrogen compounds, and contains high concentrations of hydrogen. The silicon nitride layer is

[0154] Next, a heat treatment is performed at 200°C to 600°C, typically 250°C to 500°C. For example, The product is then placed in a furnace and heat-treated at 350°C for 1 hour in a nitrogen atmosphere. A cross-sectional view of this stage corresponds to FIG.

[0155] In the above manner, the resistor 354 and the thin film transistor 355 are formed using the oxide semiconductor layer. It can be manufactured.

[0156] The above-mentioned process sequence is an example and is not particularly limited. An example of the manufacturing process will be shown and described.

[0157] A first conductive film is formed on a substrate 900. Then, a first photolithography process is performed. Then, a resist is formed on the first conductive film. Then, the first conductive film is patterned by using the resist as a mask. The conductive film is selectively etched to form a first wiring 901 and a gate terminal 902 .

[0158] Next, an insulating film is formed to cover the first wiring 901 and the gate terminal 902. A second oxide semiconductor film is formed. Then, a second conductive film is formed. Then, a second photoconductor film is formed. A lithography process is performed to form a resist on the second conductive film. The second conductive film and the second oxide semiconductor film are selectively etched using the second conductive film and the second oxide semiconductor film as a mask. The first wiring 907, the third wiring 908 and the buffer layers 1010a and 1010b are formed. The cross-sectional view after completing the steps up to this stage corresponds to Figure 16(A).

[0159] Next, a third photolithography process is performed to form a resist on the insulating film. Then, the insulating film is selectively etched using the resist as a mask to reach the first wiring 901. An insulating layer 903 having a contact hole 904 is formed.

[0160] Next, a first oxide semiconductor film is formed. Then, a fourth photolithography step is performed. Then, a resist is formed over the first oxide semiconductor film. The first oxide semiconductor film is selectively etched to form the first oxide semiconductor layer 905 and the second oxide semiconductor layer 906. The oxide semiconductor layer 906 is formed. A cross-sectional view of the stage where the steps up to this point are completed is shown in FIG. )

[0161] Next, a silicon oxide film is formed by sputtering. A lithography process is performed to form a resist on the silicon oxide film. A silicon oxide film is selectively etched as a mask to cover the second oxide semiconductor layer 906. A silicon oxide layer 909 is formed.

[0162] Next, gas containing hydrogen compounds such as silane (SiH4) and ammonia (NH3) is Using the plasma CVD method, a passivation film was formed on the entire surface of the substrate. A silicon nitride layer 910 is deposited.

[0163] Next, heat treatment is performed at 200°C to 600°C in a nitrogen atmosphere. A cross-sectional view of this stage corresponds to FIG.

[0164] Through the above steps, the resistor 354 and the thin film transistor formed using the oxide semiconductor layer are In addition, in the steps described in FIG. 16(A) to (C), After the contact hole 904 is formed, the first oxide semiconductor film can be formed. Therefore, the number of steps in which the bottom surface of the contact hole is exposed can be reduced. This allows greater freedom in the selection of materials for the wiring 901.

[0165] The resistor and the thin film transistor described in this embodiment are formed using an oxide semiconductor layer. Therefore, the driving circuit having the resistor element and the thin film transistor has good dynamic characteristics. In addition, silane (SiH 4) and the plasma CVD method using gases containing hydrogen compounds such as ammonia (NH3) a silicon nitride layer formed by the above method is provided in direct contact with the first oxide semiconductor layer, In addition, an oxide semiconductor layer serving as a barrier layer is formed on the second oxide semiconductor layer used in the thin film transistor. A silicon nitride layer is provided through the silicon layer. The first oxide semiconductor layer that is in direct contact with the silicon oxide layer has a higher concentration than the second oxide semiconductor layer. As a result, the resistance value of the first oxide semiconductor layer is reduced by the resistance value of the second oxide semiconductor layer. This makes it possible to reduce the resistance of the thin film transistor fabrication process and To provide a driving circuit in which a manufacturing process for a resistor element is not required separately and the manufacturing process is reduced. It is possible.

[0166] (Embodiment 2) In this embodiment, an example of a resistor element and a thin film transistor different from those in the first embodiment will be described. This will be described with reference to Fig. 17. Fig. 17 shows the line AB in Fig. 8 described in the first embodiment. 13 shows the cross-sectional structures of the resistor elements and thin film transistors corresponding to the lines CD and CD.

[0167] A first wiring 901 and a gate terminal 902 are provided on a substrate 900. An insulating layer 903 is provided on the line 901 and the gate terminal 902. The materials of the line 901, the gate terminal 902, and the insulating layer 903 are the same as those described in the first embodiment. Therefore, the description of the first embodiment is incorporated in this embodiment.

[0168] A first oxide semiconductor layer containing nitrogen at a high concentration is formed on the insulating layer 903 so as to overlap the first wiring 901. A second oxide semiconductor layer containing nitrogen at a high concentration overlapping the conductor layer 2001 and the gate terminal 902. A conductor layer 2002 is provided. The first wiring 901 is a contact formed in an insulating layer 903. The first oxide semiconductor layer 2001 containing nitrogen at a high concentration is in contact with the hole 904. There are.

[0169] Note that the first oxide semiconductor layer 2001 containing nitrogen at a high concentration and the The second oxide semiconductor layer 2002 is the same as the first oxide semiconductor film and The nitrogen oxide formed from the oxide semiconductor film formed under different film formation conditions from the second oxide semiconductor film. Specifically, the oxide semiconductor layer has a high oxygen concentration. The ratio of nitrogen (N) (N / O) is in the range of 0.05 to 0.8, preferably 0.1 or less. The oxide semiconductor layer has a refractive index of 0.5 or less.

[0170] For example, when an oxide semiconductor film containing nitrogen at a high concentration is formed by a sputtering method, The film may be formed using a sputtering gas containing nitrogen gas. , a target with In2O3:Ga2O3:ZnO=1:1:1 (In:Ga:Zn= 1:1:0.5) was used, pressure 0.4 Pa, direct current (DC) power supply 500 W, argon gas flow The flow rate of the gas is 35 sccm, and the nitrogen gas flow rate is 5 sccm. C) Using a power source is preferable because it reduces dust and makes the film thickness distribution uniform. A photolithography process is performed on an oxide semiconductor film containing nitrogen at a high concentration. A first oxide semiconductor layer 2001 containing nitrogen and a second oxide semiconductor layer 2002 containing nitrogen at a high concentration A semiconductor layer 2002 is formed.

[0171] Next, a second wiring 907 and a third wiring 908 are provided. The second wiring 907 is made of a high-concentration One end of the first oxide semiconductor layer 2001 containing nitrogen at a high concentration and one end of the second oxide semiconductor layer 2002 containing nitrogen at a high concentration are The third wiring 908 covers one end of the second oxide semiconductor layer 2002. The second wiring 907 and the third oxide semiconductor layer 2002 are connected to each other. The wiring 908 can be made of the material described in the first embodiment. In this embodiment, the description of the first embodiment is incorporated.

[0172] Next, a silicon oxide layer 2002 containing nitrogen at a high concentration is formed on the second oxide semiconductor layer 2002. The silicon oxide layer is a silicon oxide film formed by sputtering. The silicon oxide film is formed by selectively etching the silicon. The film is formed using a sputtering gas containing argon and oxygen, or using silicon oxide. The film is formed by using carbon as a target and argon as a sputtering gas. can be done.

[0173] At this stage, the reaction is heated to 200°C to 600°C in an atmosphere containing a substance that serves as a hydrogen atom source. The heat treatment is carried out at 350°C, typically 250°C to 500°C. The heat treatment is carried out for 1 hour. The atmosphere containing the substance that supplies hydrogen atoms is hydrogen and Alternatively, a mixed atmosphere of a rare gas such as argon or the like can be used.

[0174] Nitrogen in the oxide semiconductor layer prevents atoms constituting the oxide semiconductor layer from being densely packed in the film. It also has the effect of promoting the diffusion and dissolution of hydrogen into the film. Hydrogen is introduced into the first oxide semiconductor layer 2001 containing nitrogen at a high concentration by the treatment. As a result, the hydrogen concentration in the first oxide semiconductor layer 2001 containing nitrogen at a high concentration is increased. The hydrogen concentration in the second oxide semiconductor layer 2002 containing nitrogen is higher than that in the second oxide semiconductor layer 2002. The resistance value of the first oxide semiconductor layer 2001 containing nitrogen at a high concentration was The resistance value of the second oxide semiconductor layer 2002 can be made lower than that of the second oxide semiconductor layer 2002 having the first oxide semiconductor layer 2002.

[0175] In addition, hydrogen compounds such as silane (SiH4) and ammonia (NH3) are applied to the entire surface of the substrate. A silicon nitride layer 910 is formed by a plasma CVD method using a gas containing The silicon nitride layer 910 is a silicon nitride containing a high concentration of hydrogen. A first oxide semiconductor layer 200 containing nitrogen at a high concentration in direct contact with a silicon nitride layer 910 It is possible to further increase the hydrogen concentration in 1 and achieve lower resistance.

[0176] As a result, the first oxide semiconductor layer 2001 having low resistance and containing nitrogen at a high concentration was formed. The resistor element 354 used and the second oxide semiconductor containing nitrogen at a high concentration to maintain a high resistance value. A thin film transistor 355 can be formed using the conductor layer 2002 .

[0177] In this embodiment, a cross-sectional structure of a resistance element corresponding to the line AB in FIG. However, as shown in FIG. 9 and FIG. 10, the first oxide semiconductor layer containing nitrogen at a high concentration was It is also possible to make it meandering. It is also possible to form wiring layers on both ends of the nitrogen-containing oxide semiconductor layer at the same time.

[0178] In this embodiment mode, a cross-sectional structure of a channel-etch type thin film transistor is shown. However, it is also possible to use a channel stop type thin film transistor. In the above, an inverted staggered thin-film transistor is shown, but a coplanar thin-film transistor is also shown. It is also possible to use a transistor.

[0179] The resistor element and the thin film transistor described in this embodiment are made of an oxide containing nitrogen at a high concentration. Therefore, the resistor element and the thin film transistor are formed using a nitride semiconductor layer. The driving circuit has good dynamic characteristics. Heat treatment is performed at 200℃ to 600℃, typically 250℃ to 500℃, in air. As a result, hydrogen is introduced into the first oxide semiconductor layer containing nitrogen at a high concentration and applied to the resistor element. Therefore, the first oxide semiconductor layer containing nitrogen at a high concentration contains nitrogen at a high concentration. The hydrogen concentration is higher in the second oxide semiconductor layer than in the first oxide semiconductor layer. The resistance value of the first oxide semiconductor layer containing nitrogen at a high concentration is This makes it possible to lower the resistance of the thin film transistor. A driving circuit in which the number of manufacturing steps is reduced by eliminating the need for a separate manufacturing step for a resistor element and a manufacturing step for a semiconductor device. can be provided.

[0180] (Embodiment 3) In this embodiment, the oxide semiconductor layer described in Embodiment 1 and the oxide semiconductor layer described in Embodiment 2 are A resistor element and a thin film transistor manufactured using an oxide semiconductor layer containing nitrogen at a high concentration The star will be described with reference to Figs. 18(A) to 18(C) and Figs. 19(A) and 19(B). 18(A) to (C) and 19(A) and (B) are diagrams showing the relationship between the AB line and the CD line in FIG. 3 shows the cross-sectional structure of a corresponding resistor element and thin film transistor.

[0181] Specifically, in this embodiment, the oxide containing high concentration of nitrogen described in the second embodiment is Regarding a structure in which a semiconductor layer is used instead of the buffer layer described in the first embodiment, FIG. This will be explained using (A) to (C) and Figures 19 (A) and (B).

[0182] First, a first conductive film is formed on a substrate 900. The first conductive film is formed by a sputtering method. Thin film deposition, such as the ion plating method, vacuum deposition method, pulsed laser deposition method, etc. Next, a first photolithography process is performed to form a resist on the first conductive film. Furthermore, the first conductive film is selectively etched using the resist as a mask. Then, a first wiring 901 and a gate terminal 902 are formed. An insulating film is formed to cover the port terminal 902. The insulating film can be formed by a sputtering method, a vacuum deposition method, or the like. Thin films such as pulsed laser deposition, ion plating, and plasma CVD Then, a second photolithography process is performed to remove the resist on the insulating film. Furthermore, the insulating film is selectively etched using the resist as a mask to form a contact. An insulating layer 903 having a contact hole 904 is formed. The materials for the terminal 902 and the insulating layer 903 are the same as those described in the first embodiment. Therefore, the description of the first embodiment is used in this embodiment. The cross-sectional view at this stage corresponds to FIG.

[0183] Next, the oxide semiconductor film 950 is formed. method, vacuum deposition method, pulsed laser deposition method, ion plating method, plasma CVD method, etc. When forming a film by sputtering, In2O3, G It is preferable to use a target made of sintered Al2O3 or ZnO. The first condition is a target made by mixing and sintering In2O3:Ga2O3:ZnO=1:1:1. The pressure was 0.4 Pa, the direct current (DC) power was 500 W, and the argon gas flow rate was 10 sccm. The oxygen gas flow rate was 5 sccm.

[0184] Next, an oxide semiconductor film 951 containing nitrogen at a high concentration is formed. The oxide semiconductor film 951 can be formed by a sputtering method, a vacuum deposition method, a pulsed laser deposition method, or the like. Thin film deposition methods such as ion plating are used. When this is carried out, it is preferable to use targets made of sintered In2O3, Ga2O3, and ZnO. One of the conditions for forming the oxide semiconductor film 951 containing nitrogen at a high concentration by sputtering is as follows. A target made of In2O3:Ga2O3:ZnO=1:1:1 mixed and sintered was used. Pressure 0.4 Pa, DC power supply 500 W, argon gas flow rate 35 sccm, nitrogen gas The flow rate is 5 sccm. The cross-sectional view at the end of the process up to this point corresponds to FIG. 18(B). do.

[0185] Next, a third photolithography process is performed to form an oxide semiconductor containing nitrogen at a high concentration. A resist is formed over the film 951. Then, the oxide semiconductor film The oxide semiconductor film 950 and the oxide semiconductor film 951 containing nitrogen at a high concentration are selectively etched to form a first a stack of a first oxide semiconductor layer 960 and a second oxide semiconductor layer 961 containing nitrogen at a high concentration; , and the second oxide semiconductor layer 962 and the second oxide semiconductor layer The cross-sectional view of the stage where the process up to this point is completed corresponds to FIG. 18(C). do.

[0186] At this stage, the material is heated to 200°C to 600°C in an atmosphere containing a substance that serves as a hydrogen atom source. The heat treatment is carried out at 350°C, typically 250°C to 500°C. The heat treatment is carried out for 1 hour. The atmosphere containing the substance that supplies hydrogen atoms is hydrogen and Alternatively, a mixed atmosphere of a rare gas such as argon or the like can be used.

[0187] Nitrogen in the oxide semiconductor layer prevents atoms constituting the oxide semiconductor layer from being densely packed in the film. It also has the effect of promoting the diffusion and dissolution of hydrogen into the film. The first oxide semiconductor layer 961 containing nitrogen at a high concentration and the second oxide semiconductor layer 962 containing nitrogen at a high concentration are formed by the treatment. As a result, hydrogen is introduced into the second oxide semiconductor layer 963 containing nitrogen at a high concentration. The first oxide semiconductor layer 961 having a high concentration of nitrogen and the second oxide semiconductor layer 9 It is possible to lower the resistance value of 63.

[0188] Next, the second conductive film is formed. The second conductive film can be formed by a sputtering method, a vacuum deposition method, or the like. Thin film deposition methods such as pulsed laser deposition and ion plating are used. Then, a fourth photolithography process is performed to form a resist on the second conductive film. Furthermore, the second conductive film is selectively etched using the resist as a mask to form a second wiring 9. The second wiring 907 and the third wiring 908 are formed from the material The material described in the first embodiment can be used as the material. In the etching process, the second wiring 907 and The oxide semiconductor layer containing nitrogen at a high concentration in a region that does not overlap with the third wiring 908 is etched. The oxide semiconductor layer in the region is also partially etched, and the oxide The semiconductor layers 964 and 966 and the oxide semiconductor layers 965, 967, and 968 each containing nitrogen at a high concentration are 19A shows a cross-sectional view of the stage after the steps up to this point are completed.

[0189] Next, a silicon oxide film is formed by sputtering. The film is formed using a silicon target and a sputtering gas containing argon and oxygen. It is also possible to use silicon oxide as a target and argon as a sputtering gas. A silicon oxide film can also be formed. Then, a fifth photolithography step is performed. Then, a resist is formed on the silicon oxide film. Then, the resist is used as a mask to perform a process of etching the silicon oxide film. The silicon film is selectively etched to form a silicon oxide layer 909 .

[0190] Next, a silicon nitride layer 910 that functions as a passivation film is formed. The silicon nitride layer 910 is formed by hydriding silicon nitride (HNO3) with silane (SiH4) and ammonia (NH3). The resistive element 354 is formed by the plasma CVD method using a gas containing a compound. A thin film transistor 355 is formed. The cross-sectional view of the stage where the process up to this point is completed is shown in FIG. Equivalent to 9(B).

[0191] The resistor 354 and the thin film transistor 355 described in this embodiment are formed using an oxide semiconductor layer. Between the wiring layer and the conductive wiring layer, hydrogen is introduced into the oxide layer containing high concentration of nitrogen, which has low resistance. Therefore, the oxide semiconductor layers and the wiring layers are The junction with the Schottky junction is better than that with the Schottky junction, and exhibits thermally stable operation. In addition, in the thin film transistor 355, an oxide semiconductor layer containing nitrogen at a high concentration can be formed. The formation of 967 and 968 maintains good mobility even at high drain voltages. It is possible.

[0192] In the above-described manufacturing process, a nitrogen-containing oxide semiconductor layer containing a high concentration is formed after the etching process of the oxide semiconductor layer. In the above example, heat treatment is performed to introduce hydrogen into an oxide semiconductor layer having a high concentration. The step of removing the nitrogen-containing oxide semiconductor film may be performed at any time after the formation of the oxide semiconductor film containing nitrogen and before the formation of the second conductive film. For example, after the formation of an oxide semiconductor film containing nitrogen at a high concentration, It is also possible to carry out the heat treatment.

[0193] In this embodiment, a cross-sectional structure of a resistance element corresponding to the line AB in FIG. However, as shown in FIGS. 9 and 10, the oxide semiconductor layer is formed in a meandering shape. As shown in FIG. 10, it is also possible to form an oxide semiconductor containing a high concentration of nitrogen. It is also possible to form wiring layers on both ends of the body layer.

[0194] In this embodiment mode, a cross-sectional structure of a channel-etch type thin film transistor is shown. However, it is also possible to use a channel stop type thin film transistor. In the above, an inverted staggered thin-film transistor is shown, but a coplanar thin-film transistor is also shown. It is also possible to use a transistor.

[0195] The resistor and the thin film transistor described in this embodiment include an oxide semiconductor layer and a high-concentration The resistor element and the gate insulating film are formed using an oxide semiconductor layer containing nitrogen. Driving circuits with thin film transistors have good dynamic characteristics. On the first oxide semiconductor layer, a water vapor such as silane (SiH4) and ammonia (NH3) is A silicon nitride layer is formed by a plasma CVD method using a gas containing a silicon compound. A second insulating film is provided in direct contact with the oxide semiconductor layer and is applied to a thin film transistor. A silicon nitride layer is provided on the oxide semiconductor layer via a silicon oxide layer serving as a barrier layer. Therefore, the first oxide layer directly contacting the silicon nitride layer containing high hydrogen concentration is Hydrogen is introduced into the first oxide semiconductor layer at a higher concentration than into the second oxide semiconductor layer. The resistance value of the first oxide semiconductor layer can be made lower than the resistance value of the second oxide semiconductor layer. This eliminates the need to provide separate processes for manufacturing thin film transistors and resistor elements. It is possible to provide a driver circuit with fewer manufacturing steps.

[0196] (Embodiment 4) In this embodiment, a driving circuit having a shift register formed of a dynamic circuit is used. An example of the circuit configuration will be described with reference to FIGS. 20(A) to (C).

[0197] The pulse output circuit 1400 shown in FIG. 20(A) receives a start pulse (SP) from an input terminal. One end of the inverter circuit 1401 is connected to the output terminal of the inverter circuit 1401. A switch 1402 to which the terminal is connected and a capacitance element connected to the other terminal of the switch 1402 The switch 1402 of the odd-numbered pulse output circuit is The first clock signal (CLK1) controls ON / OFF. The switch 1402 of the pulse output circuit is turned on and off by the second clock signal (CLK2). The flow is controlled.

[0198] FIG. 20B shows the detailed circuit configuration of the pulse output circuit. The circuit 1400 includes thin film transistors 1411 and 1413, a resistor element 1412, and a capacitor element 1414. 14. The odd-numbered pulse output circuits output a first clock signal (CLK1). The even-numbered pulse output circuits are connected to a wiring 1415 for supplying a second clock. The pulse output circuit 14 is connected to a wiring 1416 for supplying a signal (CLK2). In FIG. 20A, a thin film transistor 1411 and a resistor element 1412 are The inverter circuit 1401 corresponds to an ERMOS circuit. 17A, and the capacitor 1414 corresponds to the switch 1402 shown in FIG. 0(A) corresponds to the capacitor 1403. As with the film transistor 1411, it is preferable to configure the film transistor as an enhancement type transistor. By using an enhancement type transistor as a switch, Since the off-current of the transistor can be reduced, power consumption can be reduced and the manufacturing process can be simplified. can be reduced.

[0199] Here, the circuit operation of the circuits shown in Figures 20(A) and (B) is summarized in Figure 20(C). In FIG. 20(C), for the sake of explanation, the timing chart of the circuit in FIG. The nodes will be described by assigning symbols A to E.

[0200] First, the first clock signal (CLK1) is at H level and the second clock signal (CL K2) explains the L level state.

[0201] In response to a start pulse (SP), an inverted signal appears at node A. The signal at node B Since the first clock signal (CLK1) is at the H level, the voltage at node A is equal to that at node A. The signal at node B is inverted by the inverter circuit at the next stage, and the signal at node B is The signal at node C is the inverted version of the second clock signal (CLK2). It does not appear at node D because it is at L level and the switch is closed.

[0202] Next, when the first clock signal (CLK1) is at the L level and the second clock signal (CL K2) explains the H level state.

[0203] The signal at node C moves to node D, and the signal at node C is reflected at node D. The signal at node D is inverted by the inverter circuit, and the signal at node D is input to node E. Then, the first clock signal (CLK1) and the second clock signal (CLK2) are inverted. By alternately setting the signal (CLK2) to H level, it functions as a shift register. can be done.

[0204] Note that the shift register having the pulse output circuit shown in this embodiment mode is a source line driver. The shift register can be used in a gate line driver circuit and a gate line driver circuit. The signal may be output via a logic circuit or the like to obtain a desired signal.

[0205] The dynamic circuit described in this embodiment has an ERMOS circuit. The circuit is composed of the resistor elements and thin film transistors described in the first to third embodiments. Therefore, the dynamic circuit has good dynamic characteristics.

[0206] (Embodiment 5) In this embodiment, an example of a display device provided with a protection circuit will be described with reference to FIGS. 21 and 22. I will use this to explain.

[0207] FIG. 21 shows an overall view of a display device. A source line driving circuit is provided on a substrate 500. 501, a first gate line driving circuit 502A, a second gate line driving circuit 502B, and The pixel section 503 is integrally formed. The area surrounded by the dotted line frame 510 in the pixel section 503 In the example of FIG. 21, the first gate line driving circuit 5 5. Although the first gate line driving circuit 502A and the second gate line driving circuit 502B are shown, only one of them may be used. In addition, in the pixels of a display device, the display element is controlled by a thin film transistor. A source line driving circuit 501, a first gate line driving circuit 502A, a second gate line driving circuit The signals that drive the 502B (clock signal, start pulse, etc.) are generated by the flexible print Substrates (Flexible Print Circuit: FPC) 504A and 504B The signal is input from the outside via the

[0208] Further, the source line driver circuit 501 and the first gate line driver circuit 502A and those of the pixel portion Protection circuits 550 and 551 are provided between them. 503 is extended from the source line driver circuit 501 and the first gate line driver circuit 502A to the pixel section 503. The protection circuits 550 and 551 protect the device from noise that may enter the device together with the signal and power supply voltage. Even if the input is large, noise may cause malfunction of downstream circuits or deterioration of semiconductor elements. Therefore, it is possible to improve reliability and yield. .

[0209] Next, a specific example of the circuit configuration of the protection circuits 550 and 551 shown in FIG. This will be explained with reference to 2(A) and (B).

[0210] The protection circuit shown in FIG. 22(A) is a diode-connected The device includes n-type thin film transistors 560 to 567 and a resistor element 568. The gate terminal and the first terminal side of the n-type thin film transistor are the anode and the second terminal side ... The two terminal side is the cathode.

[0211] The anode of the diode-connected n-type thin film transistor 560 is connected to the low power supply potential VSS. The diode-connected n-type thin film transistor 561 is connected to a wiring that supplies a The anode is connected to the cathode of a diode-connected n-type thin film transistor 560, The cathode is connected to the wiring 569. Also, a diode-connected n-type thin film transistor The anode of the resistor 562 is connected to the wiring 569. The anode of the transistor 563 is connected to the anode of the diode-connected n-type thin film transistor 562. The cathode is connected to the high power supply potential VDD. 5, the diode-connected n-type thin film transistor 564 to the diode-connected n-type thin film transistor 56 7 is a diode-connected n-type thin film transistor 560 The resistor element 568 is connected in the same manner as the thin film transistor 563. The terminal to which the input is received and the terminal to which the output potential Vout is output are connected in series.

[0212] The operation of the protection circuit shown in FIG. 22(A) will be described below.

[0213] When the input potential Vin from the drive circuit is abnormally high, specifically, The power supply potential VDD and the forward voltages of the diode-connected n-type thin film transistors 562 and 563 If the sum of the voltage drops is higher than the sum of the voltage drops, the diode-connected n-type thin film transistors 562 and 563 is turned on, and the potential of the wiring 569 is set to the high voltage potential VDD and the diode-connected n-type thin film transistor This indicates a potential equivalent to the sum of the forward voltage drops of the transistors 562 and 563 .

[0214] On the other hand, when the input potential Vin from the driver circuit is abnormally low, specifically, the low power supply potential VS S to the forward voltage drop of the diode-connected n-type thin film transistors 560 and 561 When the potential is low, the diode-connected n-type thin film transistors 560 and 561 are conductive, and the The potential of the line 569 is connected to the low voltage potential VSS via a diode-connected n-type thin film transistor 5 This means that the potential will be equivalent to the potential reduced by the forward voltage drop of 60 and 561.

[0215] Therefore, the protection circuit can keep the output potential Vout within a certain range.

[0216] In this embodiment, the diode-connected n-type thin film transistors 560 to A diode-connected n-type thin film transistor 563 is connected in the same manner as A diode-connected n-type thin film transistor 564 and a diode-connected n-type thin film transistor 567 are provided. The diode-connected n-type thin film transistor 564 and the diode By providing an n-type thin film transistor 567 connected to the It is possible to increase the current path when in is abnormally high or low. This can further improve the reliability of the display device.

[0217] In addition, the resistor element 568 reduces abrupt changes in the potential of the wiring 569, and the semiconductor element of the pixel portion This can prevent deterioration or destruction of the child.

[0218] The protection circuit shown in FIG. 22B includes a resistor element 570, a resistor element 571, and a diode-connected and an n-type thin film transistor 572 connected to the resistor element 570. The diode-connected n-type thin film transistor 572 is connected in series to a wiring 573. is.

[0219] The resistor element 570 and the resistor element 571 reduce abrupt changes in the potential of the wiring 573. In addition, the deterioration or destruction of the semiconductor element in the pixel portion can be prevented. A reverse bias is applied to the wiring 573 by the n-type thin film transistor 572 connected to the Therefore, it is possible to prevent a current from flowing through the capacitor.

[0220] In addition, when only a resistance element is connected in series to a wiring, a sudden change in the potential of the wiring is mitigated, The deterioration or destruction of the semiconductor element in the pixel portion can be prevented. When only n-type thin-film transistors are connected in series to wiring, the wiring is reverse-biased due to potential fluctuations. This can prevent a forward bias current from flowing.

[0221] The protection circuit of this embodiment is not limited to the configuration shown in FIGS. There is no need to change the design. As long as the circuit configuration performs a similar function, it is possible to change the design as needed.

[0222] The protection circuit described in this embodiment is the same as that described in the first to third embodiments. Therefore, the protection circuit has good dynamic characteristics.

[0223] (Embodiment 6) In this embodiment mode, a semiconductor device having the resistor element and the thin film transistor described in any of the embodiments 1 to 3 will be described. As an example of a semiconductor device, a light-emitting display device that utilizes electroluminescence is shown. A light-emitting display device having a light-emitting element using electroluminescence is shown. The light-emitting elements are classified according to whether the light-emitting material is an organic compound or an inorganic compound. In general, the former is called an organic EL element and the latter an inorganic EL element.

[0224] In an organic EL element, electrons and positive electrodes are released from a pair of electrodes by applying a voltage to the light-emitting element. The holes are then injected into a layer containing a light-emitting organic compound, and a current is passed through them. The recombination of carriers (electrons and holes) causes light-emitting organic compounds to form excited states. When the excited state returns to the ground state, light is emitted. Such a light-emitting element is called a current-excitation type light-emitting element.

[0225] Inorganic EL elements are classified into dispersion type inorganic EL elements and thin film type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of light-emitting material are dispersed in a binder. The emission mechanism is a donor-based ion exchange reaction that utilizes the donor and acceptor levels. This is an acceptor recombination type emission. Thin-film inorganic EL elements sandwich the light-emitting layer between dielectric layers. The structure is sandwiched between electrodes, and the light emission mechanism is the inner shell electron transition of metal ions. This is a localized emission that utilizes light. Here, an organic EL element is used as the light-emitting element for explanation.

[0226] The structure and operation of an applicable pixel will be described. 1 shows a pixel including an n-channel type thin film transistor applied to a channel forming region.

[0227] FIG. 23 is a diagram showing an example of a pixel configuration. A pixel 6400 in FIG. 23 is a thin-film transistor. The thin film transistor 640 has a light emitting element 6403. 1 has a gate terminal connected to a gate line 6406 and a first terminal connected to a source line 6405. The thin film transistor 6402 has a gate terminal connected to the second terminal of the thin film transistor 6401. The first terminal is connected to the power supply line 6407, and the second terminal is connected to the first terminal of the light emitting element 6403. The power supply line 6407 is connected to a high power supply potential VDD. It is set.

[0228] The second electrode of the light emitting element 6403 corresponds to a common electrode 6408. The second light emitting element 6403 is electrically connected to a common potential line formed on one substrate. A low power supply potential VSS is set to the electrode (common electrode 6408). For example, VSS can be set to GND, 0V, etc. Also, set the power line 6407 The potential difference between the high power supply potential VDD set to the first electrode and the low power supply potential VSS set to the second electrode is A high power supply potential V The potential difference between DD and the low power supply potential VSS becomes equal to or greater than the forward threshold voltage of the light emitting element 6403. The respective potentials are set as follows.

[0229] Next, the structure of the light-emitting element will be described with reference to FIG. When the thin film transistor shown in FIG. 12(A) is used as a thin film transistor of a light emitting display device, In the thin film transistor of the light-emitting display device shown in this embodiment mode, Any of the thin film transistors shown in to 3 can be applied.

[0230] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a thin film transistor and a light emitting element are formed on the substrate, and light is emitted from the surface opposite the substrate. The top surface emission takes the light out from the surface on the substrate side, the bottom surface emission takes the light out from the surface on the substrate side, There are light-emitting elements with a double-sided emission structure that emit light from the opposite side. The pixel configuration shown in Figure 23 is The present invention can be applied to any light emitting element with any emission structure.

[0231] A light emitting element having a top emission structure will be described with reference to FIG.

[0232] In FIG. 24A, a thin film transistor 7001 is an n-type transistor, and a light emitting element 7002 emits light. FIG. 24(A) shows a cross-sectional view of a pixel when light emitted from the light emitting element exits to the anode 7005 side. The cathode 7003 of the electrode 7002 and the thin film transistor 7001 are electrically connected to each other. A light-emitting layer 7004 and an anode 7005 are laminated in this order on the cathode 7003. Various materials can be used for the conductive layer as long as the function is small and the conductive layer reflects light. For example, Ca, Al, CaF, MgAg, AlLi, etc. are preferable. It can be made up of a single layer or multiple layers stacked together. In the case where the cathode 7003 is composed of a plurality of layers, an electron injection layer, an electron transport layer, The light-emitting layer, the hole transport layer, and the hole injection layer are laminated in this order. Note that it is not necessary to provide all of these layers. The anode 7005 is formed using a light-transmitting conductive material, for example. For example, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide Indium oxide with titanium oxide, indium tin oxide with titanium oxide, indium Indium tin oxide, indium zinc oxide, indium tin oxide doped with silicon oxide, etc. Any conductive oxide having optical transparency may be used.

[0233] The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 is the light-emitting element 7002. In the case of the pixel shown in FIG. 24(A), the light emitted from the light emitting element 7002 corresponds to The light is emitted toward the anode 7005 as shown by the arrow.

[0234] Next, a light emitting element having a bottom emission structure will be described with reference to FIG. The cathode 7011 is n-type, and the light emitted from the light-emitting element 7012 is emitted to the cathode 7013 side. FIG. 24B shows a cross-sectional view of a pixel in the case where the thin film transistor 7011 is electrically connected to the A cathode 7013 of a light-emitting element 7012 is formed on the connected conductive layer 7017 having light-transmitting properties. A light-emitting layer 7014 and an anode 7015 are laminated in this order on the cathode 7013. In the case where the anode 7015 is transparent, a light reflecting or blocking layer is provided so as to cover the anode. A shielding layer 7016 for preventing the light from entering the cathode 7013 may be formed. Similarly, various conductive materials with small work functions can be used. The film thickness is set to a level that allows light to pass through (preferably, about 5 nm to 30 nm). For example, 700 nm thick aluminum can be used as the cathode 7013. The light-emitting layer 7014 may be composed of a single layer as in FIG. 24(A), or may be composed of a plurality of layers. The anode 7015 does not need to transmit light. However, similarly to FIG. 24(A), the insulating film 11 can be formed using a conductive material having light-transmitting properties. The shielding layer 7016 can be made of, for example, a metal that reflects light. There is no limitation to the material, and for example, a resin to which a black pigment is added may be used.

[0235] The region where the light-emitting layer 7014 is sandwiched between the cathode 7013 and the anode 7015 is the light-emitting element 701. In the case of the pixel shown in FIG. 24B, the light emitted from the light-emitting element 7012 is , and is emitted toward the cathode 7013 as indicated by the arrow.

[0236] Next, a light emitting element having a dual emission structure will be described with reference to FIG. 7027) is a light-transmitting conductive layer electrically connected to a thin film transistor 7021. A cathode 7023 of the light-emitting element 7022 is formed on the cathode 7023. 24 and an anode 7025 are laminated in this order. The cathode 7023 is the same as in FIG. In addition, various conductive materials with small work functions can be used. The thickness of the film is set to a level that allows light to pass through. For example, the cathode 7023 is made of Al having a thickness of 20 nm. The light-emitting layer 7024 can be a single layer, as in FIG. The film may be constructed by laminating a plurality of layers. The electrode 7025 is made of a light-transmitting conductive material, as in FIG. It can be formed.

[0237] The overlapping portion of the cathode 7023, the light-emitting layer 7024, and the anode 7025 constitutes the light-emitting element 7 In the case of the pixel shown in FIG. 24C, the light emitted from the light-emitting element 7022 Light is emitted to both the anode 7025 side and the cathode 7023 side as indicated by the arrows.

[0238] Although the organic EL element has been described as the light-emitting element here, inorganic light-emitting elements may also be used. An EL element may also be provided.

[0239] Next, the appearance and The cross section will be described with reference to FIG. 25. FIG. 25(A) shows a thin film formed on a first substrate. A panel in which the film transistor and the light emitting element are sealed between the second substrate and the film transistor and the light emitting element by a sealant. 25(B) is a top view of the device, and FIG. 25(B) corresponds to a cross-sectional view taken along line EF in FIG. 25(A).

[0240] A pixel portion 4502, a source line driver circuit 4503a, and a fourth The sealant 45 is disposed so as to surround the gate line driver circuits 4503a and 4504b. 05 is provided. Also, the pixel portion 4502, the source line driver circuits 4503a and 4503b A second substrate 4506 is provided on the gate line driver circuits 4504a and 4504b. Therefore, the pixel portion 4502, the source line driver circuits 4503a and 4503b, and the gate line The driver circuits 4504a and 4504b are formed by a first substrate 4501, a sealant 4505, and a second substrate 4502. The plate 4506 and the filler 4507 are sealed together. Highly airtight and low outgassing protective film (lamination film, UV-resistant film) It is preferable to package (enclose) the package using a cover material such as a plastic film.

[0241] In addition, the pixel portion 4502 provided on the first substrate 4501 is connected to a source line driver circuit 450 Similar to the gate line driver circuits 4503a and 4503b and the gate line driver circuits 4504a and 4504b, In FIG. 25B, a thin film transistor manufactured using A thin film transistor 4510 included in the source line driver circuit 4503a and a thin film transistor The example shows a 4509 transistor.

[0242] The thin film transistors 4509 and 4510 have the structure shown in FIG. An example of applying a thin film transistor will be described. Any of the thin film transistors described in Embodiments 1 to 3 can be used for the transistor.

[0243] The light-emitting element 4511 has a first electrode which is a pixel electrode. The electrode layer 4517 is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. The light-emitting element 4511 is configured as a first electrode layer 4517, an electroluminescent The second electrode layer 4512 and the second electrode layer 4513 are stacked in a stacked structure. The light emitting element 4511 is not fixed according to the direction of the light to be extracted from the light emitting element 4511. The configuration of can be changed as appropriate.

[0244] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. In particular, a photosensitive material is used to form an opening on the first electrode layer 4517, and the side of the opening is It is preferable that the wall is formed to have an inclined surface having a continuous curvature.

[0245] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers may be laminated. It doesn't matter whether it is completed or not.

[0246] In order to prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light-emitting element 4511, the second electrode A protective film may be formed on the layer 4513 and the partition wall 4520. The protective film may be formed of silicon nitride. A silicon layer, a silicon oxynitride layer, a DLC layer, etc. can be formed.

[0247] In addition, source line driver circuits 4503a and 4503b, gate line driver circuits 4504a and 45 Various signals and potentials applied to the pixel portion 4502 are provided through the FPC 4518a, Powered by 518b.

[0248] In this embodiment, the connection terminal electrode 4515 is a first electrode layer of the light-emitting element 4511. The terminal electrode 4516 is formed from the same conductive film as the thin film transistor 4509. The source electrode layer and the drain electrode layer 4510 are formed from the same conductive film.

[0249] The connection terminal electrode 4515 is a terminal of the FPC 4518a and an anisotropic conductive film 4519. The two are electrically connected via a

[0250] The second substrate is transparent to light. In that case, glass plates, plastic plates, polyester films, etc. Alternatively, a light-transmitting material such as an acrylic film is used.

[0251] In addition, filler 4507 can be used with inert gases such as nitrogen and argon, as well as ultraviolet-curing gases. Resin or thermosetting resin can be used, PVC (polyvinyl chloride), acrylic , polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or E VA (ethylene vinyl acetate) can be used. In this embodiment, Nitrogen was used.

[0252] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates), color filters, etc. may be installed as appropriate. In addition, the polarizing plate or the circular polarizing plate may be provided with an anti-reflection film. It is possible to apply an anti-glare treatment that can diffuse reflected light and reduce glare.

[0253] Source line driver circuits 4503a and 4503b and gate line driver circuits 4504a and 4504 b may be implemented as a drive circuit formed on a separately prepared substrate. Only the gate line driving circuit or a part of it, or only the gate line driving circuit or a part of it, is formed separately. The present embodiment is not limited to the configuration of FIG.

[0254] The light-emitting display device described in this embodiment mode includes the resistor element and the thin film transistor described in any of the first to third embodiments. Therefore, the light-emitting display device has favorable dynamic characteristics.

[0255] (Embodiment 7) In this embodiment mode, a semiconductor device having the resistor element and the thin film transistor described in any of the embodiments 1 to 3 will be described. As an example of a semiconductor device, electronic paper will be shown.

[0256] FIG. 26 shows an active matrix type electronic paper. The electronic paper in FIG. The twisted ball display method is a method of dividing the screen into black and white. The spherical particles are used in a display element, and the electrode layer is a first electrode layer and a second electrode layer. A potential difference is generated between the first electrode layer and the second electrode layer to control the orientation of the spherical particles. This is a method for displaying information by

[0257] A thin film transistor 581 provided on a first substrate 580 is a thin film transistor of a bottom gate structure. A first terminal or a second terminal is connected to a first electrode layer 587 and an insulating layer 585. The first electrode layer 587 and the second electrode layer 588 are in contact with each other at the opening to be formed and are electrically connected. Between the 88 and the black area 590a and the white area 590b, the surrounding area is filled with liquid. A spherical particle 589 including a cavity 594 is disposed between a first substrate 580 and a second substrate 596. The spherical particles 589 are surrounded by a filler 595 such as resin. See FIG. 26. In this embodiment, the first electrode layer 587 corresponds to a pixel electrode, and the second electrode layer 588 corresponds to a pixel electrode. The second electrode layer 588 corresponds to a common electrode.

[0258] Also, instead of the twist ball, an electrophoretic element can be used. The body is a 10μm to 2 cm diameter encapsulating positively charged white particles and negatively charged black particles. Microcapsules with a diameter of about 0.1 μm are used. When an electric field is applied to the microcapsules by the first and second electrode layers, White particles and black particles move in opposite directions, allowing the display to be white or black. The display element that applies this principle is the electrophoretic display element, which is generally called electronic paper. Electrophoretic display elements have a higher reflectivity than liquid crystal display elements, so auxiliary lights are not required. It also consumes little power and the display can be seen even in dimly lit places. In addition, even if power is not supplied to the display, the image once displayed can be retained. Therefore, it is necessary to prevent a distance between the radio wave source and a semiconductor device with a display function (simply a display device, or a device equipped with a display device). The displayed image can be stored even if the semiconductor device (also called a semiconductor device equipped with a This makes it possible.

[0259] The electronic paper shown in this embodiment is the same as the resistor element and the thin film shown in the first to third embodiments. The electronic paper has good dynamic characteristics due to the transistors.

[0260] (Embodiment 8) In this embodiment, the resistor element and the thin film transistor shown in the first to third embodiments are As an example of a semiconductor device having the above, an electronic device will be described.

[0261] FIG. 27A shows a portable game machine, which includes a housing 9630, a display unit 9631, and a speaker 963. 2, operation keys 9633, a connection terminal 9634, a recording medium reading unit 9635, etc. The portable game machine shown in FIG. 27(A) can be used with a program or The function of reading data and displaying it on the display unit, and wirelessly communicating with other portable gaming machines to transmit information The portable gaming machine shown in FIG. 27(A) has the following functions: The functions are not limited to these, and the device may have a variety of functions.

[0262] FIG. 27B shows a digital camera having a housing 9640, a display unit 9641, and a speaker 96 42, operation keys 9643, connection terminal 9644, shutter button 9645, image receiving unit 964 6. The digital camera with a television receiving function shown in FIG. 27(B) can have Functions for taking still images, shooting videos, and automatically or manually correcting captured images Functions, such as acquiring various information from the antenna, capturing images, or acquiring information from the antenna The function to save the captured information, the function to display the captured image or the information obtained from the antenna on the display. In addition, the digital camera with a television receiving function shown in FIG. The functions of the mobile camera are not limited to those described above, and the mobile camera may have a variety of functions.

[0263] FIG. 27C shows a television receiver, which includes a housing 9650, a display portion 9651, and a speaker 965 2, operation keys 9653, connection terminals 9654, etc. A television receiver has two functions: to process television radio waves and convert them into image signals, and to process image signals and It has functions such as converting signals suitable for display and converting the frame frequency of image signals. Note that the functions of the television receiver shown in FIG. 27(C) are not limited to these. It can have a variety of functions.

[0264] FIG. 28A shows a computer, which includes a housing 9660, a display unit 9661, and a speaker 966 2. Operation keys 9663, connection terminals 9664, pointing devices 9665, external connections The computer shown in FIG. 28(A) can have various information. The function to display information (still images, videos, text images, etc.) on the display unit, Functions for controlling processing by programs, communication functions such as wireless communication or wired communication, The ability to connect to various computer networks using the communication function, It can have a function of transmitting or receiving data. The functions possessed by the computer are not limited to those described above, and the computer may have a variety of functions.

[0265] Next, FIG. 28B shows a mobile phone, which includes a housing 9670, a display portion 9671, and a speaker 96 72, operation keys 9673, microphone 9674, etc. The mobile phone shown in Figure 1 has the function of displaying various information (still images, videos, text images, etc.). A function to display the calendar, date, or time on the display, and to operate the information displayed on the display Or editing functions, functions to control processing by various software (programs), etc. Note that the functions of the mobile phone shown in FIG. 28(B) are not limited to these. It can have a variety of functions.

[0266] The electronic devices described in this embodiment mode include the resistor elements and thin film transistors described in Embodiments 1 to 3. Therefore, the electronic device has good dynamic characteristics. [Explanation of symbols]

[0267] 100 Substrates 101 Source line driver circuit 102A Gate line driving circuit 102B Gate line driving circuit 103 Pixel section 104A FPC 104B FPC 201 Clock signal level shifter 202 Start pulse level shifter 203 Pulse output circuit 204 NAND circuit 205 Buffer 206 Sampling Switch 251 Shift Register 300 Pulse output circuit 301 Switch 302 Inverter circuit 303 Inverter Circuit 304 Switch 305 Inverter circuit 331 Pulse output circuit 332 Pulse output circuit 350 Pulse output circuit 351 Thin-film transistor 352 Resistance element 353 Thin-film transistor 354 Resistance element 355 Thin-film transistor 356 Thin Film Transistor 357 Resistance Element 358 Thin Film Transistor 359 Wiring 360 Wiring 500 boards 501 Source line driver circuit 502A Gate line driving circuit 502B Gate line driving circuit 503 Pixel section 504A FPC 504B FPC 550 protection circuit 551 Protection circuit 560 Thin Film Transistor 561 Thin Film Transistor 562 Thin Film Transistor 563 Thin Film Transistor 564 Thin Film Transistor 565 Thin Film Transistor 566 Thin Film Transistor 567 Thin Film Transistor 568 Resistor Element 569 Wiring 570 Resistance element 571 Resistor Element 572 Thin Film Transistor 573 Wiring 580 Substrate 581 Thin Film Transistor 585 Insulation Layer 587 Electrode layer 588 Electrode layer 589 Spherical particles 590a black area 590b White area 594 Cavity 595 Filling material 596 Board 601 Resistance element 602 Thin Film Transistor 603 Resistance element 604 Thin Film Transistor 605 Resistance element 606 Thin Film Transistor 607 Resistance element 608 Thin Film Transistor 701 Resistor element 702 Thin Film Transistor 703 Thin Film Transistor 730 Capacitive element 731 Thin Film Transistor 721 Thin Film Transistor 751 Clock signal level shifter 752 Start Pulse Level Shifter 753 Pulse output circuit 754 NAND circuit 755 Buffer 781 Shift Register 801 Power line 802 power line 803 Control Signal Line 804 Control signal line 805 Control signal line 806 Oxide semiconductor layer 807 Wiring layer 808 wiring layer 809 Contact Hole 900 Substrate 901 First Wiring 902 Gate terminal 903 Insulation Layer 904 Contact Hole 905 Oxide semiconductor layer 906 Oxide semiconductor layer 907 Wiring 908 Wiring 909 Silicon oxide layer 910 Silicon nitride layer 911a Buffer layer 911b Buffer layer 911c Buffer layer 911d Buffer layer 911e Buffer layer 912 Wiring 950 Oxide Semiconductor Film 951 Oxide semiconductor film 960 Oxide semiconductor layer 961 Oxide semiconductor layer 962 Oxide semiconductor layer 963 Oxide semiconductor layer 964 Oxide semiconductor layer 965 Oxide semiconductor layer 966 Oxide semiconductor layer 967 Oxide semiconductor layer 968 Oxide semiconductor layer 1001 Channel protection layer 1010a Buffer layer 1010b Buffer layer 1400 Pulse output circuit 1401 Inverter circuit 1402 Switch 1403 Capacitive element 1411 Thin-film transistor 1412 Resistor element 1413 Thin-film transistor 1414 Capacitive element 1415 Wiring 1416 Wiring 2001 Oxide semiconductor layer 2002 Oxide semiconductor layer 4501 Board 4502 Pixel section 4503a Source line driver circuit 4503b Source line driver circuit 4504a Gate line driver circuit 4504b Gate line driver circuit 4505 Sealing material 4506 Board 4507 Filling material 4509 Thin-film transistor 4510 Thin-film transistor 4511 Light emitting element 4512 Electroluminescent layer 4513 Electrode layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode layer 4518a FPC 4518b FPC 4519 Anisotropic conductive film 4520 Bulkhead 6400 pixels 6401 Thin-film transistor 6402 Thin film transistor 6403 Light emitting element 6405 Source Line 6406 Gate line 6407 Power line 6408 Common electrode 7001 Thin film transistor 7002 Light emitting element 7003 Cathode 7004 Light-emitting layer 7005 Anode 7011 Thin film transistor 7012 Light emitting element 7013 Cathode 7014 Light-emitting layer 7015 Anode 7016 Shielding layer 7017 Conductive layer 7021 Thin film transistor 7022 Light emitting element 7023 Cathode 7024 Light-emitting layer 7025 Anode 7027 Conductive layer 9630 Case 9631 Display section 9632 Speaker 9633 Operation key 9634 Connection terminal 9635 Recording medium reading unit 9640 Chassis 9641 Display section 9642 Speaker 9643 Operation key 9644 Connection terminal 9645 Shutter button 9646 Image receiving unit 9650 Chassis 9651 Display section 9652 Speaker 9653 Operation key 9654 Connection terminal 9660 Case 9661 Display section 9662 Speaker 9663 Operation key 9664 Connection terminal 9665 Pointing Device 9666 External connection port 9670 Chassis 9671 Display section 9672 Speaker 9673 Operation key 9674 Microphone

Claims

[Claim 1] a resistor element in which the first oxide semiconductor layer is used as a resistance component; a thin film transistor in which a second oxide semiconductor layer having a lower hydrogen concentration than the first oxide semiconductor layer is used for a channel formation region; a silicon oxide layer provided on the second oxide semiconductor layer; a silicon nitride layer provided over the first oxide semiconductor layer and the silicon oxide layer.

Images