Standard cell structure

Abstract

To provide standard cells preventing latch-up in the standard cell.SOLUTION: A standard cell 500 includes: a plurality of transistors including a first type transistor and a second type transistor; and a plurality of contacts, at least one input line and at least one output line, a VDD contact line, and a VSS contact line, which are coupled to the plurality of transistors. The first type transistor includes a first set of fin structures 501 electrically coupled together, and the second type transistor includes a second set of fin structures 502 electrically coupled together. A gap between the first type transistor and the second type transistor is not greater than 3×Fp-λ, where Fp is a pitch distance between two adjacent fin structures in the first type transistor and λ is a minimum processing size of the standard cell.SELECTED DRAWING: Figure 5(a)

Description

[Technical field]

[0001] The present invention relates to semiconductor devices within a monolithic semiconductor die, and more particularly to an optimized standard cell integrated into the monolithic semiconductor die based on a unified scaling and stretching platform that can effectively reduce the size of logic circuits within the monolithic semiconductor die without reducing minimum feature size. [Background technology]

[0002] Improvements in performance and cost of integrated circuits have been mainly achieved by process scaling technology according to Moore's Law, and the process variation in transistor performance due to the miniaturization of manufacturing processes to a minimum of 28 nm (or less) is a challenge. In particular, logic circuit scaling for increasing memory density, reduction in operating voltage (Vdd) for reducing standby power consumption, and yield improvement required to realize larger capacity logic circuits are becoming increasingly difficult to achieve.

[0003] Standard cells are commonly used and are basic elements in logic circuits. Standard cells may comprise basic logic function cells (such as an inverter cell, a NOR cell, and a NAND cell, 2x inverter cells, 2x NOR cells, and 2x NAND cells) as shown in Figures 1(a) to 1(f). However, even with the scaling of manufacturing processes to a minimum of 22 nm or less (also called "minimum feature size", "λ", or "F"), the size of the contacts and the layout of the metal wiring may not be large enough to accommodate the size of the λ. 2 or F 2 The total area of ​​a standard cell, represented by .times. ...

[0004] Some of the reasons why the total area of ​​a standard cell increases dramatically when the minimum feature size decreases can be explained as follows. A conventional standard cell, for example an inverter as shown in FIG. 1(a), is connected by using multiple interconnects, which have their first interconnect layer M1 for connecting the diffusion levels (source and drain regions) of transistors. There is a need to increase the second interconnect layer M2 and / or the third interconnect layer M3 for facilitating signal transfer (such as input or output) without increasing the die size by using only M1, in which case a structure Via-1 made of some kind of conductive material is formed to connect M2 to M1. Thus, there is a vertical structure formed by diffusion through a contact connection with M1, i.e., "Diffusion-Contact (Con)-M1". Similarly, another structure can be formed as "Gate-Con-M1" for connecting a gate to M1 through a contact structure.

[0005] Furthermore, if a connection structure needs to be formed from the M1 interconnect through Via 1 to connect to the M2 interconnect, it is called "M1-Via 1-M2". A more complex interconnect structure from the gate level to the M2 interconnect may be represented as "Gate-Con-M1-Via 1-M2". Furthermore, the stacked interconnect system may have an "M1-Via 1-M2-Via 2-M3" or "M1-Via 1-M2-Via 2-M3-Via 3-M4" structure, etc. Since the gates in the two access transistors (the NMOS and PMOS transistors of the inverter as shown in FIG. 1(a)) are connected to the inputs located in the second interconnect layer M2, in a conventional inverter, such metal connection must first go through the interconnect layer M1. That is, the conventional interconnect system in the inverter may not allow the gates to connect directly to M2 without bypassing the M1 structure. As a result, the required space between one M1 interconnect and another increases the die size, and in some cases the wiring connections may prevent certain efficient channeling intentions from using M2 directly across the M1 region. Furthermore, it is difficult to form a self-aligned structure between Via 1 to the contacts, and at the same time, both Via 1 and the contacts are each connected to their own interconnect system.

[0006] Furthermore, in a conventional standard cell (of an inverter as shown in FIG. 1(a)), there is at least one NMOS transistor 11 and one PMOS transistor 12, each disposed in some adjacent regions (such as n-well and p-well) of a p-substrate, formed adjacent to each other in close proximity, forming a parasitic junction structure called an n+ / p / n / p+ parasitic bipolar element, with its contour starting from the n+ region of the NMOS transistor 11 to the p-well, to the adjacent n-well, and further to the p+ region (p-well) of the PMOS transistor 12, as shown in FIG. 2. If a large noise occurs in either the n+ / p junction or the p+ / n junction, a very large current may flow abnormally through this n+ / p / n / p+ junction, which may possibly shut down the operation of a part of the CMOS circuitry and cause the whole chip to malfunction. Such an abnormal phenomenon, called latch-up, adversely affects CMOS operation and must be avoided.

[0007] One way to increase resistance to latch-up, which is certainly a weakness of CMOS, is to increase the distance from the n+ region to the p+ region. Therefore, increasing the distance from the n+ region to the p+ region to avoid the latch-up problem also increases the size of the standard cell.

[0008] FIG. 3(a) shows a "stick diagram" representing the layout and connections between PMOS and NMOS transistors of a 5 nm (UHD) standard cell of one semiconductor company (Samsung). The stick diagram only includes active areas (red horizontal lines) and gate lines (blue vertical lines). In the following, the active areas may be called "fins". Of course, there are still many contacts that are directly coupled to the PMOS and NMOS transistors on the one hand, and to input terminals, output terminals, high-level voltage Vdd, and low-level voltage VSS (or ground "GND") on the other hand. In particular, each transistor includes two active areas or fins (indicated by dark red) for forming the channel of the transistor so that the W / L ratio can be maintained within an acceptable range. The area dimension of the inverter cell is equal to X×Y, where X=2×Cpp and Y=cell_height, where Cpp is the distance between the contacts and the poly pitch (Cpp). It is shown that some active areas or fins (called "dummy fins" and shown by light red color) are not utilized in the PMOS / NMOS of this standard cell, and the potential reason is likely related to the latch-up problem between PMOS and NMOS. Thus, the latch-up distance between PMOS and NMOS in Figure 3(a) is 3×Fp-λ (e.g., =14λ), where Fp is the fin pitch (e.g., =5λ).

[0009] Based on available data on Cpp (54nm) and cell_height (216nm) for Samsung 5nm (UHD) standard cells, the cell area is 23328nm x 23328nm 2 (Or, 933.12λ, where Lambda (λ) is the minimum feature size of 5 nm. 2 ) is calculated by equating the L_DELTA_PMOS_to_NMOS L_DELTA_PMOS with the L_DELTA_PMOS_to_NMOS L_DELTA_PMOS. Figure 3(b) shows a Samsung 5nm (UHD) standard cell and its dimensions. As shown in Figure 3(b), the latch-up distance between PMOS and NMOS is about 15λ, Cpp is 10.8λ, and cell_height is 43.2λ.

[0010] Additionally, publicly available information regarding Cpp and cell_height for different process technology nodes (or feature sizes) is shown in the table below.

[0011] [Table 1]

[0012] [Table 2]

[0013] [Table 3]

[0014] Using the above table, the scaling trends for area dimensions (2 x Cpp x cell_height) versus different process technology nodes for the three foundries can be shown in Figure 4. As the technology node decreases (e.g., from 22 nm to 5 nm), λ 2 It is clear that the area dimension of a conventional standard cell (2 × Cpp × cell_height) increases dramatically. For conventional standard cells, the smaller the process node, the smaller the λ 2 The reduced area dimensions become larger. Such a dramatic increase can be caused by the difficulty of proportionally reducing the gate / source / drain contact dimensions as λ decreases, the difficulty of proportionally reducing the latch-up distance between PMOS and NMOS, and the reduction in interference within metal layers as λ decreases.

[0015] Therefore, there is a need to propose a new standard cell structure that can solve the above problems. Summary of the Invention

[0016] One embodiment of the present disclosure is a standard cell comprising: a substrate having a well region; a plurality of transistors including a first type transistor and a second type transistor, the first type transistor being formed within the well region and the second type transistor being formed outside the well region; a plurality of contacts coupled to the plurality of transistors; at least one input line electrically coupled to the plurality of transistors; an output line electrically coupled to the plurality of transistors; a VDD contact line electrically coupled to the plurality of transistors; and a VSS contact line electrically coupled to the plurality of transistors, the first type transistors including a first set of fin structures electrically coupled to each other, the second type transistors including a second set of fin structures electrically coupled to each other, a gap between the first type transistors and the second type transistors is no greater than 3×Fp−λ, where Fp is a pitch distance between two adjacent fin structures in the first type transistors, and λ is a minimum feature dimension of the standard cell.

[0017] According to one aspect of the present disclosure, a width of a fin structure in a first type transistor is Fw, and a gap between the first type transistor and a second type transistor is not greater than 3×Fp−Fw, where Fw is greater than λ.

[0018] According to one embodiment of the present disclosure, the pitch distance Fp between two adjacent fin structures in the first type transistor is 3λ.

[0019] According to one aspect of the present disclosure, the gap between the first type transistor and the second type transistor is approximately equal to 5λ.

[0020] According to one aspect of the present disclosure, the pitch distance Fp between two adjacent fin structures in the first type transistor is 3.5λ. However, this is merely an example, and the pitch distance Fp is not limited to the above, and in certain other embodiments, the pitch distance Fp may be 3.0λ.

[0021] According to one aspect of the disclosure, the gap between the first type transistor and the second type transistor is approximately equal to 2.5λ. In certain other embodiments, the pitch distance Fp may be 3.0λ.

[0022] Another embodiment of the present disclosure is a standard cell comprising: a plurality of transistors, the plurality of transistors including PMOS transistors and NMOS transistors; a plurality of contacts coupled to the plurality of transistors; at least one input line electrically coupled to the plurality of transistors; an output line electrically coupled to the plurality of transistors; a VDD contact line electrically coupled to the plurality of transistors; and a VSS contact line electrically coupled to the plurality of transistors, wherein the PMOS transistors include a first set of fin structures electrically coupled to each other and the NMOS transistors include a second set of fin structures electrically coupled to each other, and during formation of the first set of fin structures and the second set of fin structures, there are no fin structures disposed between the PMOS transistors and the NMOS transistors.

[0023] According to one exemplary aspect of the present disclosure, the gap between the edge of the PMOS transistor and the edge of the NMOS transistor is smaller than the pitch distance between two adjacent fin structures in the PMOS transistor.

[0024] According to one embodiment of the present disclosure, the pitch distance Fp between two adjacent fin structures in a PMOS transistor is 3.5λ.

[0025] According to one aspect of the present disclosure, the gap between the PMOS and NMOS transistors is approximately equal to 2.5λ.

[0026] Yet another embodiment of the present disclosure is a standard cell comprising a plurality of transistors, a set of contacts coupled to the plurality of transistors, at least one input line electrically coupled to the plurality of transistors, an output line electrically coupled to the plurality of transistors, a VDD contact line electrically coupled to the plurality of transistors, and a VSS contact line electrically coupled to the plurality of transistors, the minimum feature size (λ) of the standard cell decreasing progressively from 22 nm to λ 2 The area dimensions of the standard cells in the converted form are the same or approximately the same.

[0027] According to one aspect of the present disclosure, the standard cell is an inverter cell, a NAND cell, or a NOR cell.

[0028] Yet another embodiment of the present disclosure is a standard cell, comprising: a plurality of transistors; a set of contacts coupled to the plurality of transistors; at least one input line electrically coupled to the plurality of transistors; an output line electrically coupled to the plurality of transistors; and a metal contact line electrically coupled to a first contact of the set of contacts. wherein the first contact is not completely covered by the metal contact line.

[0029] According to one aspect of the present disclosure, the width of the metal contact line is the same or approximately the same as the width of the first contact.

[0030] According to one aspect of the disclosure, the standard cell further comprises a heavily doped silicon plug formed on a portion of the first contact that is not covered by the metal contact line, the heavily doped silicon plug contacting the metal contact line.

[0031] Yet another embodiment of the present disclosure is a standard cell comprising: a plurality of transistors; a set of contacts coupled to the plurality of transistors; a first metal line electrically coupled to the plurality of transistors; and a second metal line electrically coupled to the plurality of transistors, the second metal line being above the first metal line, wherein at least one of the set of contacts connects directly to the second metal line without passing through the first metal line.

[0032] According to one aspect of the present disclosure, at least one of the set of contacts is a gate contact.

[0033] Yet another embodiment of the present disclosure is a standard cell comprising: a plurality of transistors; a set of contacts coupled to the plurality of transistors; a first metal line electrically coupled to the plurality of transistors; and a second metal line electrically coupled to the plurality of transistors, the plurality of transistors being formed based on a semiconductor substrate, and at least one of the plurality of transistors comprising a fin structure and a channel layer covering the fin structure, the channel layer being a doped layer independent of the semiconductor substrate and formed without ion implantation.

[0034] According to one aspect of the present disclosure, the channel layer covers a first sidewall and a second sidewall of the fin structure and does not cover a top surface of the fin structure.

[0035] According to one aspect of the present disclosure, the channel layer comprises a top portion covering a top surface of the fin structure and a side portion covering a first sidewall and a second sidewall of the fin structure, the top portion and the side portion being not formed simultaneously.

[0036] The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication containing one or more color drawing(s) will be provided by the Japan Patent Office (JPO) upon request and payment of the necessary fee.

[0037] The above and other aspects of the present disclosure will become better understood with regard to the following detailed description of one preferred, but non-limiting, embodiment(s), the following description being made with reference to the accompanying drawings, in which: [Brief description of the drawings]

[0038] [Figure 1(a)] 1A-1D are equivalent circuit diagrams showing basic logic function cells of the prior art: an inverter cell, a NOR cell, and a NAND cell, respectively; [Figure 1(b)] 1A-1D are equivalent circuit diagrams showing basic logic function cells of the prior art: an inverter cell, a NOR cell, and a NAND cell, respectively; [Figure 1(c)] 1A-1D are equivalent circuit diagrams showing basic logic function cells of the prior art: an inverter cell, a NOR cell, and a NAND cell, respectively; [Figure 1(d)] 1A-1D are equivalent circuit diagrams showing basic logic function cells of the prior art: an inverter cell, a NOR cell, and a NAND cell, respectively; [Figure 1(e)] 1A-1D are equivalent circuit diagrams showing basic logic function cells of the prior art: an inverter cell, a NOR cell, and a NAND cell, respectively; [Figure 1(f)] 1A-1D are equivalent circuit diagrams showing basic logic function cells of the prior art: an inverter cell, a NOR cell, and a NAND cell, respectively; [Diagram 2] FIG. 1 shows a cross section of conventional NMOS and PMOS structures of a standard cell. [Figure 3(a)] FIG. 1 is a stick diagram representing the layout and connections of PMOS and NMOS transistors in one semiconductor company's (Samsung) 5 nm (UHD) standard cell. [Figure 3(b)] FIG. 3(a) is a stick diagram showing the dimensions of a Samsung 5 nm (UHD) standard cell. [Figure 4] FIG. 13 shows the scaling trends for area dimension (2×Cpp×cell_height) versus different process technology nodes for three foundries. [Figure 5(a)] FIG. 2 is a stick diagram illustrating a novel inverter standard cell layout style in accordance with the present invention. [Figure 5(b)] FIG. 5(b) is a stick diagram with dimensions of the inverter standard cell depicted in FIG. 5(a). [Figure 5(c)] FIG. 5 is a diagram showing a series of process layouts for forming an inverter standard cell based on FIG. 5(a) to FIG. 5(b). [Figure 5(d)] FIG. 5 is a diagram showing a series of process layouts for forming an inverter standard cell based on FIG. 5(a) to FIG. 5(b). [Figure 5(e)] FIG. 5 is a diagram showing a series of process layouts for forming an inverter standard cell based on FIG. 5(a) to FIG. 5(b). [Figure 5(f)] FIG. 5 is a diagram showing a series of process layouts for forming an inverter standard cell based on FIG. 5(a) to FIG. 5(b). [Figure 6(a)] FIG. 11 is a stick diagram illustrating a layout style of a novel inverter standard cell according to another embodiment of the present invention. [Figure 6(b)] FIG. 6(b) is a stick diagram with dimensions of the inverter standard cell depicted in FIG. 6(a). [Figure 6(c)] FIG. 6 is a diagram showing a series of process layouts for forming an inverter standard cell based on FIG. 6(a) to FIG. 6(b). [Figure 6(d)] FIG. 6 is a diagram showing a series of process layouts for forming an inverter standard cell based on FIG. 6(a) to FIG. 6(b). [Figure 6(e)] FIG. 6 is a diagram showing a series of process layouts for forming an inverter standard cell based on FIG. 6(a) to FIG. 6(b). [Figure 6(f)]FIG. 6 is a diagram showing a series of process layouts for forming an inverter standard cell based on FIG. 6(a) to FIG. 6(b). [Figure 7(a)] FIG. 2 is a stick diagram illustrating a layout style of a novel NAND standard cell according to another embodiment of the present invention. [Figure 7(b)] FIG. 7(b) is a stick diagram with dimensions of the inverter standard cell depicted in FIG. 7(a). [Figure 7(c)] FIG. 7 is a diagram showing a series of process layouts for forming an inverter standard cell based on FIG. 7(a) to FIG. 7(b). [Figure 7(d)] FIG. 7 is a diagram showing a series of process layouts for forming an inverter standard cell based on FIG. 7(a) to FIG. 7(b). [Figure 7(e)] FIG. 7 is a diagram showing a series of process layouts for forming an inverter standard cell based on FIG. 7(a) to FIG. 7(b). [Figure 7(f)] FIG. 7 is a diagram showing a series of process layouts for forming an inverter standard cell based on FIG. 7(a) to FIG. 7(b). [Figure 8(a)] FIG. 2 illustrates a top view of a scaled metal-oxide-semiconductor field effect transistor (mMOSFET) used in a novel standard cell in accordance with the present invention. [Figure 8(b)] FIG. 2 shows a cross-section of the pad oxide layer, the pad nitride layer over the substrate, and the STI oxide 1 formed in the substrate. [Figure 8(c)] FIG. 2 illustrates an intrinsic gate (TG) and a dummy shield gate (DSG) formed on / above an active area. [Figure 8(d)] FIG. 2 shows that a spin-on dielectric (SOD) is deposited and a properly designed gate mask layer is deposited and etched. [Figure 8(e)] FIG. 2 shows that the nitride layer over the dummy shield gate (DSG), the DSG, a portion of the dielectric insulator corresponding to the DSG, and the p-type substrate corresponding to the DSG are removed. [Figure 8(f)]FIG. 13 shows that the gate mask layer is removed, the SOD is etched, and an oxide layer is deposited to form STI-oxide-2. [Figure 8(g)] FIG. 1 shows an oxide-3 layer is deposited and etched to form oxide-3 spacers, a lightly doped drain (LDD) is formed in a p-type substrate, a nitride layer is deposited and etched back to form nitride spacers, and the dielectric insulator is removed. [Figure 8(h)] FIG. 1 shows that intrinsic silicon electrodes are grown by selective epitaxial growth (SEG) technique. [Figure 8(i)] FIG. 1 shows that a CVD-STI-Oxide 3 layer is deposited and etched back, the intrinsic silicon electrodes are removed, and the source (n+ source) and drain (n+ drain) of the mMOSFET are formed. [Figure 8(j)] FIG. 13 shows that oxide spacers are deposited and etched to form contact hole openings. [Figure 8(k)] FIG. 13 shows that a layer of SOD is deposited to fill the pores on the substrate and CMP is used to planarize the surface. [Figure 8(l)] FIG. 8(k) is a top view of FIG. [Figure 8(m)] FIG. 8(l) shows a photoresistive layer formed on the structure in FIG. 8(l). [Figure 8(n)] FIG. 13 illustrates the removal of the nitride cap layer in the exposed gate extension region by anisotropic etching techniques to reveal the conductive metal gate layer. [Figure 8(o)] FIG. 13 shows that the photoresistive layer and the SOD layer are removed to form open regions on top of both the source and drain regions and spacers are formed. [Figure 8(p)] FIG. 8(o) is a top view of FIG. [Figure 8(q)] FIG. 1 shows that a metal-1 layer interconnect network is formed. [Figure 8(r)] The top view of FIG. 8(q) shows that the gate is connected to the source region by a metal-1 layer. [Figure 9(a)]FIG. 13 is a top view of a construction phase of an mMOSFET used in a novel standard cell according to another embodiment of the present disclosure. [Figure 9(b)] 9(a) is a cross-section of the transistor during the construction phase along cut line C9A1 shown in FIG. 9(a). [Figure 9(c)] 9(a) is a cross-section of the transistor during the construction phase along cut line C9A2 shown in FIG. 9(a). [Figure 9(d)] FIG. 13 is a top view showing the structure after the second and fourth conductor pillars have been formed on the first and third conductor pillars. [Figure 9(e)] FIG. 9(d) is a cross-sectional view taken along the cutting line C9D1 shown in FIG. [Figure 9(f)] FIG. 9(d) is a cross-sectional view taken along the cutting line C9D2 shown in FIG. [Figure 9(g)] FIG. 8 is a top view illustrating the structure after a first conductive layer and a second dielectric sublayer 860 are formed over the first dielectric layer, according to one embodiment of the present disclosure. [Figure 9(h)] FIG. 9(g) is a cross-sectional view taken along the cutting line C9G1 shown in FIG. [Figure 9(i)] FIG. 9(g) is a cross-sectional view taken along the cutting line C9G2 shown in FIG. [Figure 9(j)] FIG. 2 is a top view illustrating the structure after a conductive layer is formed over the upper dielectric layer, according to one embodiment of the present disclosure. [Figure 9(k)] FIG. 9(j) is a cross-sectional view taken along the cutting line C9J1 depicted in FIG. [Figure 9(l)] FIG. 9(j) is a cross-sectional view taken along the cutting line C9J2 depicted in FIG. [Figure 10(a)] FIG. 2 is a top view of an mMOSFET used in a novel standard cell according to one embodiment of the present disclosure. [Figure 10(b)] FIG. 10(b) is a cross-sectional view taken along a cutting line C10A1 depicted in FIG. [Figure 10(c)] FIG. 10A is a cross-sectional view taken along a cutting line C10A2 depicted in FIG. [Figure 10(d)] FIG. 13 is a top view of another mMOSFET used in a new standard cell according to another embodiment of the present disclosure. [Figure 10(e)] FIG. 10(d) is a cross-sectional view taken along the cutting line C10D1 shown in FIG. [Figure 10(f)] FIG. 10(d) is a cross-sectional view taken along the cutting line C10D2 shown in FIG. [Figure 11] FIG. 2 illustrates a cross-section of an NMOS transistor used in a novel standard cell according to another embodiment of the present disclosure. [Figure 12(a)] FIG. 2 is a top view illustrating a combined structure of a PMOS transistor and an NMOS transistor used in a novel standard cell according to one embodiment of the present disclosure. [Figure 12(b)] 12(a) is a cross-sectional view of a PMOS transistor and an NMOS transistor taken along a cutting line (X-axis) in FIG. [Figure 12(c)] 12(a) is a cross-sectional view of a PMOS transistor and an NMOS transistor taken along the cutting line (Y-axis) in FIG. [Figure 13] FIG. 1 is a diagram showing a comparison of area dimensions of a new standard cell provided by the present invention with those of conventional products provided by various other companies. [Figure 14(a)] 5(a)-5(b) and 6(a)-6(b) are top views and corresponding equivalent circuit diagrams of a standard cell having one single NOR cell and one single NAND cell according to some embodiments of the present disclosure. For an embodiment of the standard cell having one single inverter, see FIGS. 5(a)-5(b) and 6(a)-6(b). [Figure 14(b)] 5(a)-5(b) and 6(a)-6(b) are top views and corresponding equivalent circuit diagrams of a standard cell having one single NOR cell and one single NAND cell according to some embodiments of the present disclosure. For an embodiment of the standard cell having one single inverter, see FIGS. 5(a)-5(b) and 6(a)-6(b). [Figure 14(c)]5(a)-5(b) and 6(a)-6(b) are top views and corresponding equivalent circuit diagrams of a standard cell having one single NOR cell and one single NAND cell according to some embodiments of the present disclosure. For an embodiment of the standard cell having one single inverter, see FIGS. 5(a)-5(b) and 6(a)-6(b). [Figure 14(d)] 5(a)-5(b) and 6(a)-6(b) are top views and corresponding equivalent circuit diagrams of a standard cell having one single NOR cell and one single NAND cell according to some embodiments of the present disclosure. For an embodiment of the standard cell having one single inverter, see FIGS. 5(a)-5(b) and 6(a)-6(b). [Figure 14(e)] 5(a)-5(b) and 6(a)-6(b) are top views and corresponding equivalent circuit diagrams of a standard cell having one single NOR cell and one single NAND cell according to some embodiments of the present disclosure. For an embodiment of the standard cell having one single inverter, see FIGS. 5(a)-5(b) and 6(a)-6(b). [Figure 14(f)] 5(a)-5(b) and 6(a)-6(b) are top views and corresponding equivalent circuit diagrams of a standard cell having one single NOR cell and one single NAND cell according to some embodiments of the present disclosure. For an embodiment of the standard cell having one single inverter, see FIGS. 5(a)-5(b) and 6(a)-6(b). [Figure 14(g)] 1A-1C are top views of a standard cell having two inverter cells, two NOR cells, and two NAND cells, and corresponding equivalent circuit diagrams, according to some embodiments of the present disclosure. [Figure 14(h)] 1A-1C are top views of a standard cell having two inverter cells, two NOR cells, and two NAND cells, and corresponding equivalent circuit diagrams, according to some embodiments of the present disclosure. [Figure 14(i)] 1A-1C are top views of a standard cell having two inverter cells, two NOR cells, and two NAND cells, and corresponding equivalent circuit diagrams, according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0039] In conventional standard cells, even with the scaling of feature size or technology node to 28 nm (or less), the transistor size cannot be scaled proportionally. The present invention discloses a novel standard cell with a compact layout style in a monolithic semiconductor die, whereby the area size of the standard cell across different technology nodes can remain uniform or insensitive to the technology node without increasing latch-up issues.

[0040] For example, Figure 5(a) is a stick diagram of a standard cell 500 according to one embodiment of the present invention. Figure 5(b) is a stick diagram with dimensions (in terms of λ) of an inverter cell 500 according to Figure 5(a). Only the gate and diffusion levels of the inverter standard cell 500 are depicted for the purpose of clear and concise description of the structure.

[0041] Here, the inverter standard cell 500 includes an NMOS transistor and a PMOS transistor, the PMOS transistor has a first fin structure consisting of two fins (with a pitch distance Fp between them being 3λ) formed in an n-well region of a semiconductor substrate (not shown) and a gate covering the fin structure, and the NMOS transistor has a second fin structure consisting of two fins (with a pitch distance Fp between them being 3λ) formed in a p-well region of a semiconductor substrate (not shown) and a gate covering the second fin structure. The NMOS transistor is separated from the PMOS transistor by a gap, and there is only one dummy fin disposed between the NMOS transistor and the PMOS transistor.

[0042] The area dimensions of the inverter standard cell 500 may enable a compact design, and as the minimum feature size (λ) of the inverter standard cell 500 decreases progressively for different technology nodes (e.g., from 22 nm to 16 nm, or from 22 nm to 5 nm), λ 2 The area dimensions of the inverter standard cell 500 in terms of conversion are the same or nearly the same. In this embodiment, the width of the active area or fin is λ, the width of the gate line (or polyline) is also similar, Cpp is 4λ, the cell_height is 24λ, and the cell area of ​​the inverter standard cell 500 (marked by the black dashed rectangle, 2×Cpp×cell_height) is 192λ. 2 It is.

[0043] 5(c)-5(f) are diagrams showing a sequence of process layouts for forming a novel inverter standard cell 500 based on FIG. 5(a) and FIG. 5(b) when λ is set to 5 nm. As shown in FIG. 5(a), a plurality of sets of fin structures (e.g., a plurality of horizontal fins) are formed on a semiconductor substrate (not shown), and two adjacent fins 501 formed in the n_well region of the semiconductor substrate are used as active regions of a PMOS transistor. Two adjacent fins 502 formed in the semiconductor substrate and adjacent to the PMOS are used as active regions of an NMOS transistor. Here, two adjacent fins 503 formed in the semiconductor substrate and between the NMOS and PMOS transistors can serve as two dummy fins. In FIG. 5(c), the gap between the PMOS and NMOS transistors is equal to or approximately equal to 3×Fp-Fw, where Fp is the fin pitch distance between the two adjacent fin structures as shown in FIG. 5(a) (e.g., Fp=3λ), and Fw is the fin pitch distance between the two adjacent fin structures as shown in FIG. 5(a). This is the fin width of the fin structure. In this embodiment, the fin width Fw is set to λ (the minimum feature size). Thus, the gap between the PMOS transistor and the NMOS transistor is equal to or approximately equal to 3×Fp-λ (for example, gap=8λ).

[0044] Further, a plurality of gate lines 504 (or polylines) are formed on the semiconductor substrate across the fin structure of the PMOS transistor, the NMOS transistor, and the dummy fin. In this embodiment, the gap (Cpp, marked in FIG. 5(a)) between two gate lines or polylines is a minimum of 4λ. In FIG. 5(c), a plurality of source / drain contacts AA_CT 505 (opening via mask layer for connecting the active areas of the source / drain regions to the metal-1 layer (M1)) and a gate contact Gate_CT 506 (opening via mask layer for directly connecting the polylines to the metal-2 layer (M2)) are formed. In FIG. 5(d), a plurality of metal-1 layers (M1) 507 (width: λ or larger) are formed to connect the plurality of source / drain contacts 505 (AA_CT mask), but the gate contact Gate_CT 506 is not connected to the metal-1 layer (M1) 507. In Figure 5(e), a number of vias 1 508 for connecting the metal-1 layer (M1) 507 to the metal-2 layer (M2) are formed on top of the metal-1 layer (M1) 507. In Figure 5(f), a number of metal-2 layers (M2) 509 are formed to connect the number of vias 1 508 to Vdd, the output terminal, and Vss respectively, and one further metal-2 layer (M2) 510 is formed to directly connect the gate contact Gate_CT 506 to the input terminal.

[0045] Figure 6(a) shows a stick diagram of a standard cell 600 according to another embodiment of the present invention. Figure 6(b) shows a stick diagram with dimensions (in terms of λ) of an inverter cell 600 according to Figure 6(a). Only the gate and diffusion levels of the inverter standard cell 600 are depicted for the purpose of clear and concise description of the structure.

[0046] The inverter standard cell 600 includes an NMOS transistor and a PMOS transistor, the PMOS transistor having a first fin structure consisting of two fins (the pitch distance Fp between them is 3λ) formed in an n-well region of a semiconductor substrate (not shown) and a gate covering the fin structure, and the NMOS transistor having a second fin structure consisting of two fins (the pitch distance Fp between them is 3λ) formed in a p-well region of a semiconductor substrate (not shown) and a gate covering the second fin structure. The NMOS transistor is separated from the PMOS transistor by a gap, and there is only one dummy fin disposed between the NMOS transistor and the PMOS transistor.

[0047] The area dimensions of the inverter standard cell 600 may enable a compact design, and as the minimum feature size (λ) of the inverter standard cell 600 decreases progressively for different technology nodes (e.g., from 22 nm to 16 nm, or from 22 nm to 5 nm), λ 2 The converted area dimensions of the inverter standard cell 600 are the same or nearly the same. In this embodiment, the width of the active area or fin is λ, the width of the gate line (or polyline) is also the same, Cpp is 4λ, the cell_height is 21λ, and the cell area of ​​the inverter standard cell 600 (depicted by the black dashed rectangle, 2×Cpp×cell_height) is 168λ. 2 It is.

[0048] 6(c)-6(f) are diagrams showing a sequence of process layouts for forming a novel inverter standard cell 600 based on FIG. 6(a) and FIG. 6(b) when λ is set to 5 nm. As shown in FIG. 6(a), a plurality of sets of fin structures (e.g., a plurality of horizontal fins) are formed on a semiconductor substrate (not shown), and two adjacent fins 601 formed in an n_well region of the semiconductor substrate are used as active regions of PMOS transistors. Two adjacent fins 602 formed in an n_well region of the semiconductor substrate and adjacent to PMOS are used as active regions of NMOS transistors. Here, only one fin 603 formed in the semiconductor substrate between the NMOS transistor and the PMOS transistor can serve as a dummy fin. In FIG. 6(c), the gap between the PMOS transistor and the NMOS transistor is equal to or approximately equal to 2×Fp-Fw, where Fp is the fin pitch distance between two adjacent fin structures shown in FIG. 6(a) (e.g., Fp=3λ), and Fw is the fin width of the fin structure. In this embodiment, the fin width Fw is set to λ (the minimum feature size). Thus, the gap between the PMOS transistor and the NMOS transistor is equal to or approximately equal to 2×Fp-λ (e.g., gap=5λ).

[0049] Further, a plurality of gate lines 604 (or polylines) are formed on the semiconductor substrate across the fin structure of the PMOS transistor, the NMOS transistor, and the dummy fin. In this embodiment, the gap (Cpp, marked in FIG. 6(a)) between two gate lines or polylines is a minimum of 4λ. In FIG. 6(c), a plurality of source / drain contacts AA_CT 605 (opening via mask layer for connecting the active areas of the source / drain regions to the metal-1 layer (M1)) and a gate contact Gate_CT 506 (opening via mask layer for directly connecting the polylines to the metal-2 layer (M2)) are formed. In FIG. 6(d), a plurality of metal-1 layers (M1) 607 (width: λ or larger) are formed to connect the plurality of source / drain contacts 605 (AA_CT mask), but the gate contact Gate_C 606 is not connected to the metal-1 layer (M1) 607. In Fig. 6(e), a number of vias 1 608 for connecting the metal-1 layer (M1) 607 to the metal-2 layer (M2) are formed based on the metal-1 layer (M1) 607. In Fig. 6(f), a number of metal-2 layers (M2) 609 are formed connecting the number of vias 1 608 to Vdd, the output terminal, and Vss respectively, and one further metal-2 layer (M2) 610 is formed connecting the gate contact Gate_C 606 directly to the input terminal.

[0050] Figure 7(a) shows a stick diagram of a standard cell 700 according to another embodiment of the present invention. Figure 7(b) shows a stick diagram with dimensions (in terms of λ) of an inverter cell 700 according to Figure 7(a). Only the gate and diffusion levels of the inverter standard cell 700 are depicted for the purpose of clear and concise description of the structure.

[0051] The inverter standard cell 700 includes an NMOS transistor and a PMOS transistor, the PMOS transistor having a first fin structure consisting of two fins (with a pitch distance Fp between them being 3.5λ) formed in an n-well region of a semiconductor substrate (not shown) and a gate covering the fin structure, and the NMOS transistor having a second fin structure consisting of two fins (with a pitch distance Fp between them being 3.5λ) formed in a p-well region of a semiconductor substrate (not shown) and a gate covering the second fin structure. The NMOS transistor is separated from the PMOS transistor by a gap, and there is only one dummy fin disposed between the NMOS transistor and the PMOS transistor.

[0052] The area dimensions of the inverter standard cell 700 may allow for a compact design, and as the minimum feature size (λ) of the inverter standard cell 700 decreases progressively for different technology nodes (e.g., from 22 nm to 16 nm, or from 22 nm to 5 nm), λ 2 The area dimensions of the inverter standard cells 700 in terms of conversion are the same or nearly the same. In this embodiment, the width of the active area or fin is λ, the width of the gate line (or polyline) is also similar, Cpp is 4λ, the cell_height is 21λ, and the cell area of ​​the inverter standard cell 500 (marked by the black dashed rectangle, 2×Cpp×cell_height is 168λ) is 168λ. 2 It is.

[0053] 7(c)-7(f) are diagrams showing a sequence of process layouts for forming a novel inverter standard cell 600 based on FIG. 7(a) and FIG. 7(b) when λ is set to 5 nm. As shown in FIG. 7(a), a plurality of sets of fin structures (e.g., a plurality of horizontal fins) are formed on a semiconductor substrate (not shown), and two adjacent fins 701 formed in an n_well region of the semiconductor substrate are used as active regions of PMOS transistors. Two adjacent fins 702 formed in an n_well region of the semiconductor substrate and adjacent to PMOS are used as active regions of NMOS transistors. Here, there is no dummy fin formed in the semiconductor substrate between the NMOS transistor and the PMOS transistor. In FIG. 7(c), the gap between the PMOS transistor and the NMOS transistor is equal to or approximately equal to Fp-Fw, where Fp is the fin pitch distance between the two adjacent fin structures shown in FIG. 7(a) (e.g., Fp=3.5λ), and Fw is the fin width of the fin structure. In this embodiment, the fin width Fw is set to λ (the minimum feature size), and thus the gap between the PMOS and NMOS transistors is equal to or approximately equal to Fp-λ (for example, gap=2.5λ).

[0054] Further, a plurality of gate lines 704 (or poly lines) are formed on the semiconductor substrate across the fin structure of the PMOS transistor, the NMOS transistor, and the dummy fin. In this embodiment, the gap (Cpp, marked in FIG. 7(a)) between two gate lines or poly lines is a minimum of 4λ. In FIG. 7(c), a plurality of source / drain contacts AA_CT 705 (opening via mask layer for connecting the active areas of the source / drain regions to the metal-1 layer (M1)) and a gate contact Gate_CT 706 (opening via mask layer for directly connecting the poly lines to the metal-2 layer (M2)) are formed. In FIG. 7(d), a plurality of metal-1 layers (M1) 707 (width: λ or larger) are formed to connect the plurality of source / drain contacts 705 (AA_CT mask), but the gate contact Gate_C 706 does not connect to the metal-1 layer (M1) 707. In Fig. 7(e), a number of vias 1 708 for connecting the metal-1 layer (M1) 707 to the metal-2 layer (M2) are formed based on the metal-1 layer (M1) 707. In Fig. 7(f), a number of metal-2 layers (M2) 709 are formed to connect the number of vias 1 708 to Vdd, the output terminal, and Vss, respectively. One further metal-2 layer (M2) 710 is formed to directly connect the gate contact Gate_C 706 to the input terminal.

[0055] Conventional standard cells may not allow the gate or source / drain to be directly connected to the metal-2 layer (M2) without bypassing the metal-1 layer (M1). The present invention discloses a novel standard cell structure in which the gate / source / drain can be directly connected to the metal-2 interconnect layer in a self-aligned manner without a transition metal-1 layer by one vertical conductive plug as follows:

[0056] In FIGS. 5(a) to 5(f), 6(a) to 6(f), and 7(a) to 7(f), the meanings of omitted symbols are as follows:

[0057] [Table 4]

[0058] Moreover, those dimensions of the inverter standard cell 500 may be readily achieved by precisely controlling the linear dimensions of the source, drain, and gate of the PMOS and NMOS transistors in the novel inverter standard cell 500, which may be as small as the minimum feature size Lambda (λ), regardless of the dimensions (or minimum feature size) of currently available technology nodes.

[0059] In conventional standard cells, even when the manufacturing process is scaled down to 28 nm or less (so-called "minimum feature size", "λ", or "F"), the dimensions of the metal-oxide-semiconductor field-effect transistors (mMOSFETs) used in the standard cells cannot be scaled down proportionately. However, in this embodiment, when two adjacent transistors (such as the PMOS and NMOS transistors in FIG. 5(a)) are connected to each other via their drain / sources, the distance between the edges of the gates of the two adjacent transistors (i.e., the latch-up distance) can be as small as 8λ. Furthermore, linear dimensions of the contact holes for the source, drain, and gate can be realized in the drain region (and similarly in the source and gate regions) that are less than λ, e.g., 0.6λ to 0.8λ.

[0060] As shown in Fig. 5(b), Fig. 6(b), and Fig. 7(b), each of the PMOS and NMOS includes multiple active areas to maintain a reasonable W / L ratio. Source / drain contacts AA_CT (for connection to the metal-1 layer (M1)) can be formed in the active areas. The present invention realizes a large gate edge to boundary edge design distance (GEBESI) between the source and isolation regions by using a temporary dummy shield gate (DSG) added on the gate-level mask to avoid photolithographic misalignment tolerances (MTP).

[0061] For example, FIG. 8(a) is an example of a miniaturized metal-oxide-semiconductor field-effect transistor (mMOSFET) 800 for use in a novel standard cell, according to one embodiment of the present invention. As shown in FIG. 8( a), mMOSFET 800 includes (1) a gate structure 810 having a length G(L) and a width G(W); (2) a source 803 on the left side of gate structure 810 having a length S(L) and a width S(W), which are the linear dimensions from the edge of gate structure 810 to the edge of isolation region 805; (3) a drain 807 on the right side of gate structure 810 having a length D(L) and a width D(W), which are the linear dimensions from the edge of gate structure 810 to the edge of isolation region 805; (4) a contact hole 809 formed by self-aligned techniques at the center of source 803, the length and width of the opening being labeled CS(L) and CS(W), respectively; and (5) a contact hole 811 formed by self-aligned techniques at the center of drain 807, the length and width of the opening being labeled CD(L) and CD(W), respectively. The length G(L), the length D(L) and the length S(L) can be accurately controlled to a minimum feature size λ. Furthermore, the length and width of the openings denoted as CS(L) and CS(W) or the length and width of the openings denoted as DS(L) and DS(W) can be less than λ, for example, between 0.6λ and 0.8λ.

[0062] The following is a brief description of the manufacturing process of the mMOSFET 800 used in the standard cell of the present invention. A detailed description of the structure of the mMOSFET 800 and its manufacturing process is disclosed in U.S. Patent Application No. 17 / 138,918, filed on December 31, 2020, entitled "MINIATURIZED TRANSISTOR STRUCTURE WITH CONTROLLED DIMENSIONS OF SOURCE / DRAIN AND CONTACT-OPENING AND RELATED MANUFACTURE METHOD," the entire contents of which are incorporated herein by reference.

[0063] As shown in Figure 8(b), a pad oxide layer 802 is formed and a pad nitride layer 804 is deposited on the substrate 801. The active area of ​​the mMOSFET 800 is also defined, and portions of the silicon material outside the active area are removed to create a trench structure, within which an oxide-1 layer is deposited and etched back to form a shallow trench isolation (STI-Oxide 1) 806 below the original horizontal surface ("HSS") of the silicon substrate.

[0064] The pad oxide layer 802 and the pad nitride layer 804 are removed, and a dielectric insulator 812 is formed on the HSS. A gate layer 810 and a nitride layer 814 are then deposited above the HSS, and the gate layer 810 and the nitride layer 814 are etched to form a true gate (TG) of the mMOSFET and a dummy shield gate (DSG) having a desired linear distance to the true gate. As shown in FIG. 8(c), the length of the true gate (TG) is λ, the length of the dummy shield gate (DSG) is also λ, and the distance between the edges of the true gate (TG) and the dummy shield gate (DSG) is also λ.

[0065] Then, a spin-on dielectric (SOD) 712 is deposited, and then the SOD 712 is etched back. As shown in Fig. 8(d), a gate mask layer 802 is formed by a photolithography mask technique, which is appropriately designed. Then, as shown in Fig. 8(e), an anisotropic etching technique is used to remove the nitride layer 614 above the dummy shield gate (DSG), and the dummy shield gate (DSG), the portion of the dielectric insulator 612 corresponding to the dummy shield gate (DSG), and the p-type substrate 601 corresponding to the dummy shield gate (DSG).

[0066] Further, the gate mask layer 802 is removed, the SOD 712 is etched, and the STI-oxide-2 1002 is deposited and then etched back, as shown in Fig. 8(f), then an oxide-3 layer is deposited and etched back to form oxide-3 spacers 1502, a lightly doped drain (LDD) 1504 is formed in the p-type substrate 601, a nitride layer is deposited and etched back to form nitride spacers 1506, and the dielectric insulator 402 is removed, as shown in Fig. 8(g).

[0067] Further, as shown in Fig. 8(h), a selective epitaxial growth (SEG) technique is used to grow an intrinsic silicon electrode 1602. Then, as shown in Fig. 8(i), a CVD-STI-oxide 3 layer 1702 is deposited and etched back to remove the intrinsic silicon 1602 and form a source region (n+ source) 1704 and a drain region (n+ drain) 1706 of the mMOSFET. The source region (n+ source) 1704 and the drain region (n+ drain) 1706 are formed between the intrinsic gate (TG) and the CVD-STI-oxide 3 layer 1702, whose position was originally occupied by the dummy shield gate (DSG), so that the length and width of the source region (n+ source) 1704 (or the drain region (n+ drain) 1706) can be at least λ. The opening of the source region (n+ source) 1704 (or the drain region (n+ drain) 1706) can be less than λ, for example 0.8λ. As shown in FIG. 8(j), such an opening can be reduced if additional oxide spacers 1802 are formed.

[0068] Furthermore, the novel standard cell allows the first metal interconnect (M1 layer) to directly connect the gate, source, and / or drain regions by self-aligned miniaturized contacts without using a conventional contact hole opening mask and / or a metal-0 translation layer for M1 connections. Following FIG. 8(i), an SOD layer 1901 is deposited to fill the holes on the substrate, including the opening 1804 of the source region (n+ source) 1704 (or the drain region (n+ drain) 1706). Then, CMP is used to planarize the surface, as shown in FIG. 8(k). FIG. 8(l) is a top view of FIG. 8(k), showing multiple fingers in the horizontal direction.

[0069] Further, as shown in Fig. 8(m), a properly designed mask is used to implement the photoresist layer 1902, which results in a specific stripe pattern along the X-axis in Fig. 8(l) with separate spaces of length GROC(L) to expose the area of ​​the gate extension region along the Y-axis in Fig. 8(l). As shown in Fig. 8(m), the most aggressive design rule is when GROC(L)=λ. Then, an anisotropic etching technique (shown in Fig. 8(n)) is used to remove the Nitride cap layer in the exposed gate extension region to reveal the conductive metal gate layer.

[0070] After that, the photoresistive layer 1902 is removed, and then the SOD layer 1901 is removed so that the opening areas on the tops of both the source region 1704 and the drain region 1706 are exposed again. Then, an oxide layer 1904 with a properly designed thickness is deposited, and then anisotropic etching techniques are used to form spacers on the four sidewalls in the opening areas of the source region 1704, the drain region 1706, and the exposed gate extension region 1903. Thus, naturally constructed contact hole openings are formed in the exposed gate extension region, the source region 1704, and the drain region 1706, respectively. FIG. 8(o) shows a cross section of such a transistor structure. FIG. 8(p) shows a top view of such a transistor structure in FIG. 8(o). The vertical length CRMG(L) of the opening in the exposed gate extension region 1903 is smaller than the length GROC(L), which may be λ.

[0071] Finally, a metal-1 layer 1905 with a properly designed thickness is formed to fill all the holes of the aforementioned contact hole openings and to be a smooth flat surface following the topography of the wafer surface. Then, as shown in FIG. 8(q), photolithography mask technology is used to generate all the connections between each of the contact hole openings to realize the required metal-1 interconnection network. FIG. 8(r) is a top view of the mMOSFET 800 shown in FIG. 8(q). Thus, this metal-1 layer completes the task of realizing both the contact filling and plug connection functions for the gate and source / drain, along with the direct interconnect function connecting all the transistors. There is no need to use conventional contact hole masks, which are expensive and very tightly controlled, and to continue with the subsequent very difficult process of drilling the contact hole openings, which would be the most difficult challenge, especially in further miniaturizing the horizontal geometry of billions of transistors. Furthermore, it precludes both the insertion of a metal plug into the contact hole opening and the CMP process to realize a metal stud, which is a complex integrated processing step that is clearly required for certain state-of-the-art technologies that produce, for example, metal zero structures.

[0072] Thereby, the dimension of the source / drain contact (such as AA_CT as shown in FIG. 5(b)) can be at least λ×λ, regardless of the technology node dimension (or minimum feature size). Similarly, the gate contact (such as Gate_CT for direct connection with the metal 2 layer (M2 shown in FIG. 5(b)) may be formed on the gate or poly line, and the dimension of the gate contact is also λ×λ. That is, the linear dimensions of the source, drain, and gate of the transistor (such as the PMOS transistor, NMOS transistor in FIG. 5(a)) and their contacts in the standard cell may be precisely controlled, and the linear dimensions can be at least Lambda (λ), the minimum feature size. In this embodiment, the source / drain contact dimensions are larger (e.g., λ (width in Y direction)×2λ (length in X direction)) and the gap between two gates or poly lines is larger than 3λ (e.g., 4 or 5λ).

[0073] Furthermore, as mentioned above, conventional standard cells may not allow the gate or diffusion to be directly connected to M2 without bypassing the M1 structure. The present invention discloses a novel standard cell in which the gate or diffusion (source / drain) area is directly connected to the M2 interconnect layer in a self-aligned manner without the transition layer M1, but elsewhere on the same die, by one vertical conductive plug consisting of Contact-A and Via-1-A, which are respectively formed during the build phase of making Contact and Via-1. As a result, the required space between one M1 interconnect and another M1 interconnect, and blocking issues in certain wiring connections are reduced.

[0074] In the following, we briefly describe an mMOSFET 900 used in a standard cell according to another embodiment of the present invention, in which the gate and diffusion (source / drain) areas are directly connected to the M2 interconnect layer in a self-aligned manner and without the transition layer M1. Figure 9(a) is a top view of the construction phase of mMOSFET 900, and Figures 9(b) and 9(c) are two cross sections of the construction phase of the transistor along cut lines C9A1 and C9A2, respectively, shown in Figure 9(a).

[0075] As shown in Figures 9(b) and 9(c), the mMOSFET 900 is formed and confined by a shallow trench isolator (STI) 905. The mMOSFET 900 has a gate terminal 902, a transistor channel region 903 below the gate terminal 902, and a source / drain region 904. The gate terminal 902 comprises a gate dielectric layer 902a, a gate conductive layer 902b formed on the gate dielectric layer 902a, and a silicon region (or seed region) 902c formed on the gate conductive layer 902b. The silicon region 902c may be made of polysilicon or amorphous silicon. The gate terminal 902 further includes a cap layer 902d (e.g., a nitride layer) on the top of the silicon region 902c, and at least one spacer (e.g., including a nitride spacer 902s1 and a thermal oxide spacer 902s2) on the sidewalls of the gate dielectric layer 902a, the gate conductive layer 902b, and the silicon region 902c. A first dielectric layer 920 is formed on the semiconductor substrate 901 at least covering the active area of ​​the mMOSFET 900, including the gate terminal 902 and the source / drain regions 904, along with the STI 905.

[0076] A plurality of open holes (such as open holes 907a and 907b) are formed in the first dielectric layer 920 to expose a top portion 91 of the silicon region 902c and a top portion 92 of the source / drain region 904. In some embodiments, the open holes 907a and 907b are formed by a photolithography process to remove portions of the first dielectric layer 920 to expose the portions of the silicon region 902c and the silicon region of the drain terminal of the source / drain region 904. In one example, each of the open holes 907a and 907b may have a dimension equal to a minimum feature dimension (e.g., a critical dimension of the mMOSFET 900). Of course, the dimension of the open holes 907a and 907b may be larger than the minimum feature dimension. The bottoms of the open holes 907a and 907b (i.e., exposed top portion 91 and exposed top portion 92), respectively, are made of a material having either polycrystalline / amorphous silicon or crystalline silicon having a high impurity concentration with high electrical conductivity. The exposed silicon region 902c of the gate terminal and the exposed silicon region of the source / drain terminal are seed regions for growing pillars based on the seed regions by selective epitaxial growth technique (SEG).

[0077] Then, as shown in FIG. 9(d)-FIG. 9(f), a heavily doped conductive silicon plug (or conductor pillar) is grown by SEG based on the exposed top portion 91 and the exposed top portion 92 to form a first conductor pillar portion 931a and a third conductor pillar portion 931b. Then, a first dielectric sublayer 940 is formed on the first dielectric layer 920 such that a top surface 940s of the first dielectric sublayer 940 is approximately coplanar with the top surfaces of the first conductor pillar portion 931a and the third conductor pillar portion 931b. The "exposed heads" (or exposed top surfaces) of the first conductor pillar portion 931a and the third conductor pillar portion 931b can be used as seeds for a subsequent SEG process. Furthermore, each of the first conductor pillar portion 931a and the third conductor pillar portion 931b has a seed region or seed pillar in its top portion, which can be used for the following selective epitaxial growth. Then, the second conductor pillar portion 932a is formed on the first conductor pillar portion 931a by a second selective epitaxial growth, and the fourth conductor pillar portion 932b is formed on the third conductor pillar portion 931b. FIG. 9(d) is a top view of the structure after the second conductor pillar portion 932a and the fourth conductor pillar portion 932b are formed on the first conductor pillar portion 931a and the third pillar portion 931b, respectively, according to an embodiment of the present disclosure. FIG. 9(e) is a cross-sectional view taken along the cutting line C9D2 depicted in FIG. 9(d). FIG. 9(f) is a cross-sectional view taken along the cutting line C9D1 depicted in FIG. 9(d).

[0078] Further, as shown in FIG. 9(g)-FIG. 9(i), a first conductive layer 950, such as copper (Cu), aluminum (Al), tungsten (W), or other suitable conductive material, may be deposited on the top surface 940s of the first dielectric sublayer 940. A second conductive sublayer 960 is then deposited on the first conductive layer 950. The first conductive layer 950 and the second dielectric sublayer 960 are patterned to define an open hollow 909, and the first conductor pillar 930A penetrates the open hollow 909 without contacting the first conductive layer 950 and the second dielectric sublayer 960. FIG. 9(g) is a top view illustrating the structure after the first conductive layer 950 and the second dielectric sublayer 960 are formed on the first dielectric sublayer 940, according to one embodiment of the present disclosure. Fig. 9(h) is a cross-sectional view taken along a cutting line C9G1 in Fig. 9(g), and Fig. 9(i) is a cross-sectional view taken along a cutting line C9G2 in Fig. 9(g).

[0079] Also, as shown in FIGS. 9(j)-9(l), an upper dielectric layer 970 is deposited to cover the second dielectric sublayer 960 and the first dielectric sublayer 940 and fill the open hollow 909. The top surface 970s of the upper dielectric layer 970 is lower than the top surface 930t of the first conductor pillar 930A (including the first conductor pillar portion or subpillar 931a and the second conductor pillar portion or subpillar 932a) and the second conductor pillar 930B (including the third conductor pillar portion or subpillar 931b and the fourth conductor pillar portion or subpillar 932b). Then, an upper conductive layer 980 is formed on the upper dielectric layer 970, and the first conductor pillar 930A connects to the upper conductive layer 980 but is not connected to the first conductive layer 950. In this example, Figure 9(j) is a top view of the structure after a conductive layer 980 is formed over the top dielectric layer 970, according to one embodiment of the present disclosure. Figure 9(k) is a cross-sectional view taken along cut line C9J1 depicted in Figure 9(j). Figure 9(l) is a cross-sectional view taken along cut line C9J2 depicted in Figure 9(j).

[0080] As mentioned above, each of the exposed silicon regions 702c of the gate terminal and the exposed silicon regions of the source / drain terminal has a seed region for growing a pillar based on the seed region by selective epitaxial growth technique (SEG). Furthermore, each of the first conductor pillar portion 931a and the third conductor pillar portion 931b also has a seed region or seed pillar in its top portion, which can be used for the following selective epitaxial growth. This embodiment can also be applied to enable the M1 interconnect (a kind of conductive terminal) or conductive layer to be directly connected to the MX interconnect layer (without connecting to the conductive layers M2, M3, ..MX-1) in a self-aligned manner by one vertical conductive or conductor plug, as long as there is a seed portion or seed pillar on the top portion of the conductive terminal and the conductive pillar portion is configured for the following selective epitaxial growth technique. The seed portion or seed pillar is not limited to silicon, and any material acceptable as a seed configured for the following selective epitaxial growth can be used.

[0081] In summary, the novel standard cell and the standard cell have at least the following advantages: (1) The linear dimensions of the source, drain, and gate of a transistor in a standard cell are precisely controlled, and the linear dimensions can be as small as Lambda (λ), the minimum feature size. Thus, if two adjacent transistors are connected to each other via their drain / source, the linear dimension of the transistor can be as small as 3λ, and the distance between the edges of the gates of two adjacent transistors can be as small as 2λ. Of course, for tolerance purposes, the linear dimension of the transistor can be about 3λ to 6λ or more, and the distance between the edges of the gates of two adjacent transistors can be 8λ or more. (2) The first metal interconnect (M1 layer) directly connects the gate, source and / or drain regions by self-aligned scaled contacts without the use of conventional contact hole opening masks and / or metal-0 intervening layers for M1 connections. (3) The gate and / or diffusion (source / drain) areas are directly connected to the metal 2 (M2) interconnect layer in a self-aligned manner without connecting the metal 1 layer (M1). Thus, the required space between one metal 1 layer (M1) interconnect layer and the other metal 1 layer (M1) interconnect layer and the blocking problem in some wiring connections are reduced. Furthermore, the same structure can be applied when the lower metal layer is directly connected to the upper metal layer by a conductor pillar, but the conductor pillar is not electrically connected to any intermediate metal layer between the lower metal layer and the upper metal layer. (4) The metal wiring for the high-level voltage Vdd and / or low-level voltage VSS in the standard cells may be located below the original silicon surface of the silicon substrate, so that interference between the dimensions of the contacts and the layout of the metal wiring connecting the high-level voltage Vdd and the low-level voltage VSS, etc. may be avoided even when the dimensions of the standard cells are reduced. Furthermore, the openings for the source / drain regions, originally used to electrically couple the source / drain regions to the metal 2 layer (M2) or metal 3 layer (M3) for Vdd or ground connection, may be omitted in the new standard cells and in the standard cells.

[0082] In some alternative embodiments, the conductor pillar may be a metal conductor pillar or may be a composite conductor pillar having a metal conductor pillar and a seed region or seed pillar on its top portion. For example, FIG. 10(a) is a top view of an mMOSFET 1000 used in a novel standard cell according to one embodiment of the present disclosure. FIG. 10(b) is a cross-sectional view taken along the cut line C10A1 depicted in FIG. 8(a). FIG. 10(c) is a cross-sectional view taken along the cut line C10A2 depicted in FIG. 10(a). In this embodiment, the conductor pillar mMOSFET 1000 used to connect the interconnect layer includes a tungsten pillar and a first highly doped silicon pillar, with a seed region or seed pillar in its top portion.

[0083] As shown in Figures 10(a)-10(c), the heavily doped N+ polysilicon pillars 931a, 932a, 931b, and 932b in Figures 9(j)-9(l) may be removed and replaced by tungsten pillars 1030w, TiN layer 1030n, and heavily doped silicon pillars. The first conductor pillar includes a metal pillar portion 1030A (including tungsten pillar 830w and TiN layer 1030n) and a heavily doped silicon pillar 1010a, and the second conductor pillar includes a metal pillar portion 1030B (including tungsten pillar 1030w and TiN layer 1030n) and a heavily doped silicon pillar 1010b. The heavily doped silicon pillars 1010a and 1010b serve as seed regions or seed pillars for growing conductor pillars configured to connect metal connections formed below. For example, the heavily doped silicon pillars 1010a and 1010b serve as seed regions or seed pillars for the following SEG process to grow another silicon pillar thereon to connect the first conductive layer 1050a or 1050b formed on the first dielectric sublayer 1040 and electrically connected to the heavily doped silicon pillars 1010a and 1010b. The conductor pillars may have seed regions or seed pillars in their top portions, which are seed regions or seed pillars for the conductor pillars that the following SEG process configures to grow another silicon pillar thereon, thus achieving a borderless contact.

[0084] In some embodiments, the width of the metal contact line (such as the first metal sublayer 1050a or 1050b) may be the same or approximately the same as the width of the contact (such as the heavily doped silicon pillar 1010a or 1010b). Of course, the width of the metal contact line may be different from the width of the first contact. As shown in Figures 10(d)-10(f), the width of the metal conductor line (such as the first metal sublayer 1050a or the second metal sublayer 1050b) is also not the same as the width of the underlying contact plug (which may be at least the minimum feature dimension of the heavily doped silicon pillar 1010a or 1010b). However, although there may be misalignment between the metal conductor and the underlying contact plug, and photolithography mask misalignment tolerances may result in the metal conductor (such as the first metal sub-layer 1050a or the second metal sub-layer 1050b) not being able to completely cover the contact (such as the heavily doped silicon pillar 1010a or 1010b as shown in Figures 10(e) and 10(f)), there is no concern that the resistance between the metal conductive layer and the contact may be too high due to insufficient contact area.

[0085] Thus, the resistance between the metal conductor and the lower contact can be well controlled. Here, the present invention uses selective growth (SEG or other selective deposition methods) to grow a specific ultra-heavily doped silicon material that connects both the metal conductor and the lower contact plug, improving the resistance problem caused by the misalignment between the metal conductor and the lower contact plug. In this embodiment, a further SEG process is performed to grow a specific ultra-heavily doped silicon material (side pillar 1020) to attach the vertical walls of the metal conductive layers 1050a and 1050b. FIG. 10(d) is a top view of another mMOSFET used in a novel standard cell according to another embodiment of the present disclosure, and FIG. 10(e) is a cross-sectional view taken along the cut line C10D1 depicted in FIG. 10(d). FIG. 10(f) is a cross-sectional view taken along the cut line C10D2 depicted in FIG. 10(d).

[0086] Conventional standard cells cannot allow the gate or source / drain to be directly connected to the metal 2 layer (M2) without bypassing the metal 1 layer (M1). The present invention discloses a novel standard cell structure in which the gate / source / drain can be directly connected to the metal-2 interconnect layer (M2) without the transition metal-1 layer (M1) in a self-aligned manner by one vertical conductive plug. A detailed description of the gate area / active area directly connected to the metal-2 interconnect layer (M2) is disclosed in U.S. Patent Application No. 17 / 528,957, filed on November 17, 2021, and entitled "INTERCONNECTION STRUCTURE AND MANUFACTURE METHOD THEREOF," the entire contents of which are incorporated herein by reference.

[0087] Furthermore, the present invention discloses a novel MOS structure in which the source and drain regions are fully separated by an insulator, which not only improves the immunity to latch-up problems but also increases the isolation distance into the silicon substrate, separates the junctions in adjacent transistors and reduces the surface distance between the junctions (e.g., 3λ), as well as the standard cell dimensions. Below, a brief description is given of a novel CMOS structure in which the n+ and p+ regions of the source and drain regions in NMOS and PMOS transistors, respectively, are fully separated by an insulator.

[0088] Please refer to FIG. 11, which shows a cross-section of an NMOS transistor 51 used in a novel standard cell according to another embodiment of the present disclosure. A gate structure 33 comprising a gate dielectric layer 331 and a gate conductive layer 332 (such as a gate metal) is above a horizontal or original surface of a semiconductor substrate (such as a silicon substrate). A dielectric cap 333 (such as a composite of an oxide layer and a nitride layer) is above the gate conductive layer 332. In addition, a spacer 34, which may include a composite of an oxide layer 341 and a nitride layer 342, is used to cover the sidewall of the gate structure 33. A trench is formed in the silicon substrate, and all or at least a portion of a source region 55 and a drain region 56 are positioned in the corresponding trench, respectively. The source (or drain) region in the MOS transistor 52 may include an N+ region or other suitable doping profile region (e.g., a gradual or step change from a P- region and a P+ region).

[0089] Further, a local isolation 48 (such as a nitride or other high-k dielectric material) is disposed in the trench and positioned below the source region, and another local isolation 48 is disposed in another trench and positioned below the drain region. Such local isolation 48 is below the horizontal silicon surface (HSS) of the silicon substrate and may be referred to as local isolation into silicon substrate (LISS) 48. The LISS 48 may be a composite of a thick nitride layer or a dielectric layer. For example, the local isolation or LISS 48 may comprise a composite local isolation including an oxide layer (referred to as oxide-3V layer 481) covering at least a portion of the sidewall of the trench and another oxide layer (oxide-3B layer 482) covering at least a portion of the bottom wall of the trench. The oxide-3V layer 481 and the oxide-3B layer 482 may be formed by a thermal oxidation process.

[0090] The composite local isolation 48 further includes a nitride layer 483 (referred to as a nitride-3 layer) on top of the oxide-3B layer 482 and in contact with the oxide-3V layer 481. It is noted that the nitride layer 483 or nitride-3 can be replaced by any suitable insulating material as long as the oxide-3V layer remains maximally as designed. Furthermore, the STI (Shallow Trench Isolation) region in FIG. 9 may include a composite STI 49 including an STI-1 layer 491 and an STI-2 layer 492, and the STI-1 layer 491 and the STI-2 layer 492 can each be made of thick oxide material by different processes.

[0091] Further, the source (or drain) region in FIG. 11 may comprise a composite source region 55 and / or drain region 56. For example, in an NMOS transistor 51, the composite source region 55 (or drain region 56) comprises at least a lightly doped drain (LDD) 551 and an N+ heavily doped region 552 in a trench. It should be noted that, in particular, the lightly doped drain (LDD) 551 abuts an exposed silicon surface having a uniform (110) crystal orientation. The exposed silicon surface has its vertical boundary with a suitable recessed thickness, labeled in FIG. 11 as the transistor body (thickness) appropriately defined and etched to be a sharp edge of the TEC (effective channel length), as opposed to the edge of the gate structure. The exposed silicon surface is substantially aligned with the gate structure. The exposed silicon surface may be the terminal surface of the transistor's channel.

[0092] A lightly doped drain (LDD) 551 and a heavily doped N+ region 552 may be formed based on a selective epitaxial growth (SEG) technique (or other suitable technique, which may be atomic layer deposition ALD or selective growth ALD-SALD) to grow silicon from the exposed TEC area, which is used as a crystal seed to form a properly ordered (110) new lattice over the LISS region, which has no seeding effect on the changing (110) crystal structure of the newly formed crystal of the composite source region 55 or drain region 56. Such newly formed crystal (including the lightly doped drain (LDD) 551 and the heavily doped N+ region 552) may be named TEC-Si, as noted in FIG. 9.

[0093] In one embodiment, the TEC is aligned or substantially aligned with the edge of the gate structure 33, the length of the LDD 551 is adjustable, and the sidewall of the LDD 551, opposite the TEC, can be aligned or substantially aligned with the sidewall of the spacer 34. The composite source (or drain) region can further comprise several tungsten (or other suitable metal material) plugs 553 formed in horizontal connection with the TEC-Si portion for the completion of the entire source / drain region. As shown in FIG. 9, the active channel current flowing to a subsequent metal interconnect such as a metal-1 layer flows through the LDD 551 and the N+ heavily doped region 552 to the tungsten 553 (or other metal material) directly connected to metal-1 with much lower resistance than a conventional silicon-to-metal contact due to a certain good metal-to-metal ohmic contact.

[0094] The source / drain contact resistance of the NMOS transistor 51 can be kept within a reasonable range depending on the structure of the merged metal-semiconductor junction utilized in the source / drain structure, as shown in FIG. 11. The merged metal-semiconductor junction in the source / drain structure can improve the current crowding effect and reduce the contact resistance. Furthermore, since the bottom of the source / drain structure is separated from the substrate by the bottom oxide (oxide-3B layer 482) (shown in FIG. 11), the separation between n+ and n+ or between p+ and p+ can be kept within a reasonable range. Thus, the spacing between two adjacent active areas of the PMOS transistor (not shown) can be reduced to 2λ. The bottom oxide (oxide-3B layer 482) can significantly reduce the source / drain junction leakage current, which in turn reduces the leakage current between n+ and n+ or between p+ and p+.

[0095] Furthermore, in conventional standard cells, metal wiring for high-level voltage Vdd and low-level voltage Vss (or ground) is arranged on the original silicon surface of the silicon substrate, and such arrangement interferes with other metal wirings if there is not enough space between them. The present invention discloses a novel standard cell in which metal wiring for high-level voltage Vdd and / or low-level voltage Vss can be arranged below the original silicon surface of the silicon substrate, so that the interference of the dimensions of contacts and the layout of metal wiring connecting high-level voltage Vdd and low-level voltage Vss, etc. can be avoided even if the dimensions of the standard cell are reduced.

[0096] In another embodiment, in the drain region of NMOS 51, tungsten or other metal material 553 is directly coupled to a P-well electrically coupled to Vdd, without oxide-3B layer 482 and nitride layer 483. Meanwhile, in the source region of NMOS 51, tungsten or other metal material 553 can be directly coupled to a p-well or P-substrate electrically coupled to ground. Thus, the openings for the source / drain regions, originally used to electrically couple the source / drain regions to the metal 2 layer (M2) or metal 3 layer (M3) for Vdd or ground connection, can be omitted in the new standard cell and in the standard cell. A detailed description of the structure and its manufacturing process is disclosed in U.S. Patent Application No. 16 / 991,044, filed on August 11, 2020, entitled "TRANSISTOR STRUCTURE AND RELATED INVERTER," the entire contents of which are incorporated herein by reference.

[0097] FIG. 12(a) is a top view showing a combined structure of PMOS transistor 52 and NMOS transistor 51 used in a novel standard cell according to one embodiment of the present disclosure. FIG. 12(b) is a cross-sectional view of PMOS transistor 52 and NMOS transistor 51 cut along the cut line (X-axis) in FIG. 12(a). As shown in FIG. 12(b), this results in a much longer path from the n+ / p junction through the p-well (or p-substrate) / n-well junction to the n / p+ junction. Possible latch-up paths from the LDD-n / p junction through the p-well / n-well junction to the n / LDD-p junction include length (1), length (2) (length of the bottom wall of one LISS region), length (3), length (4), length (5), length (6), length (7) (length of the bottom wall of another LISS region), and length (8) as marked in FIG. 12(b). On the other hand, in a conventional CMOS structure combining PMOS transistor 12 and NMOS transistor 11 shown in FIG. 2, the possible latch-up path from n+ / p junction through p-well / n-well junction to n / p+ junction only includes length (d), length (e), length (f), and length (g) (shown in FIG. 2). Such possible latch-up path in FIG. 12(b) is longer than the path in FIG. 2. Therefore, from the viewpoint of device layout, the ensured edge distance (Xn+Xp) between PMOS transistor 52 and NMOS transistor 51 in FIG. 12(b) can be smaller than the edge distance in FIG. 2. For example, the ensured edge distance (Xn+Xp) can be about 2 to 4λ, for example 3λ.

[0098] Furthermore, unlike conventional standard cells, the present invention utilizes cross-shaped local isolation (LISS) into the silicon substrate (e.g., nitride-3+oxide-3) between the PMOS transistor 52 and the NMOS transistor 51 of the standard cell, so that the possible latch-up path between the PMOS transistor 52 and the NMOS transistor 51 can be longer than that in conventional CMOS, and the latch-up distance or ensured edge distance between the PMOS transistor 52 and the NMOS transistor 51 can be shorter than that used in conventional standard cells.

[0099] Therefore, the latch-up distance between PMOS transistor 52 and NMOS transistor 51 in the present invention is a minimum of 8λ, regardless of the technology node size (or minimum feature size). In the present invention, the n+ and p+ regions of the source and drain regions in the NMOS and PMOS transistors, respectively, are fully separated by insulators, which not only improves resistance to latch-up problems but also increases the isolation distance into the silicon substrate to separate the junctions in PMOS transistor 52 and NMOS transistor 51 such that the surface distance between the junctions can be reduced. A detailed description of the novel combined PMOS and NMOS structure is disclosed in U.S. patent application Ser. No. 17 / 318,097, filed May 12, 2021, and entitled "COMPLEMENTARY MOSFET STRUCTURE WITH LOCALIZED ISOLATIONS IN SILICON SUBSTRATE TO REDUCE LEAKAGES AND PREVENT LATCH-UP," the entire contents of which are incorporated by reference herein.

[0100] To solve the problem of small I-on current when source / drain contact dimensions are small, the present invention may further use a selective growth method (e.g., selective epitaxial growth (SEG) technique) to grow a thin channel layer 1001 covering the original body of the active region (such as fin structure 1003) under the gate structure 33 of the PMOS transistor 52 (or NMOS transistor 51) to improve the electron / hole mobility. For example, FIG. 12(c) is a cross-sectional view of the PMOS transistor 52 and the NMOS transistor 51 cut along the cut line (Y-axis) in FIG. 12(a). The thin channel layer 1001 is a doped channel layer formed without ion implantation. Moreover, the thin channel layer 1001 is not a part of the original silicon substrate, and thus the thin channel layer 1001 is independent of the semiconductor substrate. Moreover, in one embodiment, the thin channel layer 1001 covers the first sidewall and the second sidewall of the fin structure 1003, but does not cover the top surface of the fin structure 1003. In another embodiment, the thin channel layer 1001 comprises a top portion (not shown) covering a top surface of the fin structure 1003 and a side portion covering a first sidewall and a second sidewall of the fin structure, the top portion and the side portion being not formed simultaneously. A detailed description of the improved I-on current of the transistor is disclosed in U.S. Provisional Patent Application No. 63 / 226,787, filed on July 29, 2021, and entitled "New Transistor Structure and Processing Method Thereof," the entire contents of which are incorporated herein by reference.

[0101] According to the above, a standard cell in which an inverter is housed (such as the novel inverter cell 500 shown in FIGS. 5(a) and 5(b)) has an area dimension of (2×Cpp×cell_height) 192λ in the novel structure of the present invention. 2 and λ 2Such area dimensions in conversion are approximately the same at least from technology node 22 nm to 5 nm as compared to conventional products provided by various companies (such as A_Company, B_Company, C_Company, etc.) as shown in Figure 13. Figure 13 is a diagram showing the results of comparing the area dimensions of the new standard cell provided by the present invention with the area dimensions of conventional products provided by various other companies.

[0102] However, the layout style and area dimensions of the novel standard cells are not limited to these items. In some other embodiments, the present invention may be utilized in a variety of standard cells (e.g., a standard cell having one single NOR cell, one single NAND cell, 2×NOR cells, or 2×NAND cells) with different layout styles and cell dimensions (e.g., 3×Cpp×cell_height, or 5×Cpp×cell_height).

[0103] For example, FIGS. 14(a)-14(f) are top views and corresponding equivalent circuit diagrams of a standard cell having one single NOR cell and one single NAND cell according to some embodiments of the present disclosure. FIGS. 14(g)-14(i) are top views and corresponding equivalent circuit diagrams of a standard cell having two inverter cells, two NOR cells, and two NAND cells according to some embodiments of the present disclosure. A standard cell having one single NOR cell, one single NAND cell, and two inverter cells may have a cell dimension of 3×Cpp×Cell_Height, and a standard cell having two NOR cells and two NAND cells may have a cell dimension of 5×Cpp×Cell_Height. For an embodiment of a standard cell having one single inverter, see FIGS. 5(a)-5(b) and 6(a)-6(b).

[0104] The present invention develops a compact layout style in a novel standard cell design. In some embodiments of the present disclosure, the novel, compact layout style has an area dimension λ that can be independent of technology scaling in terms of λ (Lambda is the minimum feature size of a technology node). 2 In the layout design described herein, the area dimensions of the standard cells across different technology nodes can remain uniform or insensitive to the technology node. Furthermore, the latch-up problem does not increase as the standard cell dimensions become smaller.

[0105] While the invention has been described by way of example and in terms of preferred embodiment(s), it is to be understood that the invention is not limited thereto, but on the contrary, it is intended to cover various modifications and similar arrangements and procedures, and therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.

Claims

1. A standard cell, a plurality of transistors, the plurality of transistors including PMOS transistors and NMOS transistors; a plurality of contacts coupled to the plurality of transistors; at least one input line electrically coupled to the plurality of transistors; an output line electrically coupled to the plurality of transistors; a VDD contact line electrically coupled to the plurality of transistors; a VSS contact line electrically coupled to the plurality of transistors; Equipped with a first set of fin structures electrically coupled to each other, and a second set of fin structures electrically coupled to each other, and the NMOS transistor includes a first set of fin structures electrically coupled to each other, and there is no fin structure disposed between the PMOS transistor and the NMOS transistor.

2. The standard cell of claim 1 , wherein a gap between an edge of the PMOS transistor and an edge of the NMOS transistor is smaller than a pitch distance between two adjacent fin structures in the PMOS transistor.

3. The standard cell of claim 1 , wherein a pitch distance Fp between two adjacent fin structures in the PMOS transistor is less than or equal to 4λ.

4. The standard cell of claim 1 , wherein the standard cell is an inverter cell, a NAND cell, or a NOR cell.

5. a metal contact line electrically coupled to a first contact of the plurality of contacts; The standard cell of claim 1 , wherein the first contact is not completely covered by the metal contact line.

6. The standard cell of claim 5 , wherein the width of the metal contact line is the same or approximately the same as the width of the first contact.

7. a heavily doped silicon plug formed on a portion of the first contact that is not covered by the metal contact line; The standard cell of claim 5 , wherein the heavily doped silicon plug contacts the metal contact line.

8. a first metal line electrically coupled to the plurality of transistors; a second metal line electrically coupled to the plurality of transistors, the second metal line being above the first metal line; Further equipped with 2. The standard cell of claim 1, wherein at least one of the plurality of contacts connects directly to the second metal line without passing through the first metal line.

9. The standard cell of claim 8 , wherein the at least one of the set of contacts is a gate contact.

10. At least one of the plurality of transistors comprises a fin structure and a channel layer overlying the fin structure; The standard cell of claim 1 , wherein the channel layer is a doped epitaxial layer.

11. The standard cell of claim 10 , wherein the channel layer covers a first sidewall and a second sidewall of the fin structure and does not cover a top surface of the fin structure.

12. 11. The standard cell of claim 10, wherein the channel layer comprises a top portion covering a top surface of the fin structure and a side portion covering a first sidewall and a second sidewall of the fin structure, the top portion and the side portion being separate, doped epitaxial layers.

Images