Semiconductor substrate, semiconductor device and method of manufacturing the same

Abstract

To provide a method of manufacturing a semiconductor substrate which has few defects and low ON-resistance.SOLUTION: A method of manufacturing a semiconductor substrate includes the steps of: forming a second silicon carbide layer in which the first conductivity type impurity concentration is lower than that of a first silicon carbide layer, the first conductivity type impurity concentration is 1×1014 atoms / cm3 or more and 1×1017 atoms / cm3 or less and the film thickness is 0.001 μm or more and 0.1 μm or less, on the first silicon carbide layer by an epitaxial growth method; forming a third silicon carbide layer in which the first conductivity type impurity concentration is 5×1017 atoms / cm3 or more and less than 1×1020 atoms / cm3 and the film thickness is 0.5 μm or more and 20 μm or less, on the second silicon carbide layer by the epitaxial growth method; forming a fourth silicon carbide layer in which the first conductivity type impurity concentration is lower than that of the third silicon carbide layer, on the third silicon carbide layer by the epitaxial growth method; and performing heat treatment of the first silicon carbide layer, the second silicon carbide layer, the third silicon carbide layer and the fourth silicon carbide layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor substrate, a semiconductor device, and a method for manufacturing the same. [Background technology]

[0002] SiC (silicon carbide) is expected to be a material for next-generation semiconductor devices. Compared to Si (silicon), silicon carbide has about three times the band gap, about ten times the breakdown electric field strength, and about three times the thermal conductivity. Therefore, by using SiC, it is possible to realize semiconductor devices that are low-loss and capable of operating at high temperatures. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2009-088223 A [Non-patent literature]

[0004] [Non-Patent Document 1] Fuji Electric Technical Review 2017vol.90 no.4 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a semiconductor substrate having fewer defects and low on-resistance, a semiconductor device, and a method for manufacturing the same. [Means for solving the problem]

[0006] In the method for manufacturing a semiconductor substrate according to the embodiment, a first conductive type impurity layer having a first conductivity type impurity concentration lower than that of the first silicon carbide layer and having a first conductive type impurity concentration of 1×10 14 atoms / cm 3 That's 1x10 17 atoms / cm 3forming a second silicon carbide layer having a thickness of 0.001 μm or more and 0.1 μm or less by epitaxial growth; and depositing a first conductive type impurity having a concentration of 5×10 on the second silicon carbide layer. 17 atoms / cm 3 That's 1x10 20 atoms / cm 3 forming a third silicon carbide layer having a thickness of 0.5 μm or more and 20 μm or less by epitaxial growth; forming a fourth silicon carbide layer having a first conductivity type impurity concentration lower than that of the third silicon carbide layer by epitaxial growth on the third silicon carbide layer; and performing heat treatment of the first silicon carbide layer, the second silicon carbide layer, the third silicon carbide layer and the fourth silicon carbide layer. [Brief description of the drawings]

[0007] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor substrate and a semiconductor device according to a first embodiment. [Diagram 2] 1A to 1C are schematic cross-sectional views illustrating manufacturing processes of the semiconductor substrate and the semiconductor device according to the first embodiment. [Diagram 3] 1A to 1C are schematic cross-sectional views illustrating manufacturing processes of the semiconductor substrate and the semiconductor device according to the first embodiment. [Figure 4] 4 is a flowchart of a manufacturing process of the semiconductor substrate and the semiconductor device according to the first embodiment. [Diagram 5] FIG. 5 is a schematic cross-sectional view of a semiconductor substrate and a semiconductor device according to a second embodiment. [Figure 6] 5A to 5C are schematic cross-sectional views illustrating manufacturing processes of the semiconductor substrate and the semiconductor device according to the second embodiment. [Figure 7] 10 is a flowchart of a manufacturing process of a semiconductor substrate and a semiconductor device according to a second embodiment. [Figure 8] FIG. 11 is a schematic cross-sectional view of a semiconductor substrate and a semiconductor device according to a third embodiment. [Figure 9] 10 is a flowchart of a manufacturing process of a semiconductor substrate and a semiconductor device according to a third embodiment. [Figure 10] 11A and 11B are schematic cross-sectional views of a semiconductor device according to a fourth embodiment; [Figure 11] 13A and 13B are schematic cross-sectional views of a semiconductor device according to a fifth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same members are designated by the same reference numerals, and the description of members that have already been described will be omitted as appropriate.

[0009] In the following description, n + , n, n - And, p + , p, p - When the notations are used, these notations indicate the relative high and low impurity concentrations in each conductivity type. + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than that of p. + type, n - The types are simply n-type and p-type. + type, p - The type is sometimes simply referred to as p-type.

[0010] The impurity concentration can be measured, for example, by SIMS (Secondary Ion Mass Spectrometry). The relative level of the impurity concentration can also be determined from the level of the carrier concentration obtained, for example, by SCM (Scanning Capacitance Microscopy). The distance, such as the depth, of the impurity region can be obtained, for example, by SIMS. The distance, such as the width and depth of the impurity region can be obtained, for example, from an SCM image.

[0011] The evaluation of defects can be performed by, for example, KOH etching, reflection X-ray topography, transmission X-ray topography, TEM (Transmission Electron Microscope), and photoluminescence imaging.

[0012] Hereinafter, the first conductivity type will be referred to as n-type, and the second conductivity type will be referred to as p-type.

[0013] In this specification, in order to indicate the positional relationship of parts, etc., the upward direction of the drawing is described as "upper" and the downward direction of the drawing is described as "lower." In this specification, the concepts of "upper" and "lower" are not necessarily terms that indicate a relationship with the direction of gravity.

[0014] (First embodiment) In the method for manufacturing a semiconductor substrate according to the present embodiment, a silicon carbide layer having a first conductivity type impurity concentration lower than that of the first silicon carbide layer and having a first conductivity type impurity concentration of 1×10 14 atoms / cm 3 That's 1x10 17 atoms / cm 3 forming a second silicon carbide layer having a thickness of 0.001 μm or more and 0.1 μm or less by epitaxial growth; and depositing a first conductive type impurity having a concentration of 5×10 on the second silicon carbide layer. 17 atoms / cm 3 That's 1x10 20 atoms / cm 3 forming a third silicon carbide layer having a thickness of 0.5 μm or more and 20 μm or less by epitaxial growth; forming a fourth silicon carbide layer having a first conductivity type impurity concentration lower than that of the third silicon carbide layer by epitaxial growth on the third silicon carbide layer; and performing heat treatment of the first silicon carbide layer, the second silicon carbide layer, the third silicon carbide layer and the fourth silicon carbide layer.

[0015] The method for manufacturing the semiconductor device of this embodiment includes the steps of forming a ninth silicon carbide layer of a second conductivity type on the fourth silicon carbide layer of the semiconductor substrate of this embodiment, forming a first electrode under the first silicon carbide layer, and forming a second electrode on the ninth silicon carbide layer.

[0016] The semiconductor substrate of the present embodiment includes a first silicon carbide layer and a first conductive type impurity having a concentration of 1×10 17 cm -3 atoms / cm 3 That's 1x10 19 cm -3 atoms / cm 3 a fifth silicon carbide layer having a first conductivity type impurity concentration of less than 5×10 17 cm -3 atoms / cm 3 That's 1x10 20 cm -3 atoms / cm 3 and a fourth silicon carbide layer provided on the third silicon carbide layer and having a first conductivity type impurity concentration lower than that of the third silicon carbide layer, wherein in a region including the first silicon carbide layer and the fifth silicon carbide layer, in a direction from the first silicon carbide layer to the fifth silicon carbide layer, a concentration gradient of the first conductivity type impurity is different from a concentration gradient of an impurity different from the first conductivity type impurity.

[0017] The semiconductor substrate of the present embodiment includes a first silicon carbide layer and a first conductive type impurity having a concentration of 1×10 17 cm -3 atoms / cm 3 That's 1x10 19 cm -3 atoms / cm 3 a fifth silicon carbide layer having a first conductivity type impurity concentration of less than 5×10 17 cm -3 atoms / cm 3 That's 1x10 20 cm -3 atoms / cm 3a third silicon carbide layer having a thickness of 0.5 μm or more and 20 μm or less, and a fourth silicon carbide layer provided on the third silicon carbide layer and having a first conductivity type impurity concentration lower than that of the third silicon carbide layer, 2 or more, and the BPD density of the third silicon carbide layer and the fourth silicon carbide layer is 0.1 pieces / cm 2 The following is the result.

[0018] Fig. 1 is a schematic cross-sectional view of a semiconductor substrate 100 and a semiconductor device 200 according to the present embodiment. Fig. 1(a) is a schematic cross-sectional view of the semiconductor substrate 100 and the semiconductor device 200 according to the present embodiment. Fig. 1(b) is a schematic view showing the impurity concentration in the Z direction of the semiconductor device 200.

[0019] The semiconductor substrate 100 includes a first silicon carbide layer 4, a fifth silicon carbide layer 12, a third silicon carbide layer 8, and a fourth silicon carbide layer .

[0020] The semiconductor device 200 includes a semiconductor substrate 100, a first electrode 60, a ninth silicon carbide layer 20, and a second electrode 62.

[0021] The semiconductor device 200 of this embodiment is a PIN diode.

[0022] Here, an X direction, a Y direction perpendicular to the X direction, and a Z direction perpendicular to the X direction and the Y direction are defined. The first silicon carbide layer 4, the fifth silicon carbide layer 12, the third silicon carbide layer 8, and the fourth silicon carbide layer 10 are provided parallel to each other in the XY plane. The Z direction is the direction in which the first electrode 60, the first silicon carbide layer 4, the fifth silicon carbide layer 12, the third silicon carbide layer 8, the fourth silicon carbide layer 10, and the second electrode 62 are stacked. The Z direction is the direction from the first electrode 60 toward the second electrode 62.

[0023] n + The first silicon carbide layer 4 is doped with an n-type impurity of, for example, 1×10 18 atoms / cm 3 More than 1×10 19 atoms / cm3 The following are included. The n-type impurity is, for example, N (nitrogen). However, the n-type impurity may be, for example, P (phosphorus). The n-type impurity may be both N (nitrogen) and P (phosphorus). The first silicon carbide layer 4 is, for example, a silicon carbide layer formed by epitaxial growth using a CVD method (Chemical Vapor Deposition method) on a substrate such as a silicon carbide substrate not shown in FIG. 1. However, the first silicon carbide layer 4 may be, for example, a silicon carbide substrate. The first silicon carbide layer 4 is, for example, a cathode layer of a PIN diode.

[0024] The n-type fifth silicon carbide layer 12 is provided on the first silicon carbide layer 4. The fifth silicon carbide layer 12 is doped with an n-type impurity of, for example, 1×10 17 atoms / cm 3 More than 1×10 19 atoms / cm 3 Alternatively, the n-type impurity concentration of the fifth silicon carbide layer 12 is half or less of the n-type impurity concentration of the first silicon carbide layer 4 or the n-type impurity concentration of the third silicon carbide layer 8. The film thickness of the fifth silicon carbide layer 12 is preferably, for example, not less than 0.001 μm and not more than 0.1 μm.

[0025] n + The third silicon carbide layer 8 is provided on the fifth silicon carbide layer 12. The third silicon carbide layer 8 is doped with, for example, 5×10 n-type impurities. 17 atoms / cm 3 More than 1×10 20 atoms / cm 3 The third silicon carbide layer 8 has a film thickness of, for example, 0.5 μm or more and 20 μm or less. The third silicon carbide layer 8 is a layer for promoting recombination of holes and electrons so that holes do not reach the silicon carbide substrate or the like during bipolar current conduction in the semiconductor device 200.

[0026] The fifth silicon carbide layer 12 is formed, for example, by forming a second silicon carbide layer 6 described later on the first silicon carbide layer 4, forming a third silicon carbide layer 8 on the second silicon carbide layer 6, and then diffusing n-type impurities from the first silicon carbide layer 4 and the third silicon carbide layer 8 into the second silicon carbide layer 6 by impurity diffusion using a heat treatment.

[0027] The third silicon carbide layer 8 is, for example, a silicon carbide layer formed on the second silicon carbide layer 6 described later by epitaxial growth using a CVD method.

[0028] In the case of epitaxial growth using CVD, the n-type impurity concentration of each silicon carbide layer is adjusted by the flow rate of the impurity gas (e.g., nitrogen), and the n-type impurity concentration at least near the interface of each silicon carbide layer has a concentration gradient depending on the time for changing the flow rate, but the concentration gradient also changes during impurity diffusion using the subsequent heat treatment.The concentration gradient is generally gentler after the heat treatment. In addition to n-type impurities, unintended impurities may be mixed in from parts inside the epitaxial growth equipment, such as Al (aluminum), B (boron), P (phosphorus), Fe (iron), Cr (chromium), Ni (nickel), Zn (zinc), and Ta (tantalum). The diffusion coefficient of impurities in SiC varies depending on the element, so the concentration gradient of n-type impurities caused by impurity diffusion using heat treatment differs from the concentration gradient of unintended impurities other than the n-type impurities.

[0029] 1B is merely an example, and it goes without saying that the impurity concentrations of the semiconductor substrate 100 and the semiconductor device 200 of the present embodiment are not limited to those shown in FIG.

[0030] n - A fourth silicon carbide layer 10 having an n-type impurity is provided on the third silicon carbide layer 8. The fourth silicon carbide layer 10 is doped with an n-type impurity of, for example, 1×10 15 atoms / cm 3 5×10 or more 16 atoms / cm 3The n-type impurity concentration of the fourth silicon carbide layer 10 is lower than the impurity concentration of the third silicon carbide layer 8. The film thickness of the fourth silicon carbide layer 10 is, for example, not less than 4 μm and not more than 50 μm.

[0031] The BPD density of the first silicon carbide layer 4 is 10 particles / cm 2 The BPD density of the fifth silicon carbide layer 12, the third silicon carbide layer 8, and the fourth silicon carbide layer 10 is 0.1 pieces / cm 2 The following is the result.

[0032] The p-type ninth silicon carbide layer 20 is provided on the fourth silicon carbide layer 10. The ninth silicon carbide layer 20 is doped with a p-type impurity of, for example, 1×10 17 atoms / cm 3 More than 1×10 20 atoms / cm 3 The following is included. The p-type impurity is, for example, Al (aluminum). The film thickness of the ninth silicon carbide layer 20 is, for example, not less than 0.1 μm and not more than 2.0 μm. The ninth silicon carbide layer 20 is, for example, an anode layer of a PIN diode.

[0033] The first electrode 60 is provided under the first silicon carbide layer 4. The first electrode 60 is in contact with the first silicon carbide layer 4, for example. The first electrode 60 includes, for example, a metal or a metal semiconductor compound. The first electrode 60 includes, for example, Ni (nickel). Note that the Ni included in the first electrode 60 may react with the first silicon carbide layer 4 to form a layer including NiSi or Ni2Si (nickel silicide). The first electrode 60 may have a layer including Ti (titanium), Ni (nickel), Ag (silver), or Au (gold) under the layer including NiSi or Ni2Si. The first electrode 60 is a cathode electrode.

[0034] The second electrode 62 is provided on the ninth silicon carbide layer 20. The second electrode 62 is in contact with, for example, the ninth silicon carbide layer 20. The second electrode 62 has, for example, a laminated structure of a barrier metal layer containing Ti (titanium) in contact with the ninth silicon carbide layer 20 and a metal layer containing Al (aluminum) provided on the barrier metal layer. The second electrode 62 may have, for example, a layer containing a metal silicide such as NiSi in a portion in contact with the ninth silicon carbide layer 20.

[0035] 2 and 3 are schematic cross-sectional views showing the manufacturing process of the semiconductor substrate 100 and the semiconductor device 200 of this embodiment. Fig. 4 is a flowchart of the manufacturing process of the semiconductor substrate 100 and the semiconductor device 200 of this embodiment.

[0036] First, on the first silicon carbide layer 4, a silicon carbide layer having an n-type impurity concentration of 1×10 14 atoms / cm 3 That's 1x10 17 atoms / cm 3 A second silicon carbide layer 6 is formed having a thickness of 0.001 μm or more and 0.1 μm or less (S102 in FIG. 4). The n-type impurity concentration of the second silicon carbide layer 6 is lower than the n-type impurity concentration of the first silicon carbide layer 4. For example, SiH4 is used as a raw material for Si (silicon), C3H8 or C2H2 is used as a raw material for C (carbon), N (nitrogen) is used as an n-type dopant, and H2 (hydrogen) is used as a carrier gas.

[0037] The second silicon carbide layer 6 is, for example, a layer for converting BPDs of SiC into TEDs (Threading Edge dislocations).

[0038] Next, on the second silicon carbide layer 6, an n-type impurity is introduced at a concentration of 5×10 by epitaxial growth using a CVD (Chemical Vapor Deposition) method. 17 atoms / cm 3 More than 1×1020 atoms / cm 3 Then, a third silicon carbide layer 8 having a thickness of 0.5 μm or more and 20 μm or less is formed (S104 in FIG. 4).

[0039] Next, on the third silicon carbide layer 8, a silicon carbide layer having a first conductivity type impurity concentration of, for example, 1×10 15 cm -3 atoms / cm 3 5×10 or more 16 cm -3 atoms / cm 3 A fourth silicon carbide layer 10 having a thickness of 4 μm or more and 50 μm or less is formed (FIGS. 2 and S106 in FIG. 4).

[0040] Next, a silicon carbide layer having an n-type impurity concentration of 1×10 17 atoms / cm 3 More than 1×10 19 atoms / cm 3 The fifth silicon carbide layer 12 is formed so that the n-type impurity concentration is less than 100%. The fifth silicon carbide layer 12 is formed by, for example, a heat treatment to diffuse impurities from the first silicon carbide layer 4 and the third silicon carbide layer 8 to the second silicon carbide layer 6. Specifically, the first silicon carbide layer 4, the second silicon carbide layer 6, the third silicon carbide layer 8 and the fourth silicon carbide layer 10 are heated for, for example, 30 minutes or more at a temperature range of 1100°C to 1700°C. As a result, the n-type impurity is diffused from the first silicon carbide layer 4 and the third silicon carbide layer 8, which have a relatively high n-type impurity concentration, to the second silicon carbide layer 6, which has a relatively low n-type impurity concentration, thereby increasing the n-type impurity concentration of the second silicon carbide layer 6. Therefore, the fifth silicon carbide layer 12 can be formed between the first silicon carbide layer 4 and the third silicon carbide layer 8. As a result, the semiconductor substrate 100 of this embodiment is obtained. (S108 in Figures 3 and 4).

[0041] The distance that the n-type impurity diffuses varies depending on the heat treatment conditions. For example, when the n-type impurity is N (nitrogen), it diffuses about 50 nm by heat treatment at 1300°C for 1 hour. The distance that the n-type impurity diffuses can be further increased by adjusting the heat treatment temperature and time. For example, the n-type impurity concentration of the fifth silicon carbide layer 12 can be set to about 1 / 10 to 1 / 2 of that of the first silicon carbide layer 4 and the third silicon carbide layer 8.

[0042] Next, on the fourth silicon carbide layer 10, for example, a p-type impurity is doped at 1×10 17 atoms / cm 3 More than 1×10 20 atoms / cm 3 A ninth p-type silicon carbide layer 20 having a thickness of 0.1 μm to 2.0 μm is formed. As the p-type dopant, for example, (CH3)3Al is used.

[0043] Next, a first electrode 60 is formed under the first silicon carbide layer 4. Furthermore, a second electrode 62 is formed on the ninth silicon carbide layer 20. In this manner, the semiconductor device 200 of the present embodiment is obtained.

[0044] The impurity diffusion step using heat treatment and the epitaxial growth step may be performed in the same apparatus, or the impurity diffusion step using heat treatment and the epitaxial growth step may be performed in separate apparatuses.

[0045] Next, the effects of the semiconductor substrate and semiconductor device of this embodiment will be described.

[0046] When a semiconductor substrate is manufactured by forming a silicon carbide layer on a silicon carbide layer including a silicon carbide substrate, dislocations and stacking faults occur in the formed silicon carbide layer due to dislocations in the silicon carbide substrate, damage to the silicon carbide substrate during a substrate processing step, etc. When a semiconductor device is manufactured using such a semiconductor substrate, this causes a decrease in the yield of the semiconductor device, which is problematic.

[0047] Among the dislocations in the silicon carbide substrate, BPDs expand into stacking faults during bipolar current flow, causing fluctuations in device characteristics. One method to suppress this is to provide a silicon carbide layer with a high impurity concentration between the silicon carbide substrate and the drift layer so that holes do not reach the silicon carbide substrate during bipolar current flow. However, there is a problem in that BPDs are easily inherited from the silicon carbide substrate to the silicon carbide layer with a high impurity concentration, and holes reach the inherited BPDs, causing the BPDs to expand into stacking faults.

[0048] In order to reduce BPDs, it is possible to convert BPDs to TEDs by providing a silicon carbide layer with a low impurity concentration between the silicon carbide substrate and the drift layer. This is because TEDs have a smaller effect on device characteristics than BPDs. However, there is a problem that the resistance of the device increases when a silicon carbide layer with a low impurity concentration is provided.

[0049] Therefore, in the method for manufacturing a semiconductor substrate according to the present embodiment, a silicon carbide layer having a first conductivity type impurity concentration lower than that of the first silicon carbide layer and having a first conductivity type impurity concentration of 1×10 14 atoms / cm 3 That's 1x10 17 atoms / cm 3 forming a second silicon carbide layer having a thickness of 0.001 μm or more and 0.1 μm or less by epitaxial growth; and depositing a first conductive type impurity having a concentration of 5×10 on the second silicon carbide layer. 17 atoms / cm 3 That's 1x10 20 atoms / cm 3forming a third silicon carbide layer having a thickness of 0.5 μm or more and 20 μm or less by epitaxial growth; forming a fourth silicon carbide layer having a first conductivity type impurity concentration lower than that of the third silicon carbide layer by epitaxial growth on the third silicon carbide layer; and performing heat treatment of the first silicon carbide layer, the second silicon carbide layer, the third silicon carbide layer and the fourth silicon carbide layer.

[0050] By providing the second silicon carbide layer 6, the BPDs in the first silicon carbide layer 4 are converted to TEDs in the layer above the first silicon carbide layer 4 with high efficiency.

[0051] Furthermore, by providing the third silicon carbide layer 8, recombination of holes and electrons is promoted, and it is possible to prevent the holes from reaching the first silicon carbide layer 4. As a result, it is possible to suppress the expansion of BPDs into stacking faults.

[0052] Furthermore, impurity diffusion from the first silicon carbide layer 4 and the third silicon carbide layer 8 to the second silicon carbide layer 6 forms a fifth silicon carbide layer 12 having a higher n-type impurity concentration than the second silicon carbide layer 6. The second silicon carbide layer 6 has a thin film thickness of 0.1 μm or less. Therefore, impurity diffusion from the first silicon carbide layer 4 and the third silicon carbide layer 8 to the second silicon carbide layer 6 is sufficiently performed, so that an increase in the resistance of the semiconductor substrate 100 can be suppressed. Furthermore, if the film thickness of the second silicon carbide layer 6 is 0.001 μm or more, the BPD of the first silicon carbide layer 4 can be converted to TED.

[0053] For example, the BPD density of the first silicon carbide layer 4 is 10 particles / cm 2 or more, the BPD densities of the fifth silicon carbide layer 12, the third silicon carbide layer 8, and the fourth silicon carbide layer 10 are set to 0.1 particles / cm 2 It is possible to have the following:

[0054] The second silicon carbide layer 6 and the third silicon carbide layer 8 are preferably formed by epitaxial growth, because impurities introduced by ion implantation are difficult to diffuse using a heat treatment.

[0055] According to the present embodiment, it is possible to provide a semiconductor substrate, a semiconductor device, and a manufacturing method thereof that have few defects and a low on-resistance.

[0056] Second embodiment In the method for manufacturing a semiconductor substrate according to the present embodiment, after the step of forming the second silicon carbide layer and before the step of forming the third silicon carbide layer, a first conductive type impurity having a concentration of 5×10 is formed on the second silicon carbide layer. 17 atoms / cm 3 That's 1x10 20 atoms / cm 3 forming a sixth silicon carbide layer having a thickness of 0.5 μm or more and 20 μm or less by epitaxial growth; and depositing a first conductive type impurity having a concentration of 1×10 on the sixth silicon carbide layer. 14 atoms / cm 3 That's 1x10 17 atoms / cm 3 The method for manufacturing a semiconductor substrate according to the first embodiment differs from the method for manufacturing a semiconductor substrate in that it further includes a step of forming a seventh silicon carbide layer having a thickness of 0.001 μm or more and 0.1 μm or less by epitaxial growth.

[0057] Here, the description of the contents that overlap with the first embodiment will be omitted.

[0058] FIG. 5 is a schematic cross-sectional view of a semiconductor substrate 110 and a semiconductor device 210 of this embodiment.

[0059] The sixth silicon carbide layer 14 is provided between the fifth silicon carbide layer 12 and the third silicon carbide layer 8. The sixth silicon carbide layer 14 is doped with an n-type impurity at a concentration of, for example, 5×10 17 atoms / cm 3 That's 1x10 20 atoms / cm 3 The sixth silicon carbide layer 14 has a film thickness of 0.5 μm or more and 20 μm or less. The sixth silicon carbide layer 14 is a layer for promoting recombination of holes and electrons so that holes do not reach a silicon carbide substrate or the like during bipolar current conduction in the semiconductor device 200, for example.

[0060] The eighth silicon carbide layer 18 is provided between the sixth silicon carbide layer 14 and the third silicon carbide layer 8. The eighth silicon carbide layer 18 is doped with an n-type impurity at a concentration of, for example, 1×10 17 atoms / cm 3 That's 1x10 19 atoms / cm 3 or less. Alternatively, the n-type impurity concentration of the eighth silicon carbide layer 18 is half or less of the n-type impurity concentration of the sixth silicon carbide layer 14 or the n-type impurity concentration of the third silicon carbide layer 8. Note that the n-type impurity concentration of the fifth silicon carbide layer 12 in this embodiment may be half or less of the n-type impurity concentration of the first silicon carbide layer 4 or the n-type impurity concentration of the sixth silicon carbide layer 14. The film thickness of the eighth silicon carbide layer 18 is 0.001 μm or more and 0.1 μm.

[0061] Fig. 6 is a schematic cross-sectional view showing the manufacturing process of the semiconductor substrate 110 and the semiconductor device 210 of this embodiment. Fig. 7 is a schematic cross-sectional view showing the manufacturing process of the semiconductor substrate 110 and the semiconductor device 210 of this embodiment.

[0062] In the manufacturing method of the semiconductor substrate 110 of this embodiment, the second silicon carbide layer 6 is formed on the first silicon carbide layer 4 (S202 in FIG. 7), the sixth silicon carbide layer 14 is formed on the second silicon carbide layer 6 (S204 in FIG. 7), the seventh silicon carbide layer 16 is formed on the sixth silicon carbide layer 14 (S206 in FIG. 7), the third silicon carbide layer 8 is formed on the seventh silicon carbide layer 16 (S208 in FIG. 7), and the fourth silicon carbide layer 10 is formed on the third silicon carbide layer 8 (S210 in FIG. 7). Next, the fifth silicon carbide layer 12 is formed between the first silicon carbide layer 4 and the sixth silicon carbide layer 14, and the eighth silicon carbide layer 18 is formed between the sixth silicon carbide layer 14 and the third silicon carbide layer 8 by impurity diffusion using a heat treatment (S212 in FIG. 7).

[0063] In the present embodiment, by using the second silicon carbide layer 6 and the seventh silicon carbide layer 16, it can be considered as using a plurality of second silicon carbide layers 6. Therefore, it is possible to improve the conversion efficiency from BPD to TED.

[0064] In particular, consider the case where the first silicon carbide layer 4 is a silicon carbide substrate. In this case, the variation in the substrate plane of the n-type impurity in the silicon carbide substrate is very large. Therefore, when the n-type impurity is diffused from the first silicon carbide layer 4, which is a silicon carbide substrate, to the second silicon carbide layer 6, the variation in the XY plane of the resistance of the fifth silicon carbide layer 12 becomes large. Also, the variation in the XY plane of the BPD conversion efficiency becomes large. In this embodiment, it is considered that the variation in the plane of the n-type impurity diffusion from the sixth silicon carbide layer 14 to the second silicon carbide layer 6 is smaller than that of the n-type impurity diffusion from the first silicon carbide layer 4, which is a silicon carbide substrate, to the second silicon carbide layer 6. Also, it is considered that the n-type impurity diffusion from the sixth silicon carbide layer 14 to the seventh silicon carbide layer 16 and the n-type impurity diffusion from the third silicon carbide layer 8 to the seventh silicon carbide layer 16 have smaller in-plane variations than the n-type impurity diffusion from the first silicon carbide layer 4, which is a silicon carbide substrate, to the second silicon carbide layer 6. This makes it possible to reduce the XY in-plane variations of the resistance component and the XY in-plane variations of the BPD conversion efficiency.

[0065] Furthermore, for example, by reducing the film thicknesses of the second silicon carbide layer 6 and the seventh silicon carbide layer 16, the n-type impurity concentrations of the fifth silicon carbide layer 12 and the eighth silicon carbide layer 18 can be made sufficiently high even if the heat treatment temperature for impurity diffusion is lowered or the heat treatment time is shortened. Therefore, the semiconductor substrate 110 and the semiconductor device 210 can be manufactured more easily.

[0066] Furthermore, if the n-type impurity concentration of the second silicon carbide layer 6 is too low, the difference in n-type impurity concentration between the first silicon carbide layer 4 or the third silicon carbide layer 8 and the second silicon carbide layer 6 is too large, and stress is generated due to the difference in lattice constant with the first silicon carbide layer 4 or the third silicon carbide layer 8, which may cause new dislocations. Therefore, for example, the n-type impurity concentration of the second silicon carbide layer 6 is set to, for example, 1×10 16 atoms / cm 3 That's 1x10 18 atoms / cm 3 In addition to the second silicon carbide layer 6, for example, an n-type impurity density of 1×10 16 atoms / cm 3 That's 1x1018 atoms / cm 3 It is considered to use the seventh silicon carbide layer 16 having the following structure. This allows for a difference in lattice constant, so that the BPD conversion efficiency can be improved while suppressing the generation of new dislocations.

[0067] This embodiment also makes it possible to provide a semiconductor substrate with fewer defects and low on-resistance, a semiconductor device, and a method for manufacturing the same.

[0068] Third embodiment The semiconductor substrate of the present embodiment differs from the semiconductor substrates of the first and second embodiments in that it further includes a silicon carbide substrate 2 and a first silicon carbide layer 4 is provided on the silicon carbide substrate 2.

[0069] The semiconductor device of the present embodiment differs from the semiconductor substrates of the first and second embodiments in that a silicon carbide substrate 2 is provided between a first electrode 60 and a first silicon carbide layer 4.

[0070] The method for manufacturing a semiconductor substrate according to the present embodiment differs from the methods for manufacturing a semiconductor substrate according to the first and second embodiments in that it further includes a step of forming a first silicon carbide layer 4 by epitaxial growth on a silicon carbide substrate 2 before the step of forming a second silicon carbide layer 6. The method for manufacturing a semiconductor substrate according to the present embodiment corresponds to the case in the first embodiment where the first silicon carbide layer 4 is formed on a silicon carbide substrate 2 by epitaxial growth.

[0071] Here, descriptions of contents that overlap with the first and second embodiments will be omitted.

[0072] Fig. 8 is a schematic cross-sectional view of the semiconductor substrate 120 and the semiconductor device 220 of this embodiment. Fig. 9 is a flowchart of the manufacturing process of the semiconductor substrate 120 and the semiconductor device 220 of this embodiment. Comparing the flowchart shown in Fig. 9 with the flowchart shown in Fig. 4, Fig. 9 differs in that it includes a step of "forming a first silicon carbide layer on a silicon carbide substrate" (302 in Fig. 9). In addition, S304, S306, S308, and S310 in Fig. 9 are the same steps as S102, S104, S106, and S108 in Fig. 4, respectively.

[0073] The variation in the n-type impurity in the silicon carbide substrate 2 is very large. Therefore, when the n-type impurity is directly diffused from the silicon carbide substrate 2 into the second silicon carbide layer 6, the variation in the resistance of the fifth silicon carbide layer 12 in the substrate plane becomes large. Also, the variation in the BPD conversion efficiency in the substrate plane becomes large. In this embodiment, by providing the first silicon carbide layer 4 between the silicon carbide substrate 2 and the second silicon carbide layer 6, it is possible to reduce these variations.

[0074] This embodiment also makes it possible to provide a semiconductor substrate with fewer defects and low on-resistance, a semiconductor device, and a method for manufacturing the same.

[0075] (Fourth embodiment) The semiconductor device of this embodiment includes a ninth silicon carbide layer of a second conductivity type provided on a fourth silicon carbide layer of a semiconductor substrate, a tenth silicon carbide layer of a first conductivity type provided on the ninth silicon carbide layer, a third electrode provided on the ninth silicon carbide layer via a first insulating film in a trench extending from the tenth silicon carbide layer to the fourth silicon carbide layer, a second insulating film provided on the third electrode, and a second electrode provided on the tenth silicon carbide layer and the second insulating film.

[0076] The manufacturing method of the semiconductor device of the present embodiment includes the steps of forming a ninth silicon carbide layer of a second conductivity type on a fourth silicon carbide layer of a semiconductor substrate, forming a tenth silicon carbide layer of a first conductivity type on the ninth silicon carbide layer, forming a trench from the tenth silicon carbide layer to the fourth silicon carbide layer, forming a first insulating film in the trench, forming a third electrode in the trench, the third electrode being provided on the ninth silicon carbide layer via the first insulating film, forming a second insulating film on the third electrode, and forming a second electrode on the tenth silicon carbide layer and the second insulating film.

[0077] Here, the description of the contents overlapping with the first to third embodiments will be omitted.

[0078] FIG. 10 is a schematic cross-sectional view of the semiconductor device of the present embodiment.

[0079] The semiconductor device of this embodiment is a trench type MOSFET.

[0080] The p-type ninth silicon carbide layer 20 is provided on the fourth silicon carbide layer 10. The ninth silicon carbide layer 20 functions as a base of the MOSFET. In FIG. 7, the ninth silicon carbide layer 20a, the ninth silicon carbide layer 20b, and the ninth silicon carbide layer 20c are illustrated.

[0081] The n-type tenth silicon carbide layer 40 is provided on the ninth silicon carbide layer 20. The tenth silicon carbide layer 40 functions as a source of the MOSFET. In FIG. 7, the tenth silicon carbide layer 40a, the tenth silicon carbide layer 40b, the tenth silicon carbide layer 40c, and the tenth silicon carbide layer 40d are illustrated.

[0082] The trench 70 reaches the fourth silicon carbide layer 10 from the tenth silicon carbide layer 40. In Fig. 7, a trench 70a and a trench 70b are illustrated.

[0083] The first insulating film 72 is provided in the trench 70. The first insulating film 72 is a gate insulating film of the MOSFET. The first insulating film 72 includes an insulating material such as silicon oxide. In FIG. 7, a first insulating film 72a and a first insulating film 72b are illustrated.

[0084] The third electrode 74 is provided in the trench 70, facing the ninth silicon carbide layer 20 via the first insulating film 72. The third electrode 74 is a gate electrode of the MOSFET. The third electrode 74 includes a conductive material such as conductive polysilicon containing impurities. In FIG. 7, the third electrode 74a and the third electrode 74b are illustrated.

[0085] The second insulating film 76 is provided on the third electrode 74. The second insulating film 76 includes an insulating material such as silicon oxide. In FIG 7, the second insulating film 76a and the second insulating film 76b are illustrated.

[0086] p + The eleventh silicon carbide layer 42 is provided on the ninth silicon carbide layer 20. The p-type impurity concentration of the eleventh silicon carbide layer 42 is higher than that of the ninth silicon carbide layer 20. The eleventh silicon carbide layer 42 is a contact region of the MOSFET. In FIG. 7, the eleventh silicon carbide layer 42a, the eleventh silicon carbide layer 42b, and the eleventh silicon carbide layer 42c are illustrated.

[0087] The second electrode 62 is provided on the tenth silicon carbide layer 40 and the second insulating film 76. The second electrode 62 is a source electrode of the MOSFET.

[0088] The first electrode 60 is a drain electrode of the MOSFET.

[0089] Since a semiconductor substrate with few defects and low on-resistance is used, this embodiment also makes it possible to provide a semiconductor device with few defects and low on-resistance and a method for manufacturing the same.

[0090] Fifth embodiment The semiconductor device of this embodiment includes a ninth silicon carbide layer of a second conductivity type provided on a fourth silicon carbide layer of a semiconductor substrate, a tenth silicon carbide layer of a first conductivity type provided on the ninth silicon carbide layer, a third electrode provided on the ninth silicon carbide layer, a first insulating film provided between the ninth silicon carbide layer and the third electrode, a second electrode provided on the tenth silicon carbide layer and the third electrode, and a second insulating film provided between the second electrode and the third electrode.

[0091] The method for manufacturing a semiconductor device of the present embodiment further includes the steps of forming a ninth silicon carbide layer of a second conductivity type on the fourth silicon carbide layer of the semiconductor substrate of the first to third embodiments, forming a tenth silicon carbide layer of a first conductivity type on the ninth silicon carbide layer, forming a first insulating film on the ninth silicon carbide layer, forming a third electrode on the first insulating film, forming a second insulating film on the third electrode, and forming a second electrode on the third electrode, the second insulating film, and the tenth silicon carbide layer.

[0092] Here, the description of the contents overlapping with the first to third embodiments will be omitted.

[0093] FIG. 11 is a schematic cross-sectional view of a semiconductor device 400 of the present embodiment.

[0094] The semiconductor device of this embodiment is a planar type MOSFET.

[0095] The p-type ninth silicon carbide layer 20 is provided on the fourth silicon carbide layer 10. The ninth silicon carbide layer 20 functions as a base of the MOSFET. In Fig. 8, the ninth silicon carbide layer 20a and the ninth silicon carbide layer 20b are illustrated. The ninth silicon carbide layer 20a and the ninth silicon carbide layer 20b are provided, for example, spaced apart from each other.

[0096] The n-type tenth silicon carbide layer 40 is provided on the ninth silicon carbide layer 20. The tenth silicon carbide layer 40 functions as a source of the MOSFET. In Fig. 8, the tenth silicon carbide layer 40a and the tenth silicon carbide layer 40b are illustrated. The tenth silicon carbide layer 40a and the tenth silicon carbide layer 40b are provided, for example, spaced apart from each other.

[0097] The third electrode 74 is provided on the ninth silicon carbide layer 20a and on the ninth silicon carbide layer 20b. The third electrode 74 is a gate electrode of the MOSFET. The third electrode 74 includes a conductive material such as conductive polysilicon containing impurities.

[0098] The first insulating film 72 is provided between the ninth silicon carbide layer 20 and the third electrode 74. The first insulating film 72 is a gate insulating film of the MOSFET. The first insulating film 72 includes an insulator such as silicon oxide.

[0099] The second electrode 62 is provided on the tenth silicon carbide layer 40 and the third electrode 74. The second electrode 62 is a source electrode of the MOSFET.

[0100] The second insulating film 76 is provided between the second electrode 62 and the third electrode 74. The second insulating film 76 includes an insulator such as silicon oxide.

[0101] The first electrode 60 is a drain electrode of the MOSFET.

[0102] Since a semiconductor substrate with few defects and low on-resistance is used, this embodiment also makes it possible to provide a semiconductor device with few defects and low on-resistance and a method for manufacturing the same.

[0103] Although some embodiments and examples of the present invention have been described, these embodiments and examples are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims.

[0104] The above-described embodiment can be summarized as the following technical proposal. (Technical proposal 1) a first conductive type impurity layer having a first conductivity type impurity concentration lower than that of the first silicon carbide layer and having a first conductive type impurity concentration of 1×10 14 atoms / cm 3 That's 1x10 17 atoms / cm 3 forming a second silicon carbide layer having a thickness of 0.001 μm or more and 0.1 μm or less by epitaxial growth; A first conductive type impurity having a concentration of 5×10 17 atoms / cm 3 That's 1x10 20 atoms / cm 3 forming a third silicon carbide layer having a thickness of 0.5 μm or more and 20 μm or less by epitaxial growth; forming a fourth silicon carbide layer having a first conductivity type impurity concentration lower than that of the third silicon carbide layer by an epitaxial growth method on the third silicon carbide layer; performing a heat treatment on the first silicon carbide layer, the second silicon carbide layer, the third silicon carbide layer, and the fourth silicon carbide layer; A method for manufacturing a semiconductor substrate comprising the steps of: (Technical proposal 2) In the step of performing the heat treatment on the first silicon carbide layer, the second silicon carbide layer, the third silicon carbide layer, and the fourth silicon carbide layer, A first conductive type impurity concentration of 1×10 17 atoms / cm3 That's 1x10 18 atoms / cm 3 forming a fifth silicon carbide layer, A method for manufacturing a semiconductor substrate according to Technical Proposal 1. (Technical proposal 3) After the step of forming the second silicon carbide layer and before the step of forming the third silicon carbide layer, A first conductive type impurity having a concentration of 5×10 17 atoms / cm 3 That's 1x10 20 atoms / cm 3 forming a sixth silicon carbide layer having a thickness of 0.5 μm or more and 20 μm or less by epitaxial growth; a first conductive type impurity having a concentration of 1×10 14 atoms / cm 3 That's 1x10 17 atoms / cm 3 forming a seventh silicon carbide layer having a thickness of 0.001 μm or more and 0.1 μm or less by epitaxial growth; Further comprising: A method for manufacturing a semiconductor substrate according to Technical Scheme 1 or 2. (Technical proposal 4) Before the step of forming the second silicon carbide layer, forming the first silicon carbide layer on a silicon carbide substrate by epitaxial growth; The method for manufacturing a semiconductor substrate according to any one of Technical Schemes 1 to 3, further comprising: (Technical proposal 5) The first silicon carbide layer has a first conductivity type impurity concentration of 5×10 17 atoms / cm 3 That's 1x10 19 atoms / cm 3 Below is the A method for manufacturing a semiconductor substrate according to any one of technical proposals 1 to 4. (Technical proposal 6) forming a ninth silicon carbide layer of a second conductivity type on the fourth silicon carbide layer of the semiconductor substrate according to any one of technical solutions 1 to 5; forming a first electrode under the first silicon carbide layer; forming a second electrode on the ninth silicon carbide layer; The method for manufacturing a semiconductor device further comprises: (Technical proposal 7) forming a ninth silicon carbide layer of a second conductivity type on the fourth silicon carbide layer of the semiconductor substrate according to any one of technical solutions 1 to 5; forming a tenth silicon carbide layer of a first conductivity type on the ninth silicon carbide layer; forming a first electrode under the first silicon carbide layer; forming a trench extending from the tenth silicon carbide layer to the fourth silicon carbide layer; forming a first insulating film in the trench; forming a third electrode in the trench, the third electrode being provided on the ninth silicon carbide layer with the first insulating film interposed therebetween; forming a second electrode on the tenth silicon carbide layer; The method for manufacturing a semiconductor device further comprises: (Technical proposal 8) forming a ninth silicon carbide layer of a second conductivity type on the fourth silicon carbide layer of the semiconductor substrate according to any one of technical solutions 1 to 5; forming a tenth silicon carbide layer of a first conductivity type on the ninth silicon carbide layer; forming a first insulating film on the ninth silicon carbide layer; forming a third electrode on the first insulating film; forming a second insulating film on the third electrode; forming a second electrode on the third electrode, the second insulating film, and the tenth silicon carbide layer; The method for manufacturing a semiconductor device further comprises: (Technical proposal 9) a first silicon carbide layer; a first conductive type impurity concentration of 1×1017 cm -3 atoms / cm 3 That's 1x10 19 cm -3 atoms / cm 3 a fifth silicon carbide layer having a thickness of less than 100 nm; a first conductive type impurity concentration of 5×10 17 cm -3 atoms / cm 3 That's 1x10 20 cm -3 atoms / cm 3 a third silicon carbide layer having a thickness of 0.5 μm or more and 20 μm or less; a fourth silicon carbide layer provided on the third silicon carbide layer, the fourth silicon carbide layer having a first conductivity type impurity concentration lower than that of the third silicon carbide layer; Equipped with a concentration gradient of a first conductivity type impurity in a region including the first silicon carbide layer and the fifth silicon carbide layer in a direction from the first silicon carbide layer to the fifth silicon carbide layer is different from a concentration gradient of an impurity different from the first conductivity type impurity; Semiconductor substrate. (Technical proposal 10) a first silicon carbide layer; a first conductive type impurity concentration of 1×10 17 cm -3 atoms / cm 3 That's 1x10 19 cm -3 atoms / cm 3 a fifth silicon carbide layer having a thickness of less than 100 nm; a first conductive type impurity concentration of 5×10 17 cm -3 atoms / cm 3 That's 1x10 20 cm -3 atoms / cm 3 a third silicon carbide layer having a thickness of 0.5 μm or more and 20 μm or less; a fourth silicon carbide layer provided on the third silicon carbide layer, the fourth silicon carbide layer having a first conductivity type impurity concentration lower than that of the third silicon carbide layer; Equipped with The first silicon carbide layer has a BPD density of 10 particles / cm 2 That is all, The third silicon carbide layer and the fourth silicon carbide layer have a BPD density of 0.1 pieces / cm 2 Below is the Semiconductor substrate. [Explanation of symbols]

[0105] 2: Silicon carbide substrate 4: First silicon carbide layer 6: Second silicon carbide layer 8: Third silicon carbide layer 10: Fourth silicon carbide layer 12: Fifth silicon carbide layer 14: Sixth silicon carbide layer 16: Seventh silicon carbide layer 18: Eighth silicon carbide layer 20: 9th silicon carbide layer 20a: ninth silicon carbide layer 20b: 9th silicon carbide layer 20c: 9th silicon carbide layer 40: 10th silicon carbide layer 42: 11th silicon carbide layer 60: 1st electrode 62: 2nd electrode 70: Trench 72: First insulating film 74:Third electrode 76: Second insulating film 100: Semiconductor substrate 110: Semiconductor substrate 120: Semiconductor substrate 200: Semiconductor device 210: Semiconductor device 220: Semiconductor devices 400: Semiconductor device

Claims

1. a first conductive type impurity layer having a first conductivity type impurity concentration lower than that of the first silicon carbide layer and having a first conductive type impurity concentration of 1×10 １４ atoms / cm ３ That's 1 x 10 １７ atoms / cm ３ forming a second silicon carbide layer having a thickness of 0.001 μm or more and 0.1 μm or less by an epitaxial growth method; A first conductivity type impurity having a concentration of 5×10 １７ atoms / cm ３ That's 1 x 10 ２０ atoms / cm ３ forming a third silicon carbide layer having a thickness of 0.5 μm or more and 20 μm or less by epitaxial growth; forming a fourth silicon carbide layer having a first conductivity type impurity concentration lower than that of the third silicon carbide layer by an epitaxial growth method on the third silicon carbide layer; performing a heat treatment on the first silicon carbide layer, the second silicon carbide layer, the third silicon carbide layer, and the fourth silicon carbide layer; A method for manufacturing a semiconductor substrate comprising the steps of:

2. In the step of performing the heat treatment on the first silicon carbide layer, the second silicon carbide layer, the third silicon carbide layer, and the fourth silicon carbide layer, A first conductive type impurity concentration of 1×10 １７ atoms / cm ３ That's 1 x 10 １８ atoms / cm ３ forming a fifth silicon carbide layer, The method for manufacturing a semiconductor substrate according to claim 1.

3. After the step of forming the second silicon carbide layer and before the step of forming the third silicon carbide layer, A first conductivity type impurity having a concentration of 5×10 １７ atoms / cm ３ That's 1 x 10 ２０ atoms / cm ３ forming a sixth silicon carbide layer having a thickness of 0.5 μm or more and 20 μm or less by an epitaxial growth method; a first conductivity type impurity having a concentration of 1×10 １４ atoms / cm ３ That's 1 x 10 １７ atoms / cm ３ forming a seventh silicon carbide layer having a thickness of 0.001 μm or more and 0.1 μm or less by an epitaxial growth method; Further comprising: The method for manufacturing a semiconductor substrate according to claim 1.

4. Prior to the step of forming the second silicon carbide layer, forming the first silicon carbide layer on a silicon carbide substrate by epitaxial growth; The method for manufacturing a semiconductor substrate according to claim 1 , further comprising:

5. The first silicon carbide layer has a first conductivity type impurity concentration of 5×10 １７ atoms / cm ３ That's 1 x 10 １９ atoms / cm ３ Below is the The method for manufacturing a semiconductor substrate according to claim 1.

6. forming a ninth silicon carbide layer of a second conductivity type on the fourth silicon carbide layer of the semiconductor substrate according to claim 1; forming a first electrode under the first silicon carbide layer; forming a second electrode on the ninth silicon carbide layer; The method for manufacturing a semiconductor device further comprises:

7. forming a ninth silicon carbide layer of a second conductivity type on the fourth silicon carbide layer of the semiconductor substrate according to claim 1; forming a tenth silicon carbide layer of a first conductivity type on the ninth silicon carbide layer; forming a first electrode under the first silicon carbide layer; forming a trench extending from the tenth silicon carbide layer to the fourth silicon carbide layer; forming a first insulating film in the trench; forming a third electrode in the trench, the third electrode being provided on the ninth silicon carbide layer with the first insulating film interposed therebetween; forming a second electrode on the tenth silicon carbide layer; The method for manufacturing a semiconductor device further comprises:

8. forming a ninth silicon carbide layer of a second conductivity type on the fourth silicon carbide layer of the semiconductor substrate according to claim 1; forming a tenth silicon carbide layer of a first conductivity type on the ninth silicon carbide layer; forming a first insulating film on the ninth silicon carbide layer; forming a third electrode on the first insulating film; forming a second insulating film on the third electrode; forming a second electrode on the third electrode, the second insulating film, and the tenth silicon carbide layer; The method for manufacturing a semiconductor device further comprises:

9. a first silicon carbide layer; a first conductivity type impurity layer having a concentration of 1×10 １７ cm －３ atoms / cm ３ That's 1 x 10 １９ cm －３ atoms / cm ３ a fifth silicon carbide layer having a thickness of less than a first conductive type impurity layer having a concentration of 5×10 １７ cm －３ atoms / cm ３ That's 1 x 10 ２０ cm －３ atoms / cm ３ a third silicon carbide layer having a thickness of 0.5 μm or more and 20 μm or less; a fourth silicon carbide layer provided on the third silicon carbide layer, the fourth silicon carbide layer having a first conductivity type impurity concentration lower than that of the third silicon carbide layer; Equipped with a concentration gradient of a first conductivity type impurity in a direction from the first silicon carbide layer to the fifth silicon carbide layer in a region including the first silicon carbide layer and the fifth silicon carbide layer is different from a concentration gradient of an impurity different from the first conductivity type impurity; Semiconductor substrate.

10. a first silicon carbide layer; a first conductivity type impurity layer having a concentration of 1×10 １７ cm －３ atoms / cm ３ That's 1 x 10 １９ cm －３ atoms / cm ３ a fifth silicon carbide layer having a thickness of less than a first conductive type impurity layer having a concentration of 5×10 １７ cm －３ atoms / cm ３ That's 1 x 10 ２０ cm －３ atoms / cm ３ a third silicon carbide layer having a thickness of 0.5 μm or more and 20 μm or less; a fourth silicon carbide layer provided on the third silicon carbide layer, the fourth silicon carbide layer having a first conductivity type impurity concentration lower than that of the third silicon carbide layer; Equipped with The first silicon carbide layer has a BPD density of 10 / cm ２ That is all, The third silicon carbide layer and the fourth silicon carbide layer have a BPD density of 0.1 cm3. ２ Below is the Semiconductor substrate.

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