Image sensor

Abstract

To provide an image sensor.SOLUTION: An image sensor includes: a first stack including a first semiconductor substrate having a first surface and a second surface opposite to the first surface, a photoelectric conversion region disposed in the first semiconductor substrate, a floating diffusion region disposed in the first semiconductor substrate and storing charges transmitted from the photoelectric conversion region, a transmission gate disposed on the first surface of the first semiconductor substrate, and a first etching stopper film disposed on an upper surface and a side wall of the transmission gate and on the first surface of the first semiconductor substrate; a second stack including a second semiconductor substrate having a first surface and a second surface opposite to the first surface, a pixel gate disposed on the first surface or the second surface of the second semiconductor substrate and electrically connected to the floating diffusion region, and a gate spacer disposed on a side wall of the pixel gate; and a third stack attached to the second stack and including a logic transistor providing signals to the pixel gate and the transmission gate.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to image sensors, and more particularly to image sensors including photodiodes. [Background technology]

[0002] An image sensor is a device that converts an optical image signal into an electrical signal. An image sensor includes a number of pixels, each of which receives incident light and converts it into an electrical signal, and includes a photodiode region. As the integration density of an image sensor increases, the size of each pixel becomes smaller, and the electrical connection components of a pixel circuit for driving each pixel also become smaller, which can cause noise or reduce photoelectric conversion efficiency, such as conversion gain. Summary of the Invention [Problem to be solved by the invention]

[0003] SUMMARY OF THE PRESENT EMBODIMENT An object of the present invention is to provide an image sensor having excellent image quality even with a small pixel size. [Means for solving the problem]

[0004] According to the technical idea of ​​the present invention, there is provided an image sensor including: a first stack including a first semiconductor substrate having a first surface and a second surface opposite to the first surface; a photoelectric conversion region disposed in the first semiconductor substrate; a floating diffusion region disposed in the first semiconductor substrate and storing charges transferred from the photoelectric conversion region; a transfer gate disposed on the first surface of the first semiconductor substrate; and a first etch stop layer disposed on an upper surface and a sidewall of the transfer gate and on the first surface of the first semiconductor substrate; a second stack attached to the first stack, the second stack including a second semiconductor substrate having a first surface and a second surface opposite to the first surface; a pixel gate disposed on the first surface or the second surface of the second semiconductor substrate and electrically connected to the floating diffusion region, and a gate spacer disposed on a sidewall of the pixel gate; and a third stack attached to the second stack, the third stack including a logic transistor providing a signal to the pixel gate and the transfer gate.

[0005] According to the technical idea of ​​the present invention, there is provided an image sensor including: a first stack including a first semiconductor substrate having a first surface and a second surface opposite to the first surface; a photoelectric conversion region disposed in the first semiconductor substrate; a floating diffusion region disposed in the first semiconductor substrate and storing charges transferred from the photoelectric conversion region; a transfer gate disposed on the first surface of the first semiconductor substrate; and a first etch stop layer disposed on an upper surface and a sidewall of the transfer gate and on the first surface of the first semiconductor substrate; a second stack attached to the first stack, the second stack including a second semiconductor substrate having a first surface and a second surface opposite to the first surface, and a pixel gate disposed on the first surface or the second surface of the second semiconductor substrate and electrically connected to the floating diffusion region; and a third stack attached to the second stack, the third stack including a logic transistor providing a signal to the pixel gate and the transfer gate; and a portion of the first etch stop layer disposed on the sidewall of the transfer gate has a sidewall extending perpendicular to the first surface of the first semiconductor substrate.

[0006] The image sensor according to the technical idea of ​​the present invention for achieving the above technical object includes a first stack; a second stack attached to the first stack; and a third stack attached to the second stack; the first stack includes a first semiconductor substrate having a first surface and a second surface opposite to the first surface, a photoelectric conversion region disposed in the first semiconductor substrate, a floating diffusion region disposed in the first semiconductor substrate and configured to store charges transferred from the photoelectric conversion region, a transfer gate disposed on the first surface of the first semiconductor substrate and having a portion disposed in a transfer trench extending into the first semiconductor substrate, a first etching stopper disposed on an upper surface and sidewalls of the transfer gate and on the first surface of the first semiconductor substrate, the second stack includes a second semiconductor substrate having a first surface and a second surface opposite to the first surface, a pixel gate disposed on the first surface or the second surface of the second semiconductor substrate and electrically connected to the floating diffusion region, a gate spacer disposed on a sidewall of the pixel gate, and a second etch stop layer disposed on the top surface of the pixel gate and on a sidewall of the gate spacer, and the third stack includes a logic transistor providing a signal to the pixel gate and the transmission gate. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic perspective view of an image sensor according to an exemplary embodiment. [Diagram 2] FIG. 2 is a layout diagram showing a first stack corresponding to one pixel of FIG. [Diagram 3] FIG. 2 is a layout diagram showing a second stack corresponding to one pixel of FIG. [Figure 4] FIG. 4 is a cross-sectional view taken along the line A1-A1' in FIG. [Diagram 5] FIG. 5 is an enlarged view of a portion CX1 in FIG. [Figure 6]FIG. 5 is an enlarged view of the CX2 portion of FIG. [Figure 7] FIG. 2 is an equivalent circuit diagram of a pixel of an image sensor according to an exemplary embodiment. [Figure 8] FIG. 2 is a layout diagram of a first stack of image sensors according to an exemplary embodiment. [Figure 9] FIG. 2 is a layout diagram illustrating an image sensor according to an example embodiment. [Figure 10] FIG. 10 is a cross-sectional view of the image sensor of FIG. [Figure 11] FIG. 2 is a layout diagram illustrating an image sensor according to an example embodiment. [Figure 12] FIG. 12 is a cross-sectional view of the image sensor of FIG. [Figure 13] FIG. 2 is a layout diagram illustrating an image sensor according to an example embodiment. [Figure 14] FIG. 2 is a layout diagram illustrating an image sensor according to an example embodiment. [Figure 15] 1 illustrates a cross-sectional view of an image sensor according to an exemplary embodiment. [Figure 16] FIG. 1 is a block diagram illustrating a configuration of an image sensor according to an exemplary embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the technical concept of the present invention will be described in detail with reference to the accompanying drawings.

[0009] FIG 1 is a perspective view that shows a schematic diagram of an image sensor 100 according to an exemplary embodiment. FIG 2 is a layout diagram showing a first stack ST1 corresponding to one pixel PX in FIG 1, and FIG 3 is a layout diagram showing a second stack ST2 corresponding to one pixel PX in FIG 1. FIG 4 is a cross-sectional view taken along line A1-A1' in FIG 3. FIG 5 is an enlarged view of a portion CX1 in FIG 4. FIG 6 is an enlarged view of a portion CX2 in FIG 4.

[0010] 1 to 6, the image sensor 100 is also a stacked type image sensor in which a first stack ST1, a second stack ST2, and a third stack ST3 are stacked in a vertical direction.

[0011] The active pixel region APR is disposed in the center of the image sensor 100, and a plurality of pixels PX may be disposed in the active pixel region APR. The plurality of pixels PX are also a region that receives light from outside the image sensor 100 and converts the light into an electrical signal. The plurality of pixels PX may be disposed in a first stack ST1 and a second stack ST2, and for example, a photoelectric conversion region PD for receiving external light may be disposed in the first stack ST1, and a transistor constituting a pixel circuit PXC for converting photocharges accumulated in the photoelectric conversion region PD into an electrical signal may be disposed in the second stack ST2.

[0012] The pad region PDR may be disposed on at least one side of the active pixel region APR, for example, on all four sides of the active pixel region APR in a plan view. A plurality of pads PAD may be disposed in the pad region PDR and configured to transmit and receive electrical signals to and from an external device, etc.

[0013] The peripheral circuit region PCR may include a logic circuit block and / or a memory element. For example, the logic circuit block may include a plurality of logic transistors LCT and may provide a constant signal to each pixel PX of the active pixel region APR or control an output signal at each pixel PX. For example, the logic transistors LCT may include at least one of a row decoder, a row driver, a column decoder, a timing generator, a correlated double sampler (CDS), an analog to digital converter, and an input / output buffer (I / O buffer).

[0014] The active pixel region APR may include a plurality of pixels PX, and a plurality of photoelectric conversion regions PD may be disposed within each of the plurality of pixels PX. In the active pixel region APR, the plurality of pixels PX may be arranged in a matrix shape with columns and rows along a first direction X parallel to the top surface of the first semiconductor substrate 110 and a second direction Y perpendicular to the first direction and parallel to the top surface of the first semiconductor substrate 110. Some of the plurality of pixels PX may also be optical black pixels (not shown). The optical black pixels function as reference pixels for the active pixel region APR and perform a function of automatically correcting a dark signal.

[0015] The first stack ST1 may include a first semiconductor substrate 110 having a first surface 110F1 and a second surface 110F2, a photoelectric conversion region PD and a floating diffusion region FD formed inside the first semiconductor substrate 110, a transmission gate TG and a first front structure FS1 arranged on the first surface 110F1 of the first semiconductor substrate 110, and a color filter CF and a microlens ML arranged on the second surface 110F2 of the first semiconductor substrate 110.

[0016] The second stack ST2 may include a second semiconductor substrate 120 having a first surface 120F1 and a second surface 120F2, a pixel transistor PXT arranged on the first surface 120F1 of the second semiconductor substrate 120, a second front surface structure FS2, and a back surface structure BS2 arranged on the second surface 120F2 of the second semiconductor substrate 120.

[0017] The third stack ST3 may include a third semiconductor substrate 130 having a first surface 130F1 and a second surface 130F2, a logic transistor LCT disposed on the first surface 130F1 of the third semiconductor substrate 130, and a third front surface structure FS3.

[0018] The second stack ST2 may be disposed between the first stack ST1 and the third stack ST3, for example, such that the second front structure FS2 of the second stack ST2 faces the third front structure FS3 of the third stack ST3, and the back structure BS2 of the second stack ST2 faces the first front structure FS1 of the first stack ST1. The first stack ST1 and the second stack ST2 may be attached to each other by a first bonding insulating layer BI1 interposed therebetween, and the second stack ST2 and the third stack ST3 may be attached to each other by a second bonding insulating layer BI2 interposed therebetween. In some embodiments, a first bonding pad BP1 surrounded by the first bonding insulating layer BI1 may be further disposed between the first stack ST1 and the second stack ST2, and a second bonding pad BP2 surrounded by the second bonding insulating layer BI2 may be further disposed between the second stack ST2 and the third stack ST3.

[0019] In an exemplary embodiment, the first to third semiconductor substrates 110, 120, and 130 may include P-type semiconductor substrates. For example, at least one of the first to third semiconductor substrates 110, 120, and 130 may be a P-type silicon substrate. In an exemplary embodiment, at least one of the first to third semiconductor substrates 110, 120, and 130 may include a P-type bulk substrate and a P-type or N-type epitaxial layer grown thereon, and in another embodiment, may include an N-type bulk substrate and a P-type or N-type epitaxial layer grown thereon. In some embodiments, the second semiconductor substrate 120 may include a portion of a silicon-on-insulator (SOI) structure, for example, a silicon layer of the SOI structure.

[0020] A pixel isolation structure 140 may be disposed in the first stack ST1 in the active pixel region APR. A plurality of pixels PX may be defined by the pixel isolation structure 140. The pixel isolation structure 140 may include a conductive layer 142, an insulating liner 144, and an upper insulating layer 146. The conductive layer 142 may be disposed inside a pixel trench 140T penetrating the first semiconductor substrate 110. The insulating liner 144 may be disposed on an inner wall of the pixel trench 140T penetrating the first semiconductor substrate 110, and may extend from the first surface 110F1 to the second surface 110F2 of the first semiconductor substrate 110, and may be interposed between the conductive layer 142 and the first semiconductor substrate 110. The upper insulating layer 146 may be disposed in a portion of the pixel trench 140T adjacent to the first surface 110F1 of the first semiconductor substrate 110.

[0021] In an exemplary embodiment, the conductive layer 142 may include at least one of doped polysilicon, a metal, a metal silicide, a metal nitride, or a metal-containing film. The insulating liner 144 may include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, etc. The top insulating layer 146 may include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, etc.

[0022] A plurality of photoelectric conversion regions PD may be disposed in the first stack ST1 in each of the pixels PX. The photoelectric conversion region PD may also be a region doped with n-type impurities. For example, the photoelectric conversion region PD has an impurity concentration difference between an upper portion and a lower portion, and has a potential gradient. Alternatively, the photoelectric conversion region PD may be formed in a form in which a plurality of impurity regions are stacked vertically.

[0023] Optionally, a liner region 148 surrounding each of the photoelectric conversion regions PD may be disposed in a portion of the first semiconductor substrate 110. The liner region 148 is disposed between the pixel isolation structure 140 and the photoelectric conversion region PD, and is also a region doped with a p-type impurity such as boron.

[0024] A floating diffusion region FD may be disposed in an internal region of the first semiconductor substrate 110 adjacent to the first surface 110F1 of the first semiconductor substrate 110. The floating diffusion region FD is also a region in which charges transferred from the photoelectric conversion region PD are stored. A ground region GND may be disposed in an internal region of the first semiconductor substrate 110 adjacent to the first surface 110F1 of the first semiconductor substrate 110. In some embodiments, at least a portion of the ground region GND is surrounded by an isolation film.

[0025] A transmission gate TG may be disposed on the first surface 110F1 of the first semiconductor substrate 110. The transmission gate TG may include a first portion TG_1 and a second portion TG_2, where the first portion TG_1 may be disposed on the first surface 110F1 of the first semiconductor substrate 110, and the second portion TG_2 may be disposed in a transmission trench TGH extending from the first surface 110F1 of the first semiconductor substrate 110 into the first semiconductor substrate 110. The second portion TG_2 may be integrally connected to the first portion TG_1, and the second portion TG_2 may overlap at least a portion of the first portion TG_1 in the vertical direction Z.

[0026] 3, the first surface 110F1 of the first semiconductor substrate 110 is illustrated as facing downward toward the second stack ST2, and the second surface 110F2 of the first semiconductor substrate 110 is illustrated as facing upward, so that the first portion TG_1 may be disposed at a vertical level lower than the first surface 110F1 of the first semiconductor substrate 110. For example, the first portion TG_1 may be disposed such that the vertical distance from the first surface 110F1 of the first semiconductor substrate 110 to the second stack ST2 is shorter than the vertical distance from the first surface 110F1 of the first semiconductor substrate 110 to the second stack ST2.

[0027] In an exemplary embodiment, a transmission gate insulating layer TGI may be disposed on an inner wall of the transmission trench TGH. The transmission gate insulating layer TGI may be interposed between the transmission gate TG and the first semiconductor substrate 110 with a relatively uniform thickness.

[0028] The first and second portions TG_1 and TG_2 of the transmission gate TG may be spaced apart from the floating diffusion region FD in a horizontal direction (e.g., a first horizontal direction X or a second horizontal direction Y) by a lateral distance ld. In an exemplary embodiment, the first stack ST1 does not include any gates other than the transmission gate TG, thereby ensuring a relatively long distance between the transmission gate TG and the floating diffusion region FD.

[0029] In an exemplary embodiment, a passivation layer 152 may be disposed on a top surface and sidewalls of the first portion TG_1 of the transmission gate TG and on the first surface 110F1 of the first semiconductor substrate 110, and a first etch stop film 154 may be disposed on the passivation layer 152. The first etch stop film 154 may be disposed on the passivation layer 152 to cover a top surface and sidewalls of the first portion TG_1 of the transmission gate TG and to cover the first surface 110F1 of the first semiconductor substrate 110. In an exemplary embodiment, the passivation layer 152 may include silicon oxide, and the first etch stop film 154 may include silicon nitride.

[0030] In an exemplary embodiment, the passivation layer 152 extends to cover the entire first face 110F1 of the first semiconductor substrate 110, and may, for example, cover the floating diffusion region FD. The passivation layer 152 is disposed directly on the top surface and sidewalls of the first portion TG_1 of the transmission gate TG, with no other material layer, such as a spacer, interposed between the top surface and sidewalls of the first portion TG_1 of the transmission gate TG and the passivation layer 152.

[0031] 4, the passivation layer 152 may be conformally formed to a relatively thin and uniform thickness on the top surface and sidewalls of the first portion TG_1 of the transmission gate TG. For example, the passivation layer 152 may include a first portion 152a disposed on the top surface of the first portion TG_1 of the transmission gate TG and a second portion 152b disposed on the sidewalls of the first portion TG_1 of the transmission gate TG, and the thickness of the first portion 152a of the passivation layer 152 is also the same as the thickness of the second portion 152b of the passivation layer 152.

[0032] The first etch stop layer 154 may be conformally formed on the passivation layer 152 to a uniform thickness to cover the top surface and sidewalls of the first portion TG_1 of the transmission gate TG.

[0033] In an exemplary embodiment, at least a portion of the sidewall 154S of the first etch stop film 154 extends vertically to the first surface 110F1 of the first semiconductor substrate 110, for example, a portion of the sidewall 154S of the first etch stop film 154 disposed on the sidewall of the first portion TG_1 of the transfer gate TG extends vertically to the first surface 110F1 of the first semiconductor substrate 110.

[0034] The first buried insulating layer 156 may be formed relatively high on the first etch stop layer 154. A first contact 158 ​​may be disposed in a first contact hole 158H penetrating the first buried insulating layer 156. The first contact hole 158H may extend in the vertical direction Z through the first buried insulating layer 156 to expose an upper surface of the first portion TG_1 of the transmission gate TG, an upper surface of the floating diffusion region FD, or an upper surface of the ground region GND. The first contact 158 ​​may be disposed in the first contact hole 158H and connected to an upper surface of the first portion TG_1 of the transmission gate TG, an upper surface of the floating diffusion region FD, or an upper surface of the ground region GND. In an exemplary embodiment, the first buried insulating film 156 may include silicon oxide, and the first contact 158 ​​may include at least one of titanium (Ti), titanium nitride (TiN), ruthenium (Ru), ruthenium nitride (RuN), tungsten (W), cobalt (Co), and molybdenum (Mo).

[0035] In an exemplary embodiment, the passivation layer 152 may be formed to a thin thickness to conformally cover the sidewalls and top surface of the transmission gate TG after patterning the transmission gate TG, and then a first etch stop layer 154 may be formed on the passivation layer 152. Then, a first buried insulating film 156 may be formed on the first etch stop layer 154 to a height that completely covers the transmission gate TG. In an etching process for removing a portion of the first buried insulating film 156 to form a first contact hole 158H, the passivation layer 152 and the first etch stop layer 154 may function as an etch stop layer.

[0036] A first front structure FS1 may be disposed on the first buried insulating film 156. The first front structure FS1 may include a plurality of first insulating layers 112, a plurality of second insulating layers 114, and a wiring layer 116. For example, the first insulating layer 112 may include silicon oxide or silicon carbon nitride, and the second insulating layer 114 may include silicon oxide or silicon carbon nitride. For example, the first insulating layer 112 and the second insulating layer 114 may include materials having an etching selectivity to each other. The wiring layer 116 is covered by the first insulating layer 112 or the second insulating layer 114 and has a multi-layer structure.

[0037] The first surface 110F1 of the first semiconductor substrate 110 may be disposed to face the second surface 120F2 of the second semiconductor substrate 120, and the first front structure FS1 disposed on the first surface 110F1 of the first semiconductor substrate 110 may be disposed adjacent to the back structure BS2 disposed on the second surface 120F2 of the second semiconductor substrate 120. A first bonding insulation layer BI1 and a first bonding pad BP1 may be disposed at the interface between the first front structure FS1 and the back structure BS2. The first bonding insulation layer BI1 may include silicon oxide or silicon carbon nitride, and the first bonding pad BP1 may include copper.

[0038] A pixel transistor PXT may be disposed in the second stack ST2 in the active pixel region APR. The pixel transistor PXT may be disposed on the first surface 120F1 of the second semiconductor substrate 120. For example, the pixel transistor PXT may include a pixel gate PXG and a source / drain region PXS. The source / drain region PXS may be disposed inside the second semiconductor substrate 120 adjacent to the pixel gate PXG. The pixel gate PXG may include at least one of doped polysilicon, a metal, a metal silicide, a metal nitride, or a metal-containing film.

[0039] A gate insulating layer PGI may be disposed between the first surface 120F1 of the second semiconductor substrate 120 and the pixel gate PXG. A gate spacer 162 may be disposed on a sidewall of the pixel gate PXG. The gate spacer 162 may include silicon nitride. The gate spacer 162 has a curved profile such that a width of a portion of the gate spacer 162 adjacent to a top surface of the pixel gate PXG is narrower than a width of a portion of the gate spacer 162 adjacent to a bottom surface of the pixel gate PXG.

[0040] A second etch stop layer 164 covering the pixel gate PXG and the gate spacer 162 may be disposed on the first surface 120F1 of the second semiconductor substrate 120. The second etch stop layer 164 may be disposed on an upper surface and a sidewall of the pixel gate PXG. The second etch stop layer 164 may be disposed to directly contact an upper surface of the pixel gate PXG, and a gate spacer 162 may be interposed between the second etch stop layer 164 and a sidewall of the pixel gate PXG. Since the gate spacer 162 has a curved profile, a portion of the second etch stop layer 164 in contact with the gate spacer 162 also has a curved profile and extends over the gate spacer 162.

[0041] In an exemplary embodiment, the pixel transistor PXT may be configured to provide signals to the photoelectric conversion region PD and the floating diffusion region FD arranged in the first stack ST1. For example, the pixel transistor PXT may include a source follower transistor SFX (see FIG. 7), a selection transistor SX, and a reset transistor RX. For example, the photoelectric conversion region PD and / or the floating diffusion region FD arranged in the first stack ST1 in one pixel PX may be electrically connected to a pixel gate PXG arranged in the second stack ST2 in the one pixel PX. For example, the photoelectric conversion region PD and / or the floating diffusion region FD arranged in the first stack ST1 in one pixel PX may be electrically connected to a pixel gate PXG constituting the source follower transistor SFX (see FIG. 7), the selection transistor SX (see FIG. 7), and the reset transistor RX (see FIG. 7) arranged in the second stack ST2 in the one pixel PX.

[0042] In an exemplary embodiment, the reset transistor RX may be configured to periodically reset the charge stored in the floating diffusion region FD. The source follower transistor SFX may be configured to act as a source follower buffer amplifier and buffer a signal due to the charge stored in the floating diffusion region. The selection transistor SX may perform switching and addressing functions to select the pixel PX.

[0043] The second stack ST2 may further include a second buried insulating film 166 covering the pixel gate PXG, and a second contact 168 electrically connected to the pixel gate PXG or the source / drain region PXS through the second buried insulating film 166. The second contact 168 is disposed in a second contact hole 168H penetrating the second buried insulating film 166, and may include at least one of, for example, titanium (Ti), titanium nitride (TiN), ruthenium (Ru), ruthenium nitride (RuN), tungsten (W), cobalt (Co), and molybdenum (Mo).

[0044] A second front structure FS2 may be disposed on the second buried insulating layer 166. The second front structure FS2 may include a plurality of first insulating layers 122, a plurality of second insulating layers 124, and a wiring layer 126. For example, the first insulating layer 122 may include silicon oxide or silicon carbon nitride, and the second insulating layer 124 may include silicon oxide or silicon carbon nitride. For example, the first insulating layer 122 and the second insulating layer 124 may include materials having an etching selectivity to each other. The wiring layer 126 is covered by the first insulating layer 122 or the second insulating layer 124 and has a multi-layer structure.

[0045] A back surface insulating layer 128 may be disposed on the second surface 120F2 of the second semiconductor substrate 120. As illustrated in FIG 4, the back surface insulating layer 128 may be disposed on the entire region of the second surface 120F2 of the second semiconductor substrate 120 and may surround a portion of the first bonding pad BP1.

[0046] The second stack ST2 may further include a vertical via VT penetrating the second semiconductor substrate 120 to electrically connect the back structure BS2 to the second front structure FS2. The vertical via VT may be disposed in a vertical via trench VTH extending in the vertical direction Z through the second semiconductor substrate 120, and the first bonding pad BP1 disposed on the second surface 120F2 of the second semiconductor substrate 120 and the wiring layer 126 included in the second front structure FS2 may be electrically connected to each other through the vertical via VT. A vertical via insulating layer VTI may be disposed on a sidewall of the vertical via VT to electrically isolate the vertical via VT from the second semiconductor substrate 120.

[0047] In an exemplary embodiment, the floating diffusion region FD included in the first stack ST1 may be electrically connected to a pixel gate PXG (e.g., a pixel gate PXG constituting a source follower transistor SFX) included in the second stack ST2 through a vertical via VT.

[0048] In some exemplary embodiments, as illustrated in FIGS. 2 and 3, a first pixel PX-1, a second pixel PX-2, a third pixel PX-3, and a fourth pixel PX-4 may be arranged in a matrix. Each of the first to fourth pixels PX-1, PX-2, PX-3, and PX-4 in the first stack ST1 has a transmission gate TG and a floating diffusion region FD. The first pixel PX-1 and the third pixel PX-3 arranged side by side in the second direction Y have mirror-symmetric shapes, and the first pixel PX-1 and the second pixel PX-2 arranged side by side in the first direction X have mirror-symmetric shapes. The layout of the pixel PX illustrated in FIGS. 2 and 3 is illustrated for illustrative purposes, and the size, shape, position, etc. of the transmission gate TG and the pixel gate PXG are not limited to those illustrated in FIGS. 2 and 3.

[0049] A color filter CF and a microlens ML may be disposed on the second surface 110F2 of the first semiconductor substrate 110.

[0050] The third stack ST3 may include a logic transistor LCT disposed on the first surface 130F1 of the third semiconductor substrate 130, and the logic transistor LCT may include a logic gate LCG and a source / drain region LCS. A third buried insulating layer 172 may be disposed on the first surface 130F1 of the third semiconductor substrate 130, and a third contact 174 may be disposed penetrating the third buried insulating layer 172.

[0051] A third front structure FS3 may be disposed on the third buried insulating layer 172 of the third stack ST3. The third front structure FS3 may include at least one first insulating layer 132, at least one second insulating layer 134, and a wiring layer 136. For example, the first insulating layer 132 may include silicon oxide or silicon carbon nitride, and the second insulating layer 134 may include silicon oxide or silicon carbon nitride. For example, the first insulating layer 132 and the second insulating layer 134 may include materials having an etching selectivity to each other. The wiring layer 136 may be covered by the first insulating layer 132 or the second insulating layer 134 and may have a multi-layer structure.

[0052] The first surface 120F1 of the second semiconductor substrate 120 may be disposed to face the first surface 130F1 of the third semiconductor substrate 130, and the second front structure FS2 disposed on the first surface 120F1 of the second semiconductor substrate 120 may be disposed adjacent to the third front structure FS3 disposed on the first surface 130F1 of the third semiconductor substrate 130. A second bonding insulation layer BI2 and a second bonding pad BP2 may be disposed at the interface between the second front structure FS2 and the third front structure FS3. The second bonding insulation layer BI2 may include silicon oxide or silicon carbon nitride, and the second bonding pad BP2 may include copper.

[0053] In an exemplary embodiment, a first bonding insulation layer BI1 and a first bonding pad BP1 may be disposed at an interface between the first front structure FS1 and the back structure BS2, the first stack ST1 and the second stack ST2 may be attached to each other, and a second bonding insulation layer BI2 and a second bonding pad BP2 may be disposed at an interface between the second front structure FS2 and the third front structure FS3, the second stack ST2 and the third stack ST3 may be attached to each other. That is, the first stack ST1, the second stack ST2, and the third stack ST3 may be attached to each other by a metal oxide hybrid wafer bonding method. However, in other embodiments, only the first bonding insulation layer BI1 is arranged at the interface between the first front structure FS1 and the back structure BS2, and only the second bonding insulation layer BI2 is arranged at the interface between the second front structure FS2 and the third front structure FS3, in which case the first stack ST1, the second stack ST2, and the third stack ST3 may be attached to each other by an oxide-oxide wafer bonding method.

[0054] In general, a spacer is formed on a sidewall of the transmission gate due to a relatively short distance from the floating diffusion region, and an ion implantation process for forming the floating diffusion region is performed using the transmission gate and the spacer as an ion implantation mask. However, etching damage may occur in a semiconductor substrate during an etching process for forming the spacer, which may increase noise due to dark current in the image sensor.

[0055] However, according to the above-described exemplary embodiment, the pixel gate PXG may be disposed in the second stack ST2, and the transmission gate TG and the floating diffusion region FD may be disposed in the first stack ST1. Therefore, even if the transmission gate TG is disposed horizontally spaced apart from the floating diffusion region FD and a spacer is not formed on a sidewall of the transmission gate TG, the ion implantation process for forming the floating diffusion region FD can be precisely controlled. Therefore, etching damage to the semiconductor substrate during the spacer formation process can be prevented, and noise generation in the image sensor 100 can be reduced or prevented.

[0056] FIG. 7 is an equivalent circuit diagram of a pixel PX of an image sensor according to an exemplary embodiment.

[0057] 7, a plurality of pixels PX may be arranged in a matrix. Each of the plurality of pixels PX may include a transmission transistor TX and a pixel transistor. Here, the pixel transistor may include a reset transistor RX, a selection transistor SX, and a source follower transistor SFX. The reset transistor RX may include a reset gate RG, the selection transistor SX may include a selection gate SG, and the transmission transistor TX may include a transmission gate TG.

[0058] Each of the pixels PX may further include a photoelectric conversion region PD and a floating diffusion region FD. The photoelectric conversion region PD may correspond to the photoelectric conversion region PD described in Figures 1 to 6. The photoelectric conversion region PD generates and accumulates photocharges in proportion to the amount of light incident from the outside, and may be a photodiode, a phototransistor, a photogate, a Pinned Photo Diode (PPD), or a combination thereof.

[0059] The transmission gate TG may transmit the charges generated in the photoelectric conversion region PD to the floating diffusion region FD. The floating diffusion region FD may accumulate and store the charges transmitted from the photoelectric conversion region PD. The source follower transistor SFX may be controlled according to the amount of photocharges accumulated in the floating diffusion region FD.

[0060] The reset transistor RX may periodically reset the charge stored in the floating diffusion region FD. The drain electrode of the reset transistor RX is connected to the floating diffusion region FD, and the source electrode of the reset transistor RX is connected to the power supply voltage V DD When the reset transistor RX is turned on, the power supply voltage V DD is transferred to the floating diffusion region FD. When the reset transistor RX is turned on, charges stored in the floating diffusion region FD may be discharged, resetting the floating diffusion region FD.

[0061] The source follower transistor SFX is connected to a current source (not shown) located outside the pixels PX and functions as a source follower buffer amplifier to amplify the potential change in the floating diffusion region FD and output it to the output line V OUT Output to.

[0062] The selection transistor SX selects a number of pixels PX by row, and when the selection transistor SX is turned on, the output voltage generated by the source follower transistor SFX is applied to the output line V OUT can be transmitted to

[0063] 8 to 15 are schematic diagrams showing image sensors according to exemplary embodiments, in which the same reference numerals as those in FIGS. 1 to 7 denote the same components.

[0064] FIG. 8 is a layout diagram of the first stack ST1 of the image sensor 100A according to the exemplary embodiment.

[0065] 8, the floating diffusion region FD may be shared by the first to fourth pixels PX-1 to PX-4. The pixel separating structure 140 is not disposed in a portion of the first semiconductor substrate 110 that vertically overlaps with the floating diffusion region FD.

[0066] FIG. 9 is a layout diagram illustrating an image sensor 100B according to an exemplary embodiment, and FIG. 10 is a cross-sectional view of the image sensor 100B of FIG.

[0067] 9 and 10, the transmission gate TG may be a dual type transmission gate. For example, two transmission gates TG may be disposed in one pixel. For example, the transmission gate TG may include a first gate TG_L and a second gate TG_R that are disposed spaced apart from each other. In some embodiments, as shown in FIG. 9, the first gate TG_L and the second gate TG_R may be disposed to have the same distance from the floating diffusion region FD.

[0068] FIG. 11 is a layout diagram illustrating an image sensor 100C according to an exemplary embodiment, and FIG. 12 is a cross-sectional view of the image sensor 100C of FIG.

[0069] 11 and 12, the transmission gate TG may be a merged dual-type transmission gate. For example, the second portion TG_2 disposed in the first semiconductor substrate 110 may include a first gate TG_L and a second gate TG_R spaced apart from each other, and the first portion TG_1 disposed on the first surface 110F1 of the first semiconductor substrate 110 may be an integrated gate connected to both the first gate TG_L and the second gate TG_R spaced apart from each other.

[0070] FIG. 13 is a layout diagram illustrating an image sensor 100d according to an example embodiment.

[0071] 13, the transmission gate TG may also be a gate-all-around type transmission gate. For example, the transmission gate TG may have a ring-shaped or annular horizontal cross-sectional shape. Of the transmission gate TG, a second portion TG_2 (see FIG. 5) disposed in the transmission gate trench TGH may have a ring-shaped or annular horizontal cross-sectional shape, and / or a first portion TG_1 (see FIG. 5) disposed on the first surface 110F1 of the first semiconductor substrate 110 may have a ring-shaped or annular horizontal cross-sectional shape.

[0072] FIG. 14 is a layout diagram illustrating an image sensor 100e according to an example embodiment.

[0073] 14, the transmission gate TG may also be a gate of a planar transistor. For example, the transmission gate TG may be disposed on the first surface 110F1 of the first semiconductor substrate 110, and a transmission gate insulating layer TGI may be disposed between the transmission gate TG and the first surface 110F1 of the first semiconductor substrate 110 and extend in the horizontal direction.

[0074] FIG. 15 is a cross-sectional view illustrating an image sensor 100f according to an example embodiment.

[0075] 15, a first surface 120F1 of the second semiconductor substrate 120 may be disposed to face a first surface 110F1 of the first semiconductor substrate 110, and a second front structure FS2 disposed on the first surface 120F1 of the second semiconductor substrate 120 may be disposed adjacent to a first front structure FS1 disposed on the first surface 110F1 of the first semiconductor substrate 110. A first bonding insulation layer BI1 and a first bonding pad BP1 may be disposed at an interface between the second front structure FS2 and the first front structure FS1.

[0076] The second surface 120F2 of the second semiconductor substrate 120 is disposed to face the first surface 130F1 of the third semiconductor substrate 130, and the back surface structure BS2 disposed on the second surface 120F2 of the second semiconductor substrate 120 may be disposed adjacent to the third front surface structure FS3 disposed on the first surface 130F1 of the third semiconductor substrate 130. A second bonding insulating layer BI2 and a second bonding pad BP2 may be disposed at the interface between the back surface structure BS2 and the third front surface structure FS3. The back surface structure BS2 may include a back surface insulating layer 128 and a wiring layer 129.

[0077] The second stack ST2 may further include a vertical via VT penetrating the second semiconductor substrate 120 to electrically connect the backside structure BS2 to the second front side structure FS2. The vertical via VT may be disposed in a vertical via trench VTH extending in the vertical direction Z through the second semiconductor substrate 120, and the wiring layer 129 disposed on the second surface 120F2 of the second semiconductor substrate 120 and the wiring layer 126 included in the second front side structure FS2 may be electrically connected to each other through the vertical via VT. A vertical via insulating layer VTI may be disposed on a sidewall of the vertical via VT to electrically isolate the vertical via VT from the second semiconductor substrate 120.

[0078] In an exemplary embodiment, the pixel gate PXG included in the second stack ST2 may be electrically connected to the logic transistor LCT included in the third stack ST3 through a vertical via VT.

[0079] Among the image sensors 100A, 100B, 100C, 100D, 100E, and 100F shown in Figs. 8 to 15, technical features of at least one of the embodiments may be combined with technical features of at least one of the other embodiments. For example, the image sensor 100A described with reference to Fig. 8 may be modified to a type in which the first surface 120F1 of the second semiconductor substrate 120 faces the first surface 110F1 of the first semiconductor substrate 110 as described with reference to Fig. 15. In addition, the image sensors 100B, 100C, 100D, and 100E described with reference to Figs. 9 to 14 may be modified to a type in which the first surface 120F1 of the second semiconductor substrate 120 faces the first surface 110F1 of the first semiconductor substrate 110 as described with reference to Fig. 15.

[0080] FIG. 16 is a block diagram illustrating a configuration of an image sensor 1100 according to an exemplary embodiment.

[0081] 16, an image sensor 1100 may include a pixel array 1110, a controller 1130, a row driver 1120, and a pixel signal processing unit 1140. The image sensor 1100 may include at least one of the image sensors 100, 100A, 100B, 100C, 100D, 100E, and 100F described in FIGS.

[0082] The pixel array 1110 includes a plurality of unit pixels arranged two-dimensionally, and each unit pixel may include a photoelectric conversion element. The photoelectric conversion element absorbs light to generate electric charges, and an electric signal (output voltage) based on the generated electric charges may be provided to the pixel signal processor 1140 via a vertical signal line. The unit pixels included in the pixel array 1110 provide output voltages one at a time in row units, and thus, the unit pixels belonging to one row of the cell array 1110 may be simultaneously activated by a selection signal output by the row driver 1120. The unit pixels belonging to the selected row may provide output voltages based on the absorbed light to an output line of a corresponding column.

[0083] The controller 1130 may control the row driver 1120 to cause the pixel array 1110 to absorb light and accumulate charges, or temporarily store the accumulated charges, and output an electrical signal based on the stored charges to the outside of the pixel array 1110. The controller 1130 may also control the pixel signal processor 1140 to measure an output voltage provided by the pixel array 1110.

[0084] The pixel signal processing unit 1140 may include a correlated double sampler (CDS) 1142, an analog-to-digital converter (ADC) 1144, and a buffer 1146. The correlated double sampler 1142 may sample and hold an output voltage provided by the pixel array 1110. The correlated double sampler 1142 may double sample a specific noise level and a level according to the generated output voltage, and output a level corresponding to the difference. In addition, the correlated double sampler 1142 may receive a ramp signal generated by a ramp signal generator 1148, compare the ramp signals with each other, and output a comparison result.

[0085] The analog-to-digital converter 1144 may convert an analog signal corresponding to a level received from the correlated double sampler 1142 into a digital signal. The buffer 1146 may latch the digital signal, and the latched signals may be sequentially output to the outside of the image sensor 1100 and transmitted to an image processor (not shown).

[0086] As mentioned above, the drawings and the specification disclose exemplary embodiments. Although specific terms are used in the present specification to describe the embodiments, these terms are merely used to describe the technical ideas of the present disclosure, and are not used to limit the meaning or the scope of the present disclosure described in the claims. Therefore, a person having ordinary skill in the art will understand that various modifications and equivalent other embodiments are possible. Therefore, the true technical scope of protection of the present disclosure should be determined by the technical ideas of the claims. [Explanation of symbols]

[0087] 142 Conductive Layer 144 Insulating Liner 140T Pixel Trench 158 First Contact PX Pixels PD Photoelectric conversion area FD Floating diffusion area TG Transmission Gate ST1 First stack ST1 Second stack ST1 3rd stack GND Ground area PX-1 First Pixel PX-2 2nd Pixel PX-3 3rd Pixel PX-4 4th Pixel

Claims

1. a first stack including: a first semiconductor substrate having a first surface and a second surface opposite to the first surface; a photoelectric conversion region disposed in the first semiconductor substrate; a floating diffusion region disposed in the first semiconductor substrate and configured to store charges transferred from the photoelectric conversion region; a transfer gate disposed on the first surface of the first semiconductor substrate; and a first etch stop layer disposed on an upper surface and a sidewall of the transfer gate and on the first surface of the first semiconductor substrate; a second stack attached to the first stack, the second stack including: a second semiconductor substrate having a first surface and a second surface opposite to the first surface; a pixel gate disposed on the first surface or the second surface of the second semiconductor substrate and electrically connected to the floating diffusion region; and a gate spacer disposed on a sidewall of the pixel gate; a third stack attached to the second stack, the third stack including logic transistors that provide signals to the pixel gate and the transmission gate.

2. 2. The image sensor of claim 1, wherein no spacers are disposed on both sidewalls of the transmission gate.

3. The image sensor of claim 1 , wherein the transmission gate is disposed horizontally spaced apart from the floating diffusion region.

4. 2. The image sensor of claim 1, wherein the sidewalls of the transfer gate are perpendicular to the first surface of the first semiconductor substrate, and the first etch stop layer is conformally disposed on the top surface and the sidewalls of the transfer gate.

5. The transmission gate comprises: a first portion disposed on the first surface of the first semiconductor substrate; 2. The image sensor of claim 1 , further comprising: a second portion disposed in a transmission trench extending from the first surface of the first semiconductor substrate into the first semiconductor substrate and integrally connected to the first portion.

6. The first stack comprises:

6. The image sensor of claim 5, further comprising a transfer gate insulating layer disposed on an inner wall of the transfer trench and interposed between the first semiconductor substrate and the second portion of the transfer gate.

7. The first stack comprises:

2. The image sensor of claim 1, further comprising a passivation layer interposed between the top surface and sidewalls of the transfer gate and the first etch stop layer, and between the first surface of the first semiconductor substrate and the first etch stop layer.

8. 8. The image sensor of claim 7, wherein a thickness of a first portion of the passivation layer disposed on the top surface of the transmission gate is the same as a thickness of a second portion of the passivation layer disposed on the sidewalls of the transmission gate.

9. 8. The image sensor of claim 7, wherein a portion of the first etch stop layer disposed on the sidewall of the transfer gate has a sidewall that extends perpendicular to the first surface of the first semiconductor substrate.

10. 8. The image sensor of claim 7, wherein the passivation layer and the first etch stop layer extend over the floating diffusion region.

Images