Semiconductor device

Abstract

To provide a semiconductor device which restrains a snapback phenomenon.SOLUTION: A semiconductor device 100 includes a first semiconductor element 10 having a second semiconductor region 7 on a first semiconductor region 5, a third semiconductor region 8 on a second semiconductor region, a first trench 14 penetrating the second semiconductor region, an in-first-trench electrode 14a, a fourth semiconductor region 2 below the first semiconductor region, an upper electrode 11 connected to the third semiconductor region, and a lower electrode 1 connected to the fourth semiconductor region, a second semiconductor element 20 that is electrically connected to the upper electrode and has a fifth semiconductor region 12 on the first semiconductor region and a sixth semiconductor region 3 connected to the lower electrode, and a dummy region 30 that is provided between the first semiconductor element and the second semiconductor element and has a seventh semiconductor region 7D on the first semiconductor region, a third trench 15 penetrating the seventh semiconductor region, and an in-third-trench electrode 15a that is electrically connected to the first trench electrode in the third trench.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Conventionally, a reverse conducting IGBT (RC-IGBT) has been proposed, which is a semiconductor device in which an insulated gate bipolar transistor (IGBT) and a free wheeling diode are formed on a single semiconductor substrate. In an RC-IGBT, when the IGBT is turned on, electrons in the drift region move to the cathode region of the diode that does not have a collector region, which suppresses the injection of holes from the collector layer of the IGBT into the drift region, making it difficult for the IGBT to undergo conductivity modulation. This phenomenon is called snapback. Also disclosed is an example in which a region called a resurf region for improving breakdown voltage is provided in the peripheral region of the semiconductor device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2015-154000 A [Patent Document 2] JP 2022-56498 A [Patent Document 3] JP 2018-46187 A [Patent Document 4] JP 2004-349556 A [Patent Document 5] Patent No. 5383009 [Non-patent literature]

[0004] [Non-Patent Document 1] UR Vemulapati, N. Kaminski, D. Silber, L. Storasta, and M. Rahimo, “Analytical Model for the Initial Snapback Phenomenon in RCIGBTs”, ISPS, August 2012, Prague, Czech Republic,

[2012] IEEE. Reprinted from the Internacional Seminar on Power Semiconductors. Summary of the Invention [Problem to be solved by the invention]

[0005] The problem to be solved by the embodiments is to provide a semiconductor device in which the snapback phenomenon is suppressed. [Means for solving the problem]

[0006] A semiconductor device according to an embodiment includes a first semiconductor element having a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type provided on the first semiconductor region, a third semiconductor region of the first conductivity type provided on the second semiconductor region, a first trench provided so as to penetrate the second semiconductor region in a depth direction, a first trench electrode provided in the first trench via a first insulating film, a fourth semiconductor region of a second conductivity type provided below the first semiconductor region on the opposite side facing the second semiconductor region, an upper electrode electrically connected to the third semiconductor region, and a lower electrode electrically connected to the fourth semiconductor region, a second semiconductor element having a fifth semiconductor region of a first conductivity type, a second trench provided so as to penetrate the fifth semiconductor region in the depth direction, a second trench electrode provided within the second trench via a second insulating film, and a sixth semiconductor region of a first conductivity type provided below the first semiconductor region and electrically connected to the lower electrode and on the opposite side facing the fifth semiconductor region; and a dummy region between the first semiconductor element and the second semiconductor element, having a seventh semiconductor region of the second conductivity type provided on the first semiconductor region, a third trench provided so as to penetrate the seventh semiconductor region in the depth direction, and a third trench electrode provided within the third trench via a third insulating film and electrically connected to the first trench electrode. Effect of the Invention

[0007] According to the embodiment of the present invention, it is possible to provide a semiconductor device in which the snapback phenomenon is suppressed. [Brief description of the drawings]

[0008] [Figure 1] 1 is a top view of an entire structure of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is an enlarged top view of a portion of FIG. 1; [Diagram 3] 3 is a cross-sectional view taken along line II in FIG. 2. [Figure 4] FIG. 3 is a cross-sectional view taken along line II-II in FIG. 2 . [Diagram 5] FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2 . [Figure 6] 4 is a cross-sectional view taken along line IV-IV in FIG. 2 . [Figure 7] Cross-sectional view taken along line VV in Figure 1. [Figure 8A] 11 shows a simulation result of an electromagnetic field distribution in a dummy portion during a snapback operation in the semiconductor device according to the first embodiment. [Figure 8B] 6 shows a simulation result of an electromagnetic field distribution in a dummy portion at a later stage of a snapback operation in the semiconductor device according to the first embodiment. [Figure 9A] 13 shows a simulation result of an electromagnetic field distribution in a dummy portion during a snapback operation in a semiconductor device according to a comparative example. [Figure 9B] 13 shows a simulation result of an electromagnetic field distribution in a dummy portion at a later stage of a snapback operation in a semiconductor device according to a comparative example. [Figure 10] FIG. 11 is a cross-sectional view of a semiconductor device according to a modified example of the first embodiment. [Figure 11] 1 is a top view of a portion of an IGBT of the semiconductor device according to the first embodiment. [Figure 12] FIG. 11 is a top view of the entire structure of a semiconductor device according to a second embodiment. [Figure 13] FIG. 13 is an enlarged top view of a portion of FIG. 12. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Next, an embodiment of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are given the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of lengths of each part, etc., differ from the actual ones. Therefore, the specific dimensions should be determined with reference to the following description. In addition, it goes without saying that the drawings include parts with different dimensional relationships and ratios.

[0010] In addition, the embodiments shown below are examples of devices for embodying the technical idea of ​​this invention, and the technical idea of ​​this invention does not specify the shape, structure, arrangement, etc. of the components as described below. Various modifications can be made to the embodiments of this invention within the scope of the claims. In addition, the terms "upper" and "lower" that specify upper and lower are used in this invention for convenience of description, and even if they are provided on the side, they fall within the scope of the rights of this invention as long as they are substantially the same as the constituent elements of this invention. In addition, "upper" includes not only the case where they are formed in contact with the object, but also the case where they are formed through another layer. In addition, in this invention, "connection" is not limited to direct connection, and even if they are connected through something such as a resistor, they fall within the scope of the rights of this invention as long as they are substantially the same as the constituent elements of this invention.

[0011] In the following description, the directions of the semiconductor device are defined by the XYZ axes. In the cross-sectional view, the left-right direction is the X-axis direction, the direction perpendicular to the paper surface is the Y-axis direction, and the direction perpendicular to the XY plane is the Z-axis direction. These directions are merely examples. Depending on the arrangement of the pattern, they can be changed as appropriate. In the following description, the semiconductor device is mainly described as an IGBT, but it is sufficient that the semiconductor device has a freewheeling diode formed on one semiconductor substrate, and a MOSFET may be used instead of the IGBT. Also, other elements with an insulated gate structure such as an electron injection enhanced insulated gate transistor (IEGT) may be used. Also, a super junction MOSFET or a complementary metal oxide semiconductor field effect transistor (CMOSFET) may be used.

[0012] (First embodiment) FIG. 1 is a top view of the overall structure of a semiconductor device 100 according to the first embodiment.

[0013] 1, the semiconductor device 100 according to the first embodiment includes a semiconductor substrate 101, a diode section 20 arranged on the semiconductor substrate 101, and an IGBT section 10 arranged around the diode section 20 on the semiconductor substrate 101. In the semiconductor device 100 according to the first embodiment, the diode section 20 is arranged in an island shape, a dummy section 30 is provided around the diode section 20, and the IGBT section 10 is arranged outside of the dummy section 30. In other words, the IGBT section 10, dummy section 30, diode section 20, dummy section 30, IGBT section 10, dummy section 30, diode section 20... are repeatedly arranged in the longitudinal direction of the trench 14 of the IGBT section 10.

[0014] The semiconductor device 100 according to the first embodiment constitutes a reverse conducting IGBT (RC-IGBT) in which an IGBT section 10 and a free wheeling diode section 20 are formed on one semiconductor substrate 101. A region for improving breakdown voltage, called a resurf region, is provided in a termination region 40 on the periphery of the semiconductor device 100. The IGBT section 10 is arranged around the diode section 20 arranged in an island shape on the semiconductor substrate 101. A boundary region 30 is provided around the diode section 20. The boundary region 30 is also called a dummy region. In the example shown in FIG. 1, a control pad section 500 is also provided on the semiconductor substrate 101. Although not shown in FIG. 1, an emitter pad 51 is provided on the IGBT section 10 and / or the diode section 20.

[0015] The control pad section 500 includes, for example, a current sense pad 50, a gate pad 52, and temperature sense pads 53 and 54. The current sense pad 50 is a control pad for detecting a current flowing in the cell region of the semiconductor device 100.

[0016] The gate pad 52 is a control pad to which a gate drive voltage is applied for controlling the on / off of the semiconductor device 100. The temperature sense pads 53 and 54 are control pads electrically connected to, for example, the anode and cathode of a temperature sense diode provided in the semiconductor device 100.

[0017] Fig. 2 is an enlarged top view of a portion of the semiconductor device 102 in Fig. 1. Fig. 2 shows the arrangement of the diode section 20, a boundary region (dummy section) 30 surrounding the diode section 20, and the IGBT section 10 surrounding the boundary region 30. The inside of the dashed line FLR represents a region where an eighth semiconductor region (FLR region) described below is provided (the boundary line between the presence or absence of the eighth semiconductor region). The dashed line DMY1 represents the boundary line between the diode section 20 and the boundary region 30. The dashed line DMY2 represents the boundary line between the IGBT section 10 and the boundary region 30.

[0018] In the IGBT section 10, a plurality of trenches 14 extend in a first direction (longitudinal direction, Y direction) and are arranged in parallel in a second direction (transverse direction, X direction). Some of the trenches 14 are each connected to each of the trenches 15 in the boundary region 30 in the Y direction.

[0019] A connection trench 16C2 extending in a second direction perpendicular to the Y direction is provided at the Y-direction end of the trench 16 of the diode section 20. The trenches 16 extend in the Y direction, are arranged in parallel in the second direction (short side direction, X direction), and are terminated in a T-structure at the connection trench 16C2.

[0020] In a boundary region 30 between the diode section 20 and the IGBT section 10 as viewed in the Y direction from the diode section 20, the trench 15 has an end spaced apart from the trench 16 of the diode section 20 and the connection trench 16C2 which are on an extension line in the Y direction. A connection trench 15C1 extending in the X direction is provided at an end in the Y direction of the trench 15 in the boundary region 30. In the boundary region 30, a plurality of trenches 15 extend in the Y direction and terminate in a T-shaped structure at the connection trench 15C1.

[0021] A first end 15EG in the Y direction extending from the trench 15 is connected to a first end 15EG in the Y direction extending from an adjacent trench 15 via a connection trench 15C1.

[0022] A second end 16EG in the Y direction extending from the trench 16 is connected to a second end 16EG in the Y direction extending from an adjacent trench 16 via a connection trench 16C2.

[0023] A distance Y1 between a first end 15EG in the Y direction extending from the trench 15 and a second end 16EG in the Y direction extending from the trench 16 is equal to or less than a distance X1 between adjacent trenches 15 in the X direction of the trenches 15 in the boundary region 30. In other words, Y1<=X1 holds.

[0024] 2, in a boundary region 30 between the diode section 20 and the IGBT section 10 as viewed in the X direction from the diode section 20, the trenches 15 extend in the Y direction and are arranged in parallel in the second direction (short-side direction, X direction). Each of the trenches 15 in the boundary region 30 is connected to each of the trenches 14 in the IGBT section 10 that are present in the Y direction from the diode section 20 at a third end 17EG, and the trenches 15 and the trenches 14 are continuous with each other.

[0025] Between a point 15FG in the first direction to which the third trench 15 extends and a point 16FG in the first direction to which the second trench 16 extends, an eighth semiconductor region 70 of the second conductivity type (FIG. 4) is provided.

[0026] With respect to the distance from the P-type eighth semiconductor region 70 having a low impurity concentration in the boundary region 30 to the emitter region 8 of the IGBT section 10, the distance WL in the longitudinal direction (Y direction) of the trench 15 is formed to be longer than the distance WS in the lateral direction (X direction) of the trench 15. In other words, WL>WS is established. There are a plurality of trenches 15 between the emitter region 8 in the X direction (WS) as viewed from the diode section 20 and the diode section 20, and these trenches 15 can prevent electrons from spreading from the emitter region to the diode section 20 side, and the distance WS can be made shorter than the distance WL.

[0027] In the IGBT section 10, a hole is formed on the P base region 7 sandwiched between the trenches 14 in the X direction, and the hole extends in the Y direction. A P-type emitter contact region 9E is formed below the bottom of the hole and above the P base region 7 in the Z direction. The n emitter region 8 is formed at the opening of the trench 14, and the n emitter region 8 is exposed on the side of the hole. The n emitter region 8 is adjacent to the trench 14 as shown in FIG. 2 and is arranged discretely in the Y direction. The n emitter regions 8 are arranged at regular intervals in the Y direction, but do not necessarily need to be arranged with regularity in the Y direction. The n emitter regions 8 may be arranged intermittently. In this way, the IGBT section 10 may include a region where the n emitter region 8 is arranged and a region where the n emitter region 8 is not arranged. By arranging the n emitter regions 8 intermittently in the IGBT section 10, excessive electron injection can be suppressed and the switching time can be shortened.

[0028] Fig. 3 is a cross-sectional view taken along line II in Fig. 2. Fig. 3 shows a cross-sectional structure taken along the XZ plane in a range spanning the diode section 20, the boundary region 30, and the IGBT section 10. In Fig. 3, a dashed line DMY1 extending in the Z direction represents the boundary between the diode section 20 and the boundary region 30. Also, a dashed line DMY2 extending in the Z direction represents the boundary between the IGBT section 10 and the boundary region 30. Note that while some of the trenches 14 taken along line II are omitted in Fig. 2, five trenches are shown in Fig. 3.

[0029] The semiconductor device 100 according to the first embodiment includes a first semiconductor element 10, a second semiconductor element 20, and a dummy region 30.

[0030] The first semiconductor element 10 has a first semiconductor region 5 of a first conductivity type, a second semiconductor region 7 of a second conductivity type provided on the first semiconductor region 5, a third semiconductor region 8 of the first conductivity type provided on the second semiconductor region 7, a first trench 14 provided so as to penetrate the second semiconductor region 7 in the depth direction, a first trench electrode 14a provided in the first trench 14 via a first insulating film 14b, a fourth semiconductor region 2 of the second conductivity type provided below the first semiconductor region 5 on the opposite side facing the second semiconductor region 7, an upper electrode 11 electrically connected to the third semiconductor region 8, and a lower electrode 1 electrically connected to the fourth semiconductor region 2.

[0031] The second semiconductor element 20 has a fifth semiconductor region 12 of the second conductivity type electrically connected to the upper electrode 11 and provided on the first semiconductor region 5, and a sixth semiconductor region 3 of the first conductivity type provided below the first semiconductor region 5, electrically connected to the lower electrode 1, and on the opposite side facing the fifth semiconductor region 12.

[0032] The dummy region 30 is located between the first semiconductor element 10 and the second semiconductor element 20, and has a second conductivity type seventh semiconductor region (P dummy region) 7D provided on the first semiconductor region 5, a third trench 15 provided so as to penetrate the seventh semiconductor region 7D in the depth direction, and a third trench electrode 15a provided in the third trench 15 via a third insulating film 15b and electrically connected to the first trench electrode 14a.

[0033] As shown in FIG. 3, the semiconductor substrate 101 includes, for example, an N-type high-resistance drift region 5, an N-type accumulation region 6 formed in the Z direction on the drift region 5 and having a higher impurity concentration than the drift region 5, P-type base regions 7, 7D and an anode region 12 formed in the Z direction on the accumulation region 6, an N-type buffer region 4 formed below the drift region 5 (in the negative Z direction), and a P-type collector region 2 and an N-type cathode region 3 formed below the buffer region 4 (in the negative Z direction).

[0034] The diode section 20 comprises an N-type high-resistance drift region 5, an N-type accumulation region 6 arranged on the drift region 5, a P-type anode region 12 provided on the accumulation region 6, and a trench 16 provided so as to penetrate the anode region 12 in the depth direction (Z direction).

[0035] In the diode section 20, the anode region 12 extends in the Y direction, sandwiched between trenches 16 extending in the Y direction. A hole is formed in the anode region 12 in the Z direction, and a P-type anode contact region 9A is provided at the bottom of the hole. An emitter electrode (upper electrode) 11 is provided inside the hole, and the anode contact region 9A is connected to the emitter electrode (upper electrode) 11. The trench 16 includes an intra-trench electrode 16a and an insulating film 16b. The intra-trench electrode 16a is connected to the emitter electrode (upper electrode) 11. The trench 16 penetrates the anode region 12, but does not penetrate the accumulation region 6.

[0036] In the boundary region 30, an N-type accumulation region 6 is disposed on the drift region 5, and a base region 7D extends in the Y direction, sandwiched between trenches 15 extending in the Y direction. A P-type dummy contact region 9D is disposed on the Z direction of the base region 7D. The dummy contact region 9D connected to the base region 7D is connected to an emitter electrode (upper electrode) 11. The trench 15 includes an intra-trench electrode 15a and an insulating film 15b. The intra-trench electrode 15a is electrically connected to the intra-trench electrode 14a of the IGBT section 10. Unlike the IGBT section 10, an emitter region 8 is not provided on the Z direction of the base region 7D in the boundary region 30 in contact with the trench 15. The trench 15 penetrates the base region 7D but does not penetrate the accumulation region 6. The base region 7D can be simultaneously formed with the same P-type doping material and impurity density as the base region 7 and the anode region 12.

[0037] The IGBT section 10 includes an N-type drift region 5, an N-type accumulation region 6 disposed on the drift region 5, a P-type base region 7 provided on the accumulation region 6, and a trench 14 provided so as to penetrate the base region 7 in the depth direction (Z direction). Here, the trench 14 does not penetrate the accumulation region 6.

[0038] In the IGBT section 10, the base region 7 extends in the Y direction, sandwiched between trenches 14 extending in the Y direction. An emitter region 8 is provided on the Z direction of the base region 7 in contact with the trenches 14. A hole is carved on the Z direction of the base region 7, and a P-type emitter contact region 9E is disposed at the bottom of the hole. The emitter contact region 9E extends in the Y direction on the base region 7 sandwiched between the trenches 14. The emitter region 8 and the emitter contact region 9E are connected to an emitter electrode (upper electrode) 11. The trench 14 includes an intra-trench electrode 14a and an insulating film 14b. The intra-trench electrode 14a is electrically connected to the gate pad 52 of FIG. 2.

[0039] An N-type emitter region 8 and a P-type emitter contact region 9E are formed in the base region 7 sandwiched between the trenches 14 in the X direction. The detailed structure will be described later with reference to FIG.

[0040] The lower electrode 1 provided in the negative Z direction of the semiconductor substrate 101 is a collector electrode connected to the P-type collector region 2 in the IGBT section 10, and a cathode electrode connected to the N-type cathode region 3 in the diode section 20. In the example of FIG. 3, the boundary line BL between the collector region 2 and the cathode region 3 is provided on the boundary line between the diode section 20 and the boundary region 30. The boundary line between the diode section 20 and the boundary region 30 is indicated by a dashed line DMY1. As indicated by a dashed line BLC1, the boundary line BL between the collector region 2 and the cathode region 3 may be provided within the boundary region 30. As indicated by a dashed line BLC2, the boundary line BL between the collector region 2 and the cathode region 3 may be provided within the IGBT section 10. As indicated by a dashed line BLA, the boundary line BL between the collector region 2 and the cathode region 3 may be provided within the diode section 20. In this way, the relative areas of the P-type collector region 2 and the N-type cathode region 3 change depending on the position of the boundary line BL between the collector region 2 and the cathode region 3. This changes the amount of carrier injection, making it possible to appropriately change the switching characteristics of the semiconductor device 100 as an RC-IGBT depending on the application.

[0041] Fig. 4 is a cross-sectional view taken along line II-II in Fig. 1. Fig. 4 shows a cross-sectional structure taken along the YZ plane spanning the diode section 20, the boundary region (dummy section) 30, and the region where the emitter electrode 11 of the IGBT section 10 is connected to the P-type emitter contact region 9E. In Fig. 4, a dashed line DMY1 extending in the Z direction represents the boundary between the diode section 20 and the boundary region 30. Also, a dashed line DMY2 extending in the Z direction represents the boundary between the IGBT section 10 and the boundary region 30. In Fig. 4, a dashed line FLR extending in the Z direction represents the boundary between the presence or absence of the eighth semiconductor region 70.

[0042] The eighth semiconductor region 70 has a bottom that is shallower than the bottom of the second trench 16 and deeper than the bottom of the seventh semiconductor region (P dummy region) 7D, and is provided between a point 15FG in the first direction to which the second trench 16 extends and a point 16FG in the first direction to which the second trench 16 extends.

[0043] That is, the eighth semiconductor region 70 is formed not only directly below the base region 7D of the boundary region 30 sandwiched between the connection trench 15C1 and the connection trench 16C2, but also extends partially below the base region 7D of the boundary region 30 in the negative Y direction beyond the sidewall of the connection trench 15C1, and also extends partially below the anode region 12 of the diode section 20 in the Y direction beyond the sidewall of the connection trench 16C2. The dashed line DL shows a schematic representation of a depletion layer in a thermal equilibrium state that spreads in the N-type semiconductor region 6. The connection trench 15C1 of the boundary region 30 includes an intra-trench electrode 15a and an insulating film 15b. The connection trench 16C2 of the diode section 20 includes an intra-trench electrode 16a and an insulating film 16b. As shown in FIG. 4, it can be seen that the provision of the eighth semiconductor region 70 reduces the depletion layer from penetrating in the Z direction into the region sandwiched between the connection trench 15C1 and the connection trench 16C2.

[0044] Furthermore, an anode contact region 9A is formed in the base region 7D between the connection trench 15C1 and the connection trench 16C2, and the anode contact region 9A is electrically connected to the emitter electrode 11.

[0045] 5 is a cross-sectional view taken along line III-III in FIG. 1. In FIG. 5, a cross-sectional structure spanning the diode section 20, the dummy section 30, and the IGBT section 10 is shown. That is, cross-sectional structures taken along the YZ plane of the trenches 14 and 16 are shown. In FIG. 5, a dashed line DMY1 extending in the Z direction represents the boundary between the diode section 20 and the boundary region 30. Also, a dashed line DMY2 extending in the Z direction represents the boundary between the IGBT section 10 and the boundary region 30. In FIG. 5, a dashed line FLR extending in the Z direction represents the boundary of the eighth semiconductor region 70. The dashed line DL diagrammatically represents a depletion layer in the N-type semiconductor region 6 in a thermal equilibrium state.

[0046] As shown in FIG. 5, a semiconductor region 70 of a second conductivity type having a junction depth deeper than that of the P anode region 12 of the diode portion 20 is provided between the first end 15EG in the extended Y direction of the trench 15 in the boundary region 30 and the second end 16EG in the extended Y direction of the trench 16 in the diode portion 20. The first end 15EG in the extended Y direction of the trench 15 in the boundary region 30 is disposed in the connection trench 15C1, and the second end 16EG in the extended Y direction of the trench 16 in the diode portion 20 is disposed in the connection trench 16C2. As shown in FIG. 5, by providing the semiconductor region 70, it can be seen that the entry of the depletion layer in the Z direction is reduced in a region where no trench is formed between the longitudinal direction of the trench 15 and the longitudinal direction of the trench 16.

[0047] FIG. 6 is a cross-sectional view taken along line IV-IV of FIG. 1. In FIG. 6, a cross-sectional structure in a range straddling the diode portion 20, the boundary region 30, and the IGBT portion 10 is shown. That is, a cross-sectional structure along the YZ plane in a range along the anode region 12, the semiconductor region 70, and the P base regions 7 and 7D is shown. The broken line DL schematically shows the depletion layer in the thermal equilibrium state in which the depletion layer spreads in the N-type semiconductor region 6. As shown in FIG. 6, by providing the semiconductor region 70, it can be seen that the entry of the depletion layer in the Z direction is reduced in a region (7D, 12) sandwiched between the connection trench 15C1 and the connection trench 16C2.

[0048] The impurity concentration NP(70) of the semiconductor region 70 is lower than the impurity concentration NP(7) of the base region 7. That is, NP(70) < NP(7) holds. Further, the impurity concentration NP(70) of the semiconductor region 70 is lower than the impurity concentration NP(12) of the anode region 12. That is, NP(70) < NP(12) holds.

[0049] Also, as shown in FIG. 6, the junction depth Z4 of the semiconductor region 70 is deeper than the junction depth Z3 of the anode region 12.

[0050] 5, the junction depth Z4 of the eighth semiconductor region 70 is shallower than the depth ZT1 of the trench 15 of the dummy region 30. Since the depth of the trench 14 of the IGBT section 10 is equal to the depth ZT1 of the trench 15 of the dummy region 30, the junction depth Z4 of the eighth semiconductor region 70 is shallower than the depth of the trench 14 of the IGBT section 10.

[0051] Furthermore, the junction depth Z 4 of the eighth semiconductor region 70 is shallower than the depth ZT 2 of the trench 16 in the diode portion 20 .

[0052] In the semiconductor device 100 according to the first embodiment, the diode section 20 is formed in an island shape, and the IGBT section 10 is formed around the diode section 20. Note that a portion of the dummy section 30 extending from the IGBT section 10 and having the trench 15 is continuous with the trench 14, so in the following description, it may be described as the trench 14 of the IGBT section (including the dummy section) 10. The trench 15 of the dummy section 30 does not have an emitter region 8, but the trench 14 of the IGBT section 10 has an emitter region 8.

[0053] The longitudinal direction of the trench 14 of the IGBT section (including the dummy section) 10 in which the trench electrode 14a is embedded with an insulating film 14b sandwiched therebetween and the longitudinal direction of the trench 16 of the diode section 20 in which the trench electrode 16a having the same potential as the emitter electrode 11 is embedded with an insulating film 16b sandwiched therebetween are formed in the same Y direction, but the two trenches are spaced apart from each other. It is desirable that the trench 16 of the diode section 20 is disposed on an extension line of the longitudinal direction of the trench 14 of the IGBT section (including the dummy section) 10. This can alleviate the electric field concentration in the boundary region 30 in a plan view, and make the depletion layer spread more gently.

[0054] In addition, it is desirable that the distance Y1 between the first end 15EG in the longitudinal direction of the trench 15 on the extension line of the trench 14 of the IGBT section 10 and the second end 16EG in the longitudinal direction of the trench 16 of the diode section 20 is the same as or less than the distance X1 (trench spacing of the dummy section 30) between adjacent trenches in the short direction (X direction) of the trench 15 on the extension line of the trench 14 of the same IGBT section 10.

[0055] A P-type semiconductor region (FLR region: eighth semiconductor region 70) having a lower impurity concentration than the P base region 7 of the IGBT section 10 is formed on the N-type drift region 5 in the boundary region 30 extending from the first longitudinal end 15EG of the trench 15 on the extension line of the trench 14 of the IGBT section 10 to the second longitudinal end 16EG of the trench 16 of the diode section 20.

[0056] This reduces the intrusion of the depletion layer in the Z direction in the accumulation region 6 below the base region 7D extending from the first longitudinal end 15EG of the trench 15 to the second longitudinal end 16EG of the trench 16. This makes it possible to make the depletion layer in the semiconductor region including the eighth semiconductor region 70 in the boundary region 30 sandwiched between the first longitudinal end 15EG of the trench 15 on the extension line of the trench 14 of the IGBT section (including the dummy section) 10 and the second longitudinal end 16EG of the trench 16 of the diode section 20 more likely to spread.

[0057] Moreover, it is desirable that the P-type eighth semiconductor region 70 having a low impurity concentration in the boundary region 30 has a deeper junction depth than the base region 7 of the IGBT section 10 and a deeper junction depth than the anode region 12 of the diode section 20. However, the junction depth of the eighth semiconductor region 70 does not have to be as deep as the bottoms (trench depths) of the trenches of the IGBT section 10 and the diode section 20. This is because the breakdown point is shifted from the boundary region 30 to the IGBT section 10 side.

[0058] The P-type eighth semiconductor region 70 having a low impurity concentration in the boundary region 30 is formed to extend further inward than the first end 15EG of the trench 15 (in the negative Y direction, which is closer to the IGBT section 10 than the first end 15EG of the trench 15) so as to include the first end 15EG of the trench 15 in the dummy section 30. Similarly, the eighth semiconductor region 70 is formed to extend further inward (in the Y direction) than the second end 16EG of the trench 16 so as to include the second end 16EG of the trench 16 in the diode section 20.

[0059] The first end 15EG of the trench 15 is connected to the first end 15EG of the adjacent trench 15 by the connection trench 15C1. That is, the first end 15EG of the trench 15 is T-shaped. The adjacent intra-trench electrodes 15a in the dummy section 30 are connected through the intra-trench electrodes 15a in the trench 15 and the intra-trench electrodes 15a in the connection trench 15C1. This eliminates the need to form a gate bus line on the semiconductor substrate 101 in the boundary region 30, and the gate bus line does not interfere with the formation of the upper electrode 11 on the semiconductor substrate 101 from the IGBT section 10 to the diode section 20. In addition, since the intra-trench electrodes 15a and 16a extend in the X direction, the electric field distribution in the X direction in the region sandwiched between the connection trench 15C1 and the connection trench 16C2 can be made more uniform.

[0060] As shown in FIG. 2, in the short direction (X direction) of the trench 14 of the IGBT section 10 as viewed from the dashed line FLR (8th semiconductor region 70), a dummy trench 15 in which no emitter region 8 is formed is arranged in parallel to the trench 14 of the IGBT section 10 between the 8th P-type semiconductor region 70 of the boundary region 30 with a low impurity concentration and the emitter region 8 so that the 8th P-type semiconductor region 70 of the boundary region 30 does not contact (reach) the emitter region 8.

[0061] 6, the boundary BL between the P collector region 2 and the N cathode region 3 is formed approximately directly below the boundary region 30 in the Z direction, but the boundary BL between the P collector region 2 and the N cathode region 3 does not have to be formed directly below the boundary region 30, and may be formed shifted. For example, the boundary BL between the P collector region 2 and the N cathode region 3 may be on the diode section 20 side of the boundary region 30. Or, it may be on the IGBT section 10 side.

[0062] The eighth semiconductor region 70 of P type with a low impurity concentration in the boundary region 30 is connected to the upper electrode (emitter electrode) 11 .

[0063] (Resurf structure) FIG. 7 is a cross-sectional view taken along line VV in FIG.

[0064] The semiconductor device 100 according to the first embodiment includes a first resurf region 220 and a second resurf region 230 in the termination region 40. The first resurf region 220 is connected to the P base region 7 to improve the breakdown voltage. The second resurf region 230 is connected to the first resurf region 220 via a depletion layer. A dashed line BLL extending in the Z direction indicates a boundary between the IGBT section 10 and the termination region 40. The lower electrode 1 is connected to the P-type collector region 2 of the IGBT section 10. The lower electrode 1 is also connected to the N-type semiconductor region 33 of the termination region 40. The N-type semiconductor region 33 is at the same potential as the cathode region 3 of the diode section 20. The N-type semiconductor region 33 is at the same potential as the N-type stopper layer 260 of the termination section. The boundary between the P-type collector region 2 of the IGBT section 10 and the N-type semiconductor region 33 is indicated by BL3.

[0065] The semiconductor substrate 101 has an N-type drift region 5 constituting one surface thereof. The multiple RESURF regions 220, 230 are made of P-type semiconductor regions having a lower impurity concentration than the P base region 7, and are formed in the surface region of the drift region 5 so as to surround the IGBT section 10. The RESURF regions 220, 230 are formed simultaneously with the P-type eighth semiconductor region 70 having a low impurity concentration in the boundary region 30, and therefore the junction depth is formed shallower than the trench 14 and deeper than the P base region 7.

[0066] Floating limiting ring diffusion layers 240, 250 are disposed on the further outer periphery of the second RESURF region 230. Furthermore, an N-type stopper layer 260 is disposed at the end portion. The stopper layer 260 is connected to the stopper electrode 130.

[0067] The floating limiting ring diffusion layers 240, 250 are provided to smooth the shape of the depletion layer and to alleviate electric field concentration. The floating limiting ring diffusion layers 240, 250 are formed of a P-type diffusion layer that is equal to or shallower than the resurf regions 220, 230. The impurity concentration of the floating limiting ring diffusion layers 240, 250 is set to be equal to or higher than the impurity concentration of the resurf regions 220, 230.

[0068] The P-type eighth semiconductor region 70 having a low impurity concentration in the boundary region 30 can be formed simultaneously with the first RESURF region 220 and the second RESURF region 230. Therefore, even if the P-type eighth semiconductor region 70 having a low impurity concentration in the boundary region 30 is additionally formed, an increase in the number of steps due to the additional formation can be suppressed.

[0069] The semiconductor device 100 according to the first embodiment is provided with the resurf regions 220 and 230, and thus can easily achieve a high breakdown voltage.

[0070] As shown in FIG. 2, the IGBT section 10 includes a portion where the emitter region 8 is formed and a portion where the emitter region 8 is not formed. The portions where the emitter region 8 is formed and the portions where the emitter region 8 is not formed are alternately and repeatedly formed. The portions where the emitter region 8 is formed and the portions where the emitter region 8 is not formed do not necessarily have to be arranged regularly. Also, as shown in FIGS. 3 to 6, the diode section 20 includes a portion where an N cathode region 3 electrically connected to the lower electrode 1 is provided. The dummy region 30 is disposed between the IGBT section 10 and the diode section 20, and includes a portion where the emitter region 8 is not formed on the upper surface side and where the P collector region 2 is formed on the lower surface side.

[0071] The IGBT section 10, the diode section 20, and the dummy section 30 have trenches 14, 16, and 15 formed therein, respectively, and the trench electrodes 14a, 16a, and 15a are provided therein. The trench electrode 14a of the IGBT section 10 and the trench electrode 15a of the dummy section 30 are electrically connected to the gate pad and are at the gate potential, and the trench electrode 15a in the trench 16 of the diode section 20 is electrically connected to the upper electrode 11. Here, in the structure of the semiconductor device 100 according to the first embodiment, the gate signal of the dummy section 30 becomes high level (the IGBT is turned on). Then, since the trench electrode 15a of the dummy section 30 has a positive charge, the movement of electrons present in the N drift region 5 around the trench electrode 15a to the cathode region 3 is reduced. As a result, compared to a comparative example (hereinafter referred to as the comparative example) in which the trench electrode 15a of the dummy portion 30 is electrically connected to the upper electrode 11, more holes are present in the N drift region 5 of the dummy portion 30, and more holes are present in the N drift region 5 in the semiconductor device 100. This makes it possible to further reduce the snapback phenomenon.

[0072] According to the semiconductor device 100 of the first embodiment, the snapback phenomenon can be suppressed by setting the intra-trench electrode 15a of the trench 15 in the dummy region 30 at the same potential as the intra-trench electrode 14a of the trench 14 in the IGBT section 10. Similarly, the intra-trench electrode 15a connected to the intra-trench electrode 14a of the IGBT section 10 is provided in the connection trench 15C1 in the dummy region 30, so that the movement of electrons present in the N drift region 5 around the connection trench 15C1 to the cathode region 3 is reduced. As a result, more holes are present in the N drift region 5 around the connection trench 15C1 in the dummy section 30 than in the comparative example, and the snapback phenomenon can be further reduced.

[0073] (Device simulation results of snapback operation) Fig. 8A shows a simulation result of the electromagnetic field distribution in the middle of the snapback operation in the dummy portion 30 in the semiconductor device 100 according to the first embodiment. Also, Fig. 8B shows a simulation result of the electromagnetic field distribution in the later stage of the snapback operation in the dummy portion 30 in the semiconductor device 100 according to the first embodiment.

[0074] 9A shows a simulation result of the electromagnetic field distribution in the middle of the snapback operation in the dummy portion 30 in the semiconductor device according to the comparative example. FIG 9B shows a simulation result of the electromagnetic field distribution in the later stage of the snapback operation in the dummy portion 30 in the semiconductor device according to the comparative example.

[0075] 8A, 8B, 9A, and 9B, the portion indicated by G indicates a portion that has the same potential as the intra-trench electrode 14a of the trench 14 in the IGBT section 10. Also, the portion indicated by E indicates a portion that has the same potential as the emitter electrode 11.

[0076] In the structure of the semiconductor device 100 according to the first embodiment, as shown in FIG. 8A and FIG. 8B, holes are diffused and present around the trench 15 in the dummy region 30, and conductivity modulation is promoted. This promotes the start of the IGBT mode and has the effect of suppressing the snapback phenomenon. The spread of holes is due to the positive potential applied to the trench electrode 15a of the dummy portion 30 when the IGBT is turned on. As electrons are attracted to the potential of the trench electrode 15a, the potential under the dummy region 30 drops, promoting the injection of holes from the collector region. As a result, holes are present around the trench 15 in the dummy region 30.

[0077] In the structure of the comparative example, it can be seen that no holes exist around the trench 15 in the dummy region 30, and the conductivity modulation is reduced. This causes the snapback phenomenon to occur significantly. In the structure of the comparative example, the intra-trench electrode 15a in the dummy region 30 has an equal potential to the emitter, so that electrons in the drift region 5 move relatively easily to the cathode region 3. Therefore, in the structure of the comparative example, the potential in the drift region 5 of the dummy region 30 does not decrease, and the injection of holes from the collector region 2 is also reduced compared to the first embodiment.

[0078] (Modification) 10 is a cross-sectional view of a semiconductor device 103 according to a modification of the first embodiment, corresponding to FIG. 3. In the semiconductor device 103 according to the modification of the first embodiment, the P base region 7D in the boundary region 30 may be connected to the upper electrode (emitter electrode) 11 via a resistor R. The P base region 7 of the IGBT section 10 close to the boundary region 30 may also be connected to the upper electrode (emitter electrode) 11 via a resistor R. The P anode region 12 of the diode section 20 close to the boundary region 30 may also be connected to the upper electrode (emitter electrode) 11 via a resistor R.

[0079] The P-type eighth semiconductor region 70 having a low impurity concentration in the boundary region 30 may be connected via a resistor to the upper electrode (emitter electrode) 11. For example, since the P-type eighth semiconductor region 70 has a low impurity concentration and is connected to the upper electrode 11 with a relatively large contact resistance, the amount of holes injected from the P-type eighth semiconductor region 70 in the boundary region 30 to the N-type drift region 5 when the diode section 20 is on can be reduced, thereby shortening the reverse recovery time of the diode section 20.

[0080] (emitter contact structure) FIG. 11 is a top view of a portion of the semiconductor device according to the first embodiment.

[0081] In the IGBT section 10, the P base region 7 extends in the Y direction, sandwiched between trenches 14 extending in the Y direction. An n emitter region 8 is disposed above the P base region 7 in the Z direction in contact with the trenches 14. A hole is formed between adjacent trenches 14, and a P-type emitter contact region 9E is disposed below the bottom of the hole and above the P base region 7 in the Z direction. The P-type emitter contact region 9E extends in the Y direction over the P base region 7 sandwiched between the trenches 14. The n emitter region 8 exposed on the side surface of the hole and the emitter contact region 9E at the bottom of the hole are connected to an emitter electrode (upper electrode) 11 embedded in the hole.

[0082] A structure is formed consisting of an n-emitter region 8 / base region 7 / n-emitter region 8 exposed on the side surface of the hole in the Y direction where the P-type emitter contact region 9E is formed. The structure is arranged on the ZY plane of the hole. The n-emitter regions 8 do not necessarily need to be arranged with regularity in the Y direction. By arranging the n-emitter regions 8 intermittently in the IGBT section 10, excessive electron injection can be suppressed and the switching time can be shortened.

[0083] (Second embodiment) FIG. 12 is a top view of the overall structure of a semiconductor device 104 according to the second embodiment.

[0084] As shown in FIG. 12, the semiconductor device 104 according to the second embodiment includes a semiconductor substrate 101, a diode section 20 extending in the X direction on the semiconductor substrate 101 and arranged in a stripe pattern, and an IGBT section 10 arranged adjacent to the diode section 20 in the plus-minus Y direction on the semiconductor substrate 101. The semiconductor device 104 according to the second embodiment also constitutes an RC-IGBT in which the IGBT section 10 and the freewheeling diode section 20 are formed on one semiconductor substrate 101, as in the first embodiment. A region for improving breakdown voltage, called a resurf region, is provided in a termination region 40 on the periphery of the semiconductor device 104. The IGBT section 10 extends in the X direction adjacent to the diode section 20 extending in the X direction on the semiconductor substrate 101 and arranged in a stripe pattern in the plus-minus Y direction, and is arranged in a stripe pattern. A boundary region (dummy region) 30 is provided between the diode section 20 and the IGBT section 10. In the example shown in FIG. 12, a control pad section 500 is also provided on the semiconductor substrate 101. 12, an emitter pad 51 is provided on the IGBT section 10 and / or the diode section 20. The control pad section 500 includes a current sense pad 50, a gate pad 52, and temperature sense pads 53 and .

[0085] Fig. 13 is an enlarged top view of a part of the semiconductor device 105 in Fig. 12. Fig. 13 shows an arrangement of a diode section 20, a boundary region (dummy section) 30 arranged adjacent to the diode section 20 in the negative Y direction, and an IGBT section 10 arranged adjacent to the boundary region 30 in the negative Y direction.

[0086] The semiconductor device 104 according to the second embodiment differs from the semiconductor device 100 according to the first embodiment only in that the IGBT section 10, the diode section 20, and the dummy section 30 are arranged in a striped pattern. The other configurations are the same as those of the first embodiment and its modified example. Therefore, a duplicated description will be omitted.

[0087] In the second embodiment as well, a semiconductor device in which the snapback phenomenon is suppressed can be provided, similarly to the first embodiment.

[0088] (Other embodiments) As described above, the present invention has been described by the embodiments, but the descriptions and drawings forming a part of this disclosure should not be understood as limiting the present invention. From this disclosure, various alternative embodiments, examples, and operation techniques will become apparent to those skilled in the art. As such, the present invention naturally includes various embodiments not described here. Therefore, the technical scope of the present invention is defined only by the invention-specifying matters related to the scope of the claims appropriate from the above description. For example, although an example has been shown in which the trenches 14, 15, and 16 do not penetrate the accumulation region 6, at least one trench may penetrate the accumulation region 6, or the accumulation region 6 may not be provided in any one of the IGBT section 10, the diode section 20, and the dummy section 30. [Explanation of symbols]

[0089] 1...Lower electrode (collector electrode, cathode electrode) 2…Collector region 3…Cathode area 4...Buffer area 5…Drift area 6…Storage area 7, 7D…base area 8…Emitter area 9A…Anode contact area 9D…Dummy contact area 9E…Emitter contact area 10...First semiconductor element (IGBT section) 11...Upper electrode (emitter electrode) 12...Anode region 13...Interlayer insulation layer 14…First trench 14a, 15a, 16a...Trench electrodes 14b, 15b, 16b...insulating film 15...Third trench (dummy trench) 15C1, 16C2…Connection trench 15EG…1st end 15FG…point 16…Second trench 16EG…2nd end 16FG…point 17EG…3rd end 20...Second semiconductor element (diode portion) 30...Boundary area (dummy part) 33...N-type semiconductor region 40…Terminal area 51, 52, 53, 54…Pads 70…8th semiconductor region 100, 102, 103, 104, 105...Semiconductor device 101...Semiconductor substrate 120...Cell electrode 130...Stopper electrode 210...Cell semiconductor region 220, 230...Resurf area 240, 250...Floating limiting ring diffusion layer 260…Stopper layer 500…Control pad section

Claims

1. a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided on the first semiconductor region 5; a third semiconductor region of the first conductivity type provided on the second semiconductor region; A first trench provided so as to penetrate the second semiconductor region in a depth direction; a first trench electrode provided in the first trench via a first insulating film; a fourth semiconductor region of a second conductivity type provided below the first semiconductor region and on an opposite side facing the second semiconductor region; an upper electrode electrically connected to the third semiconductor region; a lower electrode electrically connected to the fourth semiconductor region; A first semiconductor element having a fifth semiconductor region of a second conductivity type electrically connected to the upper electrode and provided on the first semiconductor region; a sixth semiconductor region of the first conductivity type provided below the first semiconductor region, electrically connected to the lower electrode, and on the opposite side facing the fifth semiconductor region; A second trench provided so as to penetrate the fifth semiconductor region in a depth direction; a second trench electrode provided in the second trench via a second insulating film; A second semiconductor element having a seventh semiconductor region of a second conductivity type provided on the first semiconductor region between the first semiconductor element and the second semiconductor element; a third trench provided to penetrate the seventh semiconductor region in a depth direction; a third trench electrode electrically connected to the first trench electrode through a third insulating film; A dummy region having A semiconductor device comprising:

2. The third semiconductor region is not provided on the seventh semiconductor region, The semiconductor device according to claim 1 , further comprising: the fourth semiconductor region below the first semiconductor region and on an opposite side facing the seventh semiconductor region.

3. The first trench is connected to the third trench provided in a first direction in which the first trench extends, The semiconductor device according to claim 1 , wherein the first trench electrode and the third trench electrode are connected to each other within the trench.

4. 4. The semiconductor device according to claim 1, wherein, in a plan view, the direction in which the second semiconductor element is arranged from the first semiconductor element is not parallel to the direction in which the third trench electrode provided between the first semiconductor element and the second semiconductor element extends.

5. the dummy region is provided so as to surround the second semiconductor element in a plan view; The semiconductor device according to claim 4 , wherein a region of said first semiconductor element is provided so as to surround a periphery of said dummy region.

6. On a side of the second semiconductor element to which the third trench extends, adjacent third trenches are connected via a connection trench; 4. The semiconductor device according to claim 3, wherein the third trench electrode is formed in the connection trench with the third insulating film interposed therebetween.

7. the second trench extends in a first direction; an eighth semiconductor region of a second conductivity type provided on the first semiconductor region between the first direction of the second trench and the first direction of the third trench; 4. The semiconductor device according to claim 3, wherein a distance in the first direction between the eighth semiconductor region and the third semiconductor region is longer than a distance in a second direction perpendicular to the first direction between the eighth semiconductor region and the third semiconductor region.

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