Semiconductor device

Abstract

To efficiently supply a power supply voltage or a ground voltage to a semiconductor device even in a semiconductor device in which pads to which bumps are connected are arranged at narrow intervals.SOLUTION: A semiconductor device includes a first pad, a first wiring connected to the first pad in a first direction in a planar view, a second wiring connected to the first pad in a second direction different from the first direction in a planar view, a second pad, a third wiring connected to the second pad in the first direction in a planar view, and a fourth wiring connected to the second pad in the second direction in a planar view. The second wiring is located between the third wiring and the first pad in the second direction, and the fourth wiring is located between the first wiring and the second pad in the second direction.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] In a semiconductor device, for example, terminals such as bumps for supplying a power supply voltage or a ground voltage from the outside may be arranged at positions overlapping with an input / output circuit, and power supply wiring for supplying the power supply voltage or the ground voltage into the semiconductor device may be arranged across multiple layers. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2009-164195 A [Patent Document 2] JP2012-234931A [Patent Document 3] International Publication No. 2016 / 063458 [Patent Document 4] U.S. Patent No. 10,186,504 [Patent Document 5] U.S. Patent No. 7,554,133 [Patent Document 6] U.S. Pat. No. 8,549,447 [Patent Document 7] U.S. Patent No. 8,013,362 Summary of the Invention [Problem to be solved by the invention]

[0004] Recently, with the miniaturization of element structures in semiconductor devices, the spacing between bumps tends to become narrower, and the space for arranging power supply wiring tends to become smaller. If this results in a decrease in the number of power supply wirings, it may become difficult to efficiently supply a power supply voltage or a ground voltage to the semiconductor device.

[0005] The present invention has been made in consideration of the above points, and has an object to efficiently supply a power supply voltage or a ground voltage within a semiconductor device even in a semiconductor device in which the pads to which bumps are connected are arranged at narrow intervals. [Means for solving the problem]

[0006] In one embodiment of the present invention, a semiconductor device has a first pad, a first wiring connected to the first pad in a first direction in a planar view, a second wiring connected to the first pad in a second direction different from the first direction in a planar view, a second pad, a third wiring connected to the second pad in the first direction in a planar view, and a fourth wiring connected to the second pad in the second direction in a planar view, wherein the second wiring is located between the third wiring and the first pad in the second direction, and the fourth wiring is located between the first wiring and the second pad in the second direction. Effect of the Invention

[0007] According to the disclosed technique, even in a semiconductor device in which the pads to which the bumps are connected are arranged at narrow intervals, a power supply voltage or a ground voltage can be efficiently supplied to the semiconductor device. [Brief description of the drawings]

[0008] [Figure 1] 1 is a diagram illustrating an overview of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 11 is a plan view showing another example of a semiconductor device. [Diagram 3] 2 is a plan view showing an example of a layout of power supply wiring in a circuit region of the semiconductor chip of FIG. 1. [Figure 4] 4 is a cross-sectional view showing an example of a cross section taken along line X1-X1' and a cross section taken along line Y1-Y1' in FIG. [Diagram 5] 1. FIG. 4 is a plan view showing another example of the layout of power supply wiring in the circuit region of the semiconductor chip of FIG. [Figure 6]FIG. 11 is a plan view showing an example of a layout of power supply wiring in a semiconductor device according to a second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, the embodiments will be described with reference to the drawings. In the following, the symbols indicating the power supply voltages are also used as symbols indicating the power supply wiring or power supply terminals to which the power supply voltages are supplied. In the plan views and cross-sectional views, the ratio of the width and thickness of each wiring, the wiring interval, the ratio of the thickness of the wiring layer, and the number of wirings wired at positions overlapping the bumps BMP in plan view are not limited to those shown in the drawings.

[0010] (First embodiment) Fig. 1 shows an overview of a semiconductor device in a first embodiment. For example, as shown in a cross-sectional view, the semiconductor device SEM shown in Fig. 1 has a wiring substrate WSUB provided with external connection terminals EXT, and a semiconductor chip CHIP1 connected to the wiring substrate WSUB via bumps BMP. The semiconductor chip CHIP1 is connected to a first surface of the wiring substrate WSUB via the bumps BMP. The external connection terminals EXT are provided on a second surface, which is the surface opposite to the first surface.

[0011] The semiconductor chip CHIP1 has a semiconductor substrate SUB on which elements such as transistors (not shown) are formed, and a multilayer wiring layer MWL provided on the bump BMP side of the semiconductor substrate SUB. As shown in the plan view, the semiconductor chip CHIP1 has a circuit area CA. The circuit area CA has a plurality of power supply wirings PW that supply a power supply voltage and a ground voltage to elements such as transistors provided in the circuit area CA. Each power supply wiring PW is electrically connected to a bump BMP to which the power supply voltage and the ground voltage are supplied.

[0012] Fig. 2 shows another example of a semiconductor device. The semiconductor chip CHIP2 shown in Fig. 2 has input / output cells IOC provided on the periphery of the chip, and a plurality of power supply wirings PW for supplying a power supply voltage VDD and a ground voltage VSS to the input / output cells IOC. The power supply voltage VDD is an example of a first power supply voltage, and the ground voltage VSS is an example of a second power supply voltage.

[0013] The semiconductor chip CHIP2 also has bumps BMP to which a power supply voltage VDD or a ground voltage VSS is supplied from outside the semiconductor chip CHIP2, for example, at positions overlapping with the regions in which the input / output cells IOC are provided in a plan view. The bumps BMP to which the power supply voltage VDD is supplied are connected to the power supply wiring VDD of the power supply wiring PW. The bumps BMP to which the ground voltage VSS is supplied are connected to the ground wiring VSS of the power supply wiring PW. The semiconductor chip CHIP2 may have a semiconductor substrate on which elements such as transistors (not shown) are formed, and a multi-layer wiring layer provided on the bump BMP side of the semiconductor substrate, similar to the semiconductor chip CHIP1 in FIG. 1.

[0014] Fig. 3 shows an example of the layout of power wiring in the circuit area CA of the semiconductor chip CHIP1 in Fig. 1. As shown in Fig. 1, bumps BMP are arranged in a staggered pattern in the circuit area CA. Note that Fig. 3 and subsequent figures show an example of the layout of power wiring of the semiconductor chip CHIP1 in Fig. 1, but the layout technique shown in Fig. 3 and subsequent figures may be applied to the layout of power wiring of the semiconductor chip CHIP2 in Fig. 2.

[0015] The semiconductor chip CHIP1 has power supply pads VDDPAD, VSSPAD and power supply wirings VDDa, VDDb, VDDc, VSSa, VSSb, and VSSc provided in a pad layer PADL arranged on the bump BMP side in the Z direction, which is the thickness direction of the chip. The power supply pad VDDPAD is an example of a first pad. The power supply pad VSSPAD is an example of a second pad. The power supply wiring VDDa is an example of a first wiring, the power supply wiring VDDb is an example of a second wiring, and the power supply wiring VDDc is an example of a fifth wiring. The power supply wiring VSSa is an example of a third wiring, the power supply wiring VSSb is an example of a fourth wiring, and the power supply wiring VSSc is an example of a sixth wiring.

[0016] The power supply pad VDDPAD is provided at a position overlapping in a plan view with a bump BMP (not shown) to which a power supply voltage VDD is supplied, and is connected to the bump BMP to which the power supply voltage VDD is supplied. The power supply pad VSSPAD is provided at a position overlapping in a plan view with a bump BMP (not shown) to which a ground voltage VSS is supplied, and is connected to the bump BMP to which the ground voltage VSS is supplied. The power supply pad VDDPAD and the power supply pad VSSPAD are provided in a staggered manner in a plan view, and are arranged at positions shifted from each other in the X direction and the Y direction. The bump BMP connected to the power supply pad VDDPAD is an example of a first bump, and the bump BMP connected to the power supply pad VSSPAD is an example of a second bump.

[0017] The semiconductor chip CHIP1 also has power supply wirings VDD and VSS provided in the multi-layer wiring layer MWL located on the opposite side of the pad layer PADL to the bump BMP. The pad layer PADL is an example of a first wiring layer, and the multi-layer wiring layer MWL is an example of a second wiring layer different from the pad layer PADL. The power supply wirings VDD and VSS correspond to the power supply wiring PW in FIG. 1. The power supply wirings VDD and VSS extend in the Y direction and are alternately arranged at intervals in the X direction.

[0018] The power supply wiring VDD is an example of a seventh wiring, and the power supply wiring VSS is an example of an eighth wiring. The X direction is an example of a first direction, and the Y direction is an example of a second direction different from the X direction. The arrangement interval of the power supply pads VDDPAD and VSSPAD and the width and interval of the power supply wirings VDDa, VDDb, VSSa, and VSSb are not limited to the example shown in Figure 3. In addition, the number of power supply wirings VDD and VSS arranged at positions overlapping with the power supply pads VDDPAD and VSSPAD in a plan view is not limited to the example shown in Figure 3.

[0019] For example, the power supply pads VDDPAD and VSSPAD and the power supply wirings VDDa, VDDb, VDDc, VSSa, VSSb, and VSSc are simultaneously formed by a semiconductor process for forming wirings in the pad layer PADL. For example, the power supply wirings VDD and VSS are simultaneously formed by a semiconductor process for forming wirings in the multilayer wiring layer MWL.

[0020] The power supply wiring VDDa is arranged along the X direction at a position crossing the power supply pad VDDPAD in a plan view, and is connected to the power supply pad VDDPAD. The power supply wiring VDDb is arranged along the X direction on both sides of the power supply pad VDDPAD in the Y direction in a plan view, and is adjacent to the power supply wiring VSSa at a predetermined interval in the Y direction. The power supply wiring VDDc is arranged on both sides of the power supply pad VDDPAD in the Y direction in a plan view, is provided between the power supply pad VDDPAD and the power supply wiring VDDb, and connects the power supply wiring VDDb to the power supply pad VDDPAD.

[0021] The width of the power supply wiring VDDb in the Y direction and the width of the power supply wiring VDDc in the X direction are set to be equal to or less than the upper limit of the width of the power supply wiring in the layout rule. Therefore, the power supply wiring VDDb, which is wider in the X direction, can be connected to the power supply pad VDDPAD without violating the layout rule. Each of the power supply wirings VDDa and VDDb is connected to the power supply wiring VDD of the multi-layer wiring layer MWL through a plurality of vias VIA. The vias VIA that connect the power supply wirings VDDa and VDDb to the power supply wiring VDD are an example of a first via.

[0022] The power supply wiring VSSa is arranged along the X direction at a position crossing the power supply pad VSSPAD in a plan view, and is connected to the power supply pad VSSPAD. The power supply wiring VSSb is arranged along the X direction on both sides of the power supply pad VSSPAD in the Y direction in a plan view, and is adjacent to the power supply wiring VDDa at a predetermined interval in the Y direction. The power supply wiring VSSc is arranged on both sides of the power supply pad VSSPAD in the Y direction in a plan view, is provided between the power supply pad VSSPAD and the power supply wiring VSSb, and connects the power supply wiring VSSb to the power supply pad VSSPAD.

[0023] The width of the power supply wiring VSSb in the Y direction and the width of the power supply wiring VSSc in the X direction are set to be equal to or less than the upper limit of the width of the power supply wiring in the layout rule. Therefore, the power supply wiring VSSb, which is wide in the X direction, can be connected to the power supply pad VSSPAD without violating the layout rule. Each of the power supply wirings VSSa and VSSb is connected to the power supply wiring VSS of the multi-layer wiring layer MWL through a plurality of vias VIA. The vias VIA that connect the power supply wirings VSSa and VSSb to the power supply wiring VSS are an example of a second via.

[0024] The power supply wiring VDDb is disposed in a position overlapping with the power supply pad VSSPAD and the power supply wirings VSSb and VSSc when extended in the X direction. That is, a part of the position of the power supply wiring VDDb in the Y direction coincides with the position of the power supply wiring VSSb in the Y direction, and another part of the position of the power supply wiring VDDb in the Y direction coincides with the position of the power supply pad VSSPAD in the Y direction.

[0025] The power supply wiring VSSb is disposed in a position where it overlaps with the power supply pad VDDPAD and the power supply wirings VDDb and VDDc when extended in the X direction. That is, a part of the position of the power supply wiring VSSb in the Y direction coincides with the position of the power supply wiring VDDb in the Y direction, and another part of the position of the power supply wiring VSSb in the Y direction coincides with the position of the power supply pad VDDPAD in the Y direction.

[0026] Also, the distance W0 between the power supply pads VDDPAD and VSSPAD in the Y direction is narrower than the width WVDDb of the power supply wiring VDDb in the Y direction and the width WVSSb of the power supply wiring VSSb in the Y direction. However, in this embodiment, the power supply wiring VDDb is arranged in the gap between the power supply pad VDDPAD and the power supply wiring VSSa, and the power supply wiring VSSb is arranged in the gap between the power supply pad VSSPAD and the power supply wiring VDDa.

[0027] This allows the power supply wirings VDDb, VSSb having widths WVDDb, WVSSb larger than the interval W0 between the power supply pads VDDPAD, VSSPAD to be efficiently arranged in a vacant area where the power supply pads VDDPAD, VSSPAD and the power supply wirings VDDa, VSSa are not arranged.

[0028] Therefore, the power supply voltage VDD supplied from each bump BMP to the power supply pad VDDPAD can be efficiently distributed to the power supply wiring VDD of the multilayer wiring layer MWL via the power supply wirings VDDa, VDDb of the pad layer PADL. Similarly, the ground voltage VSS supplied from each bump BMP to the power supply pad VSSPAD can be efficiently distributed to the power supply wiring VSS of the multilayer wiring layer MWL via the power supply wirings VSSa, VSSb of the pad layer PADL. In other words, when the bumps BMP are arranged in a staggered pattern, the power supply resistance of the path for supplying the power supply voltage VDD and the ground voltage VSS to the power supply wirings VDD, VSS of the multilayer wiring layer MWL from each bump BMP can be reduced.

[0029] On the other hand, for example, when connecting an auxiliary power supply wiring extending in the X direction to the power supply wiring VDDc and connecting an auxiliary power supply wiring extending in the X direction to the power supply wiring VSSc, the width of each of the auxiliary power supply wirings becomes narrower or the wiring itself becomes difficult. Even if the auxiliary power supply wiring can be wired, the size of the vias VIA connecting each of the auxiliary power supply wirings to the power supply wirings VDD, VSS of the multilayer wiring layer MWL becomes smaller.

[0030] In this case, the power supply voltages VDD and VSS supplied from each bump BMP cannot be efficiently distributed to the power supply wirings VDD and VSS of the multi-layer wiring layer MWL, making it difficult to reduce the power supply resistance from each bump BMP to the power supply wirings VDD and VSS. Recently, the arrangement pitch of the bump BMP has tended to become smaller due to the miniaturization of semiconductor processes, and the space between the power supply wirings VDDa and VSSa has tended to become smaller. For this reason, it is becoming increasingly difficult to reduce the power supply resistance.

[0031] FIG. 4 shows examples of cross sections taken along lines X1-X1' and Y1-Y1' in FIG. 3. The cross section shown in FIG. 4 is obtained by inverting the cross section of the semiconductor chip CHIP1 in FIG. 1 upside down. Elements such as transistors formed on the semiconductor substrate SUB are omitted in FIG. The semiconductor chip CHIP1 has a multilayer wiring layer MWL, a pad layer PADL, and an insulating film INS1, which are provided in this order on the semiconductor substrate SUB. The bump BMP is connected to a power supply pad VDDPAD exposed in an opening OPEN of the insulating film INS1. The insulating film INS1 may be a laminate of multiple insulating films.

[0032] In the cross section along the X1-X1' line, a via VIA connected to a power supply wiring VDDa provided in the pad layer PADL, a power supply wiring VDD connected to the via VIA, and a power supply wiring VSS are formed in the insulating film INS2 on the pad layer PADL side in the multilayer wiring layer MWL. In addition to power supply wiring, signal wiring may be formed in the multilayer wiring layer MWL. In addition, in the multilayer wiring layer MWL, not only wiring but also elements such as transistors may be formed in a region on the semiconductor substrate SUB side of the insulating film INS2. In addition, the insulating film INS2 may be formed by stacking a plurality of insulating films.

[0033] In the cross section along the line Y1-Y1', a via VIA connected to a power supply wiring VSSa provided in the pad layer PADL and a power supply wiring VSS connected to the via VIA are formed in the insulating film INS2 on the pad layer PADL side in the multilayer wiring layer MWL. The power supply wiring VSSa is disposed between two power supply wirings VDDb connected to two bumps BMP(VDD) via power supply wirings VDDa and VDDc, respectively.

[0034] Fig. 5 shows another example of the layout of power supply wiring in the circuit area CA of the semiconductor chip CHIP1 of Fig. 1. Detailed description of the layout that is the same as or similar to that of Fig. 3 will be omitted. The layout shown in Fig. 5 is similar to the layout of Fig. 3, except that the number of vias VIA connected to the power supply wiring VDDa, VDDb differs between near and far from the power supply pad VDDPAD in the X direction, and the number of vias VIA connected to the power supply wiring VSSa, VSSb differs between near and far from the power supply pad VSSPAD in the X direction.

[0035] The number of vias connecting the power wiring VDDa, VDDb to the power wiring VDD increases as the wiring is farther away from the power pad VDDPAD in the X direction. The number of vias connecting the power wiring VSSa, VSSb to the power wiring VSS increases as the wiring is farther away from the power pad VSSPAD in the X direction. Therefore, the layout density of the power wiring VDD increases as the wiring is farther away from the power pad VDDPAD in the X direction, and the layout density of the power wiring VSS increases as the wiring is farther away from the power pad VSSPAD in the X direction.

[0036] This makes it possible to suppress the difference between the supply capability of the power supply voltage VDD to the power supply wiring VDD arranged away from the power supply pad VDDPAD in the X direction in a plan view and the supply capability of the power supply voltage VDD to the power supply wiring VDD arranged close to the power supply pad VDDPAD in the X direction. Similarly, it is possible to suppress the difference between the supply capability of the ground voltage VSS to the power supply wiring VSS arranged away from the power supply pad VSSPAD in the X direction in a plan view and the supply capability of the ground voltage VSS to the power supply wiring VSS arranged close to the power supply pad VSSPAD in the X direction.

[0037] Since a uniform power supply voltage VDD can be supplied to each power supply wiring VDD and a uniform ground voltage VSS can be supplied to each power supply wiring VSS, the difference in electrical characteristics (performance) of the circuit formed in the semiconductor chip CHIP1 due to the positions of the power supply pads VDDPAD and VSSPAD can be suppressed. For example, the performance of the semiconductor device SEM is determined according to the circuit with the lowest performance. In this embodiment, the deterioration of the circuit performance can be suppressed, so that the performance of the semiconductor device SEM can be improved and the yield of the semiconductor device SEM can be improved.

[0038] As described above, in the first embodiment, the power supply voltage VDD supplied from each bump BMP to the power supply pad VDDPAD can be efficiently distributed to the power supply wiring VDD of the multilayer wiring layer MWL via the power supply wirings VDDa and VDDb of the pad layer PADL. Similarly, the ground voltage VSS supplied from each bump BMP to the power supply pad VSSPAD can be efficiently distributed to the power supply wiring VSS of the multilayer wiring layer MWL via the power supply wirings VSSa and VSSb of the pad layer PADL. That is, when the bumps BMP are arranged in a staggered pattern, the power supply resistance of the path for supplying the power supply voltage VDD and the ground voltage VSS to the power supply wirings VDD and VSS of the multilayer wiring layer MWL from each bump BMP can be reduced.

[0039] The power supply wiring VDDb is arranged between the power supply pad VDDPAD and the power supply wiring VSSa, and the power supply wiring VSSb is arranged between the power supply pad VSSPAD and the power supply wiring VDDa. This makes it possible to efficiently arrange the power supply wirings VDDb and VSSb having widths WVDDb and WVSSb larger than the interval W0 between the power supply pads VDDPAD and VSSPAD in a vacant area where the power supply pads VDDPAD and VSSPAD and the power supply wirings VDDa and VSSa are not arranged.

[0040] By setting the width of the power supply wiring VDDc in the X direction to be equal to or less than the upper limit of the width of the power supply wiring in the layout rule, the power supply wiring VDDb, which is wider in the X direction, can be connected to the power supply pad VDDPAD. Similarly, by setting the width of the power supply wiring VSSc in the X direction to be equal to or less than the upper limit of the width of the power supply wiring in the layout rule, the power supply wiring VSSb, which is wider in the X direction, can be connected to the power supply pad VSSPAD.

[0041] A part of the position of the power supply wiring VDDb in the Y direction coincides with the position of the power supply wiring VSSb in the Y direction, and another part of the position of the power supply wiring VDDb in the Y direction coincides with the position of the power supply pad VSSPAD in the Y direction. This makes it possible to efficiently arrange the power supply wiring VDDb, VSSb in the free area where the staggered power supply pads VDDPAD, VSSPAD and the power supply wiring VDDa, VSSa are not arranged.

[0042] The number of vias connecting the power supply wiring VDDa and VDDb to the power supply wiring VDD increases as they are farther away from the power supply pad VDDPAD in the X direction. The number of vias connecting the power supply wiring VSSa and VSSb to the power supply wiring VSS increases as they are farther away from the power supply pad VSSPAD in the X direction.

[0043] This makes it possible to suppress the difference between the supply capability of the power supply voltage VDD to the power supply wiring VDD arranged away from the power supply pad VDDPAD in the X direction in a plan view and the supply capability of the power supply voltage VDD to the power supply wiring VDD arranged close to the power supply pad VDDPAD in the X direction. Similarly, it is possible to suppress the difference between the supply capability of the ground voltage VSS to the power supply wiring VSS arranged away from the power supply pad VSSPAD in the X direction in a plan view and the supply capability of the ground voltage VSS to the power supply wiring VSS arranged close to the power supply pad VSSPAD in the X direction.

[0044] Since a uniform power supply voltage VDD can be supplied to each power supply wiring VDD and a uniform ground voltage VSS can be supplied to each power supply wiring VSS, the difference in electrical characteristics (performance) of the circuit formed in the semiconductor chip CHIP1 due to the positions of the power supply pads VDDPAD and VSSPAD can be suppressed. For example, the performance of the semiconductor device SEM is determined according to the circuit with the lowest performance. In this embodiment, the deterioration of the circuit performance can be suppressed, so that the performance of the semiconductor device SEM can be improved and the yield of the semiconductor device SEM can be improved.

[0045] Second embodiment Fig. 6 shows an example of the layout of power supply wiring in the semiconductor device of the second embodiment. Detailed description of the layout that is the same as or similar to that of Fig. 3 will be omitted. The layout shown in Fig. 6 is similar to the layout of Fig. 3, except that a power supply wiring VDDd is arranged instead of the power supply wirings VDDb and VDDc, and a power supply wiring VSSd is arranged instead of the power supply wirings VSSb and VSSc.

[0046] The power supply wirings VDDd are provided on both sides of the power supply pad VDDPAD in the Y direction, two at a time, extending in the Y direction, with their tips adjacent to the power supply wiring VSSa at a predetermined interval. The power supply wirings VSSd are provided on both sides of the power supply pad VSSPAD in the Y direction, two at a time, extending in the Y direction, with their tips adjacent to the power supply wiring VDDa at a predetermined interval. The widths of the power supply wirings VDDd and VSSd in the X direction are set to be equal to or less than the upper limit of the width of the power supply wiring in the layout rule.

[0047] By extending the power supply wirings VDDd, VSSd in the Y direction, the Y direction length of the vias VIA connected to the power supply wirings VDDd, VSSd can be made longer than the Y direction length of the vias VIA connected to the power supply wirings VDDb, VSSb in Fig. 3. Therefore, the power supply resistance of the paths that respectively supply the power supply voltage VDD and the ground voltage VSS to the power supply wirings VDD, VSS of the multilayer wiring layer MWL from each bump BMP can be further reduced compared to the layout in Fig. 3.

[0048] As described above, the second embodiment can also provide the same effects as the first embodiment. For example, the power supply voltage VDD supplied from the bump BMP to the power supply pad VDDPAD can be efficiently distributed to the power supply wiring VDD, and the ground voltage VSS supplied from the bump BMP to the power supply pad VSSPAD can be efficiently distributed to the power supply wiring VSS. That is, compared to the case where the power supply wirings VDDb and VSSb are not provided, the power supply resistance of the path for supplying the power supply voltage VDD and the ground voltage VSS to the power supply wirings VDD and VSS of the multilayer wiring layer MWL from each bump BMP can be reduced.

[0049] Furthermore, in the second embodiment, by extending the power supply wirings VDDd, VSSd in the Y direction, the length in the Y direction of the vias VIA connected to the power supply wirings VDDd, VSSd can be made longer than the length in the Y direction of the vias VIA connected to the power supply wirings VDDb, VSSb in Fig. 3. Therefore, the power supply resistance of the paths for respectively supplying the power supply voltage VDD and the ground voltage VSS to the power supply wirings VDD, VSS of the multilayer wiring layer MWL from each bump BMP can be further reduced compared to the layout in Fig. 3.

[0050] Although the present invention has been described above based on the embodiments, the present invention is not limited to the requirements shown in the above embodiments. These points can be changed without departing from the spirit of the present invention, and can be appropriately determined according to the application form. [Explanation of symbols]

[0051] BMP Bump CA circuit area CHIP1, CHIP2 Semiconductor chips EXT External connection terminal INS1, INS2 insulating film IOC Input / Output Cell MWL multilayer wiring layer OPEN opening PADL Pad Layer PW Power supply wiring SEM Semiconductor device SUB Semiconductor Substrate VDD Power supply voltage, power supply wiring VDDa, VDDb, VDDc, VDDd power supply wiring VDDPAD Power Pad VSS Ground voltage, power supply wiring VSSa, VSSb, VSSc, VSSd power wiring VSSPAD Power Pad VIA WSUB Wiring Board

Claims

1. A first pad; a first wiring connected to the first pad in a first direction in a plan view; a second wiring connected to the first pad in a second direction different from the first direction in a plan view; A second pad; a third wiring connected to the second pad in the first direction in a plan view; a fourth wiring connected to the second pad in the second direction in a plan view; having the second wiring is located between the third wiring and the first pad in the second direction; The fourth wiring is located between the first wiring and the second pad in the second direction. Semiconductor device.

2. The second pad is disposed at a position shifted from the first pad in the first direction and the second direction. The semiconductor device according to claim 1 .

3. The distance between the first pad and the second pad in the second direction is narrower than the width of the second wiring in the second direction. The semiconductor device according to claim 1 .

4. The distance between the first pad and the second pad in the second direction is narrower than the width of the fourth wiring in the second direction. The semiconductor device according to claim 3 .

5. a first power supply voltage is supplied to the first pad; A second power supply voltage different from the first power supply voltage is supplied to the second pad. The semiconductor device according to claim 1 .

6. a fifth wiring provided between the first pad and the second wiring and connecting the first pad and the second wiring; a sixth wiring provided between the second pad and the fourth wiring and connecting the second pad and the fourth wiring; having a width of the fifth wiring in the first direction is narrower than a width of the second wiring in the first direction; The width of the sixth wiring in the first direction is narrower than the width of the fourth wiring in the first direction. The semiconductor device according to claim 1 .

7. A portion of the position of the second wiring in the second direction coincides with a position of the fourth wiring in the second direction. The semiconductor device according to claim 1 .

8. a seventh wiring and an eighth wiring provided at intervals in the first direction and extending in the second direction in a second wiring layer different from a first wiring layer in which the first wiring, the second wiring, the third wiring, and the fourth wiring are provided; a first via connecting the first wiring and the second wiring to the seventh wiring; a second via connecting the third wiring and the fourth wiring to the eighth wiring; the number of the first vias connecting the first wiring and the second wiring to the seventh wiring increases as the vias are spaced apart from the first pad in the first direction; The number of the second vias connecting the third wiring and the fourth wiring to the eighth wiring increases as the vias are spaced apart from the second pad in the first direction.

8. The semiconductor device according to claim 1, wherein the first insulating layer is a conductive layer.

9. a plurality of second wirings extending in the second direction on both sides of the first pad in the second direction; The second pad has a plurality of fourth wirings extending in the second direction on both sides of the second pad in the second direction. The semiconductor device according to claim 1 .

10. a first bump connected to the first pad; and a second bump connected to the second pad. The semiconductor device according to claim 1 .

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