Composite substrate including transfer foil with porous silicon carbide layer, power semiconductor device, and manufacturing method

Abstract

To provide a composite substrate including a transfer foil with a porous silicon carbide layer, and a method of manufacturing a power semiconductor device.SOLUTION: A method of manufacturing a silicon carbide device includes forming a transfer foil (110) that includes a porous silicon carbide layer (116). A composite substrate (100) is formed that includes the transfer foil and a support substrate (190). The transfer foil and the support substrate (190) are brought into contact with each other and connected to each other. An epitaxial layer (120) is formed on a side of the porous silicon carbide layer (116) opposite to the support substrate (190). The composite substrate (100) is divided into a device substrate (150) and a reclaim substrate (160). The device substrate includes the epitaxial layer, and the reclaim substrate includes the support substrate.SELECTED DRAWING: Figure 1D

Description

[Technical field]

[0001] Examples of the present disclosure relate to a composite substrate including a transfer foil with a porous silicon carbide layer, a power semiconductor device, and a method of manufacturing the power semiconductor device. The method uses the transfer foil to transfer the porous silicon carbide layer to a support substrate. The composite substrate includes the transfer foil and the support substrate. A power semiconductor device can be obtained from the composite substrate. [Background technology]

[0002] Fabrication of semiconductor wafers generally involves forming a crystal ingot by vertical zone melting or by withdrawing a seed rod from a crucible filled with molten semiconductor material, and slicing the crystal ingot. The typical slicing process destroys a significant portion of the previously produced crystal. An alternative technique obtains an epitaxial semiconductor wafer by forming a thin release layer near the front side of a reusable semiconductor seed wafer, epitaxially growing a semiconductor layer on the front side, and then mechanically cutting the epitaxially grown semiconductor layer from the seed wafer by the release layer. For example, the epitaxially grown semiconductor wafer is cleaved away from the single crystal base substrate along the release layer formed by laser radiation. There is a constant need for a method to provide semiconductor wafers in an economical manner. Summary of the Invention

[0003] An embodiment of the present disclosure relates to a method for manufacturing a silicon carbide device. The method includes forming a transfer foil including a porous silicon carbide layer. A composite substrate is formed including the transfer foil and a support substrate, where the transfer foil and the support substrate are brought into contact with and connected to each other. An epitaxial layer is formed on a side of the porous silicon carbide layer opposite the support substrate. The composite substrate is divided into a device substrate and a reclaim substrate, where the device substrate includes the epitaxial layer and the reclaim substrate includes the support substrate.

[0004] The method decouples the process of providing a suitable epitaxy seed from the actual epitaxy process, simplifying the fabrication of thin silicon carbide substrates for power semiconductor devices. A high-quality source substrate provides the epitaxy seed, and a low-cost support substrate can be used for the epitaxy process. The porous silicon carbide layer first transfers the epitaxy seed to the low-cost support substrate, and then allows efficient separation of the device substrate, in which the electronic elements are formed, from the low-cost support substrate.

[0005] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.

[0006] The accompanying drawings are helpful for a further understanding of the embodiments and are an integral part of the description. The drawings illustrate embodiments of a power semiconductor device, a composite substrate, and a method for manufacturing a semiconductor device, and together with the description, help to explain the embodiments. The following detailed description and claims include further embodiments. [Brief description of the drawings]

[0007] [Figure 1A] 1A-1D are schematic vertical cross-sectional views of a transfer foil, a composite substrate, a device substrate, and a reclaimed substrate at various stages of a semiconductor device manufacturing method, including transferring and horizontally splitting a porous silicon carbide layer, according to one embodiment. [Figure 1B] 1A-1D are schematic vertical cross-sectional views of a transfer foil, a composite substrate, a device substrate, and a reclaimed substrate at various stages of a semiconductor device manufacturing method, including transferring and horizontally splitting a porous silicon carbide layer, according to one embodiment. [Figure 1C] 1A-1D are schematic vertical cross-sectional views of a transfer foil, a composite substrate, a device substrate, and a reclaimed substrate at various stages of a semiconductor device manufacturing method, including transferring and horizontally splitting a porous silicon carbide layer, according to one embodiment. [Figure 1D]1A-1D are schematic vertical cross-sectional views of a transfer foil, a composite substrate, a device substrate, and a reclaimed substrate at various stages of a semiconductor device manufacturing method, including transferring and horizontally splitting a porous silicon carbide layer, according to one embodiment. [Figure 2A] 2A-2D are schematic vertical cross-sectional views of a transfer foil, a composite substrate, a device substrate and a reclaimed substrate at various stages of a semiconductor device manufacturing method, including transferring a porous silicon carbide layer and splitting horizontally, according to one embodiment, involving a transfer foil including an auxiliary layer. [Figure 2B] 2A-2D are schematic vertical cross-sectional views of a transfer foil, a composite substrate, a device substrate and a reclaimed substrate at various stages of a semiconductor device manufacturing method, including transferring a porous silicon carbide layer and splitting horizontally, according to one embodiment, involving a transfer foil including an auxiliary layer. [Figure 2C] 2A-2D are schematic vertical cross-sectional views of a transfer foil, a composite substrate, a device substrate and a reclaimed substrate at various stages of a semiconductor device manufacturing method, including transferring a porous silicon carbide layer and splitting horizontally, according to one embodiment, involving a transfer foil including an auxiliary layer. [Figure 2D] 2A-2D are schematic vertical cross-sectional views of a transfer foil, a composite substrate, a device substrate and a reclaimed substrate at various stages of a semiconductor device manufacturing method, including transferring a porous silicon carbide layer and splitting horizontally, according to one embodiment, involving a transfer foil including an auxiliary layer. [Figure 3A] 3A-3D are schematic vertical cross-sectional views of a composite substrate and a device substrate at various stages of a semiconductor device manufacturing method including transferring and horizontally splitting a porous silicon carbide layer according to one embodiment, which relate to the formation of electronic elements prior to splitting the porous silicon carbide layer. [Figure 3B]3A-3D are schematic vertical cross-sectional views of a composite substrate and a device substrate at various stages of a semiconductor device manufacturing method including transferring and horizontally splitting a porous silicon carbide layer according to one embodiment, which relate to the formation of electronic elements prior to splitting the porous silicon carbide layer. [Figure 3C] 3A-3D are schematic vertical cross-sectional views of a composite substrate and a device substrate at various stages of a semiconductor device manufacturing method including transferring and horizontally splitting a porous silicon carbide layer according to one embodiment, which relate to the formation of electronic elements prior to splitting the porous silicon carbide layer. [Figure 3D] 3A-3D are schematic vertical cross-sectional views of a composite substrate and a device substrate at various stages of a semiconductor device manufacturing method including transferring and horizontally splitting a porous silicon carbide layer according to one embodiment, which relate to the formation of electronic elements prior to splitting the porous silicon carbide layer. [Figure 4A] 4A-4C are schematic vertical cross-sectional views of a source substrate and a transfer foil at various stages of a semiconductor device manufacturing method, including forming a porous silicon carbide layer for a transfer foil on a source substrate, according to one embodiment, including transferring a porous silicon carbide layer and splitting the layer horizontally. [Figure 4B] 4A-4C are schematic vertical cross-sectional views of a source substrate and a transfer foil at various stages of a semiconductor device manufacturing method, including forming a porous silicon carbide layer for a transfer foil on a source substrate, according to one embodiment, including transferring a porous silicon carbide layer and splitting the layer horizontally. [Figure 4C] 4A-4C are schematic vertical cross-sectional views of a source substrate and a transfer foil at various stages of a semiconductor device manufacturing method, including forming a porous silicon carbide layer for a transfer foil on a source substrate, according to one embodiment, including transferring a porous silicon carbide layer and splitting the layer horizontally. [Diagram 5]1 is a schematic vertical cross-sectional view of a composite substrate including a porous silicon carbide layer and a silicon carbide recycled substrate, according to one embodiment, in which the porous silicon carbide layer is bonded directly onto the silicon carbide recycled substrate. FIG. [Figure 6] 1 is a schematic vertical cross-sectional view of a composite substrate including a porous silicon carbide layer and a silicon carbide recycled substrate according to one embodiment, where an interface layer is formed between the porous silicon carbide layer and the silicon carbide recycled substrate. FIG. [Figure 7] FIG. 1 is a schematic vertical cross-sectional view of a silicon carbide power diode having a laterally homogeneously doped porous silicon carbide portion. [Figure 8] FIG. 2 is a schematic vertical cross-sectional view of a silicon carbide power transistor having a laterally homogeneously doped porous silicon carbide portion. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] In the following detailed description, reference is made to the accompanying drawings, which form a part of this application, and in which are shown by way of illustration specific embodiments in which the composite wafer, power semiconductor device, and method of manufacturing the semiconductor device may be practiced. Other embodiments may be utilized, and structural or logical changes may be made, without departing from the concepts of the present disclosure. Features shown or described for one embodiment may be used on or in conjunction with other embodiments to yield yet further embodiments. The present disclosure is intended to include such modifications and variations. Examples are set forth in a manner that should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. Corresponding elements are indicated by the same reference numerals in different drawings unless otherwise noted.

[0009] Terms such as "having," "containing," "including," "comprising," and the like are open-ended in that they indicate the presence of stated structures, elements, or features, but do not exclude the presence of additional elements or features. The articles "a," "an," and "the" are intended to include the plural as well as the singular unless the context clearly indicates otherwise.

[0010] The term "directly electrically connected" refers to a permanent, low resistance ohmic connection between the directly electrically connected elements, e.g., direct contact between the elements involved or a low resistance connection via metal and / or highly doped semiconductor material. The terms "electrically connected" and "signal connected" include a direct electrical connection and further allow for additional electrical elements in the signal or power path between the electrically connected or signal connected elements.

[0011] The term "power semiconductor device" refers to active semiconductor devices, such as diodes and transistors, having a high voltage blocking capability of at least 30V, e.g., 48V, 100V, 600V, 1.6kV, 3.3kV or more, and having a nominal on-state or forward current of at least 200mA, e.g., 1A, 10A or more.

[0012] Ranges given for physical dimensions are inclusive of the boundaries. For example, a range for a parameter y from a to b is understood to mean a≦y≦b. The same is true for ranges with certain boundaries, such as "at most" and "at least."

[0013] The major components of a compound or alloy layer or structure are those elements whose atoms form the compound or alloy.

[0014] The term "on" should not be construed to mean only "directly on." Rather, when an element is disposed "on" another element (e.g., a layer is "on" another layer or "on" a substrate), additional components (e.g., additional layers) may be disposed between the two elements (e.g., when a layer is "on" a substrate, additional layers may be disposed between the layer and the substrate).

[0015] According to one aspect of the present disclosure, a method for manufacturing a semiconductor device may include forming a transfer foil including a porous silicon carbide layer. A composite substrate may be formed that may include the transfer foil and a support substrate, and the transfer foil and the support substrate are brought into contact with each other and connected to each other. An epitaxial layer may be formed on the side of the porous silicon carbide layer opposite the support substrate. The composite substrate is divided into a device substrate and a reclaimed substrate, the device substrate including the epitaxial layer and the reclaimed substrate including the support substrate.

[0016] A transfer foil may have two parallel foil surfaces and a uniform thickness given by the distance between the two foil surfaces. In the following, two surfaces or planes may be considered to be "parallel" if the (e.g. imaginary) extension of the two surfaces or planes subtends an angle of less than 5° or less than 3° or less than 1°.

[0017] The transfer foil can be a rigid film that can consist of a porous silicon carbide layer, or it can be a layer stack that includes at least one auxiliary layer in addition to the porous silicon carbide layer. The auxiliary layer(s) can include or consist of a material different from the porous monocrystalline silicon carbide. If the layer stack includes one single auxiliary layer, the auxiliary layer can include or consist of an organic material or an inorganic material. If the layer stack includes two or more auxiliary layers, all the auxiliary layers can include or consist of an organic material, all the auxiliary layers can include or consist of an inorganic material, or at least one of the auxiliary layers can include or consist of an organic material and at least one of the other auxiliary layers can include or consist of an inorganic material. For example, the auxiliary layer or at least one of the auxiliary layers is silicon-based and includes silicon oxide and / or silicon nitride. The auxiliary layer or at least one of the auxiliary layers can be silicon carbide-based. The auxiliary layer or at least one of the auxiliary layers can be carbon-based. The auxiliary layer can include glass, ceramic, or resin.

[0018] The lateral extent of the transfer foil can be large enough to completely cover the planar major surface of a standard wafer. In particular, the transfer foil can be shaped so that it covers a circle with a diameter of at least 4 inches, 150 mm, 200 mm, or 300 mm. The shape of the transfer foil in the horizontal plane can be a circle or a polygon, for example, a rectangle, a square, or a hexagon.

[0019] The porous silicon carbide layer may have two parallel main surfaces. The thickness of the porous silicon carbide layer, given by the distance between the two main surfaces, may be uniform along the porous silicon carbide layer. It may also be possible for the thickness of the porous silicon carbide layer to vary along the porous silicon carbide layer by up to 35% (or up to 10% or up to 5%) of the average thickness of the porous silicon carbide layer. The thickness of the porous silicon carbide layer may be in the range of 1 nm to 50 μm.

[0020] The porous silicon carbide layer comprises a monocrystalline 3D support structure ("skeleton structure") with closed and / or connected (e.g., communicating) pores. The major surface of the porous silicon carbide layer is preferably a Si-O-Si, Si-F2 and / or CH x The compound may be covered with a functional group such as

[0021] Defining the porosity of a layer as the ratio of void volume (i.e., "empty volume") in the layer to the total volume of the layer, the average porosity of a porous silicon carbide layer is in the range of 10% to 80%, such as in the range of 30% to 60%. Local porosity, determined for a unit volume larger than the maximum pore size, may vary from 1% to 80%.

[0022] In the porous silicon carbide layer, the local porosity may be homogeneous. Alternatively, the porosity of the porous silicon carbide layer may be uniform only along a direction parallel to the major surfaces and may vary in a direction perpendicular to the major surfaces. For example, the porosity may increase gradually or stepwise with increasing distance to one or both major surfaces, or may decrease with increasing distance to both major surfaces. The porous silicon carbide layer may include vertically stacked sublayers of different porosity. For example, the porous silicon carbide layer may include a coarse-porous sublayer and a fine-porous sublayer, the porosity of the coarse-porous sublayer being greater than the porosity of the fine-porous sublayer. For example, the coarse-porous sublayer may include large pores with an average diameter greater than 50 nm, e.g., in the range of 50 nm to 200 nm, and a high overall porosity of at least 30% and at most 80%, e.g., in the range of 40% to 60%. The microporous sublayer may contain small pores with an average diameter of at most 50 nm, eg, less than 40 nm, and a low overall porosity of at most 50%, eg, in the range of 5% to 35%.

[0023] The porous silicon carbide layer may include a skin layer portion, the skin layer portion containing pores at a porosity of less than 5% or being nearly pore-free. The skin layer portion may be directly adjacent to one of the major surfaces of the porous silicon carbide layer.

[0024] The transfer foil may be obtained by forming a porous surface layer along the top surface of a source substrate of single crystal silicon carbide and cutting the porous surface layer or a portion of the porous surface layer from the source substrate.

[0025] Forming the porous surface layer may include metal assisted photochemical etching (MAPCE), which may use a noble metal layer as an electrode.

[0026] Alternatively, the porous surface layer may be formed by electrochemical etching, which induces anodic dissolution of the source substrate. For example, the source substrate may be contacted with an electrolyte containing fluorine, e.g., hydrofluoric acid (HF), and a surface active agent (surfactant). The surfactant may contain tetramethylammonium hydroxide (TMAH), potassium hydroxide (KOH), and / or ethanol. Alternatively, the electrolyte may be an aqueous HF solution. A cathode electrode may be immersed in the electrolyte, and a potential may be applied between the cathode electrode and the source substrate, which forms the anodic electrode. The electrochemical etching may be a dark process or may be photoelectrochemical etching, which is assisted by light.

[0027] The transfer foil including the porous silicon carbide layer can be cut from the source substrate by mechanical force. For example, a stressor layer can be applied to the top surface of the porous surface layer, and the mechanical stress induced by the stressor layer in the source substrate can cause the porous silicon carbide layer to cleave along a horizontal plane. The stressor layer can be part of the transfer foil. The stressor layer can be removed before or after forming the composite substrate.

[0028] The transfer foil and the support substrate are brought into contact with each other and connected to each other, and a stable and permanent chemical bond can be formed between the first main surface (bonding surface) of the porous silicon carbide layer and the process surface of the support substrate. The support substrate is made of a support material different from that of the source substrate or includes a top layer of a substrate material different from the base material of the source substrate from which the porous silicon carbide layer is obtained.

[0029] The process surface of the support substrate extends along two orthogonal horizontal (transverse) directions. A normal onto the process surface defines the vertical direction.

[0030] The substrate material and the source substrate may have the same main components silicon and carbon, but different microstructures (German: Gefuge). The support substrate may be a substrate other than a defect-free or nearly defect-free monocrystalline silicon carbide substrate and may be less expensive than the source substrate from which the porous silicon carbide layer is obtained.

[0031] Connecting the transfer foil and the support substrate together forms an integral composite substrate.

[0032] The epitaxial layer may be formed directly on the second main surface (epitaxy surface) of the porous silicon carbide layer of the transfer foil. For example, the epitaxial layer may be formed directly on the skin layer portion of the porous silicon carbide layer. Forming the epitaxial layer includes a deposition process and, if applicable, a thermal treatment for recrystallization of the deposited material to obtain 4H-SiC. The deposition process may include chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), metal organic vapor phase epitaxy (OMVPE) and / or molecular beam epitaxy (MBE). The epitaxial layer forms a silicon carbide single crystal, and the atoms of the single crystal continue the crystal lattice of the porous silicon carbide layer.

[0033] Dividing the composite substrate may include splitting the porous silicon carbide layer horizontally into two portions, e.g., cleaving the porous silicon carbide layer horizontally, and the composite substrate is separated into a device substrate and a reclaimed substrate. The device substrate may include an epitaxial layer and further include a device portion of the cleaved porous silicon carbide layer. The reclaimed substrate may include a support substrate and further include a reclaimed portion of the cleaved porous silicon carbide layer.

[0034] The device substrate is separated in one piece from the reclaimed substrate, with the reclaimed portion of the cleaved porous silicon carbide layer remaining connected to the support substrate.

[0035] The regenerated portion of the cleaved porous silicon carbide layer may form a continuous layer or may include laterally separated islands. The device portion of the cleaved porous silicon carbide layer may form a continuous layer or may include laterally separated islands.

[0036] Splitting the composite substrate may include mechanically stressing the composite substrate in a manner such that the splitting process in the porous silicon carbide layer relieves the mechanical stress before another portion of the composite substrate is mechanically damaged. The mechanical stress may act in a horizontal transverse direction, a horizontal radial direction, a vertical direction, and / or as a torsional shear stress. Creating the mechanical stress may include creating a temperature differential along the vertical direction, exploiting differences in thermal expansion coefficients between the composite substrate and at least one support structure rigidly connected to one of the major surfaces of the composite substrate, twisting and / or pulling a chuck rigidly connected to one of the major surfaces of the composite substrate, and / or applying a lever force to peel off the device substrate.

[0037] Alternatively or additionally, splitting the composite substrate may include selectively physically and / or chemically damaging the skeletal structure of the porous silicon carbide layer until the device substrate separates from the reclaimed substrate or until application of a relatively weak mechanical force is sufficient to sever the device substrate from the composite substrate. For example, a horizontal fluid beam, a horizontal particle beam or horizontal radiation may be directed at the exposed lateral surfaces of the porous silicon carbide layer to remove material from the skeletal structure and weaken the skeletal structure of the porous silicon carbide layer. Alternatively or additionally, damaging the skeletal structure may include filling the pores with a supplemental filler material and using the physical properties of the supplemental filler material to damage the skeletal structure. Alternatively or additionally, damaging the skeletal structure may utilize the large pore surface for highly selective chemical decomposition or conversion of silicon carbide in the porous silicon carbide layer into volatile components and / or less mechanically stable compounds.

[0038] The epitaxial layer may be separated from the base portion along the porous structure after doped regions of electronic elements, insulator structures and / or conductive structures are formed on and / or in the epitaxial layer. For example, the epitaxial layer may be separated from the base portion after forming the semiconductor portion of a semiconductor device in the epitaxial layer. The separation process may include separating (e.g., cleaving) the porous structure along a substantially horizontal plane through the rough porous laminate portion.

[0039] After removal of the reclaimed portion of the cleaved porous silicon carbide layer, the reclaimed substrate may be reused as a support substrate. The device substrate may be used to manufacture semiconductor devices, and the device portion of the cleaved porous silicon carbide layer may be completely removed. Alternatively, the device portion of the cleaved porous silicon carbide layer may be smoothed and / or planarized, e.g., planarized.

[0040] The method decouples advanced epitaxy from porosification, enabling cost-effective production of thin silicon carbide device substrates, such as those suitable for power semiconductor devices.

[0041] According to one embodiment, the support substrate may include a polycrystalline silicon carbide substrate, a single crystal silicon carbide wafer of a different polytype than the polytype of the porous silicon carbide layer, or a single crystal silicon carbide recycled substrate.

[0042] The polycrystalline silicon carbide substrate may be an untreated or nearly untreated polycrystalline silicon carbide wafer. The monocrystalline silicon carbide substrate of a polytype different from that of the porous silicon carbide layer may comprise or consist of 2H-SiC, 3C-SiC, and / or 6H-SiC when the porous silicon carbide layer is formed from 4H-SiC.

[0043] The single crystal silicon carbide recycled substrate may include any polytype of single crystal silicon carbide, but is not suitable for obtaining defect-free standard silicon carbide semiconductor devices on an economic scale. The recycled substrate may be a single crystal 4H-SiC wafer that does not meet at least one of the relevant specifications set up for the wafer for the manufacture of power semiconductor devices. For example, the single crystal silicon carbide recycled wafer contains more impurity atoms and / or more crystal defects, has a resistivity outside the specified range or a surface orientation outside the specified range. The support substrate may be less expensive than the source substrate.

[0044] According to one embodiment, forming the composite substrate may include bonding a porous silicon carbide layer and a support substrate together such that a permanent bond is formed between the porous silicon carbide layer and the support substrate.

[0045] Permanent bonds can be glueless or adhesive bonds. Glueless bonds are formed by direct bonds or fusion bonds (German: Schmelzbonden). Adhesive bonds are formed by applying adhesives.

[0046] For example, the bonding surface of the porous silicon carbide layer may be directly bonded to the process surface of the support substrate. In this case, there may be no adhesive material or no material other than the material from the support substrate and the porous silicon carbide layer along the interface between the porous silicon carbide layer and the support substrate. The direct bond may be based on a direct chemical bond between two bonding members. For example, the two bonding members may be two of: (i) the support substrate, (ii) the porous silicon carbide layer, (iii) an (optional) non-adhesive bonding layer on the support substrate, (iv) an (optional) non-adhesive bonding layer on the porous silicon carbide layer. The non-adhesive bonding layer may include or consist of a semiconductor material and / or a metallic material.

[0047] Fusion bonding may include pre-bonding at ambient temperature and annealing at elevated temperature. Pre-bonding brings the bonding surface of the porous silicon carbide layer into physical contact with the process surface of the support substrate. Annealing may activate and / or strengthen the chemical bond between the support substrate and the porous silicon carbide layer. Direct bonding (fusion bonding) may be assisted by applying a silicon carbide-based liquid, liquid silicon carbide precursor or amorphous silicon onto the process surface of the support substrate and / or the bonding surface of the porous silicon carbide layer prior to pre-bonding.

[0048] Alternatively, the porous silicon carbide layer of the transfer foil can be adhesively bonded onto the process surface of the support substrate through an intermediate adhesive layer, the bond being based on chemical bonds between the cured adhesive layer and the support substrate and between the cured adhesive layer and the porous silicon carbide layer.

[0049] Adhesive bonding may include applying a curable adhesive to the process surface of the support substrate and / or to the bonding surface of the porous silicon carbide layer, pressing the support substrate and the transfer foil with the curable adhesive therebetween against one another, and curing the adhesive, which hardens to form a cured adhesive layer. The curable adhesive may be applied, by way of example, as a liquid, as a tape, or as a layer on a tape.

[0050] Generally, surface pretreatment or conditioning may be performed prior to bonding. For example, such pretreatment or conditioning may include treatment with plasma and / or wet chemical solutions.

[0051] According to one embodiment, the porous silicon carbide layer may include a bonding surface having a C-face, and forming the composite substrate includes bonding the bonding surface of the porous silicon carbide layer to a support substrate.

[0052] The C-face bonding surface may simplify direct bonding of the transfer foil to the Si-face of a single crystal recycled substrate of the same polytype as the porous silicon carbide layer. Bonding the C-face of the porous silicon carbide layer to a support substrate may leave the Si-face of the porous silicon carbide layer accessible for further processing.

[0053] According to one embodiment, the porous silicon carbide layer may include an epitaxy surface having a Si-face, and an epitaxial layer may be formed on the epitaxy surface of the porous silicon carbide layer.

[0054] A porous silicon carbide layer may be formed with significantly less porosity along a surface having a Si-face than along a surface having a C-face.

[0055] Growing an epitaxial layer on a Si-faced epitaxy surface can be less complicated than growing an epitaxial layer on a C-face.

[0056] According to one embodiment, electronic elements may be formed in and / or on the epitaxial layers prior to dividing the composite substrate.

[0057] The electronic element may be an active semiconductor element. For example, the electronic element is a semiconductor diode or a transistor. A doped semiconductor region of the electronic element, such as an anode region of the semiconductor diode or a source / emitter region of the transistor, may be formed in the epitaxial layer. An anode electrode of the semiconductor diode or a source / emitter electrode of the transistor may be formed on the epitaxial layer. A gate electrode of the transistor may be formed on the epitaxial layer or in a trench extending from the front side into the epitaxial layer.

[0058] According to one embodiment, the method may include backside processing of the exposed back surface of the device substrate.

[0059] Splitting the composite substrate includes cleaving the porous silicon carbide layer such that the back surface of the device substrate is separated from the front surface of the reclaimed substrate, the exposed back surface being formed by the device portion of the cleaved porous silicon carbide layer.

[0060] The backside processing may include CMP, which planarizes and / or recesses the device portion of the cleaved porous silicon carbide layer, which may be completely removed from the device substrate, or the planarized device portion of the cleaved porous silicon carbide layer forms a porous backside layer of the device substrate. Alternatively or additionally, the backside processing may include introducing dopants through the exposed back surface, a selective thermal treatment, and / or deposition of a material, e.g., deposition of a metal layer.

[0061] According to one embodiment, a metal layer may be formed on the exposed back surface of the device substrate.

[0062] The metal layer may be a homogeneous layer or may be a layer stack comprising two or more vertically stacked sublayers of different composition and / or structure.

[0063] According to one embodiment, an ohmic contact may be formed on the backside of the device substrate.

[0064] Forming the ohmic contact may include introducing an impurity through the exposed back surface of the device substrate to form a highly doped contact layer along the back surface and forming a metal layer on the highly doped contact layer, the metal layer and the highly doped contact layer forming the ohmic contact. Introducing the impurity may include implanting a dopant through the back surface of the device substrate. Forming the ohmic contact may include a localized thermal treatment of the back surface, for example, laser thermal annealing (LTA).

[0065] The metal layer may form the electrodes of a vertical semiconductor device, with current flowing between the front side and the back side in the forward mode of a semiconductor diode or in the on-state of a power transistor.

[0066] According to one embodiment, forming the transfer foil can include forming a porous surface layer on a front side of a single crystal silicon carbide source substrate and separating a foil portion of the porous surface layer from the source substrate, the foil portion forming a porous silicon carbide layer of the transfer foil.

[0067] The source substrate has a planar first major surface extending along two orthogonal horizontal (transverse) directions, with a normal onto the first major surface defining a vertical direction.

[0068] The foil portion is removed in one piece from the remainder of the source substrate. The substrate portion of the porous surface layer may remain connected to the non-porous substrate portion of the source substrate that has been made non-porous. The substrate portion may form a continuous layer or may include laterally separated islands.

[0069] Separating the foil portion from the porous surface layer may include mechanically stressing the source substrate in a manner that splits the porous surface layer horizontally into two portions and relieves the mechanical stress in the porous surface layer before another portion of the source substrate is mechanically damaged. The mechanical stress may act in a horizontal transverse direction, a horizontal radial direction, a vertical direction, or as a torsional shear stress. Creating a mechanical stress may include creating a temperature difference along a vertical direction, exploiting differences in thermal expansion coefficients between the source substrate and at least one support structure rigidly connected to one of the major surfaces of the source substrate, twisting and / or pulling a chuck rigidly connected to one of the major surfaces of the source substrate, and / or applying a lever force to peel off the foil portion.

[0070] Alternatively or additionally, separating the foil portion of the porous surface layer from the source substrate may include selectively physically and / or chemically damaging the skeletal structure of the porous surface layer until the foil portion of the porous surface layer breaks off from the substrate portion or until application of a relatively weak mechanical force is sufficient to break the foil portion off from the source substrate. For example, a horizontal fluid beam, a horizontal particle beam or horizontal radiation may be directed at the exposed lateral surface of the porous surface layer to remove material from the skeletal structure and weaken the skeletal structure of the porous surface layer. Alternatively or additionally, damaging the skeletal structure may include filling the pores with a supplemental filler material and using the physical properties of the supplemental filler material to damage the skeletal structure. Alternatively or additionally, damaging the skeletal structure may take advantage of the large pore surface for highly selective chemical decomposition or conversion of silicon carbide in the porous surface layer to volatile components and / or less mechanically stable compounds.

[0071] The transfer foil may include an auxiliary layer applied to one of the major surfaces of the porous silicon carbide layer. For example, the auxiliary layer may be formed or applied on the porous surface layer prior to splitting the porous surface layer. Alternatively, or in addition, the auxiliary layer may be applied to at least one of the major surfaces of the porous silicon carbide layer after separating the foil portion from the source substrate.

[0072] The reclaimed portion of the source substrate including the substrate portion of the porous surface layer and the non-porous substrate portion of the source substrate may be reworked, for example, the substrate portion of the porous surface layer may be planarized or completely removed such that in a next cycle, an additional porous surface layer may be formed in the reworked reclaimed portion of the source substrate.

[0073] According to one embodiment, forming the porous surface layer may include metal assisted photochemical etching (MAPCE).

[0074] MAPCE can form a porous silicon carbide layer on the C-face of the source substrate.

[0075] According to one embodiment, splitting the composite substrate may include creating a horizontal mechanical stress in the porous silicon carbide layer.

[0076] The horizontal mechanical stress may be generated by radial forces, transverse forces, and / or by torsional forces. The mechanical stress may generate and / or promote the growth of horizontal cracks in the vertical columns of the skeletal structure in the porous silicon carbide layer until the composite substrate is separated into two parts.

[0077] Creating a horizontal mechanical stress may include forming or securely attaching, e.g., bonding, a stressor layer on a major surface of the composite substrate and exposing the composite substrate to a thermal treatment, where the different degrees of thermal expansion in the composite substrate and the stressor layer create a radial mechanical stress in the composite substrate, which may have a maximum value in the horizontal layer portion with the highest porosity.

[0078] According to another aspect of the present disclosure, a composite substrate may include a support substrate comprising single crystal silicon carbide. A single crystal porous silicon carbide layer is on a process surface of the support substrate, the polytype of the support substrate being different from the polytype of the porous silicon carbide layer, and / or the support substrate being a recycled wafer. An epitaxial layer is formed on the side of the porous silicon carbide layer opposite the support substrate.

[0079] The support substrate may include a non-porous single crystal silicon carbide layer or may consist of non-porous single crystal silicon carbide.

[0080] According to one embodiment, the single crystal porous silicon carbide layer may be in direct contact with a process surface of a support substrate. For example, the single crystal porous silicon carbide layer is directly bonded to a non-porous single crystal silicon carbide layer of a support substrate or to a support substrate made of non-porous single crystal silicon carbide. A chemical bond, for example a silicon-carbon bond, is formed between the single crystal porous silicon carbide layer and the support substrate.

[0081] According to one embodiment, the epitaxial layer may be in direct contact with the porous silicon carbide layer. For example, the porous silicon carbide layer may include a low-porosity skin layer portion having a porosity of less than 5% and a thickness of at most 300 nm. The epitaxial layer may be in direct contact with the low-porosity skin layer portion.

[0082] According to another aspect of the disclosure, a power semiconductor device may include a monocrystalline porous silicon carbide portion having laterally uniform porosity. A non-porous silicon carbide portion is in direct contact with a major surface of the porous silicon carbide portion. An active semiconductor element includes a semiconductor region formed in the non-porous silicon carbide portion. A first loading electrode is formed on a front side of the non-porous silicon carbide portion opposite the porous silicon carbide portion. A second loading electrode is formed on a rear side of the porous silicon carbide portion opposite the major surface of the porous silicon carbide portion.

[0083] According to one embodiment, the single crystal porous silicon carbide portion may have a constant dopant concentration gradient in the lateral direction.

[0084] In the skeletal structure of the porous silicon carbide portion, the dopant concentration does not vary along the lateral direction.

[0085] The doping level in the porous silicon carbide portion and the doping level in the non-porous silicon carbide portion may be the same or at least similar, with the doping level in the porous silicon carbide portion being at most 50% below or above the doping level in the non-porous silicon carbide portion. Alternatively, the doping level in the porous silicon carbide portion is more than 50% below or above the doping level in the non-porous silicon carbide portion.

[0086] 1A-1D relate to an embodiment having a transfer foil 110 that includes at most a porous silicon carbide layer 116 as shown in FIG. 1A.

[0087] The porous silicon carbide layer 116 has two parallel main surfaces 111, 112. The main surfaces 111, 112 are planar or at least approximately planar and have lateral extensions along two orthogonal horizontal directions. The first main surface 111 on a first side of the porous silicon carbide layer 116 may have a carbon face (C-face). The second main surface 112 on a second side of the porous silicon carbide layer 116 may have a silicon face (Si-face).

[0088] The lateral extension may be large enough to completely cover the front side of a standard wafer having a diameter of at least 4 inches, 150 mm, 200 mm or 300 mm. The horizontal shape of the porous silicon carbide layer 116 may be rectangular or circular, by way of example. The distance between the first main surface 111 and the second main surface 112 corresponds to a thickness th1 along a vertical direction perpendicular to the horizontal direction. The thickness th1 of the porous silicon carbide layer 116 may be in the range of 5 nm to 100 μm, for example, 10 μm to 30 μm.

[0089] The porous silicon carbide layer 116 comprises closed and / or connected pores embedded in a single crystal, larger support structure (skeleton structure). The single crystal support structure has a 4H polytype. The dopant concentration in the single crystal support structure is uniform in the horizontal direction and may be uniform or may exhibit stepless or stepwise variation along the vertical direction.

[0090] The porosity of the porous silicon carbide layer is constant in the horizontal direction. In the vertical direction, the porosity of the porous silicon carbide layer is constant or has a stepless or stepwise variation. The average porosity of the porous silicon carbide layer is in the range of 10% to 80%, for example in the range of 30% to 60%. Along the second major surface 112, the porosity may be less than 5%, for example less than 1%. Along the first major surface 111, the porosity may be higher than along the second major surface 112, for example higher than 50%.

[0091] The first major surface 111 and / or the second major surface 112 of the porous silicon carbide layer may be Si-O-Si, Si-F2 and / or CH x The compound may be covered with a functional group such as

[0092] The porous silicon carbide layer 116 is brought into contact with a planar process surface 191 of a support substrate 190. A stable and permanent chemical bond is formed between the porous silicon carbide layer 116 and the support substrate 190.

[0093] The support substrate 190 includes or consists of a non-porous substrate material, the thermal expansion coefficient of which and the thermal expansion coefficient of the porous silicon carbide layer 116 are equal or may deviate from each other by at most 5% from the average value of the two thermal expansion coefficients.

[0094] The lateral extension of the support substrate 190 may accommodate a standard wafer having a diameter of at least 4 inches, 150 mm, 200 mm, or 300 mm.

[0095] The material of the support substrate 190 is different from a non-porous monocrystalline silicon carbide substrate having the polytype of the porous silicon carbide layer 116 and meeting the specifications for a source substrate for the manufacture of power semiconductor devices, for example with respect to resistivity, crystal orientation, crystal defect density, dopant concentration, hydrogen content, and / or oxygen content. For example, the substrate material of the support substrate 190 can be monocrystalline 3C-SiC, 2H-SiC, or 6H-SiC or polycrystalline silicon carbide. Alternatively, the support substrate is a recycled wafer that does not meet the specifications for an initial substrate for the manufacture of power semiconductor devices.

[0096] Connecting the porous silicon carbide layer 116 and the support substrate 190 may include direct bonding or fusion bonding, with or without applying liquid silicon carbide onto the process surface 191 of the support substrate 190 and / or the first major surface 111 (bonding surface) of the porous silicon carbide layer 116 prior to contacting the bonding surface 111 of the porous silicon carbide layer 116 and the process surface 191 of the support substrate 190 with each other.

[0097] FIG. 1B shows an integral composite substrate 100 including a porous silicon carbide layer 116 and a support substrate 190 .

[0098] An epitaxial layer 120 is formed directly on the second major surface 112 (epitaxy surface) of the porous silicon carbide layer 116. Forming the epitaxial layer 120 includes a deposition process and, if applicable, a thermal treatment for recrystallization of the deposited material to obtain 4H-SiC. The deposition process may include chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), metal organic vapor phase epitaxy (OMVPE) and / or molecular beam epitaxy (MBE). The epitaxial layer 120 grows in registry with the crystal lattice of the porous silicon carbide layer 116. The initial phase of epitaxy may be controlled to facilitate some lateral overgrowth across gaps in the epitaxy surface 112 of the porous silicon carbide layer 116.

[0099] 1C, the integral composite substrate 100 includes a support substrate 190, a porous silicon carbide layer 116, and an epitaxial layer 120 grown on the epitaxy surface 112 of the porous silicon carbide layer 116. The epitaxial layer 120 forms a single crystal and continues the crystal lattice of the porous silicon carbide layer 116 with atoms of the single crystal. The porous silicon carbide layer 116 may include a low-porosity skin layer along the epitaxy surface 112, which skin layer forms prior to and / or during an initial phase of epitaxy.

[0100] One or more active electrical elements may be formed in and / or on the epitaxial layer 120. The porous silicon carbide layer 116 is then cleaved at a substantially horizontal cleavage portion 115. The cleavage portion 115 may include a coarse-porous stack portion of the porous silicon carbide layer 116. In particular, the cleavage portion 115 may include a vertical high-porosity sublayer of the porous silicon carbide layer 116, in which the porosity of the porous silicon carbide layer 116 has a maximum value. The vertical extension of the cleavage portion 115 may be small relative to the thickness th1 of the porous silicon carbide layer 116. The cleavage portion 115 may be at a distance from both the epitaxial layer 120 and the support substrate 190, or may be directly adjacent to the support substrate 190.

[0101] Cleaving the porous silicon carbide layer 116 may include attaching a stressor substrate having a thermal expansion coefficient different from that of the composite substrate 100 to at least one of the major surfaces of the composite substrate 100, and then cooling or heating a composite including the stressor substrate and the composite substrate 100 to generate thermo-mechanical stress in the porous silicon carbide layer 116 along a horizontal radial direction.

[0102] Alternatively, thermo-mechanical stress can be induced in the porous silicon carbide layer 116 by creating a vertical temperature gradient in the composite substrate 100. Any type of cleaving process described above can be used.

[0103] As shown in Figure 1D, the composite substrate 100 of Figure 1C is separated into a device substrate 150 and a reclaimed substrate 160. The device substrate 150 includes the epitaxial layer 120 and the device portion 118 of the porous silicon carbide layer 116. The reclaimed substrate 160 includes the reclaimed portion 119 of the porous silicon carbide layer 116 and a support substrate 190.

[0104] The device substrate 150 may be further processed. For example, the device portion 118 of the porous silicon carbide layer 116 may be removed from the device substrate 150. The removal of the device portion 118 may include mechanical, chemical, physical polishing, or a combination of different polishing methods, such as chemical mechanical polishing (CMP). The CMP may expose the back surface of the epitaxial layer 120. A metal layer may be deposited on the back surface of the epitaxial layer 120. From the device substrate 150, the semiconductor die of the power semiconductor device is obtained by dicing.

[0105] The reclaimed portion 119 of the cleaved porous silicon carbide layer 116 is removed from the reclaimed substrate 160. The reclaimed substrate 160 may then be reused as another support substrate 190, and the process of transferring the porous silicon carbide layer 116 to a support substrate, growing an epitaxial layer on the porous silicon carbide layer 116, and splitting a device substrate off of the resulting composite substrate may be repeated.

[0106] 2A-2D, the transfer foil 110 includes a backlayer 117 formed on or attached to the epitaxy surface 112 of the porous silicon carbide layer 116, as shown in FIG. 2A.

[0107] The auxiliary layer 117 may be a homogenous layer or a layer stack including at least two vertically stacked layers of different composition and / or microstructure. The auxiliary layer 117 may include an adhesive tape and / or a rigid support layer.

[0108] An interface layer 130 may be formed on the process surface 191 of the support substrate 190. The interface layer 130 may include a layer containing silicon. For example, the interface layer 130 may include or consist of silicon nitride.

[0109] The porous silicon carbide layer 116 is brought into contact with the planar process surface 131 of the interface layer 130. A stable and permanent chemical bond is formed between the porous silicon carbide layer 116 and the interface layer 130. The backlayer 117 is removed.

[0110] 2B shows the porous silicon carbide layer 116 with the bonding surface 111 bonded directly to the interface layer 130. In the absence of the interface layer 130, the porous silicon carbide layer 116 is bonded directly to the support substrate 190.

[0111] 2C and 2D show the growth of an epitaxial layer 120 on the epitaxy surface 112 of the porous silicon carbide layer 116 and the split of the composite substrate 100 along the cleaved portion 115 of the porous silicon carbide layer 116, as described above with reference to FIGS. 1C and 1D, along with the difference in the interfacial layer 130 formed between the porous silicon carbide layer 116 and the support substrate 190.

[0112] 3A-3D show a method of obtaining a semiconductor die 200 from a device substrate 150 that has been cleaved away from a composite substrate 100 using a porous silicon carbide layer 116 applied through a transfer foil 110.

[0113] The composite substrate 100 is formed by bonding a transfer foil 110 including a porous silicon carbide layer 116 onto a process surface 191 of a support substrate 190 and epitaxially growing a low n-doped epitaxial layer 120 on the epitaxy surface 112 of the porous silicon carbide layer 116.

[0114] The semiconductor regions, conductive structures, and insulating structures of electronic elements 210 are formed in and / or on epitaxial layer 120 .

[0115] 3A, the epitaxial layer 120 includes a number of equally sized device regions 220 arranged along two orthogonal horizontal directions. In each device region 220, the same type of electronic element 210 is formed.

[0116] In the illustrated embodiment, acceptor atoms are implanted through the main surface 121 at the front side of the epitaxial layer 120 opposite the porous silicon carbide layer 116 to form a p-doped anode region 281 in each device region 220. Depositing and patterning a metal layer or metal layer stack forms an anode electrode 282 in each device region 220, with the anode electrode 282 forming an ohmic contact with the anode region 281. Depositing and patterning an insulator layer or insulator layer stack forms a passivation structure 283 in each device region 220, covering, among other things, the sidewalls of the anode electrode 282.

[0117] The composite substrate 100 is separated into a device substrate 150 and a reclaimed substrate as described with reference to FIG. 1D.

[0118] FIG. 3B shows a device substrate 150 including the epitaxial layer 120 and the device portion 118 of the porous silicon carbide layer.

[0119] A polishing process removes the device portion 118 of the porous silicon carbide layer, exposing the epitaxial layer 120 on the backside of the device substrate 150 .

[0120] As shown in FIG. 3C, a back surface 152 of the device substrate 150 exposes the epitaxial layer 120 .

[0121] Donor atoms may be introduced, for example, implanted, through the back surface 152 of the device substrate 150. One or more metal-containing layers are deposited on the back surface 152 of the device substrate 150. Before or after depositing the one or more metal-containing layers, a localized thermal treatment activates the introduced donor atoms.

[0122] The activated donor atoms form a highly doped contact layer 122 along the back surface 152 of the device substrate 150. The deposited metal-containing layer or layers form a metal layer structure 170. The highly doped contact layer 122 and the metal layer structure 170 form an ohmic contact.

[0123] A dicing process laterally separates the device regions 220 of the device substrate 150 from one another, with each separated device region 220 forming a vertical power semiconductor diode semiconductor die 200 with a cathode electrode formed from a portion of the metal layer structure 170. A forward current of the power semiconductor diode flows between the anode electrode 282 on the front side and the cathode electrode on the back side of the semiconductor die 200.

[0124] Instead of a power semiconductor diode, a vertical transistor, e.g., a MOSFET or IGBT, may be formed in the semiconductor die 200. Instead of completely removing the device portion 118 of the porous silicon carbide layer 116 and forming the metal layer structure 170 on the surface of the epitaxial layer 120, CMP may remove only a portion of the device portion 118 of the porous silicon carbide layer 116, and the metal layer structure 170 is formed on the recessed and planarized surface of the device portion 118 of the porous silicon carbide layer 116.

[0125] 4A-4C illustrate a process for forming a transfer foil 110 that includes a single crystal, porous silicon carbide layer 116. FIG.

[0126] 4A shows a non-porous single crystal silicon carbide source substrate 300. The source substrate 300 is a single crystal wafer or boule and has two parallel major surfaces 301, 302. The polytype of silicon carbide is 4H. The first major surface 301 may have an off-axis cut of about 4 degrees relative to the

[0001] main crystal plane. The first major surface 301 on the front side of the source substrate 300 has a C-plane.

[0127] A porous surface layer 310 is formed on a first major surface 301 of a source substrate 300 by MAPCE. MAPCE porosifies (makes porous) a surface layer of the source substrate 300 below the first surface 301.

[0128] 4B shows the source substrate 300 with the porous surface layer 310 formed by MAPCE and the non-porous substrate portion 390. The porous surface layer 310 is formed in a section of the source substrate 300 directly beneath the first major surface 301.

[0129] A separation process divides the porous surface layer 310 into a foil portion 316 and a substrate portion 315. The foil portion 316 comprises a first layer portion of the porous surface layer 310 and forms the porous silicon carbide layer 116 of the transfer foil 110. The substrate portion 315 comprises a second layer portion of the porous surface layer 316. The substrate portion 315 and the non-porous substrate portion 390 of the porous surface layer 310 form the reclaimed portion 360 of the source substrate 300.

[0130] Before or after separating the foil portion 316 and the substrate portion 315, a backing layer may be formed on or attached to the front side of the foil portion 316, such that the transfer foil 110 includes the porous silicon carbide layer 116 and the backing layer.

[0131] The reclaimed portion of the source substrate including the substrate portion of the split porous surface layer and the non-porous substrate portion of the source substrate are reworked, e.g., the substrate portion of the porous surface layer is planarized or completely removed so that an additional porous surface layer can be formed in the reworked reclaimed portion of the source substrate in a next cycle.

[0132] 5 and 6 show a composite substrate 100 that includes a support substrate 190 that includes single crystal silicon carbide. A single crystal porous silicon carbide layer 116 of 4H polytype is present on a process surface 191 of the support substrate 190. The support substrate 190 is a recycled wafer or has a polytype different from 4H.

[0133] An epitaxial layer 120 is formed on the epitaxy surface 112 of the porous silicon carbide layer 116 opposite the support substrate 190. The epitaxial layer 120 is in direct contact with the porous silicon carbide layer 116. The porous silicon carbide layer 116 includes a low porosity skin layer portion having a porosity of less than 5%. The epitaxial layer 120 is in direct contact with the low porosity skin layer portion.

[0134] 5, the single crystal porous silicon carbide layer 116 is in direct contact with the process surface 191 of the support substrate 190. Silicon-carbon bonds are formed between the single crystal porous silicon carbide layer 116 and the support substrate 190.

[0135] 6, the single crystal porous silicon carbide layer 116 is in direct contact with an interfacial layer 130 formed on a process surface 191 of a support substrate 190. A chemical bond is formed between the single crystal porous silicon carbide layer 116 and the interfacial layer 130. A chemical bond is also formed between the interfacial layer 130 and the support substrate 190. The interfacial layer 130 may include nitrogen atoms.

[0136] 7 and 8 show semiconductor dies 200 of power semiconductor devices 501, 502 obtainable from the composite substrate of FIG.

[0137] The semiconductor die 200 includes a monocrystalline silicon carbide body 230 having a planar front surface 231 on a front side and an opposed planar back surface 232. The front surface 231 and the back surface 232 are parallel to each other and extend in a horizontal direction. The distance between the front surface 231 and the back surface 232 defines a thickness of the silicon carbide body. A vertical direction is defined that is orthogonal to the horizontal direction.

[0138] The silicon carbide body 230 includes a single crystal porous silicon carbide portion 270 and a non-porous silicon carbide portion 280 between the porous silicon carbide portion 270 and the front surface 231. The non-porous silicon carbide portion 280 is in direct contact with the planar horizontal major surface 271 of the porous silicon carbide portion 270.

[0139] A first charging electrode 291 is formed on a front side of the non-porous silicon carbide portion 280 opposite the porous silicon carbide portion 270. A second charging electrode 292 is formed on a rear side of the porous silicon carbide portion 270 opposite the main surface 271 of the porous silicon carbide portion 270. The first charging electrode 291 and the second charging electrode include one or more metal layers. An insulating passivation structure 283 covers a portion of the front surface 231 next to the first charging electrode 291, a portion of the first charging electrode 291, and a sidewall of the first charging electrode 291.

[0140] The semiconductor body 230 includes a highly doped contact portion 222 formed along a back surface 232 of the semiconductor body 230 and a lightly doped drift region between the front surface 231 and the contact portion 222. The contact portion 222 is obtained from the contact layer 122 of the device substrate 150 as shown in Figure 3D. In the illustrated embodiment, the contact portion 222 is formed entirely in the porous silicon carbide portion 270. The contact portion 222 and the second loading electrode 292 form an ohmic contact.

[0141] 7 shows a power semiconductor diode 501 in which a first charge electrode 291 forms an anode electrode 282 and a second charge electrode 292 forms a cathode electrode. The anode electrode 282 forms or is connected to an anode terminal A. The cathode electrode forms or is connected to a cathode terminal K. The contact portion 222 is highly n-doped. A p-doped anode region 281 is formed along the front surface 231 of the semiconductor body 230. The anode region 281 and the anode electrode 282 form an ohmic contact. The anode region 281 and the drift region 235 form a p-n junction.

[0142] 8 shows a power transistor 502 in which a first load electrode 291 forms the source electrode and a second load electrode 292 forms the drain electrode. The source electrode forms or is connected to a source terminal S. The drain electrode forms or is connected to a drain terminal D. The contact portion 222 is highly n-doped. A transistor control region 284 is formed along the front surface 231 of the semiconductor body 230. The transistor control region 284 includes an n-doped source region of the transistor cell TC and one or more p-doped wells separating the source region and the n-doped drift region 235. The source electrode forms an ohmic contact with the source region and the p-doped well.

[0143] The porosity of the porous silicon carbide portion 270 does not vary along the lateral direction. The porosity is constant along the lateral direction. The porosity decreases along the vertical direction with increasing distance to the back surface 232 of the silicon carbide body 230.

[0144] The dopant concentration in the porous silicon carbide portion 270 does not vary along the lateral direction. The dopant concentration is constant along the lateral direction.

Claims

1. 1. A method of manufacturing a semiconductor device, the method comprising: forming a transfer foil (110) comprising a porous silicon carbide layer (116); forming a composite substrate (100) comprising the transfer foil (110) and a support substrate (190), the transfer foil (110) and the support substrate (190) being brought into contact with each other and connected to each other; forming an epitaxial layer (120) on a side of the porous silicon carbide layer (116) opposite the support substrate (190); Dividing the composite substrate (100) into a device substrate (150) and a reclaimed substrate (160), the device substrate (150) comprising the epitaxial layer (120) and the reclaimed substrate (160) comprising the support substrate (190); A method comprising:

2. the support substrate (190) comprises a polycrystalline silicon carbide substrate, a substrate comprising a monocrystalline silicon carbide of a polytype different from the polytype of the porous silicon carbide layer, and / or a silicon carbide recycled substrate; The method of claim 1.

3. forming the composite substrate (100) includes bonding the transfer foil (110) to the support substrate (190); The method of claim 1.

4. the porous silicon carbide layer (116) comprises a bonding surface (111) having a C-plane, and forming the composite substrate (100) comprises bonding the bonding surface (111) of the porous silicon carbide layer (116) to the support substrate (190). The method of claim 1.

5. the porous silicon carbide layer (116) has an epitaxy surface (112) having a Si-face, and the epitaxial layer (120) is formed on the epitaxy surface (112) of the porous silicon carbide layer (116); The method of claim 1.

6. forming semiconductor regions (281, 284) of an electronic element (210) in and / or on said epitaxial layer (120) prior to dividing said composite substrate (100); The method of claim 1 further comprising:

7. Backside treatment of the exposed back surface of said device substrate (150). The method of claim 1 further comprising:

8. forming a metal layer structure (170) on the exposed back surface of said device substrate (150); The method of claim 1 further comprising:

9. forming an ohmic contact on the backside of the device substrate (150); The method of claim 1 further comprising:

10. forming the transfer foil (110) comprises forming a porous surface layer (310) on a front side of a single crystal silicon carbide source substrate (300) and separating a foil portion (316) of the porous surface layer (310) from the source substrate (300), the foil portion (316) forming the porous silicon carbide layer (116) of the transfer foil (110); The method of claim 1.

11. forming the porous surface layer (310) comprises metal-assisted photochemical etching; The method of claim 10.

12. splitting the composite substrate (100) comprises inducing a horizontal mechanical stress in the porous silicon carbide layer (116).

12. The method according to any one of claims 1 to 11.

13. a support substrate (190) comprising single crystal silicon carbide; a single crystal porous silicon carbide layer (116) on a process surface (191) of said support substrate (190), wherein the polytype of said support substrate (190) is different from the polytype of said porous silicon carbide layer (116) and / or said support substrate (190) is a recycled wafer; an epitaxial layer (120) formed on a side of the porous silicon carbide layer (116) opposite the support substrate (190); A composite substrate comprising:

14. the single crystal porous silicon carbide layer (116) is in direct contact with the process surface (191) of the support substrate (190); The composite substrate according to claim 13.

15. the epitaxial layer (120) is in direct contact with the porous silicon carbide layer (116); The composite substrate according to claim 13.

16. a single crystal porous silicon carbide portion (270) having laterally uniform porosity; a non-porous silicon carbide portion (280) in direct contact with a major surface (271) of the porous silicon carbide portion (270); an active electronic element (210) comprising a semiconductor region formed in said non-porous silicon carbide portion (280); a first charging electrode (291) formed on a front side of the non-porous silicon carbide portion (280) opposite the porous silicon carbide portion (270); a second charging electrode (292) formed on a rear side of the porous silicon carbide portion (270) opposite the main surface (271) of the porous silicon carbide portion (270); A power semiconductor device comprising:

17. the single crystal porous silicon carbide portion (270) has a constant dopant concentration gradient in the lateral direction; 17. The power semiconductor device of claim 16.

Images