Semiconductor device

Abstract

To provide a transistor with good electrical characteristics, a transistor with stable electrical characteristics, and a semiconductor device with high integration density.SOLUTION: There is provided a semiconductor device including a transistor 100. The transistor includes: a first insulator 103; an oxide semiconductor 104b; a second insulator 105; a first conductor 106; a third insulator 108 formed on a side wall of the first conductor; a second conductor 109a and a third conductor 109b in contact with a top surface of the oxide semiconductor, a side surface of the oxide semiconductor, and a side surface of the third insulator; a fourth insulator 110 in contact with a side surface of the second conductor and a side surface of the third conductor; and a fifth insulator 111 in contact with top surfaces of the fourth insulator, the second conductor and the third conductor. The top surface of the fourth insulator has a substantially flat region. The oxide semiconductor has a first region overlapping with the first conductor, and a second region 135 having lower resistance lower than the first region.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One aspect of the present invention relates to a transistor and a semiconductor device, and a method for manufacturing the same. do.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect of the present invention relates to an object, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition of matter. It concerns the science of matter.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Displays (liquid crystal displays, light-emitting displays, etc.), lighting devices, electro-optical devices A power storage device, a memory device, a semiconductor circuit, an imaging device, an electronic device, and the like include a semiconductor device. There may be cases where this occurs. [Background technology]

[0004] In recent years, transistors using oxide semiconductors have been attracting attention. Since the film can be formed using a sputtering method, it can be used for transistors that make up large display devices. In addition, a transistor using an oxide semiconductor film has high field-effect mobility. Since the display has a high degree of uniformity, it is possible to realize a highly functional display device in which a driving circuit is integrally formed. It is possible to use some of the production equipment for silicon-film transistors with some modifications. This has the added benefit of reducing capital investment.

[0005] A transistor including an oxide semiconductor has an extremely low leakage current in a non-conducting state. For example, it is known that a transistor using an oxide semiconductor has an extremely low leakage current. A low-power CPU that utilizes this characteristic has been disclosed (see Patent Document 1). .). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2012-257187 A Summary of the Invention [Problem to be solved by the invention]

[0007] It is an object of the present invention to provide a transistor having a small parasitic capacitance. Another object of the present invention is to provide a transistor with high frequency characteristics. One of our goals is to provide It is an object of the present invention to provide a transistor having good electrical characteristics. Another object of the present invention is to provide a transistor having a high power consumption. Another object of the present invention is to provide a highly reliable transistor. Another object of the present invention is to provide a novel transistor. Alternatively, a semiconductor device having at least one of these transistors is provided. This is one of the challenges.

[0008] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. Other issues can be extracted from the drawings, claims, etc. [Means for solving the problem]

[0009] One aspect of the present invention is a semiconductor device including a first insulator, an oxide semiconductor on the first insulator, and an oxide semiconductor. a second insulator on the first conductor; a first conductor on the second insulator; and a first conductor adjacent to the side of the first conductor. A third insulator and a second conductive layer in contact with a side of the oxide semiconductor and a side of the third insulator. a fourth conductive member in contact with a side of the second conductive member and a side of the third conductive member; an insulator, and a fifth insulator in contact with the top surfaces of the fourth insulator, the second conductor, and the third conductor; and a semiconductor device having the above structure. Here, the upper surface of the fourth insulator has a substantially planarized region. The height of the upper ends of the second conductor and the third conductor is approximately equal to the height of the upper end of the fourth insulator. The fourth insulator has excess oxygen, and the oxide semiconductor is a second insulator overlapping the first conductor. a first region having a resistance lower than that of the first region, and a second region having a resistance lower than that of the first region, The fifth insulator has a lower oxygen permeability than the fourth insulator.

[0010] In the above configuration, the third insulator is a sidewall insulating layer, a sidewall insulating film, or a sidewall insulating film. In the above-mentioned structure, the semiconductor device may include a transistor. Preferably, the first conductor is connected to the second conductor as the gate electrode of the transistor. The second conductor and the third conductor are used as a source electrode or a drain electrode of the transistor. The insulator is the gate insulator (called the gate insulating film or gate insulating layer) of the transistor. It is preferable for the system to function as a

[0011] In the above configuration, the fourth insulator has an opening that reaches the first insulator, and the opening A fifth insulator is disposed in the opening, and the opening is configured to include an oxide semiconductor, a second insulator, and a second It is preferable that the fifth insulator is disposed so as to surround the conductor on all four sides. It is preferable that the hydrogen permeability is lower than that of the sintered body.

[0012] In the above configuration, at least one of the first insulator and the fifth insulator It is preferable that the first layer contains oxygen and aluminum. The region may have a region overlapping with the third insulator. The regions are tungsten, aluminum, titanium, magnesium, vanadium, and antimony. , arsenic, and sulfur.

[0013] In the above-mentioned configuration, the semiconductor device has a sixth insulator, and the sixth insulator has a protruding portion. The oxide semiconductor is preferably formed on and in contact with the protruding portion. The body includes a first membrane, a second membrane in contact with an upper surface of the first membrane, and a third membrane in contact with an upper surface of the second membrane. and a second film, wherein the electron affinity of the second film is greater than that of the first film and the third film. The electron affinity of the first conductor is greater than that of the second film, and the first conductor is electrically connected to the side of the second film through the second insulator. The sum of the height of the protrusion and the thickness of the first film is less than the thickness of the third film and the thickness of the second insulating film. The thickness of the second conductor and the third conductor is preferably greater than the sum of the thicknesses of the first and second conductors. It is preferable that it contacts either the upper surface of the second film or the upper surface of the third film.

[0014] In the above configuration, the fourth insulator has a third region that is mixed with the fifth insulator. The third region may also have excess oxygen.

[0015] Alternatively, one embodiment of the present invention includes forming a first insulator on a substrate, and then forming a semiconductor device on the first insulator. A first insulator is formed on the oxide semiconductor. A first conductor is formed over the insulator 2, and then a first element is added to the oxide semiconductor film; Then, a third insulator is formed on the first conductor and the oxide semiconductor. A fourth insulator is formed on a side surface of the first electrode by etching the insulator, and then A second conductor is deposited on the first conductor and the fourth insulator, and then a second conductor is deposited on the second conductor. A fifth insulator is deposited, and then the surface of the fifth insulator is planarized by chemical mechanical polishing. While the first region of the second conductor and the second region of the fifth insulator are both forming a third conductor, a fourth conductor and a sixth insulator by removing a region including the Then, a seventh insulator is formed on the sixth insulator to form a first transistor. The present invention relates to a method for manufacturing a semiconductor device, and a method thereof. The height of the top ends of the third conductor and the fourth conductor is equal to the height of the top end of the sixth insulator. In general, the first conductor serves as the gate electrode of the first transistor, and the third conductor The first conductor and the fourth conductor are used as a source electrode or a drain electrode of the first transistor. The first insulator and the seventh insulator have lower hydrogen permeability than the sixth insulator, At least one of the first insulator and the seventh insulator is made of aluminum oxide or nitride. Contains silicon.

[0016] In the above configuration, the fourth insulator may be called a sidewall insulating layer or a sidewall insulating film. In the above configuration, the first element is tungsten, aluminum, titanium, or the like. At least one of the following elements: zinc, magnesium, vanadium, antimony, arsenic, and sulfur It may include any one of them.

[0017] Alternatively, one embodiment of the present invention includes forming a first insulator on a substrate, and then forming a semiconductor device on the first insulator. A first insulator is formed on the oxide semiconductor. A first conductor is deposited on the second insulator, and then a third insulator is deposited on the first conductor. Then, a fourth insulator is formed by removing a portion of the third insulator, and then A second conductor is formed by removing a portion of the first conductor, and then an oxide semiconductor is formed. A first element is added to the body, then a fifth insulator is deposited on the fourth insulator, and then a third insulator is deposited on the fourth insulator. A sixth insulator is formed on the sidewall of the first conductor by removing a part of the fifth insulator, Then, a third conductor is formed on the sixth insulator, and then a seventh insulator is formed on the third conductor. The surface of the seventh insulator is planarized by chemical mechanical polishing while the third conductor is formed. and removing a region including both the first region having the seventh insulator and the second region having the seventh insulator. Thus, a fourth conductor, a fifth conductor, and an eighth insulator are formed, and the first transistor A ninth insulator is then formed on the sixth insulator, the fourth conductor and the fifth conductor. In this case, the first region and the second region are a first region and a second region. The second conductor overlaps the first insulator and the ninth insulator, and the first insulator and the ninth insulator have a higher hydrogen permeability than the eighth insulator. At least one of the first insulator and the ninth insulator is low in oxygen and aluminum. It is preferred to have a minium.

[0018] In the above configuration, the sixth insulator may be called a sidewall insulating layer or a sidewall insulating film. In the above configuration, the first element is tungsten, aluminum, titanium, or the like. At least one of the following elements: zinc, magnesium, vanadium, antimony, arsenic, and sulfur It may include any one of them. Effect of the Invention

[0019] It is possible to provide a fine transistor. Or, a transistor with small parasitic capacitance. Alternatively, a transistor with high frequency characteristics can be provided. It is possible to provide a transistor having good electrical characteristics. Alternatively, a transistor with low power consumption can be provided. It is also possible to provide a highly reliable transistor. The present invention provides novel transistors or at least some of these transistors. It is possible to provide a semiconductor device having at least one of the above.

[0020] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these are described in the specification. The above will become apparent from the description, drawings, claims, etc. From the above description, it is possible to extract other effects. [Brief description of the drawings]

[0021] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention. [Diagram 2] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention. [Diagram 3] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 4] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 5] FIG. 1 is a top view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 6] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 7] 1A to 1C illustrate an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 8] 1A to 1C illustrate an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 9] 1A to 1C illustrate an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 10] 1A to 1C illustrate an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 11] 1A to 1C illustrate an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 12] 1A to 1C illustrate an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 13] 1A to 1C illustrate an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 14] 1A to 1C illustrate an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 15] 1A to 1C illustrate an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 16] 1A to 1C illustrate an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 17] 1A to 1C illustrate an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 18] 1A to 1C illustrate an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 19] 1A to 1C illustrate an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 20] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention. [Figure 21] FIG. 2 is a diagram for explaining an energy band structure. [Figure 22]FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 23] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 24] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 25] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 26] 1A to 1C illustrate an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 27] Cs-corrected high-resolution TEM image of a cross section of CAAC-OS, and a schematic cross-sectional diagram of CAAC-OS. [Figure 28] Cs-corrected high-resolution TEM image of the CAAC-OS in the plane. [Figure 29] 13A to 13C show structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. [Diagram 30] Electron diffraction pattern of CAAC-OS. [Diagram 31] FIG. 1 shows the change in the crystal part of an In-Ga-Zn oxide due to electron irradiation. [Diagram 32] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 33] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 34] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 35] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 36] FIG. 1 is a circuit diagram of a semiconductor device according to one embodiment of the present invention. [Figure 37] FIG. 1 is a circuit diagram of a semiconductor device according to one embodiment of the present invention. [Figure 38] FIG. 2 is a block diagram showing an example of the configuration of a CPU. [Figure 39] FIG. 1 is a circuit diagram showing an example of a memory element. [Diagram 40] FIG. 1 illustrates an example of an imaging apparatus. [Diagram 41] FIG. 1 illustrates an example of an imaging apparatus. [Diagram 42] FIG. 1 illustrates an example of an imaging apparatus. [Diagram 43] 1A to 1C are diagrams illustrating an example of the configuration of a pixel. [Diagram 44] 1A to 1C are diagrams illustrating an example of the configuration of a pixel. [Diagram 45] FIG. 1 is a circuit diagram showing an example of an imaging device. [Figure 46] FIG. 1 is a cross-sectional view showing an example of the configuration of an imaging apparatus. [Figure 47] FIG. 1 is a cross-sectional view showing an example of the configuration of an imaging apparatus. [Figure 48] 1A and 1B are a block diagram and a circuit diagram illustrating an example of a display device. [Figure 49] FIG. 1 is a block diagram illustrating an example of a display device. [Figure 50] 1A and 1B illustrate an example of a display device. [Figure 51] 1A and 1B illustrate an example of a display device. [Figure 52] FIG. 2 is a diagram illustrating an example of a display module. [Figure 53] FIG. 1 is a block diagram illustrating an example of an RF tag. [Figure 54] FIG. 1 is a diagram explaining an example of how to use an RF tag. [Figure 55] FIG. 1 is a perspective view showing a cross-sectional structure of a package using a lead frame type interposer. [Figure 56] 1A to 1C are diagrams illustrating examples of electronic devices. [Figure 57] FIG. 2 is a top view showing an example of a film forming apparatus. [Figure 58] FIG. 1 is a cross-sectional view showing an example of a film forming apparatus. [Figure 59] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 60] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above embodiment, and various changes and modifications may be made in the form and details without departing from the spirit and scope of the present invention. It will be easily understood by those skilled in the art that the present invention can be realized by the following embodiments. However, the present invention should not be construed as being limited to the above description. In the drawings, the same reference numerals are used to denote the same parts or parts having similar functions. , and repeated explanations may be omitted.

[0023] In addition, the position, size, range, etc. of each component shown in the drawings are intended to facilitate understanding of the invention. For this reason, the actual location, size, range, etc. may not be shown. The present invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings, etc. For example, in the actual manufacturing process, layers and resist masks are formed by processes such as etching. Although the number may be unintentionally reduced, it may be omitted to make it easier to understand. .

[0024] In addition, in the drawings, in order to facilitate understanding of the invention, illustration of some components is omitted. Also, some hidden lines may be omitted.

[0025] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components. It does not indicate any order or ranking, such as the order of processes or stacking. In addition, even if a term is not accompanied by an ordinal number in this specification, etc., it is possible to avoid confusion of the constituent elements. In order to avoid this, ordinal numbers may be used in the claims. Even if a term is given an ordinal number in the specification, a different ordinal number may be given in the claims. In addition, even if a term is given an ordinal number in this specification, etc., In the claims, ordinal numbers may be omitted.

[0026] In addition, the terms "electrode" and "wiring" used in this specification and the like refer to these components functionally. This is not intended to be limiting. For example, an "electrode" may be used as a part of a "wire." , and vice versa. Furthermore, the terms "electrode" and "wiring" may be used interchangeably to refer to the plural "electrodes" and "wirings." This also includes cases where the wiring is formed integrally.

[0027] In this specification, the terms "upper" and "lower" refer to the positional relationship of components directly above or below each other. It is not limited to being directly under and in direct contact with the insulator. If the expression is "electrode B", electrode B does not need to be formed directly on insulator A. This does not exclude the inclusion of other components between the insulator A and the electrode B.

[0028] In addition, the source and drain functions may be different in some cases, such as when transistors of different polarities are used. When the direction of the current changes during circuit operation, they may be interchanged depending on the operating conditions. Therefore, it is difficult to determine which is the source and which is the drain. In this specification, the terms source and drain can be used interchangeably. It shall be so.

[0029] In addition, in the present specification and the like, when it is explicitly stated that X and Y are connected, In this case, X and Y are electrically connected, and X and Y are functionally connected. The case where X and Y are directly connected is also considered to be disclosed in the present specification. Therefore, the present invention is not limited to a specific connection relationship, for example, a connection relationship shown in a drawing or a sentence. Any connections other than those shown in the drawings or text shall be deemed to be included in the drawings or text. do.

[0030] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a "device having some electrical function." "of" is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects. Therefore, even if it is expressed as "electrically connecting", in the actual circuit, In some cases, there may be no physical connection, just wires running along the line.

[0031] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. When the transistor is on, the gate electrode overlaps with the semiconductor (the part through which current flows). In the region where a channel is formed (also called a "channel forming region"), The source (source region or source electrode) and the drain (drain region or drain electrode) Note that in one transistor, the channel length is the distance between the In other words, the channel length of a transistor is not always the same. Therefore, in this specification, the channel length is defined as the area in which the channel is formed. It can be any one of the values, the maximum value, the minimum value or the average value in the range.

[0032] The channel width is the width of the semiconductor (or transistor) when it is in the on state. The area where the gate electrode overlaps with the electrode (the area where the current flows) forms a channel. This refers to the length of the part of the region where the source and drain face each other. In a transistor, the channel width does not necessarily have the same value in all regions. That is, The channel width of a transistor may not be determined to a single value. In the fine print, the channel width is any one value or the maximum value in the region where the channel is formed. , the minimum or average value.

[0033] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width (also called the effective channel width) and the The channel width that is actually used (also called the "apparent channel width") may differ from the actual channel width. For example, When the gate electrode covers the side of the semiconductor film, the effective channel width is For example, the effect of fine and fast current may become unnegligible. In a transistor where the electrodes cover the side of the semiconductor, the portion of the channel region formed on the top surface of the semiconductor In this case, the proportion of the channel region formed on the side of the semiconductor may be large. In the case of , the effective channel width is larger than the apparent channel width.

[0034] In such cases, it may be difficult to estimate the effective channel width through actual measurements. For example, to estimate the effective channel width from the design value, the shape of the semiconductor must be known. Therefore, if the shape of the semiconductor is not known accurately, Channel width is difficult to measure accurately.

[0035] Therefore, in this specification, the apparent channel width is referred to as the "enclosed channel width (SCW: S In addition, in this specification, In this document, when simply referring to channel width, it means enclosed channel width or apparent channel width. In this specification, when the term "channel width" is used, It may refer to the effective channel width. Note that channel length, channel width, and effective channel The channel width, apparent channel width, and enclosed channel width are determined by analyzing cross-sectional TEM images. The value can be determined, for example, by

[0036] In addition, the field effect mobility of the transistor and the current value per channel width are calculated. In some cases, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0037] The impurities in a semiconductor are, for example, substances other than the main components that make up the semiconductor. Elements with a concentration of less than 0.1 atomic percent can be considered impurities. For example, The DOS (Density of State) of the semiconductor increases and carrier mobility The degree of conductivity may decrease, and the crystallinity may decrease. In the case of a conductor, impurities that change the properties of the semiconductor include, for example, elements of Group 1, Group elements, Group 13 elements, Group 14 elements, Group 15 elements, and elements other than the main components of oxide semiconductors transition metals, especially hydrogen (which is also contained in water), lithium, sodium , silicon, boron, phosphorus, carbon, nitrogen, etc. In the case of oxide semiconductors, for example, hydrogen In addition, if the semiconductor is silicon, oxygen vacancies may be formed due to the inclusion of impurities such as In this case, impurities that change the properties of a semiconductor include, for example, oxygen and group 1 elements excluding hydrogen. These include the elements of Group 2, Group 13, and Group 15.

[0038] In addition, in this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Approximately parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. In addition, "perpendicular" and "orthogonal" mean that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it includes the case where the angle is between 85° and 95°. "Perpendicular" refers to two straight lines that form an angle between 60° and 120°.

[0039] In this specification and the like, the terms "same," "the same," "equal," and "equal" are used to refer to counting values ​​and measurement values. When referring to "uniform" or "uniform" (including their synonyms), excluding the above and include a margin of error of plus or minus 20%.

[0040] In this specification, the etching step is performed after the photolithography step. In this case, unless otherwise specified, the resist mask formed in the photolithography process is It is to be removed after the etching process is completed.

[0041] In this specification, the high power supply potential VDD (hereinafter, simply referred to as "VDD" or "H potential") The low power supply potential VSS is a power supply potential that is higher than the low power supply potential VSS. The VSS potential (hereinafter simply referred to as "VSS" or "L potential") is the potential lower than the high power supply potential VDD. The power supply potential is lower than the ground potential. For example, if VDD is at ground potential, VSS is at a potential lower than ground potential, When VSS is at ground potential, VDD is at a potential higher than ground potential.

[0042] The words "membrane" and "layer" may be interchangeable depending on the circumstances. For example, the term "conductive layer" may be replaced with "conductive Alternatively, for example, the term "insulating film" may be used. In some cases, the terminology may be changed to the term "insulating layer."

[0043] In this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. vinegar.

[0044] (Embodiment 1) In this embodiment, a structural example of a semiconductor device of one embodiment of the present invention will be described.

[0045] <Configuration example> FIG. 1A is a top view of a semiconductor device according to one embodiment of the present invention. 1(B) shows a cross section taken along dashed line L1-L2 and a cross section taken along dashed line W1-W2 in FIG. The semiconductor device shown in FIG. 1 includes a substrate 101, an insulator 102 on the substrate 101, and a A transistor 100, an insulator 110 covering the transistor 100, and an insulating layer on the insulator 110. and an edge 111.

[0046] The transistor 100 includes an oxide layer 104 on an insulator 103 and an insulating layer 104 on the oxide layer 104. A body 105, a conductor 106 on the insulator 105, and an insulator formed on the side wall of the conductor 106. 108, and a conductor 109a and a conductor 109b contacting the side of the oxide layer 104 and the side of the insulator 108. The insulator 108 may be adjacent to the side of the conductor 106. preferable.

[0047] The conductor 106 serves as a first gate electrode of the transistor 100, and the conductors 109a and The insulating layer 109b is a source electrode or a drain electrode of the transistor 100. Bodies 105 preferably each function as a gate insulator for transistor 100. .

[0048] Here, the oxide layer 104 can be formed as a single layer or as multiple layers. For example, As shown in (B), the oxide layer 104 is made up of an oxide layer 104a, an oxide layer 104b, and an oxide layer 104c. It is preferable that the oxide layer 104b is formed of three layers, the oxide layer 104a, the oxide layer 104b, and the oxide layer 104c. and oxide layer 104c is formed on and in contact with oxide layer 104b.

[0049] The oxide layers 104a and 104c are closer to being insulators than the oxide layer 104b. Therefore, when a gate voltage is applied, the oxide layer 104a, the oxide layer 104b, and the oxide layer 10 Of these, the oxide layer 104b is more likely to form a channel than the oxide layer 104c. The oxide layer 104a and the oxide layer 104c may be referred to as insulators.

[0050] The transistor 100 shown in FIG. 1B includes an oxide layer 104a on an insulator 103 and an oxide The oxide layer 104b is in contact with the upper surface of the oxide layer 104a, and the oxide layer 104b is in contact with the upper surface of the oxide layer 104b. The insulating layer 108 is a dielectric layer 104c and an insulator 105 on the oxide layer 104c. The insulator 108 has a region in contact with the upper surface of the insulator 105. The lower surface of the insulator 108 is in contact with the upper surface of the conductor 106. The conductor 109a and the conductor 109b are formed on the oxide layer 104. b has an area in contact with the upper surface of

[0051] In addition, the transistor 100 has a region in the oxide layer 104 that overlaps with the insulator 108 and a region in the oxide layer 104 that overlaps with the insulator 108. The region overlapping with the conductor 109a and the conductor 109b contains a compound different from the main component of the oxide layer 104. The metal element 131 is included in the insulator 105, the oxide layer 104, and the The metal element 131 may be included in the insulator 103. The end of the region 135 is shown by a dashed line in FIG. 1(B) as an example. Region 135 is formed above the dashed line indicating the end of region 135 .

[0052] In the oxide layer 104, the region 135 is the source region of the transistor 100 or Therefore, the region sandwiched between the regions 135 of the oxide layer 104 can function as a drain region. It can function as a channel forming region.

[0053] As shown in FIG. 1B, the height of the upper end of the insulator 110 and the height of the conductor 109a and the conductor It is preferable that the heights of the upper ends of the insulator 110 and the conductor 109b are approximately the same. The upper surfaces of the conductor 109a, the conductor 109b, the insulator 108, and the insulator 107 are continuous and flat. It is preferable that the surface is flat, and an insulator 111 is formed on the flat surface.

[0054] In FIG. 1 and the like, the oxide layer 104 is one of the oxide layers 104a and 104c. A structure not including either of them may also be used.

[0055] As shown in FIG. 1B, the insulator 103 may have a protrusion. In that case, the oxide The layer 104 is preferably formed in contact with the upper portion of the protrusion. The sum of the thicknesses of the oxide layers 104a and 104b is greater than the sum of the thicknesses of the oxide layers 104c and 104b. In some cases, the characteristics of the transistor 100 can be improved by increasing the be.

[0056] FIG. 59(A) shows a cross section corresponding to the dashed line L1-L2 in the cross section shown in FIG. 1(B). The semiconductor device according to one embodiment of the present invention may be modified as shown in FIG. In other words, the insulator 107 does not necessarily have to be provided on the conductor 106. It is more preferable to have an insulator 107 on the conductor 106. By providing the body 107, the manufacturing process of the transistor 100 can be stabilized. By stabilizing the manufacturing process, the characteristics of the transistor 100 can be improved. It is possible to do so.

[0057] The transistor 100 also includes an insulator 118 and a conductor 117 on the insulator 102, In the example shown in FIG. 1B, the conductor 117 is formed so as to fill the insulator 118. The insulator 103 is formed so as to fill the insulator 118. 18. Here, conductor 117 is formed as the second gate electrode of transistor 100. The potential of the second gate electrode of the transistor 100 is preferably the potential of the first gate electrode of the transistor 100. It may be the same potential as the input, the ground potential (GND potential), or any other potential. By changing the potential of the second gate electrode independently of the potential of the first gate electrode, The threshold voltage of the transistor can be changed.

[0058] By providing the conductor 106 and the conductor 117 with the oxide layer 104 interposed therebetween, By setting the conductor 106 and the conductor 117 at the same potential, the carriers are Since the area in which the carriers flow becomes larger in the film thickness direction, the amount of carrier movement increases. As a result, the on-state current of the transistor 100 is increased and the field effect mobility is also increased. .

[0059] Thus, transistor 100 is a transistor having a large on-current relative to its area. That is, the area occupied by the transistor 100 is required for the required on-current. Therefore, a highly integrated semiconductor device can be realized.

[0060] In addition, since the first gate electrode and the second gate electrode are formed of a conductive layer, The function of preventing the electric field generated outside the device from acting on the semiconductor layer in which the channel is formed (particularly The second gate electrode is electrically isolated from the semiconductor layer. By forming the second gate electrode larger and covering the semiconductor layer with the second gate electrode, the electric field shielding function can be improved. can be done.

[0061] The conductor 106 and the conductor 117 each have a function of shielding an electric field from the outside. Therefore, the electric charges of the charged particles generated above the conductor 106 and below the conductor 117 are oxidized. As a result, the channel forming region of the semiconductor layer 104 is not affected. Applying a negative charge to the GBT (Gate Bias-Temperature) strain In addition, the conductors 106 and 117 are connected to the drain electrode The electric field generated from the drain electrode can be blocked from acting on the semiconductor layer. It is possible to suppress the fluctuation in the on-current rising voltage caused by the voltage fluctuation. This effect is evident when a potential is applied to the conductor 106 and the conductor 117. Occurs in writing.

[0062] The BT stress test is a type of accelerated test that detects the transitions that occur during long-term use. It is possible to evaluate the characteristic changes (aging) of transistors in a short time. The amount of change in the threshold voltage of a transistor before and after testing is an important indicator for investigating reliability. The smaller the change in threshold voltage before and after the BT stress test, the higher the reliability. It can be said that this is a transistor with high performance.

[0063] The conductor 106 and the conductor 117 are also included. By making the transistors have the same potential, the amount of variation in the threshold voltage is reduced. At the same time, the variation in electrical characteristics between the stars is reduced.

[0064] In addition, the transistor having the second gate electrode has a positive charge applied to the gate +GB The change in threshold voltage before and after the T stress test was also observed for a transistor without a second gate electrode. Smaller than Zysta.

[0065] In addition, when light is incident from the second gate electrode side, the second gate electrode is provided with a light-shielding property. By forming the conductive film, it is possible to prevent light from entering the semiconductor layer from the second gate electrode side. This prevents the semiconductor layer from being photodegraded and the threshold voltage of the transistor is shifted. This can prevent deterioration of electrical characteristics such as thermal breakdown.

[0066] In addition, in the cross section shown in FIG. 1(B) corresponding to the dashed line L1-L2, The end 315 of the insulator 108 is located outside the end 316 of the conductor 117. As shown in FIG. 0(A), the positions of the end 315 and the end 316 may be approximately aligned. As shown in FIG. 60(B), the end 315 may be located more inward than the end 316.

[0067] In addition, in the semiconductor device of one embodiment of the present invention, an insulator 112 over an insulator 111 and an insulator 11 0, a contact plug 113 formed to fill the insulator 111 and the insulator 112 a, contact plug 113b, contact plug 113c, and the insulator 112 The conductor 114 may include a conductor 114a, a conductor 114b, and a conductor 114c. a, the conductor 114b, and the conductor 114c can be used for, for example, wiring. can.

[0068] In addition, the semiconductor device according to one embodiment of the present invention includes a semiconductor element between the substrate 101 and the insulator 102. It may have children, etc.

[0069] FIG. 2A is a top view of a semiconductor device according to one embodiment of the present invention. 2, a cross section taken along a dashed line L1-L2 and a cross section taken along a dashed line W1-W2 are shown. The semiconductor device shown in FIG. The structure of the insulator 108 in the semiconductor device 100 is different from that in FIG. 1. In FIG. 1(B), 2B, the surface of the conductor 106 is approximately aligned with the bottom surface of the insulator 108. The surface of the insulator 108 is approximately the same as the bottom surface of the oxide layer 104c. In FIG. 2B, the insulator 108 is in contact with the top surface of the oxide layer 104b. In addition, the oxide layer 104c and the end of the insulator 105 are insulated in FIG. 2B, the edge of the conductor 106 is approximately aligned with the edge of the conductor 108. I will.

[0070] As shown in FIG. 2B, the transistor 100 has a side surface of the oxide layer 104b. It may have a contacting insulator 108b.

[0071] As shown in FIG. 3A, the end of the oxide layer 104c is closer to the end of the insulator 108 than the end of the oxide layer 104c. In the transistor 100 shown in FIG. The end of the oxide layer 104c is located outside the end of the insulator 108. The portions are located outside the ends of the conductors 109a and 109b.

[0072] As shown in FIG. 59(B), the end of the oxide layer 104c and the end of the insulator 105 The oxide may be located outside the end of the conductor 109a or the conductor 109b. The end of the insulating layer 104c and the end of the insulator 105 may be approximately aligned. It is not necessary for them to be aligned as shown.

[0073] Also, as shown in FIG. 59(C), the end of the insulator 105 is located outside the insulator 108. In addition, the conductor 109 may be located inside the ends of the conductor 109a and the conductor 109b. In FIG. 59(C), the end of the oxide layer 104c is not aligned with the end of the conductor 109a or the conductor 109b. Although an example in which the fixing portion is located on the outside of the part is shown, it may be located on the inside.

[0074] The end of the oxide layer 104c is connected to the end of the conductor 109a and the end of the conductor 109b. In this case, the conductor 109a and the conductor 109b may be located outside the Between the insulator 103, there is an oxide layer 104c.

[0075] As shown in FIG. 4, the end of the oxide layer 104c is approximately aligned with the oxide layer 104b. Good too.

[0076] <Explanation of components>

[0077] [Oxide layer 104] The oxide layer 104 includes an oxide layer 104a, an oxide layer 104b, and an oxide layer 104c. It is preferred to have a laminated configuration.

[0078] For example, an oxide semiconductor containing indium (In) is used as the oxide layer 104. For example, when the oxide semiconductor contains indium, the carrier mobility (electron mobility) is improved. In addition, it is preferable that the oxide semiconductor contains an element M.

[0079] The element M is preferably aluminum, gallium, yttrium or tin. Other elements that can be used for element M include boron, silicon, titanium, iron, and nickel. Ru, Germanium, Zirconium, Molybdenum, Lanthanum, Cerium, Neodymium, Hafnium However, the element M is the same as above. In some cases, it is acceptable to combine multiple elements of the above. For example, the element M has a bond energy with oxygen of The element M has a high energy. For example, the element M increases the energy gap of an oxide semiconductor. In addition, the oxide semiconductor preferably contains zinc. Semiconductors may be more prone to crystallization if they contain zinc.

[0080] However, the oxide layer 104 is not limited to an oxide containing indium. For example, indium oxide, zinc tin oxide, gallium tin oxide, gallium oxide, etc. However, oxides containing zinc, oxides containing gallium, oxides containing tin, etc. may be used. I don't.

[0081] The oxide layer 104 is formed using, for example, an oxide semiconductor having a wide energy gap. The energy gap of the oxide semiconductor used in the oxide layer 104 is, for example, 2.5 eV or more and 4. 2 eV or less, preferably 2.8 eV to 3.8 eV, and more preferably 3 eV to 3 It is less than .5 eV.

[0082] Oxide semiconductors are formed by sputtering, CVD (Chemical Vapor Deposition) osition) method (MOCVD(Metal Organic Chemical V apor deposition) method, ALD (Atomic Layer Depos) method ition), thermal CVD or PECVD (Plasma Enhanced Ch (including, but not limited to, empirical vapor deposition) MBE (Molecular Beam Epitaxy) method or PLD (Pulse d Laser Deposition) method. Plasma CVD method The MOCVD method, ALD method, or thermal CVD method can provide high-quality films at relatively low temperatures. When a deposition method that does not use plasma is used, damage to the deposition surface is less likely to occur. Furthermore, a film with fewer defects can be obtained.

[0083] The CVD and ALD methods are deposition methods in which particles emitted from a target are deposited. It is a film forming method in which a film is formed by a reaction on the surface of the object to be treated. Therefore, this is a film forming method that is not easily affected by the shape of the workpiece and has good step coverage. In addition, the ALD method has excellent step coverage and thickness uniformity, making it ideal for achieving high aspect ratios. However, the ALD method is relatively slow in forming a film. Because the deposition rate is slow, it should be used in combination with other deposition methods such as CVD, which has a faster deposition rate. may be preferred.

[0084] In the CVD and ALD methods, the composition of the resulting film is controlled by the flow rate ratio of the source gases. For example, in the CVD and ALD methods, the flow rate ratio of the source gases can be adjusted to any value. In addition, for example, in the CVD method and the ALD method, the film formation By changing the flow rate ratio of the source gas while heating, a film with a continuously changing composition can be formed. When forming a film while changing the flow rate ratio of the source gas, multiple film forming chambers can be used. Compared to deposition using a vacuum, the time required for deposition is shorter due to the time required for transportation and pressure adjustment. Therefore, the productivity of the transistor and the semiconductor device can be improved. There may be cases where this occurs.

[0085] For example, the oxide layer 104 may be formed by thermal CVD using InGaZnO X (X>0) Film is formed In the case of trimethylindium (In(CH 3 ) 3 ), trimethylgallium (Ga( CH 3 ) 3 ), and dimethylzinc (Zn(CH 3 ) 2 ) is used. Not limited to the above, triethylgallium (Ga(C)) may be used instead of trimethylgallium. 2 H 5 ) 3 ) can be used instead of dimethyl zinc, and diethyl zinc (Zn(C 2H 5 ) 2 ) can also be used.

[0086] For example, the oxide layer 104 may be formed by an ALD method using InGaZnO X (X>0) Film is formed In the case of 3 ) 3 Gas and O 3 The gases were repeatedly introduced to produce InO 2 Forming layers Then, Ga(CH 3 ) 3 Gas and O 3 The gas is introduced repeatedly in sequence to form a GaO layer. , and then Zn(CH 3 ) 2 Gas and O 3 The gases are introduced repeatedly in sequence to form a ZnO layer. The order of these layers is not limited to this example. O 2 Layer and InZnO 2 Layers, GaInO layers, ZnInO layers, GaZnO layers and other mixed compounds A layer may be formed. 3 H bubbled with inert gas such as Ar instead of gas 2 O gas may be used, but it should be O gas that does not contain H. 3 It is preferable to use In(C H 3 ) 3 Instead of gas, In(C 2 H 5 ) 3 Gas and tris(acetylacetonato) ink Tris(acetylacetonato)indium may also be used. c) 3 Also called Ga(CH 3 ) 3 Instead of gas, Ga(C 2 H 5 ) 3 Gas and Tori Tris(acetylacetonato)gallium may also be used. ) Gallium is Ga(acac) 3 Also called Zn(CH 3 ) 2 Gas and zinc acetate The gas species is not limited to these.

[0087] When oxide semiconductor is deposited by sputtering, in order to reduce the number of particles, It is preferable to use a target containing M. Also, it is preferable to use an oxide target having a high atomic ratio of element M. When using a target containing indium, the electrical conductivity of the target may be reduced. When using a sintered material, the conductivity of the target can be increased, making DC and AC discharge easier. This makes it easier to handle large-area substrates. This improves the productivity of semiconductor devices. It is possible.

[0088] In addition, when forming an oxide semiconductor film by sputtering, the atomic ratio of the target is I n:M:Zn is 3:1:1, 3:1:2, 3:1:4, 1:1:0.5, 1:1:1, 1 :1:2, 1:4:4, 4:2:4.1 etc. would be good choices.

[0089] When an oxide semiconductor film is formed by a sputtering method, the atomic ratio of the target may deviate. In particular, the atomic ratio of zinc in the target is The atomic ratio of the formed film may be smaller than the atomic ratio. When the ratio of the number of atoms of zinc contained is between 40 atomic % and 90 atomic % There is.

[0090] The oxide layer 104a and the oxide layer 104c are formed of oxygen other than the oxygen constituting the oxide layer 104b. It is preferable that the metal layer is made of a material containing one or more of the same metal elements. When such a material is used, the interface between the oxide layer 104a and the oxide layer 104b, and The interface state can be made less likely to occur at the interface between the oxide layer 104c and the oxide layer 104b. This makes it difficult for carriers to be scattered or captured at the interface, and the field effect of the transistor is improved. It is also possible to improve the mobility of the transistor. Therefore, it is possible to realize a semiconductor device having good electrical characteristics. This makes it possible.

[0091] The thickness of the oxide layer 104a and the oxide layer 104c is preferably 3 nm or more and 100 nm or less. The thickness of the oxide layer 104b is preferably 3 nm or more and 50 nm or less. 00 nm or less, preferably 3 nm or more and 100 nm or less, and more preferably 3 nm or more and 50 nm or less.

[0092] The oxide layer 104b is an In-M-Zn oxide (an oxide containing In, the element M, and Zn). and when the oxide layer 104a and the oxide layer 104c are also In-M-Zn oxide, The oxide layer 104a and the oxide layer 104c are formed of In:M:Zn=x 1 :y 1 :z 1 [Atomic number ratio], and the oxide layer 104b is In:M:Zn=x 2 :y 2 :z 2 [Atomic ratio], y 1 / x 1 y 2 / x 2 The oxide layer 104a, the oxide layer 104c, and the oxide layer 104b are larger than the oxide layer 104a. Preferably, y is selected as the y-type oxide layer 104b. 1 / x 1y 2 / x 2 More than 1.5 times larger than The oxide layer 104a, the oxide layer 104c, and the oxide layer 104b are selected so that the thickness of the oxide layer 104a, the oxide layer 104c, and the oxide layer 104b is larger than the thickness of the oxide layer 104b. More preferably, y 1 / x 1 y 2 / x 2 The oxide layer 104a is more than twice as large as the The oxide layer 104c and the oxide layer 104b are selected. More preferably, y 1 / x 1 but y 2 / x 2 The oxide layer 104a, the oxide layer 104c, and the oxide layer 104b are three times larger than the oxide layer 104a. At this time, in the oxide layer 104b, y 1 x 1 That's all. This is preferable because it can provide stable electrical characteristics to the transistor. 1 x 1 Three times Above this value, the field effect mobility of the transistor decreases, so 1 x 1 Three times It is preferable that the oxide layer 104a and the oxide layer 104c have the above-mentioned structure. As a result, the oxide layers 104a and 104c have a smaller oxygen deficiency than the oxide layer 104b. It is possible to make the layer less susceptible to defects.

[0093] When the oxide layer 104a is an In-M-Zn oxide, the sum of In and M is 100a. When In is less than 50 atomic %, M is preferably less than 50 atomic %. ic% or more, more preferably In is less than 25 atomic % and M is 75 atomic % or less. When the oxide layer 104b is an In-M-Zn oxide, In and When the sum of M is 100 atomic %, In is preferably higher than 25 atomic %. Preferably, M is less than 75 atomic %, and more preferably, In is more than 34 atomic %. In addition, the oxide layer 104c is an In-M-Zn oxide. When the sum of In and M is 100 atomic %, In is preferably 50 atomic % or less. %, M is higher than 50 atomic %, and more preferably In is 25 atomic %. % or less, and M is higher than 75 atomic %. The same type of oxide as that of the oxide layer 104a may be used.

[0094] For example, the oxide layer 104a containing In or Ga and the oxide layer 104b containing In or Ga Layer 104c is In:Ga:Zn=1:3:2, 1:3:4, 1:3:6, 1:6: In-Ga-ZnO oxide formed using targets with atomic ratios of 4, 1:9:6, etc. Formed using targets with atomic ratios such as In:Ga=1:9 or 7:93. The oxide layer 104b may be, for example, an In-Ga oxide. Using targets with atomic ratios of In:Ga:Zn=1:1:1 or 3:1:2, The oxide layer 104a and the oxide layer 104b may be formed of In-Ga-Zn oxide. The atomic ratios of the oxide layer 104b are the above atomic ratios with an error of ±20. Includes % variation.

[0095] The oxide layer 104b has a higher electron affinity than the oxide layer 104a and the oxide layer 104c. For example, the oxide layer 104b is made of the oxide layer 104a and the oxide layer 104b. The electron affinity of the layer 104c is 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or less. More preferably, the oxide is 0.15 eV or more and 0.4 eV or less. The electron affinity is the energy difference between the vacuum level and the bottom of the conduction band.

[0096] Indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, it is preferable that the oxide layer 104c contains indium gallium oxide. The Ga atom ratio [Ga / (In+Ga)] is, for example, 70% or more, preferably 80% or more. More preferably, it is set to 90% or more.

[0097] However, the oxide layer 104a and / or the oxide layer 104c is made of gallium oxide. For example, when gallium oxide is used as the oxide layer 104c, the electrode 105a Alternatively, the leakage current occurring between the electrode 105b and the conductor 106 can be reduced. That is, the off-state current of the transistor 100 can be reduced.

[0098] The oxide layer 104a and the oxide layer 104c have a higher electron affinity than, for example, the oxide layer 104b. Since the stress is smaller, it is closer to an insulator than the oxide layer 104b. Therefore, when a gate voltage is applied, Among the oxide layers 104a, 104b, and 104c, the oxide layer 104b Channels are easily formed in the

[0099] In addition, a transistor using an oxide semiconductor in the semiconductor layer where the channel is formed ("OS transistor") In order to give stable electrical characteristics to the oxide semiconductor, it is necessary to reduce the insulators in the oxide semiconductor. The oxide layer 104b is made intrinsic or substantially intrinsic by reducing impurities and oxygen vacancies. For example, the oxide layer 104b may be formed of an oxide semiconductor that can be regarded as being non-oxidative. By supplying at least one oxide layer, oxygen vacancies may be reduced. The channel formation region in the insulating film 4b is an oxide semiconductor that can be regarded as intrinsic or substantially intrinsic. is preferred.

[0100] In addition, at least the oxide layer 104b of the oxide layer 104 is CAAC-OS (CA xis Aligned Crystalline Oxide Semiconductor It is preferable to use the CAAC-OS. Explain in detail.

[0101] Here, the regions that are not CAAC or regions other than the regions having the c-axis orientation are at least In any case, the oxide layer 104b preferably accounts for less than 20% of the entire oxide semiconductor film. .

[0102] The CAAC-OS has a dielectric anisotropy. The dielectric constant in the c-axis direction is larger than that in the b-axis direction. The transistor with the gate electrode arranged in the c-axis direction using CAAC-OS has Since the dielectric constant of is large, the electric field generated from the gate electrode easily reaches the entire CAAC-OS. This makes it possible to reduce the subthreshold swing value (S value). Transistors that use CAAC-OS as the body film are less susceptible to increases in S value due to miniaturization.

[0103] In addition, the dielectric constant of CAAC-OS in the a-axis and b-axis directions is small, so the source and drain Therefore, the effect of the electric field between the insulators is reduced. This makes it difficult for defects such as short circuiting to occur, thereby improving the reliability of the transistor.

[0104] Here, the channel length modulation effect is the effect that occurs when the drain voltage is higher than the threshold voltage. This refers to the phenomenon in which the depletion layer expands from the drain side, shortening the effective channel length. The channel effect is a phenomenon in which the electrical properties such as the threshold voltage decrease due to the shortening of the channel length. The smaller the transistor, the greater the deterioration of electrical characteristics due to these phenomena. is likely to occur.

[0105] [Energy band structure of oxide semiconductor film] Here, the oxide layer 104a, the oxide layer 104b, and the oxide layer 104c are stacked. The function and effect of the oxide layer 104 will be described with reference to the energy The following explanation will be given using a band structure diagram. Figure 21(A) shows the band structure of the A1-A2 dashed line in Figure 1(B). FIG. 21(A) shows the energy band structure of the region indicated by the arrow. 1 shows the energy band structure of the channel formation region of a transistor 100.

[0106] In Figure 21(A), Ec382, Ec383a, Ec383b, Ec383c, Ec38 6 are the insulator 103, the oxide layer 104a, the oxide layer 104b, and the oxide layer 104 c shows the energy of the bottom of the conduction band of the insulator 105. An example in which the material layer 104a is not used will be described.

[0107] Here, the electron affinity is the difference between the vacuum level and the energy at the top of the valence band (the "ionization potential"). It is also called the potential. It is the value obtained by subtracting the energy gap from the potential. The chip is equipped with a spectroscopic ellipsometer (HORIBA JOBIN YVON UT-300 The energy difference between the vacuum level and the top of the valence band can be measured using ultraviolet photoelectron Spectroscopic analysis (UPS: Ultraviolet Photoelectron Spectrum) This can be measured using a fluoroscopy device (PHI VersaProbe).

[0108] The In- The energy gap of Ga-Zn oxide is about 3.5 eV and the electron affinity is about 4.5 eV. In addition, the In was formed using a target with an atomic ratio of In:Ga:Zn=1:3:4. The energy gap of Ga-Zn oxide is about 3.4 eV, and the electron affinity is about 4.5 eV. In addition, the I was formed using a target with an atomic ratio of In:Ga:Zn=1:3:6. The energy gap of n-Ga-Zn oxide is about 3.3 eV, and the electron affinity is about 4.5 eV. In addition, the film was formed using a target with an atomic ratio of In:Ga:Zn=1:6:2. The energy gap of In-Ga-Zn oxide is about 3.9 eV, and the electron affinity is about 4.3 e V. The target was formed with an atomic ratio of In:Ga:Zn=1:6:8. The energy gap of the In-Ga-Zn oxide is about 3.5 eV and the electron affinity is about 4.4 The atomic ratio of In:Ga:Zn was 1:6:10. The energy gap of the synthesized In-Ga-Zn oxide is about 3.5 eV, and the electron affinity is about 4 0.5 eV. In addition, a target with an atomic ratio of In:Ga:Zn=1:1:1 was used. The energy gap of the formed In-Ga-Zn oxide is about 3.2 eV, and the electron affinity is about The atomic ratio of the target was In:Ga:Zn=3:1:2. The energy gap of the In-Ga-Zn oxide formed by this method is about 2.8 eV, and the electron affinity is It is about 5.0 eV.

[0109] Since insulators 103 and 105 are insulators, Ec382 and Ec386 are It is closer to the vacuum level than Ec383a, Ec383b, and Ec383c (it has a smaller electron affinity). ).

[0110] Also, Ec383a is closer to the vacuum level than Ec383b. a is 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more, higher than Ec383b 0.7 eV or less, more preferably 0.15 eV to 0.4 eV, close to the vacuum level is preferred.

[0111] Also, Ec383c is closer to the vacuum level than Ec383b. c is 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more, higher than Ec383b 0.7 eV or less, more preferably 0.15 eV to 0.4 eV, close to the vacuum level is preferred.

[0112] Here, between the oxide layer 104a and the oxide layer 104b, there is a layer of oxide In some cases, the oxide layer 104b may have a mixed region with the oxide layer 104b. Between the oxide layer 104b and the oxide layer 104c, there may be a mixed region of the oxide layer 104b and the oxide layer 104c. The mixed region has a low interface state density. The stack of the oxide layer 104c and the oxide layer 104b has a continuous energy distribution near the interface between the stack. (also called a continuous junction).

[0113] At this time, the electrons are not transferred to the oxide layer 104a and the oxide layer 104c, but to the oxide layer Therefore, the oxide layer 104a and the oxide layer 104b are mainly moved. the interface state density at the interface between the oxide layer 104b and the oxide layer 104c; By lowering the surface state density, the movement of electrons in the oxide layer 104b is inhibited. Therefore, the on-state current of the transistor 100 can be increased.

[0114] In addition, the interface between the oxide layer 104a and the insulator 103, and the interface between the oxide layer 104c and the insulator 104 are Although a trap level 390 due to impurities or defects may be formed near the interface of 5, The oxide layer 104a and the oxide layer 104c are present, and therefore the oxide layer 104b and the oxide layer 104c are not interfering with each other. Therefore, the distance between the trap level and the ion beam can be increased.

[0115] When the transistor 100 has an s-channel structure, the oxide layer 104b Therefore, the thicker the oxide layer 104b, the larger the channel region. That is, the thicker the oxide layer 104b, the higher the on-state current of the transistor 100. For example, the thickness can be set to 20 nm or more, preferably 40 nm or more, and more preferably The oxide layer 104b has a region having a thickness of 60 nm or more, more preferably 100 nm or more. However, the productivity of a semiconductor device including the transistor 100 may decrease. Therefore, for example, the thickness is 300 nm or less, preferably 200 nm or less, and more preferably 1 The oxide layer 104b may have a region with a thickness of 50 nm or less.

[0116] In order to increase the on-state current of the transistor 100, the thickness of the oxide layer 104c is For example, less than 10 nm, preferably 5 nm or less, and more preferably The oxide layer 104c may have a region of 3 nm or less. The oxide layer 104b in which the channel is formed is doped with an element other than oxygen that constitutes the adjacent insulator ( It has the function of blocking the intrusion of oxides (hydrogen, silicon, etc.). The layer 104c preferably has a certain thickness. For example, it is preferably 0.3 nm or more. or an oxide layer 104c having a region with a thickness of 1 nm or more, more preferably 2 nm or more. This can be done as follows.

[0117] In order to increase reliability, the oxide layer 104a is thick and the oxide layer 104c is thin. For example, it is preferably 10 nm or more, more preferably 20 nm or more, and even more preferably 4 100 nm or more, more preferably 60 nm or more. By increasing the thickness of the oxide layer 104a, the thickness of the oxide layer 104a can be reduced. The distance from the interface with a to the oxide layer 104b in which the channel is formed can be increased. However, since the productivity of a semiconductor device having the transistor 100 may decrease, for example, For example, a thickness of 200 nm or less, preferably 120 nm or less, and more preferably 80 nm or less. The oxide layer 104a may have a thick region.

[0118] Note that silicon in an oxide semiconductor can become a carrier trap or a carrier generation source. Therefore, it is preferable that the silicon concentration of the oxide layer 104b is low. Between the material layer 104b and the oxide layer 104a, for example, secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry (1×1 0 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than, more Preferably 2 x 10 18 atoms / cm 3 The silicon concentration is less than 100 nm. In addition, between the oxide layer 104b and the oxide layer 104c, a concentration of 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than, even more preferred Or 2×10 18 atoms / cm 3 The silicon concentration is less than 100 nm.

[0119] In order to reduce the hydrogen concentration in the oxide layer 104b, the oxide layer 104a and the oxide It is preferable to reduce the hydrogen concentration in the oxide layer 104a and the oxide layer 104c. is 2×10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Further details are below. Preferably 5 x 10 18 atoms / cm 3 The hydrogen concentration range is as follows: In order to reduce the nitrogen concentration in the oxide layer 104b, the oxide layer 104a and the oxide layer 104 It is preferable to reduce the nitrogen concentration in the oxide layer 104a and the oxide layer 104c. In MS, 5 × 10 19 atoms / cm 3 Less than 5 x 10 18 atom s / cm 3Less than or equal to 1×10 18 atoms / cm 3 The following is more preferable: is 5 x 10 17 atoms / cm 3 The nitrogen concentration ranges as follows:

[0120] Note that when copper is mixed into an oxide semiconductor, electron traps may be generated. A jump may cause the threshold voltage of a transistor to shift in the positive direction. Therefore, it is preferable that the copper concentration on the surface or inside of the oxide layer 104b is as low as possible. The copper concentration of the material layer 104b is 1×10 19 atoms / cm 3 Below, 5 x 10 18 atoms / cm 3 or less, or 1×10 18 atoms / cm 3 It is preferred that the region stomach.

[0121] The above-mentioned three-layer structure is an example. For example, the oxide layer 104a or the oxide layer 104c Alternatively, a two-layer structure may be used. On or under the layer 104c, the oxide layer 104a, the oxide layer 104b and the oxide layer 104c are Alternatively, the semiconductor layer may have a four-layer structure having any one of the semiconductors exemplified as c. On the oxide layer 104a, under the oxide layer 104a, on the oxide layer 104c, and under the oxide layer 104c. At least two of the oxide layers 104a, 104b and 104 It may also be an n-layer structure (n is an integer of 5 or more) having any one of the semiconductors exemplified as c. I don't.

[0122] In particular, the transistor 100 illustrated in this embodiment has an oxidized layer in the channel width direction. The upper surface and side surfaces of the oxide layer 104b are in contact with the oxide layer 104c, and the lower surface of the oxide layer 104b is in contact with the oxide layer 104c. The oxide layer 104 is formed in contact with the oxide layer 104a (see FIG. 1C). b is covered with the oxide layer 104a and the oxide layer 104c. The effect can be further reduced.

[0123] The band gaps of the oxide layer 104a and the oxide layer 104c are It is preferable that the band gap is wider than that of 4b.

[0124] According to one embodiment of the present invention, a transistor with little variation in electrical characteristics can be realized. Therefore, a semiconductor device with little variation in electrical characteristics can be realized. According to one embodiment of the present invention, a highly reliable transistor can be realized. It is possible to realize a highly reliable semiconductor device.

[0125] In addition, the band gap of oxide semiconductors is 2 eV or more, so A transistor that uses an oxide semiconductor for a conductor film can have an extremely small off-state current. Specifically, when the source-drain voltage is 3.5 V and the temperature is 25°C, The off-state current per 1 μm of channel width is 1×10 -20 Less than A, 1×10 -22 Less than A, yes Iwa 1×10 -24 That is, the on-off ratio can be increased by 20 orders of magnitude to less than 15 A. It can contain zero or less digits.

[0126] According to one embodiment of the present invention, a transistor with low power consumption can be realized. As a result, a semiconductor device with low power consumption can be realized.

[0127] [Insulator 102] The insulator 102 may be aluminum nitride, aluminum oxide, aluminum oxide nitride, or oxide. Aluminum nitride, magnesium oxide, silicon nitride, silicon oxide, silicon oxynitride , silicon oxide nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide nium, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicon Materials selected from the group consisting of oxides, nitrides, and tungsten are used in a single layer or in a laminated form. A mixture of multiple materials, including oxide, nitride, and nitride oxide, is used. Good too.

[0128] In this specification, the term "nitride oxide" refers to a compound that contains more nitrogen than oxygen. In addition, an oxynitride is a compound that contains more oxygen than nitrogen. The content of oxygen can be measured, for example, by Rutherford Backscattering (RBS) spectroscopy. It can be measured using ion scattering spectrometry (ICS) etc. do.

[0129] In particular, the insulator 102 is preferably formed using an insulating material that has low impurity permeability. For example, it is preferable that the oxygen permeability is low. Also, for example, it is preferable that the hydrogen permeability is low. For example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, and aluminum are preferred. , silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium Insulating materials containing lanthanum, neodymium, hafnium or tantalum are used in a single layer or in For example, aluminum oxide is used as an insulating material with low impurity permeability. Aluminum, aluminum nitride, aluminum oxide nitride, aluminum oxide nitride, gallium oxide , germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide Examples of the insulating material include tantalum oxide, hafnium oxide, tantalum oxide, and silicon nitride. The insulator 102 is made of a highly insulating material such as indium tin zinc oxide (In-Sn-Zn oxide). may also be used.

[0130] The insulator 102 may include an oxide containing indium. The insulator 102 may comprise an oxide containing indium and zinc. The insulator 102 may have an oxide having indium, zinc, and the element M. oxides having indium and zinc, or oxides having indium, zinc By containing lead and an oxide containing element M, oxygen permeability can be reduced. There may be cases where this occurs.

[0131] The method for forming the insulator 102 is not particularly limited, and may be a sputtering method, a CVD method, an MBE method, or the like. Alternatively, various methods such as PLD, ALD, and spin coating can be used. The thickness of the insulator 102 and the insulator 110 is 10 nm or more and 500 nm or less, preferably 50 The thickness may be set to 300 nm or more.

[0132] For example, when an aluminum oxide film is formed as the insulator 102 by using a thermal CVD method, The raw gas is made by vaporizing a liquid containing a solvent and an aluminum precursor compound (such as TMA). , H as the oxidizing agent 2 Two types of gases are used: trimethylaluminum and O. is Al(CH 3 ) 3Another material liquid is tris(dimethylamido)al. Aluminum, triisobutylaluminum, aluminum tris(2,2,6,6-tetramethylammonium chloride) methyl-3,5-heptanedionate).

[0133] By using an insulating material with low impurity permeability for the insulator 102, The diffusion of impurities can be suppressed, and the reliability of the transistor can be improved. By using an insulating material with low permeability to pure substances, the diffusion of impurities from the insulator 112 side is suppressed. This can suppress the current flow and improve the reliability of the transistor.

[0134] The insulator 102 may be a laminate of multiple insulators made of these materials.

[0135] [Insulator 111 and insulator 110b] The insulators 111 and 110b are made of an insulating material that has low impurity permeability. For example, the insulator 111 and the insulator 110b are preferably formed of an oxygen-permeable material. For example, the insulators 111 and 110b preferably have low hydrogen permeability. For example, the insulators 111 and 110b preferably have low water permeability. It is preferable that the temperature is low. For the method of manufacturing the insulator 111 and the insulator 110b, refer to the description of the insulator 102. It is possible.

[0136] The low oxygen permeability of the insulators 111 and 110b allows the oxide layer 104b In some cases, it may be possible to prevent excess oxygen supplied to the outside from diffusing outward.

[0137] [Insulator 103] Examples of the insulator 103 include silicon oxide, silicon oxynitride, silicon nitride oxide, Silicon nitride, aluminum oxide, aluminum oxynitride, aluminum oxide nitride, nitride The insulator 402 and the insulating film 403 may be formed of aluminum or the like. The body 412 can be formed by a sputtering method, a CVD method (thermal CVD method, MOCVD method, PEC In particular, the VD method, MBE method, ALD method, PLD method, etc. can be used. When the insulating film is formed by a CVD method, preferably a plasma CVD method, the covering property is improved. In addition, to reduce damage caused by plasma, thermal CV The D method, the MOCVD method or the ALD method is preferred.

[0138] The insulator 103 may also have a charge trapping layer. For example, as shown in FIG. The edge 103 has a laminated structure of an insulator 103a, an insulator 103b, and an insulator 103c. The insulator 103b may be hafnium oxide, aluminum oxide, tantalum oxide, or aluminum. The insulator 103b may be made of silicate or the like to function as a charge trap layer. The insulating layer 103a and the insulating layer 103c may be, for example, silicon oxide, silicon oxynitride, or silicon oxynitride. Silicon nitride, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide The insulator 103b can be made of, for example, tungsten, aluminum nitride, or the like. By doing so, it is possible to vary the threshold voltage of the transistor. The electrons can be injected by utilizing, for example, the tunnel effect. By adding an electric field, tunnel electrons can be injected into the insulator 103b.

[0139] The insulator 103 can be formed using the same materials and methods as the insulator 102. In order to prevent an increase in the hydrogen concentration in the oxide layer 104, the hydrogen concentration in the insulator 103 is Specifically, the hydrogen concentration in the insulator 103 is preferably reduced by SIMS. 2×10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Less than 5×10, more preferably 18 atoms / cm 3 In order to prevent an increase in the nitrogen concentration in the oxide semiconductor, In particular, it is preferable to reduce the nitrogen concentration in the insulator 103. The nitrogen concentration in the sample was 5×10 19 atoms / cm 3 Less than, preferably is 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 The following applies.

[0140] The insulator 103 is an insulator that releases oxygen when heated ("insulator containing excess oxygen"). It is preferable to form the film using a material that is free of oxygen by TDS analysis. The amount of oxygen removed, converted into atoms, is 1.0×10 18 atoms / cm 3 More than 3, preferably 3 .0×10 20 atoms / cm 3 It is preferable to use an insulator having the above properties.

[0141] Insulators containing excess oxygen can also be formed by subjecting the insulator to a process that adds oxygen. The process of adding oxygen can be carried out by heat treatment in an oxygen atmosphere, ion implantation equipment, or ion This can be done using a doping device or a plasma treatment device. The gases are: 16 O 2 or 18 O 2 Such as oxygen gas, nitrous oxide gas or ozone In this specification, the process of adding oxygen is called "oxygen doping." The treatment of adding oxygen is also called “adding treatment”. For example, after the formation of the insulator 118, the insulator 103 This may be performed after the formation of the oxide layer 104e or before the formation of the oxide layer 104f. The high density plasma may be generated by using microwaves. In the Zuma treatment, for example, an oxidizing gas such as oxygen or nitrous oxide may be used. A mixture of a chemical gas and a rare gas such as He, Ar, Kr, or Xe may be used. In the plasma processing, a bias may be applied to the substrate. Oxygen ions can be attracted to the substrate. High density plasma processing does not heat the substrate. For example, when a high density plasma treatment is performed instead of the heat treatment, The same effect can be obtained at a lower temperature than the heat treatment. For example, after the formation of the insulator 118, after the formation of the insulator 103, before the formation of the oxide layer 104e, etc. Just go.

[0142] Here, for example, a processing chamber for forming the insulator 103 and a processing chamber for performing high-density plasma processing are provided. A multi-chamber system has a processing chamber for transferring the substrate between the chambers. By using a chamber device, the deposition of the insulator 103 and the high-density plasma treatment can be performed. By performing the process continuously without exposing the film to the atmosphere, the incorporation of impurities into the film and the interface is reduced. This is also preferable because it can shorten the process time, which leads to cost reduction. In addition, the process can be simplified, which may improve the yield. For example, the substrate processing chamber may be set to a reduced pressure atmosphere.

[0143] Similarly, for example, a processing chamber for forming the insulator 103 and a processing chamber for forming the oxide layer 104d are a processing chamber for forming the oxide layer 104e, and a processing chamber for performing high density plasma processing. A multi-chamber having a processing chamber for performing a process and a substrate transfer chamber for transferring a substrate between each processing chamber. By using this device, the deposition of the insulator 103, the high-density plasma treatment, and the oxide layer The deposition of the oxide layer 104d and the deposition of the oxide layer 104e are performed successively without exposure to the atmosphere. This is preferable because it is possible to

[0144] The thickness of the insulator 103 is preferably 1 nm or more and 50 nm or less, and more preferably 3 nm or more and 30 nm or less. More preferably, the thickness is 5 nm or more and 10 nm or less. Alternatively, oxygen doping may be performed after the formation of the insulator 103. After the insulator 103 is formed, heat treatment may be performed. The insulator 103 is formed of, for example, silicon oxide.

[0145] <Configuration example 2> 5A is a top view of the semiconductor device. Also, FIG. 6A is a diagram showing the structure of the semiconductor device along the dashed line L in FIG. 6(B) shows a cross section taken along dashed line W1-W2 in FIG. 5(A). The semiconductor device shown in FIG. 5A, FIG. 6A, and FIG. 6B includes a transistor 10. 0 and an insulator 102 located below the transistor 100. and an insulator 110b surrounding the transistor 100 on all four sides. The transistor 100 is surrounded on all six sides by the body 111 and the insulator 110b. In FIG. 6(A), the insulator 110b is connected to the contact plug 113a and the contact plug 113b. In FIG. 6B, the insulator 110b is located outside the contact 13b. The outer side of the contact plug 113c and the contact plug 113d is the outer side of the For example, with the transistor 100 at the center, the distance from the transistor 100 is longer. This refers to the following.

[0146] As shown in FIG. 5B, the insulator 102, the insulator 111, and the insulator 110b The semiconductor device shown in FIG. On the top surface, the two transistors 100 are surrounded by an insulator 110b. However, in the cross section of the semiconductor device, an insulator 111 is disposed above the two transistors 100. 102 below. Thus, the two transistors 100 are connected by the insulator 1 The semiconductor device is surrounded on all six sides by the insulating material 110b, the insulating material 111, and the insulating material 110b. On the upper surface, the insulator 110b preferably has a closed shape. For example, polygons, circles, ellipses, and closed curves made by connecting curves and straight lines are included. For example, it may be a rectangle as shown in FIG. 5(A), or may be a square as shown in FIG. 5(B). The rectangle may have rounded corners.

[0147] The characteristics of the transistor 100 may change due to the movement of water, hydrogen, or oxygen. The insulators 102, 111, and 110b separate the six transistors 100. Since the transistor 100 is surrounded, hydrogen and hydrogen from outside the surrounded area are not introduced into the transistor 100. This can prevent contamination and release of oxygen from the transistor 100 outside the enclosed area. Therefore, the fluctuation in the characteristics of the transistor 100 can be suppressed.

[0148] Note that one embodiment of the present invention has been described in this embodiment. In the following, one embodiment of the present invention will be described. However, the embodiment of the present invention is not limited to these. That is, various inventive aspects are described in this and other embodiments. Therefore, one embodiment of the present invention is not limited to a specific embodiment. For example, one embodiment of the present invention As examples, the channel forming region, the source / drain region, and the like of a transistor such as the transistor 100 Although the case where the region or the like includes an oxide semiconductor has been described above, one embodiment of the present invention is not limited thereto. In some cases, or depending on the circumstances, various trans A channel forming region of a transistor, or a source / drain region of a transistor etc. may have various semiconductors. Various transistors, channel formation regions of transistors, or The source and drain regions of the transistors are made of, for example, silicon, germanium, silicon Germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium lithium The semiconductor layer may have at least one of silicon, gallium nitride, and organic semiconductors. For example, depending on the circumstances, various transactions in one aspect of the present invention may be performed. A transistor, a channel forming region of a transistor, or a source / drain region of a transistor The region etc. may not include an oxide semiconductor.

[0149] (Embodiment 2) In this embodiment mode, a manufacturing method of the semiconductor device shown in Embodiment 1 will be described.

[0150] <Production method> A method for manufacturing the semiconductor device shown in FIG. 1 will be described with reference to FIGS.

[0151] An insulator 102 is formed on a substrate 101. Next, an insulator 118 is formed on the insulator 102. Next, a mask 301 is formed on the insulator 118 (see FIG. 7(A)).

[0152] There is no particular restriction on the material used for the substrate 101, but it should be at least able to withstand the subsequent heat treatment. For example, barium borosilicate glass or aluminum Glass substrates such as borosilicate glass, ceramic substrates, quartz substrates, sapphire substrates, etc. etc. can be used.

[0153] The substrate 101 is a single crystal semiconductor substrate made of silicon, silicon carbide, or the like. Using polycrystalline semiconductor substrates, compound semiconductor substrates made of silicon germanium, etc. Also, a strained transistor or a FIN type transistor on an SOI substrate or a semiconductor substrate may be used. Any semiconductor element may be used. High Electron Mobility Transistor (HEMT) Gallium arsenide, aluminum gallium arsenide, and indium gallium arsenide are applicable to tor Alternatively, silicon germanium, gallium nitride, indium phosphide, silicon germanium, etc. may be used. That is, the substrate 101 is not limited to being a simple support substrate, but may be a substrate on which other devices such as transistors are formed. In this case, the gate, source, or drain of the transistor 100 may be a substrate. At least one of the drains may be electrically connected to the other device.

[0154] The substrate 101 may be a flexible substrate. When a flexible substrate is used, transistors, capacitors, and the like may be directly formed on the flexible substrate. A transistor or a capacitor is formed on another substrate, and then the transistor or capacitor is peeled off and transferred to a flexible substrate. In order to peel and transfer the film from the production substrate to the flexible substrate, A peeling layer may be formed between a transistor, a capacitor, and the like.

[0155] The flexible substrate may be, for example, a metal, an alloy, a resin, or a glass, or a fiber thereof. The lower the linear expansion coefficient of the flexible substrate used for the substrate 101, the more environmentally friendly it is. The flexible substrate used for the substrate 101 has a linear expansion coefficient of, for example, is 1×10 -3 / K or less, 5×10 -5 / K or less, or 1×10 -5 / K or less Examples of resins include polyester, polyolefin, and polyamide. (nylon, aramid, etc.), polyimide, polycarbonate, acrylic resin, etc. In particular, aramid has a low linear expansion coefficient and is therefore suitable for use as a flexible substrate.

[0156] The mask 301 may be produced by a lithography method using a resist, for example. Alternatively, a hard mask made of an inorganic film or a metal film may be formed. The deposition method can be carried out by appropriately using a photolithography method, a printing method, an ink-jet method, or the like. If the resist mask is formed by printing or inkjet method, a photomask is not used. This reduces manufacturing costs.

[0157] The formation of a resist mask by photolithography involves applying a photomask to a photosensitive resist. The resist is then removed by irradiating light through the exposed area (or the unexposed area) with a developer. The light irradiated onto the photosensitive resist is KrF excimer laser light, Ar F excimer laser light, EUV (Extreme Ultraviolet) light, etc. In addition, immersion technology is used, in which the space between the substrate and the projection lens is filled with liquid (e.g. water) for exposure. Also, instead of the light, an electron beam or an ion beam may be used. When an electron beam or an ion beam is used, a photomask is not required. The resist mask can be removed by dry etching such as ashing or by using a special remover. This can be done by using a wet etching method. Both the annealing and annealing techniques may be used.

[0158] Next, a portion of the insulator 118 is removed using the mask 301 to form an opening 306. (See FIG. 7B.) The insulator 118 can be removed by, for example, dry etching. good.

[0159] Next, a conductor 117d is formed on the upper surface of the insulator 118 and in the opening 306 (FIG. 7( See C). ).

[0160] Next, a part of the conductor 117d is removed to form the conductor 117 (FIG. 7( The conductor 117d can be removed by, for example, chemical mechanical polishing. It is preferable to use a polishing method such as the (Mechanical Polishing: CMP) method. Alternatively, dry etching may be used. For example, a technique such as etch back may be used. can be used.

[0161] Here, the CMP method is a method for flattening the surface of a workpiece by a combination of chemical and mechanical processes. Generally, a polishing cloth is attached to the polishing stage, and the workpiece is placed between the polishing cloth and the polishing While supplying slurry (abrasive) to the workpiece, the polishing stage and the workpiece are rotated or swung. The chemical reaction between the slurry and the surface of the workpiece and the mechanical abrasion between the polishing cloth and the workpiece occur simultaneously. This is a method of polishing the surface of a workpiece by the action of abrasive grains.

[0162] Next, the insulator 103, the oxide layer 104d, the oxide layer 104e, and the oxide layer 104f are formed on the insulator 118 and the conductor 117. Layer 104e is then deposited.

[0163] Next, impurities such as moisture or hydrogen contained in the oxide layers 104d and 104e are removed. In order to further reduce the amount of foreign matter and to highly purify the oxide layers 104d and 104e, It is preferable to carry out a heat treatment.

[0164] For example, the heating may be performed under a reduced pressure atmosphere, an inert atmosphere such as nitrogen or a rare gas, an oxidizing atmosphere, or an ultra Dry air (measured using a CRDS (Cavity Ring Down Laser Spectroscopy) type dew point meter When the moisture content is measured, it should be 20 ppm or less (-55°C in terms of dew point), preferably 1 ppm or less. The oxide layer 104d and the oxide layer 104 are subjected to a chlorine treatment under an atmosphere of 10 ppb or less of air. 4e is subjected to a heat treatment. The oxidizing atmosphere is an oxidizing atmosphere such as oxygen, ozone, or nitrogen oxide. An inert atmosphere is an atmosphere containing 10 ppm or more of chemical gas. This refers to an atmosphere in which the amount of harmful gases is less than 10 ppm and which is filled with nitrogen or rare gases.

[0165] In addition, by performing a heat treatment, the oxygen contained in the insulator 103 is released at the same time as the impurities are released. is diffused into the oxide layer 104d and the oxide layer 104e, and the oxide semiconductor layer In addition, after the heat treatment in an inert gas atmosphere, the oxygen vacancies caused by the desorption can be reduced. To compensate for the lost oxygen, an atmosphere containing oxidizing gas at 10 ppm or more, 1% or more, or 10% or more The heat treatment may be performed in a vacuum. For example, the oxide layer 104a and the oxide layer 104b may be formed at any time after the formation of the oxide layer 104e. Heat treatment may be performed after the formation of the oxide layer 104b. This may be done.

[0166] There is no particular limitation on the heating device used for the heat treatment. Alternatively, the device may be a device that heats the workpiece by thermal radiation. For example, an electric furnace or a RTA (Lamp Rapid Thermal Anneal) equipment, GRTA (Ga Rapid Thermal Anneal (RTA) equipment The LRTA device uses a halogen lamp. , metal halide lamps, xenon arc lamps, carbon arc lamps, high pressure sodium The light (electromagnetic waves) emitted from lamps such as mercury lamps and high-pressure mercury lamps The GRTA device is a device that uses high-temperature gas to perform heat treatment. .

[0167] The heat treatment is carried out at a temperature of 250°C to 650°C, preferably 300°C to 500°C. The treatment time should be within 24 hours. Heat treatment for more than 24 hours will result in a decrease in productivity. This is not desirable because it

[0168] After the oxide layer 104d or the oxide layer 104e is formed, the oxygen doping treatment is performed. You may go.

[0169] Next, a mask 302 is formed on the oxide layer 104e (see FIG. 8(A)). Mask 3 For 02, see mask 301. Then, mask 302 is used to remove oxide layer 104 e, the oxide layer 104d and the insulator 103 are partially removed, and the oxide layer 104a and The oxide layer 104b is formed (see FIG. 8B). d, and the insulator 103 is removed by, for example, dry etching or wet etching. It is possible.

[0170] When etching conductors, semiconductors, and insulators using dry etching, A gas containing a halogen element can be used as the mixing gas. An example of a gas is chlorine (Cl 2 ), boron trichloride (BCl 3 ), silicon tetrachloride (SiCl 4 ) or carbon tetrachloride (CCl 4 ) and other chlorine-based gases, carbon tetrafluoride (CF 4 ), sulfur hexafluoride (SF 6 ), nitrogen trifluoride (NF 3 ) or trifluoromethane (C HF 3 Fluorine gases such as hydrogen bromide (HBr) or oxygen can be used appropriately. In addition, an inert gas may be added to the etching gas used. Methane (CH 4 ), ethane (C 2 H 6 ), propane (C 3 H 8 ), or butane (C 4 H 10 ) and other hydrocarbon gases A mixture of active gases may also be used.

[0171] In addition, the dry etching method is parallel plate type RIE (Reactive Ion Etching). Etching) method, ICP (Inductively Coupled Plasm) a: Inductively Coupled Plasma (DF-CCP) method, Dual Frequency Capacitive Dual Frequency Excitation Capacitively Coupled Plasma Method The etching conditions can be set so that the desired processed shape can be obtained. (For example, the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side, The temperature of the electrode on the side of the electrode can be adjusted appropriately.

[0172] Next, the top and side surfaces of the oxide layer 104b, the side surfaces of the oxide layer 104a, and the insulator 103, an oxide layer 104f, an insulator 105d, a conductor 106d, and an insulator 107d After that, a mask 303 is formed on the upper surface of the insulator 107d (FIG. 8(C)). For mask 303, see mask 301.

[0173] Next, a mask 303 is used to remove a portion of the insulator 107d and the conductor 106d. The insulating layer 107 and the conductor 106 are formed by removing the insulating layer 107 and the conductor 106 (FIG. 9( See A). ).

[0174] The conductive material for forming the conductor 106 may be aluminum, chromium, copper, silver, Gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium selected from the group consisting of tungsten, niobium, manganese, magnesium, zirconium, and beryllium. Materials containing one or more metal elements can be used. In addition, materials that do not contain impurity elements such as phosphorus can be used. Highly conductive semiconductors, such as polycrystalline silicon, nickel silicide, etc. Silicide may also be used. The conductor 106 may be a conductive layer made of these materials. Several layers may be used.

[0175] The conductor 106 is made of indium tin oxide (ITO). de), indium oxide containing tungsten oxide, indium oxide containing tungsten oxide Zinc oxide, indium oxide with titanium oxide, indium tin oxide with titanium oxide Conductive materials containing oxygen such as indium zinc oxide and silicon-doped indium tin oxide Alternatively, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. In addition, a laminated structure that combines the above-mentioned material containing a metal element and a conductive material containing oxygen In addition, the above-mentioned material containing the metal element and the conductive material containing nitrogen may be combined. In addition, the above-mentioned materials containing metal elements and materials containing oxygen can be used as lamination structures. A laminated structure may be formed by combining a conductive material containing nitrogen and a conductive material containing oxygen. The thickness of the conductor 106 is preferably 10 nm or more and 500 nm or less, and more preferably 20 nm or more and 300 nm or less. nm or less, and more preferably 30 nm to 200 nm. In the present embodiment, a laminate of titanium nitride and tungsten is used as the conductive layer 126. A 150 nm thick tungsten layer is formed on a 10 nm thick titanium nitride layer.

[0176] The method for forming the conductor 106 is not particularly limited, and may be a deposition method, a CVD method, a sputtering method, etc. Various methods for forming the above-mentioned can be used.

[0177] [Metal element 131] Next, the metal element 131 is introduced using the conductor 106 and the insulator 107 as a mask. (See FIG. 9(C)). In FIG. 9(C), the metal element 131 is indicated by an arrow. The introduction of element 131 can be carried out using ion implantation or plasma doping. In FIG. 9C, the edge of the region 135 into which the metal element 131 is introduced is indicated by a dashed line. The depth of the region 135 into which the metal element is introduced and the concentration of the metal element contained in the region 135 are can be determined by the processing conditions of the ion implantation method, the plasma doping method, etc. .

[0178] As the metal element 131, it is preferable to use one or more metal elements. For example, Element 131: tungsten, aluminum, titanium, magnesium, vanadium, One or more of the following elements may be used: antimony, arsenic, and sulfur. The dose of metal element 131 is 1×10 12 ions / cm 2 More than 1×10 16 ions / cm 2 Less than or equal to 1×1013 ions / cm 2 More than 1×10 15 ions / c m 2 The acceleration voltage during the introduction of the metal element 131 is preferably 5 kV or more and 50 kV or less. Preferably, the voltage is 10 kV or more and 30 kV or less. Tungsten is used as a mask. When element 131 is introduced, a self-aligned region 135 is formed adjacent to the channel forming region. It is possible.

[0179] Here, the metal element 131 is, for example, tungsten or titanium, which easily bonds with oxygen. When the material is formed, an oxide of the metal element 131 is formed, and the metal element 131 is In the case where oxygen vacancies (also called "Vo") in the oxide layer 104 increase in the region where oxygen is introduced, In addition, when hydrogen is bonded to Vo to form VoH, the carrier density in the region increases and the resistivity decreases.

[0180] After the introduction of the metal element 131, a heat treatment may be performed. The heat treatment is preferably performed at 200° C. More preferably, the temperature is 300° C. or higher and 450° C. or lower. The heat treatment may be performed at a temperature of 400°C or higher. Hydrogen bonds to Vo by this heat treatment, and VoH becomes Once formed, the carrier density in that region is further increased and the resistivity is further reduced.

[0181] Thus, the region 135 in the oxide layer 104 overlaps the conductor 106 of the oxide layer 104. The carrier density is higher and the resistivity is smaller than that of the oxidized region (channel formation region). The region 135 in the oxide layer 104 overlaps with the conductor 106 of the oxide layer 104 (channel-shaped region). The resistance may be lower than the area of ​​the

[0182] In this embodiment, tungsten is used as the metal element 131. The introduction of tungsten into a portion of the oxide layer 104 causes the oxide layer 104 to A region containing tungsten oxide is formed.

[0183] Next, the insulator 108d is formed on the insulator 105d and the insulator 107 (FIG. 9( See C). ).

[0184] Next, the insulator 108d is etched by anisotropic dry etching to remove the conductor 10 At this time, the insulator 108 and the conductor 105d are formed on the side wall of the insulator 105. The areas not overlapping either of the conductive bodies 106 are also etched to form the insulator 105 . In addition, the region of the oxide layer 104f that does not overlap either the insulator 108 or the conductor 106 The oxide layer 104c is also etched away from the insulating layer 108. A portion of the oxide layer 104b is exposed.

[0185] At this time, a part of the exposed oxide layer 104b is etched, and the oxide layer 104b having a protrusion is left. In this case, the oxide layer 04b may be formed. FIG. 20A shows a transistor 100 having a protrusion 104b. 20(B) is a plan view of the resistor 100. Also, FIG. 20(B) is a plan view of the resistor 100 shown in FIG. 11 is a cross-sectional view taken along line W1-W2 in FIG.

[0186] [Insulator 107 and Insulator 108] Here, a part of the insulator 108d is etched by anisotropic dry etching to form the insulator When forming 108, it is preferable that the insulator 107 is not etched. The etching rate of the insulator 107 is slower than that of the insulator 108d. Therefore, the insulator 107 preferably has a main element different from that of the insulator 108. Alternatively, for example, the insulator 107 may be, for example, the insulator 10 The thickness of the insulator 107 is preferably 5 nm or more and 100 nm or less. It is preferable that the thickness is 10 nm or more and 50 nm or less.

[0187] As an example, silicon oxide or silicon oxynitride is used as the insulator 108. Silicon nitride or silicon nitride oxide is used as the insulator 107. By making the atomic ratio of nitrogen higher than that of the insulator 108, the insulator 108 is etched. In addition, the etching rate of the insulator 107 may be slowed down.

[0188] As a further example, the insulator 108 may be silicon oxide, silicon oxynitride, or nitride. Silicon oxide or silicon nitride is used as the insulator 107, and aluminum nitride or oxide is used as the insulator 108. When aluminum, aluminum oxide nitride, or aluminum oxide nitride can be used There is.

[0189] As a further example, the insulator 108 may be silicon oxide, silicon oxynitride, or nitride. When silicon oxide or silicon nitride is used, the oxide layer 104 is used as the insulator 107. In some cases, a material that can be used as a

[0190] Here, the insulator 108d is etched by anisotropic dry etching. In some cases, an insulator may be formed on more than just the sidewall of the conductor 106. For example, the oxide layer 104 Insulators may be formed on the side walls of b.

[0191] Next, a conductor 109d is formed on the insulator 103, the oxide layer 104b, and the insulator 107. (See FIG. 10(B)). Here, the conductor 109d covers the side surface of the insulator 108. The thickness of the conductor 109d is preferably 5 nm or more and 500 nm or less. More preferably, the thickness is 0 nm or more and 200 nm or less, and further preferably, the thickness is 15 nm or more and 100 nm or less. In this embodiment, conductor 109d is made of tungsten having a thickness of 20 nm.

[0192] Alternatively, the conductor 109d may be a titanium oxide layer having a thickness of 5 nm and a 20 nm thick silicon dioxide film on the titanium oxide. The three-layer structure was made of tungsten with a thickness of 5 nm and titanium oxide on tungsten with a thickness of 5 nm. It's fine.

[0193] Next, a part of the conductor 109d is removed using a mask to form the conductor 109e (FIG. 10(C). After that, an insulator 110d is formed (see FIG. 11(A)).

[0194] [Conductor 109a and Conductor 109b] Next, the insulator 110d and the conductor 109 are placed on the substrate 101 so as to make the upper surface flat. By removing a part of the insulating layer 109e, the conductor 109a and the conductor 109b are formed (FIG. 1 1(B). Here, by removing a part of the conductor 109e, the conductor 109d The area overlapping with the conductor 106 is removed to separate the conductor 109e. A conductive body 109a and a conductive body 109b can be formed.

[0195] Here, the insulator 110d and the conductor 109e are removed by a polishing method such as a CMP method. Alternatively, dry etching may be used. For example, etch-back or the like may be used. Just use the method.

[0196] When a polishing method such as a CMP method is used to remove the insulator 110d and the conductor 109e, The polishing speed of the conductor 109d and the insulator 110d may vary within the surface of the sample. In this case, in a portion where the polishing speed is high, the insulator 107 may be exposed for a long time. The polishing speed of the insulator 107 is slower than that of the conductor 109e and the insulator 110d. It is preferable that the polishing speed of the insulator 107 is slow. In the polishing step 110d, the insulator 585 serves as a polishing stopper film. It is possible.

[0197] In one embodiment of the present invention, for example, when a mask is formed using lithography, In the case of the mask, the position where the mask is formed may vary depending on the accuracy of the lithography equipment. In such a case, the ends of the conductors 109a and 109b and the insulator On the other hand, in one embodiment of the present invention, a distance is generated between the end of the conductor 108 and the end of the conductor 108. There is no need to use a mask or the like when forming the conductive material 109a and the conductive material 109b. The surface area of ​​the transistor 100 can be reduced. By making the size smaller, it is possible to realize high integration of the circuits included in the semiconductor device.

[0198] Also, the insulator 110, the conductor 109a, the conductor 109b, the insulator 108, and the insulator The upper surface of 107 is a continuous flat plane. By forming an insulator 111 on the plane, As a result, for example, the coverage of the insulator 111 may be improved, and the hydrogen permeability may be reduced. In addition, the blocking ability of the insulator 111 is improved, so the insulator 111 can be made thin. By making the insulator 111 thinner, it is possible to, for example, dry etch the insulator 111. When the opening is provided using a metal film or the like, the etching time can be shortened. If the masking time is too long, for example, the mask width will shrink and the opening will become larger. For example, by shortening the etching time, finer This is preferable because it allows a suitable opening to be provided.

[0199] The conductors 109a and 109b may be made of, for example, tungsten, polysilicon, etc. In addition, the side and bottom surfaces of the material can be made of a conductive material having high embedding properties. The barrier layer (diffusion prevention layer) is made of a titanium layer, a titanium nitride layer, or a laminate of these layers. For example, as shown in FIG. 3B, the conductor 109a may be replaced with the conductor 109j. The three layers are conductor 109k and conductor 109l, conductor 109b is conductor 109m, and conductor 1 The conductive layer 109j may have a three-layer structure of the conductive layer 109j, the conductive layer 109n, and the conductive layer 109o. It is preferable that the conductor 109l and the conductor 109m are used as a barrier layer. The conductor 109o may be a barrier layer. When the barrier layer functions as an electrode, the electrode may also include the barrier layer.

[0200] The conductors 109a and 109b are made of, for example, tungsten or titanium. When the conductor 109a and the oxide layer 104 are formed of a material that has a property of extracting oxygen from the oxide layer 104, The V o in the oxide layer 104 in contact with the conductor 109b increases. In the region 135 formed in the conductor 109, the region where the conductor 109a and the conductor 109b are in contact with each other is called a "kick". The carrier density increases and the resistivity decreases. Note that hydrogen bonds with Vo to form VoH. When the region is exposed to the ion beam, the carrier density in the region increases further, and the resistivity decreases further.

[0201] Therefore, the carrier density in the oxide layer 104 is higher than that in the region overlapping with the insulator 108. The carrier density may become high in the region where the conductor 109a and the conductor 109b contact each other. In addition, the resistivity of the conductor 104 is higher than that of the region overlapping with the insulator 108 in the oxide layer 104. The resistivity of the region where the oxide 9a and the conductor 109b contact each other may be reduced. The resistance of the conductor 109a and the conductor 109b is higher than the resistance of the region of the layer 104 that overlaps with the insulator 108. The resistance of the area in contact with 109b may be low.

[0202] Next, the insulator 111 is applied on the insulator 110, the conductor 109a, the conductor 109b, etc. A film is formed (see FIG. 12(A)).

[0203] In this embodiment, aluminum oxide is deposited by sputtering as the insulator 111. A gas containing oxygen is used as a sputtering gas. When the insulator 111 is formed by the above, the interface between the insulator 111 and the surface on which the insulator 111 is formed and In the vicinity of the insulator 110, a mixed layer is formed in which the insulators 110 and 111 are mixed together. A mixed layer 145 is formed at and near the interface of 111.

[0204] The mixed layer 145 contains a part of the sputtering gas. Since a gas containing oxygen is used as the puttering gas, the mixed layer 145 contains oxygen. Thus, the mixed layer 145 has an excess of oxygen.

[0205] Next, a heat treatment is performed. The heat treatment is preferably performed at a temperature of 200° C. or higher and 500° C. or lower, more preferably Preferably, the reaction is carried out at a temperature of 300°C or higher and 450°C or lower, and more preferably at a temperature of 350°C or higher and 400°C or lower. The temperature of the heat treatment performed at this time is preferably the same as that of the heat treatment performed after the introduction of the metal element 131. The temperature shall be less than or equal to 100°C.

[0206] The heat treatment causes the oxygen contained in the mixed layer 145 to diffuse. The excess oxygen is absorbed through the insulator 110, the insulator 103, the insulator 108, the insulator 105, etc. The insulator 1 diffuses into the oxide layer 104a, the oxide layer 104b, and the oxide layer 104c. By using materials that are difficult to permeate oxygen as the insulating layer 102 and the insulating layer 103, the mixed layer 145 The excess oxygen contained in the oxide layer 104b is effectively absorbed through the insulators 110 and 103. The diffusion of excess oxygen contained in the mixed layer 145 is shown in FIG. Indicated by an arrow in 2(B).

[0207] Next, the insulator 112 is formed on the insulator 111. An opening 307 is formed in the insulating material 110, reaching the conductor 109a and the like (FIG. 13( See A). ).

[0208] Next, a conductor is formed on the insulator 112 and in the opening 307, and the substrate 101 is A part of the conductor is removed to flatten the upper surface, forming a contact plug 113. a, contact plug 113b and contact plug 113c are formed (FIG. 13( B). The conductor can be removed by, for example, a CMP method.

[0209] The contact plug 113a, the contact plug 113b, and the contact plug 11 As 3c, for example, a highly embeddable conductive material such as tungsten or polysilicon is used. Although not shown, the side and bottom surfaces of the material may be covered with a titanium layer, a nitride layer, or the like. Alternatively, the substrate may be covered with a barrier layer (diffusion prevention layer) made of a titanium dioxide layer or a laminate of these layers. In this case, the electrode may also include the barrier layer.

[0210] The insulator 112 can be formed of the same material and by the same method as the insulator 103. The insulator 112 may be polyimide, acrylic resin, benzocyclobutene resin, polya Organic materials having heat resistance, such as amides and epoxy resins, can be used. In addition to the above materials, low-k materials, siloxane resins, and PSG (lingala The material can be shaped by using these materials. The insulator 112 may be formed by stacking a plurality of insulators formed of the above-mentioned material.

[0211] The siloxane resin is a Si-O- formed material that is made from a siloxane material. This corresponds to a resin containing Si bonds. Siloxane-based resins have organic groups (e.g., arsenic) as substituents. Alternatively, the organic group may have a fluoro group. It's fine if you're there.

[0212] The method for forming the insulator 112 is not particularly limited, and may be a sputtering method, a SOG method, or the like, depending on the material. method, spin coating, dip coating, spray coating, droplet ejection method (inkjet method, etc.), printing A printing method (screen printing, offset printing, etc.) may be used. By combining this process with other heat treatment processes, it is possible to efficiently manufacture transistors. do.

[0213] Next, the sample surface was subjected to chemical mechanical polishing (CMP). Then, a polishing process (also called a "CMP process") is performed (see FIG. 11(A)). CMP processing reduces the unevenness of the sample surface and improves the insulating properties of the sample. Furthermore, the coverage of the conductive layer can be improved.

[0214] Then, the conductors 114a, 114b, and 114c are formed on the insulator 112. By forming the above, the semiconductor device shown in FIG. 1 can be manufactured (see FIG. 14).

[0215] The insulators 118, 105d, 110d, and 112 are formed as follows: The method for forming the insulator 103 can be referred to. The insulators 110 and 112 are made of the same material and have the same structure as the insulator 103. It is possible.

[0216] In addition, the conductor 117d, the conductor 109d, the contact plugs 113a to 113c, and the conductor The formation of the conductors 114a to 114c can be performed by referring to the conductor 106d. 17, the conductor 109a, the conductor 109b, the contact plugs 113a to 113c, and the conductor Bodies 114a-c may use the materials and configurations shown for conductor 106. .

[0217] In FIG. 9B, a metal element 131 is added before the insulator 108 is formed. However, as shown in FIG. 15(A), after FIG. 9(A), before adding the metal element 131, 5(A), an insulator 108d is formed, and then, as shown in FIG. A body 108 may be formed, and then a metal element 131 may be added as shown in FIG. 15(C). Then, the insulator 110, the conductor 109a, the conductor 109b, the insulator 111, the insulator 11 2. Contact plugs 113a, conductors 114a, etc. are formed to obtain the semiconductor device shown in FIG. In FIG. 16, compared to the area under the insulator 108, In the outer region, the concentration of the metal element 131 may be higher.

[0218] <Production method 2> Next, a manufacturing method of the semiconductor device shown in FIG. 2 will be described with reference to FIGS.

[0219] Using the method shown in FIG. 7(A) to FIG. 9(A), the insulator 102 on the substrate 101, the insulating The body 118, the conductor 117, the insulator 103, the oxide layer 104a, the oxide layer 104b, the oxide The layer 104f, the insulator 105d, the conductor 106, and the insulator 107 are then formed. 106 is used as a mask to remove the insulator 105d and a part of the oxide layer 104f, and the insulator 1 05 and an oxide layer 104c are formed (see FIG. 17(A)). In FIG. 17(A), The oxide layer 104c, the insulator 105, the conductor 106, and the insulator 107 are generally aligned. It is preferable that they coincide.

[0220] Next, the metal element 131 is introduced using the conductor 106 and the insulator 107 as a mask. In FIG. 17B, the metal element 131 is indicated by an arrow, and the metal element 1 The edge of region 135 where 31 is introduced is shown by a dashed line.

[0221] Next, the insulator 108d is formed on the oxide layer 104b, the insulator 103 and the insulator 107. (See FIG. 17(C)). After that, the conductor 10 is formed by anisotropic dry etching. An insulator 108 is formed on the side wall of the insulating film 6 (see FIG. 18(A)). By etching the insulator 108d by etching, the side wall of the conductor 106 is Insulators may also be formed on the side walls of the oxide layer 104b. 108b is formed.

[0222] Next, the conductor 109a, the conductor 109b, an insulator 110, and an insulator 111 are formed (see FIG. 18(B)).

[0223] In this embodiment, aluminum oxide is deposited by sputtering as the insulator 111. A gas containing oxygen is used as a sputtering gas. When the insulator 111 is formed by the above, the interface between the insulator 111 and the surface on which the insulator 111 is formed and In the vicinity of the insulator 110, a mixed layer is formed in which the insulators 110 and 111 are mixed together. A mixed layer 145 is formed at and near the interface of 111.

[0224] The mixed layer 145 contains a part of the sputtering gas. Since a gas containing oxygen is used as the puttering gas, the mixed layer 145 contains oxygen. Thus, the mixed layer 145 is a layer having excess oxygen.

[0225] Next, a heat treatment is performed. The heat treatment is preferably performed at a temperature of 200° C. or higher and 500° C. or lower, more preferably Preferably, the reaction is carried out at a temperature of 300°C or higher and 450°C or lower, and more preferably at a temperature of 350°C or higher and 400°C or lower. The temperature of the heat treatment performed at this time is preferably the same as that of the heat treatment performed after the introduction of the metal element 131. The temperature should be less than or equal to 100°C.

[0226] The heat treatment causes the oxygen contained in the mixed layer 145 to diffuse. The excess oxygen that is introduced is transferred to the oxide layer 10 through the insulators 110, 103, 108, etc. 4a, oxide layer 104b, and oxide layer 104c. By using a material that is difficult for oxygen to permeate as the body 102, the excess oxygen contained in the mixed layer 145 can be easily removed. The element is efficiently diffused into the oxide layer 104b via the insulator 110, the insulator 103, etc. The diffusion of excess oxygen contained in the mixed layer 145 is shown by the arrows in FIG. As shown in Fig.

[0227] Then, the insulator 112, the contact plug 113a, the conductor 114a, etc. are formed, and the insulating layer 112 is formed as shown in FIG. A semiconductor device shown in FIG. 19B can be manufactured.

[0228] <Structure 300> In forming the conductor 109a and the conductor 109b shown in FIG. A part of the insulator 110d and the conductor 109e are removed so as to make the upper surface flat with respect to the When a polishing method such as a CMP method is used to remove the insulator 110d and the conductor 109e, The polishing rate of the sample may vary across the surface of the sample. In such cases, the polishing rate is faster at certain points. In some places, excessive polishing occurs, resulting in the insulator 108, the insulator 107, and one of the conductors 106 being polished. In this case, by densely arranging the structures such as the conductor 106, This is preferable because excessive polishing can be suppressed in some cases.

[0229] FIG. 22(A) shows a channel of a semiconductor device having a structure 100d that will become a transistor 100. 22(A) shows an example of a cross section in the longitudinal direction of the panel. The height of the upper surface of the region where the structure 100d is provided and the region where the structure 100d is not provided is The difference in length is defined as length 311. Here, it is preferable that length 311 is small. By reducing the size of the insulating layer 109, the insulating layer 109 can be formed after the formation of the conductors 109a and 109b. In some cases, the flatness of the surface of the body 110 can be improved.

[0230] The semiconductor device shown in FIG. 22B includes a structure 100d which becomes the transistor 100 and a structure The structure 300d is adjacent to the structure 100d. By including the structure 300 in the semiconductor device, the insulator 110d and the conductor 109d This is preferable because excessive polishing can be suppressed in the removal step.

[0231] The structure 100d preferably includes a conductor 106. 0d) may have the same structure as transistor 100 (structure 100d); or The structure 300 (structure 300d) is a partial structure of the transistor 100 (structure 100d). In the example shown in FIG. 23, the structure 300d has the same components as the structure 100d. Among the components, the conductor 109e, the conductor 106, the insulator 108, the insulator 107, and the insulator 1 05, has the oxide layer 104c, but does not have the oxide layer 104b or the oxide layer 104a.

[0232] In addition, in FIG. 23, a structure 300d is an example in which the insulator 103 does not have a protrusion. Alternatively, the convex portion of the insulator 103 of the structure 300d may be formed on the insulator 103 of the structure 100d. In some cases, the height of the insulator 110 is smaller than the height of the protrusion of the insulator 110. d, the area where the structure 100d is provided and the area where the structure 300d is provided The difference in height between the upper surfaces is defined as a length 314. 22(A) , the length 314 can be made shorter than the length 311 shown in FIG. .

[0233] Distance between the conductor 106 of the structure 100d and the conductor 106 of the structure 300d Here, the length 312 is, for example, the length in the channel direction of the transistor 100. The length 313 of the oxide layer 104b in the cross section is 0.5 times or more and 10 times or less, or 1 time or more. The upper limit is 5 times or less.

[0234] Furthermore, the structure 300 does not have to function as a semiconductor element in a semiconductor device. For example, the structure 300 does not need to be connected to a wiring. In this case, the signal input to the circuit does not need to be electrically connected to the structure 300. The structure 300 may be called a dummy pattern or a dummy element.

[0235] FIG. 24(A) shows an example of a semiconductor device having two structures 100d. In FIG. 24(B), a part of the insulator 110d and the conductor 109d are removed. ) two transistors 100 are obtained.

[0236] In FIG. 24A, when two structures 100d are sparsely arranged, the insulating 110d and a part of the conductor 109d are removed, as shown in FIG. In this case, a recess may be formed in the insulator 110 between the two transistors 100. However, excessive polishing occurs, resulting in the removal of portions of insulator 108, insulator 107, and conductor 106. There is a possibility that it may be lost.

[0237] As shown in FIG. 25(A), one or more structures 300d are provided adjacent to the structure 100d. By forming the conductor 109a, the conductor 109b, and the insulator 110, This is preferable because excessive polishing can be suppressed (see FIG. 25(B)). This is preferable because the surface can be made flatter. In some cases, it may be possible to roughly align the upper ends of the conductors 109a and 109b, which is preferable. stomach.

[0238] In addition, in FIG. 25(C), the structure 300 is made up of a conductor 109a, a conductor 109b, and a conductor 109c. 06, insulator 108, insulator 107, insulator 105, oxide layer 104c, 104b and oxide layer 104a. By forming the conductor 109a, the conductor 109b, and the insulator 110, This is preferable because excessive polishing can be prevented.

[0239] <Production method 3> Next, a manufacturing method of the semiconductor device shown in FIGS. 6A to 6C will be described with reference to FIGS.

[0240] As shown in FIG. 7(A) to FIG. 11(B), an insulator 102, a conductor 11, and a 7, insulator 118, insulator 103, oxide layer 104a, oxide layer 104b, oxide layer 10 4c, insulator 105, conductor 106, insulator 107, insulator 108, conductor 109e, and Then, an insulator 110 and the like are formed (see FIG. 26(A)).

[0241] Next, an opening is formed in the insulator 110, the insulator 103 and the insulator 118, reaching the insulator 102. A portion 308 is formed (see FIG. 26(B)).

[0242] Next, an insulator that will become the insulator 110b is formed on the insulator 110 and in the opening 308. Then, the upper surface of the insulator 110 is aligned parallel to the substrate 101 so that the upper surface of the insulator 110 is exposed. Then, as shown in FIG. 26(C), the insulating layer 110b is removed. By forming an insulator 111 on the semiconductor 110 and the insulator 110b, the semiconductor 110 shown in FIG. A device can be fabricated.

[0243] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0244] (Embodiment 3) Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include CAAC-OS, polycrystalline oxide semiconductors, and nc-O S(nanocrystalline oxide semiconductor), pseudo Amorphous-like Oxide Semiconductor (a-like OS) e Semiconductor, and amorphous oxide semiconductor.

[0245] From another point of view, the oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor. Crystalline oxide semiconductors are classified into single crystal oxide semiconductors, CAAC- These include OS, polycrystalline oxide semiconductor, and nc-OS.

[0246] The definition of an amorphous structure is generally that it is not fixed in a metastable state and is isotropic. It is known that the bond angle is flexible and the bond length is short. In other words, it is a structure that has discrete order but does not have long-range order.

[0247] On the other hand, in the case of an essentially stable oxide semiconductor, In addition, it cannot be called an oxide semiconductor because it is not isotropic. The oxide semiconductor, which is not amorphous (for example, has a periodic structure in a microscopic region), is transformed into a completely amorphous oxide. However, a-like OS is a semiconductor that can be used in a small area. Although it has a periodic structure, it has voids and is an unstable structure. Therefore, its physical properties are similar to those of an amorphous oxide semiconductor.

[0248] <caac-os> CAAC-OS is an oxide having multiple crystal parts (also called "pellets") aligned along the c-axis. It is one of the compound semiconductors.

[0249] Transmission Electron Microscope (TEM) A combined analysis image of the bright-field image and the diffraction pattern of CAAC-OS (" When observing the "high-resolution TEM image," multiple pellets can be confirmed. On the other hand, high-resolution TEM images reveal the boundaries between pellets, i.e., grain boundaries (grain boundaries). Therefore, CAAC-OS is unable to clearly confirm the identity of the It can be said that the decrease in electron mobility caused by grain boundaries is unlikely to occur.

[0250] The following describes the CAAC-OS observed by TEM. 1 shows a high-resolution TEM image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. For high-resolution TEM imaging, spherical aberration correction is required. The spherical aberration corrector function was used. , specifically called a Cs-corrected high-resolution TEM image. Cs-corrected high-resolution TEM images are obtained, for example, This is performed using an atomic resolution analytical electron microscope such as the JEM-ARM200F manufactured by JEOL Ltd. It is possible.

[0251] A Cs-corrected high-resolution TEM image of the enlarged area (1) in Figure 27(A) is shown in Figure 27(B). From FIG. 27(B), it can be confirmed that the metal atoms are arranged in layers in the pellet. The arrangement of each metal atom layer is determined by the surface on which the CAAC-OS film is to be formed (also called the “formation surface”). ) or reflects the unevenness of the top surface, and is parallel to the surface on which the CAAC-OS is formed or the top surface. do.

[0252] As shown in FIG. 27(B), CAAC-OS has a characteristic atomic arrangement. ) shows the characteristic atomic arrangement with auxiliary lines. ) the size of a single pellet can be 1 nm or more, or 3 nm or more. It can be seen that the size of the gap caused by the inclination between the plate and the pellet is about 0.8 nm. Therefore, the pellets can also be called nanocrystals (nc). CAAC-OS is also used as a C-Axis Aligned Nanoclip The semiconductor may also be referred to as an oxide semiconductor having metal ions.

[0253] Here, based on the Cs-corrected high-resolution TEM image, the pellets of CAAC-OS on the substrate 5120 were The layout of the 5100 is shown diagrammatically as a stack of bricks or blocks. (See FIG. 27(D)). Between the pellets observed in FIG. 27(C), The portion where the inclination occurs corresponds to an area 5161 shown in FIG.

[0254] FIG. 28(A) shows the C 28(A) shows the s-corrected high-resolution TEM images of regions (1), (2) and (3) in FIG. ) are enlarged Cs-corrected high-resolution TEM images shown in Fig. 28(B), Fig. 28(C), and Fig. 28(D), respectively. As shown in Figure 28(D), Figure 28(B), Figure 28(C) and Figure 28(D) show that the pellet It can be seen that the metal atoms are arranged in a triangular, quadrangular or hexagonal shape. However, no regularity is observed in the arrangement of metal atoms among different pellets.

[0255] Next, C was analyzed by X-ray diffraction (XRD). AAC-OS will be explained. For example, InGaZnO 4 CAAC-O When the out-of-plane structural analysis is performed on S, the result is as shown in Figure 29(A). As shown in the figure, a peak may appear at a diffraction angle (2θ) of around 31°. ZnO 4 Since the crystal orientation of CAAC-OS is attributed to the (009) plane of the crystal, it is considered that the crystal orientation of CAAC-OS is c-axis oriented. It can be seen that the crystal has a c-axis oriented in a direction substantially perpendicular to the surface on which the crystal is formed or to the upper surface.

[0256] In addition, in the out-of-plane structural analysis of CAAC-OS, 2θ is 31 In addition to the peaks around 2θ of 36°, a peak may also appear around 2θ of 36°. The peaks in the vicinity indicate that some of the CAAC-OS contains crystals that do not have the c-axis orientation. The more preferable CAAC-OS is a structure obtained by the out-of-plane method. The analysis shows a peak at 2θ around 31° and no peak at 2θ around 36°.

[0257] On the other hand, in-pla, X-rays are incident on CAAC-OS from a direction nearly perpendicular to the c-axis. When the structure is analyzed by the NE method, a peak appears at 2θ of about 56°. This peak is I nGaZnO 4 In the case of CAAC-OS, 2θ is set to 5 The sample was fixed at approximately 6° and analyzed while rotating around the normal vector of the sample surface (φ axis). Even if a φ scan is performed, no clear peak appears, as shown in FIG. 29(B). In contrast, InGaZnO 4 In the case of a single crystal oxide semiconductor, 2θ is fixed to about 56° and φ When scanned, it is assigned to a crystal plane equivalent to the (110) plane, as shown in Figure 29(C). Six peaks are observed. Therefore, from the structural analysis using XRD, CAAC-OS It can be seen that the orientation of the a-axis and the b-axis is irregular.

[0258] Next, we will explain the CAAC-OS analyzed by electron diffraction. ZnO 4 For CAAC-OS with a crystal of 300 nm, a probe diameter of 300 nm was used parallel to the sample surface. When an electron beam of 1000 nm is incident on a sample, a diffraction pattern such as that shown in Figure 30(A) ("selected area transmission electron This diffraction pattern may be caused by InGaZn O 4 The spots due to the (009) plane of the crystal are included. However, the pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is aligned with the surface on which the film is formed or the upper surface. On the other hand, the same specimen was subjected to a pulse perpendicular to the specimen surface. FIG. 30(B) shows the diffraction pattern when an electron beam with a lobe diameter of 300 nm is incident. A ring-shaped diffraction pattern can be seen in Figure 30(B). However, it was found that the a-axis and b-axis of the pellets contained in CAAC-OS do not have any orientation. The first ring in FIG. 30(B) is made of InGaZnO 4 Crystal (010) This is believed to be due to the (100) plane and the (101) plane. The gluing is thought to be due to the (110) surface, etc.

[0259] As described above, the CAAC-OS is an oxide semiconductor with high crystallinity. Crystallinity can be reduced by the inclusion of impurities or the generation of defects, so the opposite view can be taken. Therefore, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

[0260] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, metal elements such as silicon have a higher acidity than metal elements that constitute oxide semiconductors. Elements with strong bonds to oxygen remove oxygen from the oxide semiconductor, which changes the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, Carbon dioxide and other molecules have a large atomic radius (or molecular radius), so the atomic arrangement of oxide semiconductors This disrupts the structure and reduces the crystallinity.

[0261] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in oxide semiconductors can act as carrier traps or In addition, oxygen vacancies in oxide semiconductors can act as carrier traps and In some cases, the SiO 2 can become a carrier generation source by capturing hydrogen.

[0262] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. There is. Specifically, 8×10 11 pieces / cm 3 Less than 1 x 10 11 / cm 3 less than , and more preferably 1×10 10 pieces / cm 3 Less than 1 x 10 -9 pieces / cm 3 The above Such an oxide semiconductor can be obtained by using a high-purity pure oxide semiconductor. CAAC-OS is a highly pure or substantially intrinsic oxide semiconductor with low impurity concentration. In other words, it can be said that the oxide semiconductor has stable characteristics.

[0263] <nc-os> In the high-resolution TEM image, the nc-OS is divided into two regions: one where the crystals can be confirmed, and the other where the clear The crystalline parts in nc-OS are In most cases, the size is between 1 nm and 10 nm, or between 1 nm and 3 nm. An oxide semiconductor having a crystal size of 10 nm or more and 100 nm or less is called a microcrystalline oxide. For example, in high-resolution TEM images, nc-OS shows grain boundaries. In some cases, the nanocrystals are not clearly visible in the pellets of CAAC-OS. Therefore, in the following, the crystalline part of nc-OS is referred to as the pellet. There is a chance to call.

[0264] nc-OS is a material that is used in microscopic regions (e.g., regions between 1 nm and 10 nm, especially regions between 1 nm and The atomic arrangement has periodicity in the region of 3 nm or less. There is no regularity in the crystal orientation between the layers. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be classified as a-like OS or amorphous oxide semiconductor. For example, the nc-OS may be a pellet with a larger diameter than the pellet. When X-rays are used, the peaks that indicate the crystal planes are In addition, for nc-OS, the probe diameter is larger than the pellet (e.g., 50 When electron diffraction is performed using an electron beam of 1 nm or more, a halo-like diffraction pattern is produced. On the other hand, for nc-OS, pellets with sizes close to or smaller than the pellets were observed. When nanobeam electron diffraction is performed using an electron beam with a lobe diameter, spots are observed. When nanobeam electron diffraction was performed on nc-OS, high brightness regions were observed in a circular (ring-like) pattern. In addition, multiple spots may be observed within a ring-shaped area. There may be cases where this occurs.

[0265] In this way, the crystal orientation between the pellets (nanocrystals) is not regular, so nc -OS with RANC (Random Aligned nanocrystals) The oxide semiconductor or NANC (Non-Aligned Nanocrystal The semiconductor may also be referred to as an oxide semiconductor having a structure including a metal oxide layer.

[0266] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the a-like OS and amorphous oxide semiconductors. However, the crystal orientation of nc-OS is not regular among different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

[0267] <a-like OS> The a-like OS is an oxide semiconductor that has a structure between the nc-OS and the amorphous oxide semiconductor. A-like OS is a semiconductor. Porosity is often observed in high-resolution TEM images. In addition, in the high-resolution TEM image, there are areas where the crystals can be clearly seen, and and an area in which no crystalline portion can be confirmed.

[0268] Because of the porosity, the a-like OS has an unstable structure. e OS has an unstable structure compared with CAAC-OS and nc-OS. This shows the change in structure due to electron irradiation.

[0269] The samples to be irradiated with electrons were a-like OS (referred to as sample A), nc-OS (hereinafter referred to as sample B) and CAAC-OS (hereinafter referred to as sample C) are prepared. Both samples are In-Ga-Zn oxides.

[0270] First, high-resolution cross-sectional TEM images of each sample are obtained. It can be seen that all the materials have crystalline parts.

[0271] The determination of which part is regarded as one crystal part can be made as follows. For example, , InGaZnO 4 The unit cell of the crystal has three In-O layers and one Ga-Zn-O layer. It is known that the structure has a total of nine layers, six of which are layered in the c-axis direction. The spacing between these adjacent layers is the same as the lattice spacing (also called the "d value") of the (009) plane. The value is about 0.29 nm, which is determined by crystal structure analysis. The areas where the spacing between the fringes is 0.28 nm to 0.30 nm are called InGaZnO 4 Crystal The lattice fringes can be considered as the InGaZnO 4 corresponds to the ab plane of the crystal do.

[0272] Figure 31 shows an example of the average size of the crystal parts (22 to 45 places) of each sample. However, the length of the lattice fringes is the size of the crystal part. It can be seen that the crystalline part of the ke OS grows in size according to the cumulative dose of electron irradiation. Specifically, as shown by (1) in FIG. 31, the initial TEM observation showed a size of about 1.2 nm. The crystal part (also called the initial nucleus), which was sized at 1000 times the size of the initial nucleus, was irradiated with electrons at a cumulative dose of 4.2 × 10 8 e - / nm 2 It can be seen that the size of the crystals grows to about 2.6 nm in the The cumulative electron dose for nc-OS and CAAC-OS was 4.2× 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals within the range of Specifically, as shown in (2) and (3) in FIG. 31, regardless of the cumulative dose of electrons, n The size of the crystal parts of c-OS and CAAC-OS is about 1.4 nm and 2. It can be seen that the size is about 1 nm.

[0273] Thus, in a-like OS, the growth of crystals can be observed by electron irradiation. On the other hand, in the case of nc-OS and CAAC-OS, the growth of the crystals due to electron irradiation is almost nonexistent. In other words, a-like OS is not seen as a nc-OS or CAAC-OS. It is clear that it has an unstable structure compared to the OS.

[0274] In addition, because of the porosity, a-like OS is more difficult to treat than nc-OS and CAAC-OS. Specifically, the density of the a-like OS is The density of the nc-OS and the CAA The density of C-OS is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form a film of an oxide semiconductor having a crystal density of less than 78%.

[0275] For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, Single-crystal InGaZnO with a rhombohedral crystal structure 4 The density of is 6.357g / cm 3 It becomes. For example, in an oxide semiconductor that satisfies the atomic ratio of In:Ga:Zn=1:1:1, The density of a-like OS is 5.0g / cm 3 More than 5.9g / cm 3 It will be less than. For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, , the density of nc-OS and the density of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0276] In some cases, single crystals of the same composition do not exist. In such cases, crystals of different compositions may be used in any ratio. By combining single crystals of the desired composition, the density equivalent to that of a single crystal of the desired composition can be estimated. The density corresponding to a single crystal of a desired composition can be obtained by combining single crystals of different compositions. The density should be as low as possible. It is preferable to estimate the size of the single crystal by combining different types of single crystals.

[0277] As described above, oxide semiconductors have various structures and each structure has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, or an nc-OS. The film may be a laminated film having two or more of the CAAC-OS and CAAC-OS.

[0278] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is Noh.

[0279] (Embodiment 4) In this embodiment, an example of a semiconductor device using a transistor disclosed in this specification will be described. I will explain this in more detail.

[0280] <Structural example of semiconductor device> 32(A) to 32(C) are cross-sectional views of the semiconductor device 400. 0 includes a transistor 100 and a transistor 281. Note that the transistor 100 is This can be replaced with another transistor shown in the above embodiment mode. FIG. 32(B) is a cross-sectional view of the transistor 100 and the transistor 281 in the channel length direction. FIG. 32C is a cross-sectional view in the channel width direction of the transistor 28 in FIG. FIG. 1 is an enlarged view of FIG.

[0281] The semiconductor device 400 uses an n-type semiconductor as the substrate 401. The transistor 281 is A channel forming region 283, a high concentration p-type impurity region 285, an insulator 286, a conductor 287, The structure 288 is provided with a low concentration of The p-type impurity region 284 is provided. The insulator 286 can function as a gate insulating layer. The transistor 281 includes a channel forming region 283. is formed on a portion of the substrate 401 .

[0282] The low concentration p-type impurity region 284 is formed by forming the conductor 287 and before forming the structure 288. The impurity element is introduced using the mask 287. That is, the low concentration p-type impurity region 284 can be formed by self-alignment. After the formation of the structure 288, the high concentration p-type impurity region 285 is formed. The region 284 has the same conductivity type as the high concentration p-type impurity region 285, and the impurity that gives the conductivity type is The concentration is lower than that of the high concentration p-type impurity region 285. In addition, the low concentration p-type impurity region 284 is It may not be provided depending on the situation.

[0283] The transistor 281 is electrically isolated from other transistors by an element isolation layer 414. The element isolation region is formed by LOCOS (Local Oxidation of Silicon). silicon) method and STI (Shallow Trench Isolation) method etc. can be used.

[0284] The transistor 281 can function as a p-channel transistor. An insulator 403 is formed on the sinter 282, and an insulator 404 is formed on the insulator 403. The insulators 403 and 404 are formed of the same material and by the same method as the insulator 111. The insulators 403 and 404 can be made of oxygen, hydrogen, water, and alkali. It is formed using insulating materials that have the function of preventing the diffusion of impurities such as lithium metals and alkaline earth metals. It is preferable that either the insulator 403 or the insulator 404 be omitted. An insulating layer may be further laminated.

[0285] The semiconductor device 400 also includes an insulator 405 having a flat surface on the insulator 404. The insulator 405 can be formed using the same material and method as the insulator 112. In addition, the surface of the insulator 405 may be subjected to CMP treatment.

[0286] In addition, a conductor 413a, a conductor 413b, and a conductor 413c are provided on the insulator 405. The conductor 413a, the conductor 413b, and the conductor 413c are formed as conductors. It can be produced using the same materials and methods as 109a.

[0287] The conductor 413a is connected to the high concentration p-type impurity region 28 via the contact plug 406a. The conductor 413b is electrically connected to one of the contact plugs 406b. The conductor 413c is electrically connected to the other of the high concentration p-type impurity regions 285. It is electrically connected to the conductor 287 via a tact plug 406c.

[0288] In addition, an insulator 407 is provided to cover the conductor 413a, the conductor 413b, and the conductor 413c. The insulator 407 is formed of the same material and by the same method as the insulator 405. In addition, the surface of the insulator 407 may be subjected to CMP processing.

[0289] Further, the insulator 102 is formed on the insulator 407. A transistor 100 is formed on the semiconductor device 100. An insulator 111 is formed on the transistor 100. The configuration of the layers above the edge 407 can be understood by taking into consideration the above embodiment. In addition, the conductor 109b is a contact plug. It is electrically connected to the conductor 413b via 112d.

[0290] <Variation 1> An n-channel transistor may be provided on the substrate 401. 33(B) is a cross-sectional view of the semiconductor device 410. 33A shows a configuration in which an n-channel transistor 282 is added to the transistor 280. The transistor 100, the transistor 281, and the transistor 282 are cut in the channel length direction. 33(A) is a cross-sectional view of the transistor 281, and FIG. 33(B) is an enlarged view of the transistor 281.

[0291] In the transistor 282, a channel forming region 1283 is formed in the well 220. The transistor 282 includes a channel forming region 1283, a high concentration n-type impurity region 1285, The insulating material 286, the conductor 287, and the structure 288 are included. A low concentration n-type impurity region 1284 is provided in the region overlapping with the body 288 .

[0292] The low concentration n-type impurity region 1284 is formed by forming the conductive material 287 and before forming the structure 288. It can be formed by introducing an impurity element using the body 287 as a mask. That is, the low concentration n-type impurity region 1284 can be formed by self-alignment. After the formation of the structure 288, a high concentration n-type impurity region 1285 is formed. The material region 1284 has the same conductivity type as the high concentration n-type impurity region 1285 and imparts the conductivity type. The impurity concentration is lower than that of the high-concentration n-type impurity region 1285. 1284 may not be provided depending on the situation.

[0293] <Variation 2> A further transistor 100 may be provided above the transistor 100. 1 is a cross-sectional view of a semiconductor device 420. The semiconductor device 420 has a transistor on the semiconductor device 410. The transistor 100a has a configuration similar to that of the transistor 100. On top of 00, an insulator 111a is provided.

[0294] The transistor 100a is provided over the insulator 112 with an insulator 407a interposed therebetween. Although not shown in FIG. 34, the insulator 112 and the insulator 103 of the transistor 100a An insulator 102a may be provided between the insulator 407a, the insulator 103a, and the insulator 1 The insulators 407, 103, 102, and 111a are insulators 407, 103, 102, and 111a, respectively. The insulator 111 can be formed using the same material and method as the insulator 111. The transistor 00a can be fabricated in the same manner as the transistor 100.

[0295] The semiconductor device 420 also includes a capacitor 141 and a capacitor 142. One of the conductors 413c constituting the conductor 141 forms the conductors 413a and 413b. The conductor 413a and the conductor 413b are provided in the same layer by using a part of the conductive layer for the purpose. The other conductor 109c constituting the capacitance element 141 can be formed by the conductor 10 A part of the conductive layer for forming the conductor 109a and the conductor 109b is used to form the conductor 109a and The conductor 109c and the conductor 413c may be disposed in the same layer. The insulating layer can function as a dielectric layer for the capacitive element 141 .

[0296] <Modification 3> 35(A) to 35(C) are cross-sectional views of the semiconductor device 430. The transistor 281 of the semiconductor device 400 is replaced with a fin-type transistor 291. By making the transistor a fin type, the effective channel The width of the channel formation region is increased, and the on-state characteristics of the transistor are improved. This increases the contribution of the electric field of the gate electrode to the off-state region, improving the off-state characteristics of the transistor. It is possible to improve the performance.

[0297] In addition, compared to the semiconductor device 400, the semiconductor device 430 has a capacitive element above the transistor. The capacitor 413 includes a conductor 114b, a second conductor, and The conductor 114b is sandwiched between the conductor 114 and the second conductor. The conductor 114b is connected to the transistor 112 via a contact plug 113b. 109b, which functions as the drain or source electrode of the transistor 100; The conductor 109b is provided in the openings of the insulator 407, the insulator 102, and the insulator 118. The gate of the transistor 291 is connected to the contact plug and the conductor 413b. It is connected to a conductor 287 which functions as an electrode.

[0298] [Semiconductor Circuits] The transistor disclosed in the present specification and the like is used in an OR circuit, an AND circuit, a NAND circuit, and Logic circuits such as NOR circuits, inverter circuits, buffer circuits, shift register circuits, Flip-flop circuits, encoder circuits, decoder circuits, amplifier circuits, analog switch circuits It can be used in various semiconductor circuits such as integrating circuits, differentiating circuits, and memory elements. .

[0299] In this embodiment, a peripheral circuit and a pixel circuit will be described with reference to FIGS. The following shows an example of a CMOS circuit that can be used in the present specification. In circuit diagrams, etc., it is preferable to use OS transistors. Circuit symbol of transistor The "OS" is added to the above.

[0300] The CMOS circuit shown in FIG. 36(A) includes a p-channel transistor 281 and an n-channel The inverter transistor 282 is connected in series and the gates of the transistors are connected together. 1 shows an example of the configuration of a capacitor circuit.

[0301] The CMOS circuit shown in FIG. 36B includes a p-channel transistor 281 and an n-channel 2 shows an example of the configuration of an analog switch circuit in which transistors 282 of the same type are connected in parallel. .

[0302] The CMOS circuit shown in FIG. 36C includes a transistor 281a, a transistor 281b, 13 shows an example of a configuration of a NAND circuit using a transistor 282a and a transistor 282b. The NAND circuit is a combination of the potentials input to the input terminals IN_A and IN_B. The output potential changes depending on the combination.

[0303] [Storage device] In the circuit shown in FIG. 37(A), one of the source and drain of the transistor 289 is connected to The structure of the memory device is connected to the gate of the transistor 1281 and one electrode of the capacitor element 257. In addition, the circuit shown in FIG. 37B is a configuration example. 2 shows a configuration example of a memory device in which one of the drains is connected to one of the electrodes of the capacitor element 257. There are.

[0304] The circuits shown in FIG. 37(A) and FIG. 37(B) are The charge input from the other drain can be held at node 256. By using an OS transistor for the transistor 289, the charge of the node 256 is retained for a long period of time. It is possible.

[0305] In FIG. 37A, a p-channel transistor is shown as a transistor 1281. However, an n-channel transistor may be used. For example, the transistor 1281 Alternatively, a transistor 281 or a transistor 282 may be used. An OS transistor may be used as the transistor 1281.

[0306] Here, regarding the semiconductor device (memory device) shown in FIG. 37(A) and FIG. 37(B), Let me explain in detail.

[0307] The semiconductor device shown in FIG. 37A includes a transistor 1281 using a first semiconductor and a The pixel includes a transistor 289 using a semiconductor, and a capacitor 257 .

[0308] The transistor 289 is an OS transistor as described in the above embodiment. The low off-state current of the transistor 289 allows long-term recording at a specific node of the semiconductor device. The contents of the memory can be retained, i.e., no refresh operation is required, or This allows the frequency of refresh operations to be reduced significantly, resulting in a semiconductor with low power consumption. It becomes a body device.

[0309] In FIG. 37A, the wiring 251 is a source or drain of the transistor 1281. The wiring 252 is electrically connected to the source or drain of the transistor 1281. The wiring 253 is electrically connected to the source or drain of the transistor 289. The wiring 254 is electrically connected to the gate of the transistor 289. The gate of transistor 1281, the source of transistor 289, The other of the drains and one of the electrodes of the capacitor 257 are electrically connected to a node 256. The wiring 255 is electrically connected to the other electrode of the capacitor 257. .

[0310] The semiconductor device shown in FIG. 37A has a feature that it can hold charge applied to the node 256. This property makes it possible to write, retain, and read information, as shown below.

[0311] [Write operation, hold operation] The writing and holding of information will be described. First, the potential of the wiring 254 is changed to This causes the potential of the wiring 253 to change to a potential at the node 256. That is, a predetermined charge is applied to node 256 (write). Charges that give two different potential levels (hereinafter referred to as "Low level charge" and "High level charge") Then, the potential of the wiring 254 is changed to By setting the potential at which the transistor 289 is turned off, a charge is held at the node 256. .

[0312] Note that the high level charge provides a higher potential to the node 256 than the low level charge. In addition, when a p-channel transistor is used as the transistor 1281, ,The high-level charge and the low-level charge are both,threshold voltage of the transistor. The charge that gives a higher potential than the charge of the transistor 1281 is an n-channel transistor. When a transistor is used, both the high-level charge and the low-level charge are This is a potential lower than the threshold voltage of the transistor. The ow level charge is a charge that provides a potential that turns off both transistors.

[0313] Since the off-state current of the transistor 289 is extremely small, the charge of the node 256 is It is held upright.

[0314] [Read operation] Next, reading of information will be described. With a potential (constant potential) applied, the wiring 255 is supplied with a read potential V R Given that, node 25 The information stored in 6 can be read out.

[0315] The potential given by the high-level charge is V H , given by the low level charge Electric potential is V L Then, the read potential V R is {(Vth-V H )+(Vth+V L )} / 2. When data is not being read, the potential of the wiring 255 is If a p-channel transistor is used for the 1281, V H At a higher potential, If an n-channel transistor is used for resistor 1281, V L If we assume a lower potential good.

[0316] For example, when a p-channel transistor is used as the transistor 1281, The Vth of the 1281 is -2V, and the V H 1V, V L If we set it to -1V, then V R -2 V. The potential written to node 256 is V H When V is connected to wire 255, R Given When this voltage is applied to the gate of transistor 1281, V R +V H , i.e. -1V is applied Since -1V is higher than Vth, the transistor 1281 does not turn on. The potential of the wiring 252 does not change. L When , wiring 255 to V R is applied to the gate of transistor 1281. R +V L , Sand That is, -3V is applied. Since -3V is lower than Vth, transistor 1281 turns on. As a result, the potential of the wiring 252 changes.

[0317] In addition, when an n-channel transistor is used as the transistor 1281, The Vth of the 1281 is 2V, H 1V, V L If we set it to -1V, then V R Let be 2V The potential written to node 256 is V H When V is connected to wire 255, R is given Then, V is applied to the gate of transistor 1281. R +V H , i.e. 3V is applied. 3V is Since the potential Vth is higher than Vth, the transistor 1281 is turned on. The potential changes. Also, the potential written to node 256 is V L When V is connected to wire 255, R is applied to the gate of transistor 1281. R +V L , i.e. 1V is applied. Since 1V is lower than Vth, the transistor 1281 does not turn on. Therefore, the potential of the wiring 252 does not change.

[0318] By determining the potential of the wiring 252, the data stored in the node 256 can be read out. This can be done.

[0319] The semiconductor device shown in FIG. 37B differs from the semiconductor device shown in FIG. 37A in that it does not include the transistor 1281. This is different from the semiconductor device shown in FIG. 37(A). This allows information to be written and retained.

[0320] The reading of data in the semiconductor device shown in FIG. When a potential that turns on the transistor 289 is applied to the wiring 25 3 and the capacitance element 257 are electrically connected, and charge is redistributed between the wiring 253 and the capacitance element 257. As a result, the potential of the wiring 253 changes. The change in the potential of the wiring 253 is (or the charge stored at node 256).

[0321] For example, the potential of the node 256 is V, the capacitance of the capacitor 257 is C, and the capacitance of the wiring 253 is If the charge component is CB and the potential of the wiring 253 before the charge is redistributed is VB0, The potential of the wiring 253 after being laid out is (CB×VB0+C×V) / (CB+C). Therefore, the state of the memory cell is such that the potential of the node 256 is V1 and V0 (V1>V0). If there are two states, the potential of the wiring 253 when the potential V1 is held (=(CB × VB0 + C × V1) / (CB + C)) is the current of the wiring 253 when the potential V0 is maintained. It can be seen that the potential is higher than the potential (=(CB×VB0+C×V0) / (CB+C)).

[0322] By comparing the potential of the wiring 253 with a predetermined potential, information can be read out. do.

[0323] The above-described semiconductor device is a transistor using an oxide semiconductor and having an extremely small off-state current. By applying the memory, it is possible to retain the memory contents for a long period of time. Refresh operations are no longer necessary or can be performed very infrequently. Therefore, a semiconductor device with low power consumption can be realized. Even if there is no potential (but it is preferable that the potential is fixed), It is possible to retain the stored contents.

[0324] In addition, the semiconductor device does not require a high voltage to write information, so there is no risk of element deterioration. For example, unlike conventional non-volatile memory, the flow of electrons to the floating gate is Since there is no injection or extraction of electrons from the floating gate, there is no degradation of the insulator. That is, the semiconductor device according to one aspect of the present invention does not have the above problems. There is no limit to the number of times that memory can be rewritten, which is a problem with memory, and the reliability of the semiconductor has been dramatically improved. Furthermore, information can be written by turning on or off the transistor. This enables high speed operation.

[0325] 〔CPU〕 In this embodiment, a semiconductor device using the above-described transistor is used as a CPU. FIG. 38 shows an example of a CPU configuration that uses the above-mentioned transistor in part. FIG.

[0326] The CPU shown in FIG. 38 includes an ALU 1191 (ALU: Arithmetic Unit) on a board 1190. tic logic unit, ALU controller 1192, instruction action decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1198 (Bus I / F), rewritable ROM 1199, and ROM interface The substrate 1190 is a semiconductor substrate, an SOI Substrates, glass substrates, etc. are used. ROM 1199 and ROM interface 1189 Of course, the CPU shown in FIG. 38 can be simplified in its configuration. This is just one example, and actual CPUs have a wide variety of configurations depending on their applications. For example, the configuration including the CPU or arithmetic circuit shown in FIG. 38 is regarded as one core, and the core is divided into multiple The CPU may also be configured to include a processor core and each core may operate in parallel. The number of bits that can be handled by a computing circuit or a data bus is, for example, 8 bits, 16 bits, 32 bits, 6 It can be 4 bits, etc.

[0327] The instructions input to the CPU via the bus interface 1198 are The signal is input to the input decoder 1193, decoded, and then passed to the ALU controller 1192, the input The interrupt controller 1194, the register controller 1197, the timing controller It is entered into RA 1195.

[0328] ALU controller 1192, interrupt controller 1194, register controller The controller 1197 and timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates a signal to control the program of the CPU. During program execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and master. The register controller 1197 determines the address of the register 1196 and processes it. It generates an address and reads or writes register 1196 depending on the CPU state. .

[0329] The timing controller 1195 also includes the ALU 1191 and the ALU controller 11 92, an instruction decoder 1193, an interrupt controller 1194, and and generates signals to control the timing of the operation of the register controller 1197. For example, The timing controller 1195 generates an internal clock signal based on the reference clock signal. The internal clock generating unit supplies an internal clock signal to the various circuits described above.

[0330] In the CPU shown in FIG. 38, a memory cell is provided in the register 1196. The above-mentioned transistors and memory devices can be used as memory cells of the memory cell 1196. Cut.

[0331] In the CPU shown in FIG. 38, the register controller 1197 In accordance with the instruction of the register 1196, the holding operation is selected. In the memory cell of 196, data is held by a flip-flop or the capacity Select whether to hold data using a flip-flop. When this is selected, the power supply voltage is supplied to the storage element in the register 1196. If data retention is selected in the capacitive element, rewriting data to the capacitive element This allows the supply of the power supply voltage to the memory cells in the register 1196 to be stopped. .

[0332] FIG. 39 is an example of a circuit diagram of a storage element that can be used as the register 1196. The memory element 730 includes a circuit 701 in which stored data is volatilized when the power is cut off, and a circuit 702 in which stored data is volatilized when the power is cut off. A circuit 702 in which data is not volatile, a switch 703, a switch 704, and a logic element 706 The circuit 702 includes a capacitor 707 and a circuit 720 having a selection function. The memory element 708 includes a transistor 709 and a transistor 710. The element 730 may further include other elements such as diodes, resistors, and inductors as necessary. It may also have.

[0333] Here, the above-mentioned memory device can be used for the circuit 702. When the supply of the power supply voltage is stopped, the gate of the transistor 709 in the circuit 702 is supplied with the ground potential. (0 V), or a potential at which the transistor 709 is turned off is continuously input. For example, the gate of the transistor 709 is grounded via a load such as a resistor.

[0334] The switch 703 is implemented by using a transistor 713 of one conductivity type (for example, an n-channel type). The switch 704 is configured to have the opposite conductivity type to the transistor 713 (e.g., p-channel Here, the first transistor of the switch 703 is The terminal corresponds to one of the source and drain of the transistor 713 and the second terminal of the switch 703. The terminal corresponds to the other of the source and drain of the transistor 713, and the switch 703 is A control signal RD is input to the gate of the transistor 713, and a voltage is applied between the first terminal and the second terminal. The conductive or non-conductive state of transistor 713 (i.e., the on or off state of transistor 713) is selected. The first terminal of the switch 704 is connected to one of the source and drain of the transistor 714. Correspondingly, the second terminal of the switch 704 is connected to the other of the source and drain of the transistor 714. In response, the switch 704 is turned on by a control signal RD input to the gate of the transistor 714. , conduction or non-conduction between the first terminal and the second terminal (i.e., the on / off state of the transistor 714) state or off state) is selected.

[0335] One of the source and drain of the transistor 709 is connected to one of the pair of electrodes of the capacitor 708. and the gate of the transistor 710. The node M2 ​​is connected to one of the source and drain of the transistor 710, which is supplied with a low power supply potential. The other is electrically connected to a wiring (for example, a GND line) that can be connected to a switch 703 The first terminal (one of the source and the drain of the transistor 713) is electrically connected to the first terminal of the transistor 713. The second terminal of the switch 703 (the other of the source and drain of the transistor 713) 704 (one of the source and drain of the transistor 714) The second terminal of the switch 704 (the other of the source and drain of the transistor 714) The switch 703 is electrically connected to a wiring that can supply a power supply potential VDD. A second terminal (the other of the source and drain of the transistor 713) and a first terminal of the switch 704 (one of the source and drain of the transistor 714) and the input terminal of the logic element 706 is electrically connected to one of a pair of electrodes of the capacitor 707. The other of the pair of electrodes of the capacitor 707 is a node M1. For example, a low power supply potential (GND, etc.) or a high power supply potential ( VDD or the like) can be input to one of the pair of electrodes of the capacitor 707. The other is electrically connected to a wiring that can supply a low power supply potential (for example, a GND line). A constant potential is input to the other of the pair of electrodes of the capacitor 708. For example, a low power supply potential (such as GND) or a high power supply potential (such as VDD) can be input. The other of the pair of electrodes of the capacitor 708 can be connected to a low power supply potential. It is electrically connected to a wiring that can supply power (for example, a GND line).

[0336] The capacitors 707 and 708 are formed by accumulating parasitic capacitances of transistors and wirings. It is possible to omit it by using it in an extreme manner.

[0337] A control signal WE is input to the gate electrode of the transistor 709. and the switch 704 is connected between the first terminal and the second terminal by a control signal RD that is different from the control signal WE. A conductive state or a non-conductive state between the first and second terminals of one switch is selected. When the terminals of the switch are in a conductive state, the first and second terminals of the other switch are in a non-conductive state. It becomes.

[0338] The other of the source and drain of the transistor 709 is connected to the data held in the circuit 701. In FIG. 39, the signal output from the circuit 701 is input to the transistor The second terminal of the switch 703 is connected to the other of the source and drain of the switch 709. The signal output from the other terminal of the transistor 713 (the other of the source and drain of the transistor 713) is The logic value of the inverted signal is inverted by the invertor 06 and is sent to the circuit 701 via the circuit 720. is entered.

[0339] In FIG. 39, the second terminal of the switch 703 (the source and drain of the transistor 713) The signal output from the other input is input to the circuit 70 via the logic element 706 and the circuit 720. 1 is an example of inputting the signal to the second terminal (transistor The signal output from the other of the source and drain of the transistor 713 is inverted in logic value. For example, the input from the input terminal may be input to the circuit 701 without being input to the circuit 701. When there is a node that holds a signal with the logic value of the signal input to the switch 70 inverted, A signal output from the second terminal of the third input terminal (the other of the source and drain of the transistor 713) is It can be input to the node.

[0340] The transistor 709 in FIG. 39 is the same as the transistor 15 shown in the first embodiment. 0 can be used. A control signal WE is input to the gate electrode, and a back gate voltage A control signal WE2 can be input to the electrode. The control signal WE2 is a signal with a constant potential. The constant potential may be, for example, a ground potential GND or the source potential of the transistor 709. The control signal WE2 is a potential smaller than the threshold potential of the transistor 709. The gate voltage of the transistor 709 is 0V. The drain current at the time of switching ON can be further reduced. It is also possible to use transistors that do not have two gates.

[0341] In addition, in FIG. 39, among the transistors used in the memory element 730, The transistors other than the transistor 709 are formed on a layer or a substrate 1190 made of a semiconductor other than an oxide semiconductor. For example, a transistor having a channel formed in a silicon layer or The memory element 7 can be a transistor in which a channel is formed in a silicon substrate. All the transistors used in 30 are transistors whose channels are formed in an oxide semiconductor layer. Alternatively, the memory element 730 may be a transistor other than the transistor 709. The transistors are transistors whose channels are formed using an oxide semiconductor layer and transistors whose channels are formed using a non-oxide semiconductor layer. A transistor having a channel formed in a semiconductor layer or substrate 1190 is combined. It may also be used.

[0342] For example, a flip-flop circuit can be used for the circuit 701 in FIG. The logic element 706 may be, for example, an inverter or a clocked inverter. This can be done.

[0343] In the semiconductor device according to one embodiment of the present invention, while a power supply voltage is not supplied to the memory element 730, The data stored in the circuit 701 is transferred to the capacitor 708 in the circuit 702. Therefore, it can be held in node M2.

[0344] As described above, a transistor in which a channel is formed in an oxide semiconductor layer has an off-state current For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor layer is extremely small. The current is higher than the off-current of a transistor whose channel is formed in crystalline silicon. Therefore, by using the transistor as the transistor 709, Therefore, the signal held in the capacitor 708 is retained for a long time even while the power supply voltage is not supplied to the memory element 730. In this way, the memory element 730 retains the memory even when the supply of the power supply voltage is stopped. It is possible to retain the contents (data).

[0345] In addition, by providing switches 703 and 704, the power supply voltage can be This can shorten the time until the circuit 701 later holds the original data again.

[0346] In the circuit 702, the signal held at node M2 ​​is applied to the gate of transistor 710. Therefore, after the supply of the power supply voltage to the storage element 730 is resumed, The signal held at M2 changes the state of transistor 710 (on or off). In other words, the signal held at node M2 ​​can be read out from circuit 702. Even if the corresponding potential varies slightly, the original signal can still be read out accurately.

[0347] Such a memory element 730 may be a memory such as a register or cache memory of a CPU. By using this in equipment, it is possible to prevent data loss in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped is restored in a short time. Therefore, the entire CPU, or one or more logical units that make up the CPU, In circuits, it is now possible to stop power supply for short periods of time, and the frequency of power supply stoppages can be increased. This allows power consumption to be reduced.

[0348] In this embodiment, the memory element 730 is used as a CPU. 30 is DSP (Digital Signal Processor), custom LS I, LSI such as PLD (Programmable Logic Device), RF It can also be applied to (Radio Frequency) tags.

[0349] [Imaging device] An imaging device will be described as an example of a semiconductor device including the above-described transistor.

[0350] <Configuration example of imaging device 600> FIG. 40A is a plan view showing a configuration example of an imaging device 600. The element unit 621, the first circuit 260, the second circuit 270, the third circuit 280, and the fourth circuit In this specification, the first circuit 260 to the fourth circuit 290 are 0 may be referred to as a "peripheral circuit" or a "drive circuit." For example, the first circuit 26 0 can be considered part of the peripheral circuit.

[0351] FIG. 40B is a diagram showing a configuration example of the pixel section 621. The pixel section 621 has p columns and q rows ( p and q are natural numbers of 2 or more) are arranged in a matrix of a plurality of pixels 622 (imaging element In FIG. 40(B), n is a natural number between 1 and p, and m is a natural number between 1 and q. are the natural numbers below.

[0352] For example, if pixels 622 are arranged in a 1920 x 1080 matrix, a so-called full High definition (also called "2K resolution," "2K1K," or "2K") resolution In addition, for example, the pixel 622 can be set to 40 When arranged in a 96 x 2160 matrix, it becomes what is known as ultra-high definition (4K resolution). (also called "4K2K", "4K", etc.) 00 can be realized. Also, for example, pixel 622 can be a matrix of 8192 x 4320. When these are arranged in a grid, they form what is known as super high vision (8K resolution, 8K4K, It is possible to realize an imaging device 600 capable of capturing images at a resolution of 1080p (also called "8K"). By increasing the number of display elements, it is possible to realize an imaging device 600 capable of imaging at a resolution of 16K or 32K. It is also possible to achieve this.

[0353] The first circuit 260 and the second circuit 270 are connected to a plurality of pixels 622. The first circuit 260 has a function of supplying a signal for driving the pixel 622. The third circuit may have a function of processing the analog signal output from the third circuit. The circuit 280 may have a function of controlling the operation timing of the peripheral circuits. The clock signal may be generated by the external clock signal. The third circuit 280 may have a function of converting the frequency of the reference potential signal. The input / output terminal may have a function of supplying a signal (for example, a ramp signal).

[0354] The peripheral circuits include at least a logic circuit, a switch, a buffer, an amplifier circuit, or a converter circuit. The transistors used in the peripheral circuits are the same as those in the pixel driving circuit 6 described later. It may be formed by using a part of the semiconductor formed to fabricate 10. A part or the whole may be implemented as a semiconductor device such as an IC.

[0355] Note that the peripheral circuits include at least one of the first circuit 260 to the fourth circuit 290. For example, the function of either the first circuit 260 or the fourth circuit 290 may be omitted. In addition to the other of the first circuit 260 or the fourth circuit 290, Alternatively, for example, the second circuit 270 or the third circuit 290 may be omitted. The function of one of the circuits 280 is added to the other of the second circuit 270 or the third circuit 280, Either the second circuit 270 or the third circuit 280 may be omitted. By adding the functions of other peripheral circuits to any one of the first circuit 260 to the fourth circuit 290, In this way, other peripheral circuits may be omitted.

[0356] As shown in FIG. 41, the first circuit 260 to the fourth circuit 261 are arranged along the periphery of the pixel portion 621. In addition, the pixel 6 in the pixel portion 621 of the imaging device 600 may be provided with a circuit 290. By arranging the pixels 622 at an angle, the row direction and the column direction can be adjusted. This allows the pixel interval (pitch) in the direction to be shortened. This can improve the quality of the captured image.

[0357] As shown in FIG. 42, a picture is overlapped above the first circuit 260 to the fourth circuit 290. A base portion 621 may be provided. FIG. 42A shows the top of the first circuit 260 to the fourth circuit 290. 42B is a top view of an imaging device 600 in which a pixel portion 621 is formed on the other side. 42(A) is a perspective view for explaining the configuration of the imaging device 600 shown in FIG.

[0358] By providing the pixel portion 621 above the first circuit 260 to the fourth circuit 290, The area occupied by the pixel portion 621 relative to the size of the imaging device 600 can be increased. This improves the light receiving sensitivity of the imaging device 600. In addition, the resolution of the imaging device 600 can be improved. In addition, the reproducibility of the image captured by the imaging device 600 can be improved. Therefore, the integration density of the imaging device 600 can be improved.

[0359] [Color filters, etc.] The pixels 622 included in the imaging device 600 are used as sub-pixels, and each of the pixels 622 By providing filters (color filters) that transmit light of different wavelengths, a color image can be produced. It is possible to obtain information for realizing the display.

[0360] FIG. 43A is a plan view showing an example of a pixel 623 for acquiring a color image. FIG. 43A shows a pixel 62 provided with a color filter that transmits light in the red (R) wavelength range. 2 (hereinafter also referred to as "pixel 622R"), a color filter that transmits light in the green (G) wavelength range. A pixel 622 (hereinafter also referred to as "pixel 622G") in which the pixel 622 is provided and a wavelength band of blue (B) A pixel 622 (hereinafter, also referred to as “pixel 622B”) is provided with a color filter that transmits light of The pixels 622R, 622G, and 622B are grouped together to form a single pixel 623. Function as.

[0361] The color filters used in the pixel 623 are not limited to red (R), green (G), and blue (B). The color filters transmit cyan (C), yellow (Y) and magenta (M) light. A pixel 623 may include a pixel 623 that detects light of at least three different wavelength ranges. By providing 22, a full color image can be obtained.

[0362] Figure 43(B) shows color filters that transmit red (R), green (G) and blue (B) light, respectively. In addition to the pixel 622 having the filter, a color filter that transmits yellow (Y) light is provided. FIG. 43(C) illustrates a pixel 623 having a pixel 622 with a cyan (C) A pixel provided with a color filter that transmits yellow (Y) and magenta (M) light. In addition to the pixel 622, a pixel 622 is provided with a color filter that transmits blue (B) light. A pixel 623 is shown as an example. A single pixel 623 detects light of four or more different wavelength ranges. By providing the pixel 622, the color reproducibility of the acquired image can be further improved. .

[0363] In addition, the pixel number ratio (or light receiving area) of the pixel 622R, the pixel 622G, and the pixel 622B The pixel ratio ( The ratio of the light receiving areas of the pixels may be a Bayer array of red, green, and blue, with red:green:blue being 1:2:1. The numerical ratio (light receiving area ratio) may be red:green:blue=1:6:1.

[0364] Although the number of pixels 622 used for the pixel 623 may be one, it is preferable to use two or more. By providing two or more pixels 622 that detect light in the same wavelength range, redundancy is increased, and the imaging device This can improve the reliability of the device 600.

[0365] In addition, it acts as a filter by absorbing or reflecting light with wavelengths shorter than the wavelength of visible light, and by blocking infrared light. By using an IR (IR: Infrared) filter that transmits light, infrared light can be detected. In addition, it is possible to realize an imaging device 600 that can detect wavelengths longer than the wavelength of visible light as a filter. UV (UV: Ultra Vio) By using a filter, it is possible to realize an imaging device 600 that detects ultraviolet light. In addition, a scintillator that converts radiation into ultraviolet light or visible light is used as a filter. This allows the imaging device 600 to function as a radiation detector for detecting X-rays, gamma rays, etc. It is also possible.

[0366] In addition, a Neutral Density (ND) filter is used as a filter. When a large amount of light is incident on the photoelectric conversion element (light receiving element), This can prevent the phenomenon of output saturation (hereinafter also referred to as "output saturation") that occurs when By combining ND filters with different light intensities, the dynamic range of the imaging device can be expanded. can be made larger.

[0367] In addition to the above-mentioned filter, a lens may be provided in the pixel 622. An example of the arrangement of the pixels 622, the filters 624, and the lenses 625 will be described with reference to the cross-sectional view of FIG. By providing the lens 625, incident light can be efficiently received by the photoelectric conversion element. Specifically, as shown in FIG. 44A, a lens 625 formed in a pixel 622, a filter 624 (filter 624R, filter 624G, filter 624B), and the pixel drive circuit The structure may be such that light 660 is incident on the photoelectric conversion element 601 through a path 610 or the like. .

[0368] However, as shown in the area surrounded by the two-dot chain line, a part of the light 660 indicated by the arrow is connected to the wiring group 62. 6, transistors, and / or capacitors may block the light. Therefore, as shown in FIG. 44(B), a lens 625 and a and a filter 624 are formed to allow the photoelectric conversion element 601 to efficiently receive incident light. By making the light 660 incident from the photoelectric conversion element 601 side, an image with high light receiving sensitivity can be obtained. An imaging device 600 can be provided.

[0369] 45(A) to 45(C) show a pixel driving circuit 6 that can be used in the pixel section 621. 45A shows an example of a pixel driver circuit 610 including a transistor 602, The transistor 604 and the capacitor element 606 are connected to the photoelectric conversion element 601. One of the source and drain of the transistor 602 is electrically connected to the photoelectric conversion element 601. The other of the source and drain of the transistor 602 is connected to a node 607 (a charge storage portion). ) is electrically connected to the gate of the transistor 604.

[0370] The transistor 602 is preferably an OS transistor. Since the off-current can be made extremely small, the capacitor 606 can be made small. 45(B), the capacitor 606 can be omitted. In addition, when an OS transistor is used as the transistor 602, the potential of the node 607 changes. Therefore, it is possible to realize an imaging device that is less susceptible to the effects of noise. Alternatively, the transistor 604 may be an OS transistor.

[0371] The photoelectric conversion element 601 has a pn-type or pin-type junction formed on a silicon substrate. A diode element can be used. Alternatively, an amorphous silicon film or a microcrystalline silicon film can be used. Alternatively, a pin-type diode element using a diode may be used. A variable resistor utilizing the photoelectric effect may also be used. It may be formed using selenium, selenium, etc.

[0372] In addition, materials capable of absorbing radiation and generating electric charges are used as photoelectric conversion elements. The material capable of absorbing radiation and generating a charge may be iodine. These include lead iodide, mercury iodide, gallium arsenide, CdTe, and CdZn.

[0373] The pixel driving circuit 610 shown in FIG. 604, a transistor 605, and a capacitor 606. The pixel driving circuit 610 shown in FIG. The element 601 is a photodiode. One of the source and drain is electrically connected to the cathode of the photoelectric conversion element 601, and the other is The anode of the photoelectric conversion element 601 is electrically connected to the wiring 611. The source or drain of the transistor 603 is electrically connected to the node The other end is electrically connected to a wiring 608. The gate of 604 is electrically connected to a node 607, and either the source or the drain is connected to a wiring. 609, and the other is electrically connected to one of the source and drain of the transistor 605. The other of the source and the drain of the transistor 605 is electrically connected to the wiring 60 One electrode of the capacitor 606 is electrically connected to a node 607. The other electrode is electrically connected to a wiring 611.

[0374] The transistor 602 can function as a transfer transistor. A transfer signal TX is supplied to the transistor 603. The transistor 603 serves as a reset transistor. A reset signal RST is supplied to the gate of the transistor 603. Transistor 604 can function as an amplifying transistor. Transistor 605 can function as a selection transistor. The gate of the transistor 605 is supplied with a selection signal SEL. In addition, VDD is supplied to the wiring 608, and VSS is supplied to the wiring 611.

[0375] Next, the operation of the pixel driving circuit 610 shown in FIG. The resistor 603 is turned on to supply VDD to the node 607 (reset operation). After that, when the transistor 603 is turned off, VDD is held at the node 607. When the transistor 602 is turned on, the photoelectric conversion element 601 receives a light amount. The potential of the node 607 changes (storage operation). Then, the transistor 602 is turned off. Then, the potential of the node 607 is held. Next, when the transistor 605 is turned on, A potential corresponding to the potential of the node 607 is output from the wiring 609 (selection operation). By detecting the potential of the photoelectric conversion element 601, the amount of light received by the photoelectric conversion element 601 can be known.

[0376] The transistors 602 and 603 may be OS transistors. As described above, the off-state current of the OS transistor can be made extremely small. Therefore, the capacitance element 606 can be made smaller. Alternatively, the capacitance element 606 can be omitted. In addition, the transistors 602 and 603 may be OS transistors. When a capacitor is used, the potential of the node 607 is less likely to fluctuate. Therefore, the node 607 is less susceptible to noise. An imaging device can be realized.

[0377] A pixel 6 using any one of the pixel driving circuits 610 shown in FIG. 45(A) to FIG. 45(C) By arranging the pixels 22 in a matrix, a high-resolution imaging device can be realized.

[0378] For example, if the pixel driving circuits 610 are arranged in a 1920×1080 matrix, Loose full HD (also called "2K resolution", "2K1K", "2K", etc.) In addition, for example, the pixel driving circuit 6 When 10 pixels are arranged in a 4096 x 2160 matrix, this becomes what is known as Ultra Hi-Vision. (also called "4K resolution", "4K2K", "4K", etc.) In addition, for example, the pixel driving circuit 610 can be configured as an 8192×43 When arranged in a matrix of 20, it produces what is known as super high vision (8K resolution, It is also called "8K4K" or "8K". By increasing the number of display elements, it is possible to create an imaging device capable of capturing images at resolutions of 16K or 32K. It is also possible to achieve this.

[0379] A structural example of a pixel 622 using the above-mentioned transistor is shown in FIG. FIG. 2 is a cross-sectional view of a portion of FIG.

[0380] The pixel 622 shown in FIG. 46 uses an n-type semiconductor as the substrate 401. The p-type semiconductor 221 of the photoelectric conversion element 601 is provided in the substrate 401. A part of it functions as the n-type semiconductor 223 of the photoelectric conversion element 601 .

[0381] The transistor 604 is provided on the substrate 401. In addition, a p-type semiconductor layer is formed on a portion of the substrate 401. The well 220 is formed in a similar manner to the formation of the p-type semiconductor 221. In addition, the well 220 and the p-type semiconductor 221 can be formed at the same time. Note that the transistor 604 may be, for example, the transistor 282. can be done.

[0382] In addition, an insulator 403 and an insulator 404 are formed on the photoelectric conversion element 601 and the transistor 604. 4, and an insulator 405 are formed. An opening 224 is formed in the region overlapping with the insulator 403 (n-type semiconductor 223), and the insulators 403 to 4 An opening 225 is formed in a region where the p-type semiconductor 221 of the semiconductor substrate 05 overlaps with the p-type semiconductor 221. A contact plug 406 is formed in the opening 225. The opening 22 can be provided in the same manner as the contact plug 113a described above. There is no particular restriction on the number or arrangement of the openings 225 and 4. This makes it possible to realize an imaging device with high image quality.

[0383] In addition, a conductor 421, a conductor 422, and a conductor 429 are formed over the insulator 405. The conductor 421 is connected to the contact plug 406 provided in the opening 224. The conductor 429 is electrically connected to the n-type semiconductor 223 (substrate 401). The contact plug 406 is electrically connected to the p-type semiconductor 221 through the contact plug 406 provided in the hole 225. The conductor 422 can function as one electrode of the capacitor 606.

[0384] In addition, an insulator 407 is formed to cover the conductor 421, the conductor 429, and the conductor 422. The insulator 407 can be formed using the same material and method as the insulator 405. In addition, a CMP process may be performed on the surface of the insulator 407. This reduces the unevenness of the sample surface and improves the coverage of the insulating and conductive layers that will be formed later. The conductor 421, the conductor 422, and the conductor 429 are the same as the conductor 114a described above. It can be formed by the same materials and methods as those described above.

[0385] In addition, the insulator 102 is formed on the insulator 407, and the conductor 427 is formed on the insulator 102. , the conductor 119, and the electrode 273 are formed. The conductor 427 is a contact plug. The conductor 119 is electrically connected to the conductor 429 through the transistor 602. The electrode 273 can function as the other electrode of the capacitor 606. The transistor 602 can be, for example, the transistor 100 described above. can.

[0386] The conductor 109a is electrically connected to the conductor 427 via a contact plug. There are.

[0387] <Variation 1> An example of the configuration of the pixel 622 different from that shown in FIG. 46 is shown in FIG. 47. FIG. 47 shows a cross-section of a part of the pixel 622. FIG.

[0388] The pixel 622 shown in FIG. 47 includes a transistor 604 and a transistor 605 on a substrate 401. The transistor 604 can function as an n-channel transistor. The transistor 605 can function as a p-channel transistor. The transistor 604 may be, for example, the transistor 282 described above. As the transistor 605, for example, the above-mentioned transistor 281 can be used.

[0389] Conductors 413a to 413d are formed over the insulator 405. 3a is electrically connected to one of the source and drain of the transistor 604, and the conductor 4 13 b is electrically connected to the other of the source and drain of the transistor 604 . The conductor 413c is electrically connected to the gate of the transistor 604. 3b is electrically connected to one of the source and drain of the transistor 605, and the conductor 4 13 d is electrically connected to the other of the source and drain of the transistor 605 .

[0390] The conductor 109b and the conductor 413c are electrically connected via a contact plug 112d. In addition, an insulator 4 is provided on the conductor 114a, the conductor 114b, and the insulator 112. The insulator 415 is formed using the same material and method as the insulator 111. It is possible.

[0391] In addition, in the pixel 622 shown in FIG. 47, a photoelectric conversion element 601 is provided on an insulator 415. In addition, an insulator 442 is provided over the photoelectric conversion element 601, and a conductor is provided over the insulator 442. 488 is provided. The insulator 442 is formed of the same material and in the same manner as the insulator 415. It is possible.

[0392] The photoelectric conversion element 601 shown in FIG. 47 includes a conductor 686 formed of a metal material or the like and a light-transmitting A photoelectric conversion layer 681 is provided between the conductive layer 682. In FIG. The photoelectric conversion element 601 using a selenium-based material is a visible The photoelectric conversion element has a high external quantum efficiency. This makes it possible to provide a highly sensitive sensor with a large amplification of electrons relative to the amount of incident light. In addition, since selenium-based materials have a high light absorption coefficient, they have the advantage that the photoelectric conversion layer 681 can be easily made thin. do.

[0393] As the selenium-based material, amorphous selenium or crystalline selenium can be used. For example, amorphous selenium can be obtained by forming a film of amorphous selenium and then performing a heat treatment. By making the grain size of the crystalline selenium smaller than the pixel pitch, the characteristic variation between pixels is reduced. Crystalline selenium also has a higher spectral sensitivity to visible light than amorphous selenium. It has the characteristics of high sensitivity and light absorption coefficient.

[0394] Although the photoelectric conversion layer 681 is illustrated as a single layer, the hole Gallium oxide or cerium oxide is provided as an injection blocking layer, and electron injection is performed on the conductor 686 side. The blocking layer may be nickel oxide or antimony sulfide. .

[0395] The photoelectric conversion layer 681 is a layer containing a compound of copper, indium, and selenium (CIS). Alternatively, a layer containing a compound of copper, indium, gallium, and selenium (CIGS) may be used. In CIS and CIGS, the avalanche phenomenon is similar to that in the case of a single layer of selenium. A usable photoelectric conversion element can be formed.

[0396] In addition, CIS and CIGS are p-type semiconductors, and n-type semiconductors are used to form junctions. Cadmium sulfide, zinc sulfide, or the like may be provided in contact with the metal.

[0397] In order to generate the avalanche phenomenon, a relatively high voltage (for example, 1 It is preferable to apply a voltage of 0 V or more to the OS transistor. Since it has high rain withstand voltage characteristics, it is easy to apply a relatively high voltage to the photoelectric conversion element. Therefore, we have developed an OS transistor with a high drain withstand voltage and a selenium-based photoconductive By combining it with a photoelectric conversion element with a photodiode, a highly sensitive and reliable imaging device can be obtained. It is possible.

[0398] The transparent conductive layer 682 may be made of, for example, indium tin oxide or indium tin containing silicon. Oxides, indium oxide containing zinc, zinc oxide, zinc oxide containing gallium, aluminum Zinc oxide containing fluorine, tin oxide, tin oxide containing antimony, or graphite In addition, the light-transmitting conductive layer 682 is not limited to a single layer, but may be a stack of different films. 47, the light-transmitting conductive layer 682 and the wiring 487 are formed by the conductor 48 8 and a contact plug 489. The conductive layer 682 and the wiring 487 may be in direct contact with each other.

[0399] The conductor 686 and the wiring 487 may have a structure in which a plurality of conductive layers are stacked. For example, the conductor 686 may be formed of two layers, a conductor 686a and a conductor 686b, and the wiring 487 may be formed of a conductor 686b. The conductive layer 487 may be a double layer of conductive material 487a and conductive material 487b. The conductors 86a and 487a are formed by selecting a low resistance metal or the like, and the conductors 686b and The conductor 487b is formed by selecting a metal or the like having good contact characteristics with the photoelectric conversion layer 681. With such a structure, the electrical characteristics of the photoelectric conversion element can be improved. In addition, some metals may cause electrolytic corrosion when in contact with the transparent conductive layer 682. Even if such a metal is used for the conductor 487a, the conductor 487b can be used to This can prevent electrolytic corrosion.

[0400] The conductor 686b and the conductor 487b are made of, for example, molybdenum or tungsten. The conductor 686a and the conductor 487a may be made of, for example, aluminum. Stacks such as titanium sandwiched between aluminum, titanium, or aluminum can be used.

[0401] The insulator 442 may have a multi-layer structure. The partition wall 477 can be formed of an organic resin or the like. Black, etc., to block light from the surroundings and / or to determine the area of ​​the light receiving part per pixel The composition may be colored.

[0402] The photoelectric conversion element 601 is made of p-type semiconductor using an amorphous silicon film or a microcrystalline silicon film. An in-type diode element or the like may be used. The photodiode has an n-type semiconductor layer The i-type semiconductor layer has a structure in which an i-type semiconductor layer and a p-type semiconductor layer are laminated in this order. The conductor layer is preferably made of amorphous silicon. The semiconductor layers are made of amorphous silicon or microcrystalline silicon containing dopants that impart the respective conductivity types. A photodiode using amorphous silicon as a photoelectric conversion layer can be used. The card has high sensitivity in the visible light wavelength range and can easily detect weak visible light.

[0403] In addition, pn-type and pin-type diode elements are designed so that the p-type semiconductor layer is the light-receiving surface. By using a p-type semiconductor layer as a light receiving surface, the output of the photoelectric conversion element 601 The current can be increased.

[0404] The photoelectric conversion element 601 formed using the above-mentioned selenium-based material, amorphous silicon, etc. It is made using general semiconductor manufacturing processes such as film formation, lithography, and etching. It is possible to manufacture.

[0405] [Display device] As an example of a semiconductor device including the above-described transistor, a display device will be described. Display devices (such as liquid crystal display devices and light-emitting display devices) are devices that have display elements. The present invention may use various configurations or have various elements.

[0406] The display device may be, for example, an EL (electroluminescence) element (organic or inorganic material) EL elements, organic EL elements, inorganic EL elements), LED chips (white LED chips, red LED chip, green LED chip, blue LED chip, etc.), transistor (depending on the current transistors that emit light when exposed to light, electron emitters, display elements using carbon nanotubes, Crystal elements, electronic ink, electrowetting elements, electrophoretic elements, MEMS (microelectromechanical systems) Display elements using a laser-electro-mechanical system (e.g., grating lasers) Light valve (GLV), digital micromirror device (DMD), DMS (Digital ·Micro·Shutter), MIRASOL (registered trademark), IMOD (Interference Modulation MEMS display elements using the shutter method, and MEMS display elements using the optical interference method MS display elements, piezoelectric ceramic displays, etc.), or at least quantum dots, etc. also has one.

[0407] In addition to these, display devices can also adjust contrast, brightness, The display device may have a display medium whose reflectance, transmittance, etc. change. For example, the display device may be a plasma display device. The display may be a plasma display panel (PDP).

[0408] An example of a display device using an EL element is an EL display. An example of a display device using electrons is a field emission display (FED). or SED type flat panel display (SED: Surface-conduction Examples include LCDs (Electron-emitter Displays).

[0409] An example of a display device that uses quantum dots for each pixel is a quantum dot display. Quantum dots are not used as display elements, but as backplanes for liquid crystal displays and the like. It may be installed in part of the light. By using quantum dots, it is possible to display with high color purity. It is possible.

[0410] An example of a display device using a liquid crystal element is a liquid crystal display device (transmissive liquid crystal display, Transflective LCD, Reflective LCD, Direct-view LCD, Projection LCD LCD display), etc.

[0411] In order to realize a semi-transmissive or reflective LCD, the pixels A part or the whole of the electrode may function as a reflective electrode. For example, A part or the whole of the pixel electrode may be made of aluminum, silver, etc. In this case, it is also possible to provide a memory circuit such as an SRAM under the reflective electrode. This makes it possible to further reduce power consumption.

[0412] An example of a display device using electronic ink, electronic liquid powder, or electrophoretic elements. Examples include electronic paper.

[0413] When using LED chips in display elements, etc., the electrodes of the LED chip and the nitride semiconductor Graphene or graphite may be placed under the A multi-layer film may be formed by stacking several layers. By this, a nitride semiconductor, for example, a crystal-containing n-type GaN semiconductor layer, etc., can be formed thereon. It is easy to form a film. Furthermore, a p-type GaN semiconductor layer having crystals can be formed on it. In addition, the graphene and graphite can be used together to form an LED chip. An AlN layer may be provided between the n-type GaN semiconductor layer having crystals. The GaN semiconductor layer of the chip may be formed by MOCVD. This allows the GaN semiconductor layer of the LED chip to be deposited by sputtering. It is Noh.

[0414] In addition, in a display element using MEMS, the space in which the display element is sealed (e.g. an element substrate on which display elements are arranged, and an opposing substrate arranged opposite the element substrate; By placing a desiccant, moisture in the MEMS and other components can be prevented. This can prevent the product from becoming difficult to move and becoming more susceptible to deterioration.

[0415] <Pixel circuit configuration example> Next, a more specific example of the configuration of the display device will be described with reference to FIG. 3 is a block diagram for explaining the configuration of a display device 3100. The display device 3131 includes a display area 3131, a circuit 3132, and a circuit 3133. The circuit 3132 includes, for example, For example, the circuit 3133 functions as a scanning line driver circuit. It works like this.

[0416] The display devices 3100 are arranged in parallel with each other and are electrically connected to each other by a circuit 3132. m scanning lines 3135 whose positions are controlled, and a circuit 3133 arranged substantially parallel to each other. and n signal lines 3136 whose potentials are controlled by the The image sensor 1 has a plurality of pixels 3130 arranged in a matrix of m rows and n columns. Note that m and n are Both are natural numbers greater than or equal to 2.

[0417] In the display area 3131, each scanning line 3135 corresponds to one of the rows of the pixels 3130. Each signal line 3136 is electrically connected to n pixels 3130 arranged in a pixel array. Among the pixels 3130, m pixels 3130 arranged in any one column are electrically connected to .

[0418] As shown in FIG. 49(A), a display area 3131 is sandwiched between a circuit 3132 and a display panel 3133. A circuit 3152 may be provided at the position of the display area 31 as shown in FIG. A circuit 3153 may be provided at a position facing the circuit 3133 across the substrate 31. 49(B), the circuit 3152 is connected to the scanning line 3135 in the same manner as the circuit 3132. However, the present invention is not limited to this. For example, the circuit 3 connected to the scanning line 3135 is 132 and the circuit 3152 may be changed every few rows. In FIG. 49(B), the circuit 3153 is 3, an example is shown in which the signal line 3136 is connected to the line 3133. However, the present invention is not limited to this. For example, For example, the circuit 3133 and the circuit 3153 connected to the signal line 3136 may be changed every few rows. In addition, the circuit 3132, the circuit 3133, the circuit 3152, and the circuit 3153 are The driving circuit may have a function other than driving the driving circuit.

[0419] In addition, the circuit 3132, the circuit 3133, the circuit 3152, and the circuit 3153 are included in the drive circuit section. The pixel 3130 includes a pixel circuit 3137 and a display element. The circuit 3137 is a circuit for driving the display element. The transistors constituting the circuit 3137 can be formed at the same time. may be formed on another substrate and electrically connected to the display device 3100. For example, a part or the whole of the driving circuit portion may be formed using a single crystal substrate. may be electrically connected to

[0420] 48(B) and 48(C) show a pixel 3130 of the display device 3100. The figure shows a circuit configuration that can be used.

[0421] <<An example of a pixel circuit for a light-emitting display device>> FIG. 48B shows an example of a pixel circuit that can be used in a light-emitting display device. The pixel circuit 3137 shown in FIG. The pixel circuit 3137 includes a display It is electrically connected to a light-emitting element 3125 that can function as an element.

[0422] One of the source electrode and the drain electrode of the transistor 3431 is connected to a data signal. The pixel electrodes 3136 are electrically connected to the n-th signal line 3136 (hereinafter, referred to as signal line DL_n) in the n-th column. Further, the gate electrode of the transistor 3431 is connected to the m-th scanning line 3 135 (hereinafter referred to as scanning line GL_m).

[0423] Transistor 3431 serves the function of controlling the writing of a data signal to node 3435. Yes.

[0424] One of a pair of electrodes of the capacitor 3233 is electrically connected to the node 3435, and the other is , and a node 3437. In addition, the source electrode and The other of the drain electrodes is electrically connected to a node 3435.

[0425] The capacitor 3233 serves as a storage capacitor for storing data written to the node 3435. It has the following functions.

[0426] One of the source electrode and the drain electrode of the transistor 3232 is connected to the potential supply line VL_a and the other is electrically connected to node 3437. The gate electrode of the transistor 3232 is electrically connected to a node 3435.

[0427] One of the source electrode and the drain electrode of the transistor 3434 is connected to the potential supply line VL_c and the other is electrically connected to node 3437. The gate electrode of the transistor 3434 is electrically connected to the scanning line GL_m.

[0428] One of the anode and the cathode of the light emitting element 3125 is electrically connected to the potential supply line VL_b. and the other is electrically connected to node 3437.

[0429] The light emitting element 3125 may be, for example, an organic electroluminescence element (organic EL element). However, the present invention is not limited to this, and examples thereof include inorganic materials. Alternatively, an inorganic EL element may be used.

[0430] For example, the potential supply line VL_a has a function of supplying VDD. The potential supply line VL_b has the function of supplying VSS. Possesses the ability.

[0431] Here, an example of the operation of a display device having the pixel circuit 3137 of FIG. First, the pixel circuits 3137 in each row are selected in sequence by the circuit 3132, and the transistors 3 431 is turned on to write a data signal (electric potential) to node 3435. A transistor 3434 is turned on to set the potential of a node 3437 to VSS.

[0432] Then, the transistor 3431 is turned off, and the data written to the node 3435 is The signal is held. Next, the transistor 3434 is turned off. The transistor 3232 The amount of current flowing between the source and drain of Therefore, the light emitting element 3125 emits light with a luminance according to the amount of current flowing. By performing this process row by row, an image can be displayed.

[0433] In addition, the pixels 3130 are each used as a sub-pixel, and different By emitting light in a wavelength range of red, a color image can be displayed. A pixel 3130 that emits light in a wavelength range, a pixel 3130 that emits light in a green wavelength range, and a pixel 3130 that emits light in a blue wavelength range. The pixel 3130 that emits light of a long wavelength range is used as one pixel.

[0434] The wavelength range of the light to be combined is not limited to red, green, and blue, but may be cyan, yellow, and A sub-pixel that emits light of at least three different wavelength ranges may be used. By providing pixels, a color image can be displayed.

[0435] In addition to red, green, and blue, one or more colors such as yellow, cyan, magenta, and white can be added. For example, in addition to red, green, and blue, a subpixel that emits light in the yellow wavelength range may be added. You may also add one or more of red, green, blue, and white to the cyan, yellow, and magenta colors. For example, adding a subpixel that emits light in the blue wavelength range in addition to cyan, yellow, and magenta. By providing one pixel with sub-pixels that emit light in four or more different wavelength ranges, This can further improve the color reproducibility of the displayed image.

[0436] In addition, the ratio of the number of red, green, and blue pixels (or the light-emitting area ratio) used in one pixel is not necessarily It does not have to be 1:1:1. For example, if the pixel ratio (light-emitting area ratio) is red:green:blue=1:1: Alternatively, the pixel ratio (light receiving area ratio) may be red:green:blue=1:2:3. .

[0437] In addition, by combining red, green, and blue color filters with the subpixels that emit white light, In addition, sub-pixels that emit light in the red, green, or blue wavelength ranges can be used to realize color displays. Each can be combined with a color filter that transmits light in the red, green, or blue wavelength range. good.

[0438] However, the present invention is not limited to a color display device, and may be applied to a monochrome display device. The present invention can also be applied to display devices.

[0439] <<An example of a pixel circuit for a liquid crystal display device>> FIG. 48(C) shows an example of a pixel circuit that can be used in a liquid crystal display device. The pixel circuit 3137 shown in FIG. The pixel circuit 3137 is electrically connected to a liquid crystal element 3432 that can function as a display element. This is being continued.

[0440] The potential of one of the pair of electrodes of the liquid crystal element 3432 is appropriately set according to the specifications of the pixel circuit 3137. The liquid crystal contained in the liquid crystal element 3432 is set. The alignment state is set by the liquid crystal element of each of the pixel circuits 3137. A common potential may be applied to one of the pair of electrodes of the terminal 3432.

[0441] The mode of the liquid crystal element 3432 is, for example, TN mode, STN mode, VA mode. , ASM(Axially Symmetric Aligned Micro-cel l) mode, OCB (Optically Compensated Birefring induction mode, FLC (Ferroelectric Liquid Crystal al) mode, AFLC (AntiFerroelectric Liquid Cry stal) mode, MVA mode, PVA (Patterned Vertical A lignment) mode, IPS mode, FFS mode, or TBA (Transv You can also use the Second Bend Alignment mode. Then, ECB (Electrically Controlled Birefring ence) mode, PDLC (Polymer Dispersed Liquid Crystal Crystal mode, PNLC (Polymer Network Liquid Crystal There are various modes, including, but not limited to, the following: Various modes can be used.

[0442] Also, a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent. The liquid crystal element 3432 may be configured by the liquid crystal having a response speed of 1 msec. c or less, and is optically isotropic, so alignment treatment is unnecessary and viewing angle dependency is small. Sai.

[0443] In the pixel circuit 3137 in the mth row and the nth column, One of the drain electrodes is electrically connected to the signal line DL_n, and the other is electrically connected to a node 3436. The gate electrode of the transistor 3431 is electrically connected to the scanning line GL_m. The transistor 3431 controls writing of a data signal to the node 3436. It has functions.

[0444] One of a pair of electrodes of the capacitor 3233 is a wiring to which a specific potential is supplied (hereinafter, referred to as a “capacitor”). The other end is electrically connected to a node 3436. The other of the pair of electrodes of the liquid crystal element 3432 is electrically connected to a node 3436. The value of the potential of the capacitance line CL is appropriately set according to the specifications of the pixel circuit 3137. The capacitance element 3233 functions as a storage capacitor to hold data written to the node 3436. Possesses the ability.

[0445] Here, an example of the operation of a display device having the pixel circuit 3137 of FIG. First, the pixel circuits 3137 in each row are selected in sequence by the circuit 3132, and the transistors A data signal is written to node 3436 by turning on starter 3431.

[0446] Next, the transistor 3431 is turned off to transmit the data signal written to the node 3436. The liquid crystal element 3432 holds a data signal according to the data signal written to the node 3436. By performing this process for each row, an image can be displayed in the display area 3131. Cut.

[0447] <Example of display device configuration> Using the transistor described in the above embodiment, a part of a driver circuit including a transistor Alternatively, the entire display can be formed on the same substrate as the pixel section to form a system-on-panel. Regarding a structural example of a display device in which the transistor described in the above embodiment can be used, This will be explained with reference to Figures 50 and 51.

[0448] [Liquid crystal display device and EL display device] Examples of the display device include a display device using a liquid crystal element and a display device using an EL element. In FIG. 50A, a pixel portion 40 provided on a first substrate 4001 is A sealant 4005 is provided to surround the first substrate 02, and the second substrate 4006 seals the first substrate 02. In FIG. 50(A), the sealing material 4005 on the first substrate 4001 In a region different from the region surrounded by the ion implantation, a single crystal semiconductor or a polycrystalline A signal line driver circuit 4003 and a scanning line driver circuit 4004 formed of semiconductor are mounted. In addition, the signal line driver circuit 4003, the scanning line driver circuit 4004, or the pixel portion 4002 Various signals and potentials are applied to the FPC (Flexible Printed Circuit). It is supplied by FPC4018a and FPC4018b.

[0449] In FIG. 50(B) and FIG. 50(C), a pixel portion 4 provided on a first substrate 4001 A sealant 4005 is provided so as to surround the 002 and the scanning line driver circuit 4004. In addition, a second substrate 4006 is provided on the pixel portion 4002 and the scanning line driver circuit 4004. Therefore, the pixel portion 4002 and the scanning line driver circuit 4004 are formed on the first substrate 400. The display element is sealed by a sealant 4005 and a second substrate 4006. In FIG. 50B and FIG. 50C, the sealant 4005 on the first substrate 4001 In a region different from the region surrounded by the A signal line driver circuit 4003 formed of a polycrystalline semiconductor is mounted. In FIG. 50C, a signal line driver circuit 4003, a scanning line driver circuit 4004, or a display Various signals and potentials are provided to the element portion 4002 through an FPC 4018 .

[0450] In addition, in FIG. 50(B) and FIG. 50(C), a signal line driver circuit 4003 is formed separately. 10, the scanning lens 4001 is mounted on the first substrate 4001, but the present invention is not limited to this configuration. A signal line driver circuit may be formed separately and mounted, or a part of a signal line driver circuit or a scanning line driver circuit may be mounted. Alternatively, only a part of the path may be formed separately and implemented.

[0451] The method of connecting the separately formed drive circuit is not particularly limited, and may be a wire bond. Ding, COG (Chip On Glass), TCP (Tape Carrier Package), COF (Chip On Film), etc. can be used. FIG. 50(A) shows a signal line driver circuit 4003 and a scanning line driver circuit 4004 mounted on a COG. FIG. 50(B) is an example in which a signal line driver circuit 4003 is mounted by COG. FIG. 50C shows an example in which a signal line driver circuit 4003 is implemented using TCP.

[0452] The display device includes a panel in which a display element is sealed, and a controller for the panel. The term "module" may also include a module on which an IC including a laser is mounted.

[0453] The pixel portion and the scanning line driver circuit provided on the first substrate have a plurality of transistors. The transistor described in the above embodiment can be applied to this.

[0454] 51(A) and 51(B) show the structure of the region indicated by the dashed line N1-N2 in FIG. 50(B). The display device shown in FIG. 51(A) and FIG. 51(B) has an electrode 40. 15, and the electrode 4015 is connected to a terminal of the FPC 4018 and an anisotropic conductive layer 4019 The electrode 4015 is electrically connected to the insulating layer 4112 and the insulating layer 4113. 111, and an opening formed in the insulating layer 4110 is electrically connected to the wiring 4014. It is being done.

[0455] The electrode 4015 is formed from the same conductive layer as the first electrode layer 4030. The source and drain electrodes of the transistor 4010 and the transistor 4011 They are formed from the same conductive layer.

[0456] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In FIG. 51(A) and FIG. 51(B), a pixel portion 4002 has a plurality of transistors. The transistor 4010 included in the scanning line driver circuit 4004 and the transistor 40 In FIG. 51A, the transistor 4010 and the transistor 4011 are shown. An insulating layer 4112, an insulating layer 4111, and an insulating layer 4110 are provided on the insulating layer 4111. In FIG. 1(B), a partition wall 4510 is formed on an insulating layer 4112 .

[0457] The transistor 4010 and the transistor 4011 are provided over an insulating layer 4102. The transistor 4010 and the transistor 4011 are formed by insulating layers 410. 2, and an insulating layer 4103 is formed on the electrode 4017. do. The electrode 4017 can function as a back-gate electrode.

[0458] The transistors 4010 and 4011 are the same as those described in the above embodiment. The transistor described in the above embodiment can be used as a transistor having a low electrical characteristic fluctuation. Therefore, the structure shown in FIG. 51(A) and FIG. 51(B) is electrically stable. The display device of this embodiment can be a highly reliable display device.

[0459] In addition, in FIG. 51(A) and FIG. 51(B), the transistor 4010 and the transistor The transistor 4011 has a structure similar to that of the transistor 160 described in the above embodiment. The example shows the case where a transistor is used.

[0460] The display device shown in FIG. 51(A) and FIG. 51(B) has a capacitor element 4020. The capacitor 4020 is connected to one of the source electrode and the drain electrode of the transistor 4010. The electrode 4021 has a region where the electrode 4021 overlaps with the insulating layer 4103 interposed therebetween. It is formed from the same conductive layer as the electrode 4017 .

[0461] In general, the capacitance of a capacitor provided in a display device is determined by the capacitance of a transistor disposed in a pixel portion. Taking into consideration leakage current and the like, the capacitance is set so that a charge can be held for a predetermined period. The capacitance may be set in consideration of the off-state current of the transistor and the like.

[0462] For example, by using an OS transistor in a pixel portion of a liquid crystal display device, the capacity of a capacitor can be reduced. The amount of the liquid crystal display can be set to 1 / 3 or less, or 1 / 5 or less, of the liquid crystal display capacity. By using a transistor, the formation of a capacitance element can be omitted.

[0463] The transistor 4010 provided in the pixel portion 4002 is electrically connected to a display element. FIG. 51(A) is an example of a liquid crystal display device using a liquid crystal element as a display element. ), a liquid crystal element 4013 which is a display element has a first electrode layer 4030, a second electrode layer The liquid crystal layer 4008 is sandwiched between an alignment film 4031 and a liquid crystal layer 4008. The insulating layer 4032 and the insulating layer 4033 functioning as the second electrode layer 4031 are provided. is provided on the second substrate 4006 side, and the first electrode layer 4030 and the second electrode layer 4031 are liquid crystal. The crystal layer 4008 is placed between them.

[0464] The spacer 4035 is a columnar spacer obtained by selectively etching an insulating layer. The distance (cell gap) between the first electrode layer 4030 and the second electrode layer 4031 is controlled. A spherical spacer may also be used.

[0465] When liquid crystal elements are used as display elements, thermotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, etc. Liquid crystal, polymer dispersed liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. These liquid crystal materials can exhibit cholesteric, smectic, cubic, and chromatic phases depending on the conditions. It shows an isotropic phase, an isotropic phase, etc.

[0466] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. When the temperature of the cholesteric liquid crystal is increased, the cholesteric phase transitions to the isotropic phase. The blue phase appears only in a narrow temperature range, so it is necessary to improve the temperature range. In order to improve the chirality, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 1 msec or less. Since the film is short and optically isotropic, no alignment treatment is required, and the viewing angle dependency is small. Since no film is required, rubbing is also unnecessary. This prevents electrostatic damage that may occur during the manufacturing process, reducing defects and damage to liquid crystal display devices. Therefore, the productivity of the liquid crystal display device can be improved.

[0467] In addition, a pixel is divided into several regions (subpixels), each of which is illuminated in a different direction. This is called multi-domain or multi-domain design, which is designed to defeat molecules in a complex manner. The following method can be used.

[0468] The specific resistance of the liquid crystal material is 1×10 9 Ω cm or more, preferably 1×10 1 1 Ω cm or more, and more preferably 1×10 12 Ω·cm or more. The specific resistance values ​​specified in the specification are those measured at 20°C.

[0469] The OS transistor used in this embodiment has a current value in an off state (off-state current value) of Therefore, the retention time of electrical signals such as image signals can be extended. When the power is on, the write interval can be set longer. This reduces the number of inputs, thereby reducing power consumption.

[0470] In addition, OS transistors have a relatively high field-effect mobility and therefore can be driven at high speed. Therefore, by using the above transistor in a pixel portion of a display device, a high-quality image can be obtained. In addition, a driver circuit section and a pixel section can be separately manufactured on the same substrate. This makes it possible to reduce the number of parts in the display device.

[0471] In addition, in display devices, black matrices (light-shielding layers), polarizing members, phase difference members, reflectors, Optical members (optical substrates) such as anti-reflection members may be provided as appropriate. For example, a polarizing substrate and Circularly polarized light produced by a retardation substrate may be used. etc. may also be used.

[0472] In addition, a light-emitting device using electroluminescence is used as a display element included in the display device. The light-emitting element that utilizes electroluminescence can be applied to a light-emitting material They are classified according to whether the material is an organic compound or an inorganic compound. The latter is called an inorganic EL element.

[0473] In an organic EL element, electrons and positive electrodes are released from a pair of electrodes by applying a voltage to the light-emitting element. The holes are then injected into a layer containing a light-emitting organic compound, and a current is passed through them. The recombination of carriers (electrons and holes) causes light-emitting organic compounds to form excited states. When the excited state returns to the ground state, light is emitted. Such a light-emitting element is called a current-excitation type light-emitting element.

[0474] Inorganic EL elements are classified into dispersion type inorganic EL elements and thin film type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of light-emitting material are dispersed in a binder. The emission mechanism is a donor-based ion exchange reaction that utilizes the donor and acceptor levels. This is an acceptor recombination type emission. Thin-film inorganic EL elements sandwich the light-emitting layer between dielectric layers. The structure is sandwiched between electrodes, and the light emission mechanism is the inner shell electron transition of metal ions. This is a localized light emission that utilizes organic EL elements. do.

[0475] The light emitting element only needs to have at least one of the pair of electrodes transparent in order to extract light. A transistor and a light emitting element are formed on the substrate, and light is emitted from the surface opposite the substrate. Top emission structure, which emits light from the top surface of the substrate, and bottom emission structure, which emits light from the bottom surface of the substrate. (bottom emission) structure and dual emission (double emission) structure that emits light from both sides There are light emitting elements having a light-emitting (emission) structure, and light emitting elements having any of the emission structures can be applied.

[0476] FIG. 51(B) shows a light-emitting display device (hereinafter referred to as an "EL display device") that uses light-emitting elements as display elements. The light-emitting element 4513 which is a display element is provided in the pixel portion 4002. The light-emitting element 4513 is electrically connected to the transistor 4010. The first electrode layer 4030, the light-emitting layer 4511, and the second electrode layer 4031 are laminated together. The configuration is not limited to the above. The configuration of 4513 can be changed as appropriate.

[0477] The partition 4510 is formed using an organic insulating material or an inorganic insulating material. An opening is formed on the first electrode layer 4030 using a resin material, and the side of the opening is continuous. It is preferable to form the inclined surface so as to have a curvature.

[0478] The light-emitting layer 4511 may be composed of a single layer or a plurality of layers may be laminated. It doesn't matter whether it's

[0479] In order to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4513, the second electrode A protective layer may be formed on the layer 4031 and the partition wall 4510. The protective layer may be silicon nitride. Con, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride , aluminum oxide nitride, DLC (Diamond Like Carbon), etc. In addition, the first substrate 4001, the second substrate 4006, and the sealing material 4 The space sealed by 005 is sealed with a filler 4514. In addition, a protective film (lamination film) that is highly airtight and has little outgassing is used to prevent exposure to the outside air. It is preferable to package (enclose) the product in a protective film (film, ultraviolet curing resin film, etc.) or a cover material. I wish.

[0480] Filler 4514 can be inert gas such as nitrogen or argon, or ultraviolet curing resin. Or thermosetting resin can be used, such as PVC (polyvinyl chloride), acrylic resin, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) can be used. For example, nitrogen can be used as a filler. That's good.

[0481] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates), color filters, etc. may be installed as appropriate. In addition, the polarizing plate or the circular polarizing plate may be provided with an anti-reflection film. It is possible to apply an anti-glare treatment that can diffuse reflected light and reduce glare.

[0482] A first electrode layer and a second electrode layer (a pixel electrode layer, a common electrode layer, In the case of the counter electrode layer, the direction of the light to be extracted, the location of the electrode layer, and The light transmitting property or the reflecting property can be selected depending on the pattern structure of the electrode layer.

[0483] The first electrode layer 4030 and the second electrode layer 4031 are made of indium tungsten oxide. Oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide oxide, indium tin oxide, indium tin oxide with titanium oxide, indium zinc oxide A conductive material with light-transmitting properties, such as indium tin oxide doped with silicon oxide, is used. It is possible.

[0484] The first electrode layer 4030 and the second electrode layer 4031 are made of tungsten (W) and molybdenum (Mo). Mo, Zirconium (Zr), Hafnium (Hf), Vanadium (V), Niobium ( Nb), Tantalum (Ta), Chromium (Cr), Cobalt (Co), Nickel (Ni), Titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag) and other metals The metal may be formed by using one or more of the following metals: do.

[0485] The first electrode layer 4030 and the second electrode layer 4031 are made of a conductive polymer (conductive polymer). The conductive polymer may be a conductive composition containing a conductive polymer. For this purpose, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, Or a derivative thereof.

[0486] In addition, since transistors are easily damaged by static electricity, etc., a protection circuit for protecting the drive circuit is It is preferable to provide a protection circuit using a non-linear element.

[0487] By using the transistor described in the above embodiment, a display device with high reliability can be provided. In addition, by using the transistor described in the above embodiment, high definition can be achieved. It is possible to provide a display device having a large display area and good display quality. A reduced force display device can be provided.

[0488] [Display module] As an example of a semiconductor device using the above-mentioned transistor, a display module will be described. The display module 6000 shown in FIG. Between FPC6003 and FPC6005, touch sensor 6004 is connected to FPC6005. A display panel 6006, a backlight unit 6007, a frame 6009, and a printer The display panel 6007 includes a backlight unit 6007, a display substrate 6010, and a battery 6011. The battery 6011, the touch sensor 6004, etc. may not be provided.

[0489] The semiconductor device of one embodiment of the present invention includes, for example, a touch sensor 6004 and a display panel 6006. , and can be used for an integrated circuit mounted on a printed circuit board 6010. The above-mentioned display device can be used for the panel 6006 .

[0490] The upper cover 6001 and the lower cover 6002 are provided with a touch sensor 6004 and a display panel. The shape and dimensions can be changed as appropriate to suit sizes such as 6006.

[0491] The touch sensor 6004 is a resistive or capacitive touch sensor that is connected to a display panel. The display panel 6006 can be used by being overlapped with the touch sensor. For example, a touch sensor electrode may be added to each pixel of the display panel 6006. It is also possible to add a capacitive touch panel function by providing a touch panel. An optical sensor is provided in each pixel of the display panel 6006 to add an optical touch sensor function. It is also possible to do the following.

[0492] The backlight unit 6007 includes a light source 6008. The display unit 6007 may be provided at an end thereof and a light diffusion plate may be used. When a light-emitting display device or the like is used for the light-emitting device 6006, the backlight unit 6007 can be omitted. It is possible.

[0493] The frame 6009 has a function of protecting the display panel 6006 and also a function of preventing the display panel 6006 from being damaged by the printed circuit board 6010. It also functions as an electromagnetic shield to block electromagnetic waves generated by the frame. 6009 may also function as a heat sink.

[0494] The printed circuit board 6010 includes a power supply circuit, a video signal, and a clock signal. A signal processing circuit is included. A battery 6011 is used as a power source for supplying power to the power supply circuit. In addition, when a commercial power source is used as the power source, In this case, the battery 6011 can be omitted.

[0495] In addition, the display module 6000 may include components such as a polarizing plate, a retardation plate, and a prism sheet. It may be added.

[0496] Note that this embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0497] [RF tag] As an example of a semiconductor device using the above-mentioned transistor, an RF tag will be described. .

[0498] The RF tag according to one embodiment of the present invention has an internal memory circuit (memory device) and stores information in the memory circuit. The sensor stores information about the sensor and transmits and receives information to and from the outside using a non-contact means, such as wireless communication. Due to these characteristics, RF tags can identify items by reading their individual information. It can be used for individual authentication systems that perform the following: For this purpose, high reliability is required.

[0499] The structure of an RF tag will be described with reference to Fig. 53. Fig. 53 shows an example of the structure of an RF tag. FIG.

[0500] As shown in FIG. 53, an RF tag 800 includes a communicator 801 (such as an interrogator or a reader / writer). An antenna 802 connected to the The above-mentioned transistor may be used for the communicator 801. 00 is a rectifier circuit 805, a constant voltage circuit 806, a demodulator circuit 807, a modulator circuit 808, a logic circuit The demodulation circuit 807 includes a signal processing circuit 809, a memory circuit 810, and a ROM 811. The semiconductor of the transistor that exhibits the rectifying action has a property that can sufficiently suppress the reverse current. For example, an oxide semiconductor may be used. This can reduce the rectification caused by the reverse current. This suppresses the degradation of the demodulation circuit output and prevents it from being saturated. The output of the demodulation circuit for the signal can be made closer to linear. The electromagnetic coupling method uses mutual induction by placing coils facing each other, and RF tags are broadly divided into three types: RFID tags, which communicate using electromagnetic induction, and RFID tags which communicate using radio waves. The 800 can be used in either of these ways.

[0501] Next, the configuration of each circuit will be described. The antenna 804 is an antenna connected to the communication device 801. The rectifier circuit 802 is used to transmit and receive a radio signal 803 to and from the antenna 802. 805 is a filter for adjusting an input AC signal generated by receiving a radio signal through the antenna 804. For example, the current is rectified by half-wave double voltage rectification, and the rectified signal is smoothed by a capacitive element in the latter stage. The rectifier circuit 805 is a circuit for generating an input potential. The limiter circuit is a circuit for limiting the amplitude of an input AC signal. When the internally generated voltage is large, the power supply is controlled so that it does not input a certain amount of power to the downstream circuit. This is a circuit for

[0502] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. The constant voltage circuit 806 may have a reset signal generating circuit inside. The reset signal generation circuit uses the stable rise of the power supply voltage to reset the logic circuit 8. This is a circuit for generating the reset signal for 09.

[0503] The demodulation circuit 807 demodulates the input AC signal by envelope detection to generate a demodulated signal. The modulation circuit 808 is a circuit for modulating the data output from the antenna 804. This is a circuit for performing modulation in response to the

[0504] The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. , a circuit that holds input information, such as a row decoder, a column decoder, a memory area, etc. The ROM 811 stores a unique number (ID) and outputs the information according to the processing. This is a circuit for doing so.

[0505] The above-mentioned circuits can be selected or omitted as appropriate.

[0506] The above-described memory device can be used for the memory circuit 810. The device is suitable for RF tags because it can retain information even when the power is cut off. Furthermore, in the memory device according to one embodiment of the present invention, the power (voltage) required for writing data is reduced. This is lower than conventional non-volatile memory, so the maximum communication distance when reading and writing data is It is also possible to prevent the difference from occurring. This can prevent erroneous writing or erroneous writing from occurring.

[0507] Furthermore, the memory device according to one embodiment of the present invention can be used as a nonvolatile memory. Therefore, it can be applied to ROM811. In that case, the producer must Prepare a separate command to write data, so that users cannot freely rewrite it. It is preferable for the manufacturer to write the unique number on the product before shipping it. Therefore, instead of assigning a unique number to every RF tag produced, only good products are shipped. This means that the unique numbers of products will be assigned only to those that have been shipped. This makes it easier to manage customers' accounts after products are shipped.

[0508] An example of the use of an RF tag according to an embodiment of the present invention will be described with reference to FIG. Its uses are wide-ranging, but include banknotes, coins, securities, bearer bonds, driver's licenses, and citizenship cards. Certificates such as certificates (see Figure 54(A)), recording media such as DVD software and video tapes (see Figure 54(B)). 54(B). ), containers such as plates, cups and bottles (see Fig. 54(C)), wrapping paper, boxes and Ribbons and other wrapping materials, bicycles and other moving objects (see Figure 54(D)), bags, glasses and other personal items. accessories, plants, animals, the human body, clothing, daily necessities, medical supplies including medicines and pharmaceuticals, or electronic equipment Devices (e.g., liquid crystal display devices, EL display devices, television devices, or mobile phones) Articles or tags attached to each article (see Figure 54(E) and Figure 54(F)). It can be installed and used anywhere.

[0509] The RF tag 800 according to one embodiment of the present invention can be attached to or embedded in a surface of an object. For example, in a book, the sensor is embedded in the paper, and in a package made of organic resin, the sensor is embedded in the paper. For example, the RF tag is embedded in the organic resin and fixed to each article. In order to achieve a small size, thinness, and light weight, the 800 is designed to match the design of the item even after it is attached to the item. It also does not affect the integrity of banknotes, coins, securities, bearer bonds, or certificates. The RF tag 800 according to one embodiment of the present invention can provide an authentication function. By utilizing this function, counterfeiting can be prevented. The RF tag 800 according to one embodiment of the present invention is attached to a product, clothing, daily necessities, electronic device, or the like. By installing this system, the efficiency of systems such as inspection systems can be improved. By attaching an RF tag 800 according to one embodiment of the present invention to a moving object, it is possible to provide a measure against theft, etc. As described above, the RF tag according to one embodiment of the present invention can improve security. The 800 can be used for each of the applications described above.

[0510] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is Noh.

[0511] (Embodiment 5) <Package using lead frame type interposer> Figure 55(A) shows the cross-sectional structure of a package using a lead frame type interposer. 55A is a perspective view showing a package of a semiconductor device according to one embodiment of the present invention. A chip 551 corresponding to The terminal 552 is connected to the chip 551 of the interposer 550. The chip 551 is placed on a surface that is supported by a mold resin 553. However, it is preferable that the terminals 552 are sealed in a state where a part of each terminal 552 is exposed. .

[0512] An example of the configuration of an electronic device in which a package is mounted on a circuit board is shown in FIG. The electronic device shown in FIG. 55(B) is installed in, for example, a mobile phone. The child device is configured by mounting a package 562 and a battery 564 on a printed wiring board 561. In addition, a printed wiring board 561 is attached to a panel 560 on which a display element is provided. Implemented by C563.

[0513] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0514] (Embodiment 6) In this embodiment, an example of an electronic device using a semiconductor device according to one embodiment of the present invention will be described. explain.

[0515] Examples of electronic devices using a semiconductor device according to one embodiment of the present invention include display devices such as televisions and monitors. equipment, lighting equipment, desktop or notebook personal computers, word processors It is stored on recording media such as a digital camera or DVD (Digital Versatile Disc). Image reproducing devices that reproduce still or moving images recorded on a DVD player, portable CD players, radios, tapes, etc. Pre-recorders, headphone stereos, stereos, table clocks, wall clocks, cordless telephones mobile phones, mobile information terminals, tablet terminals, portable games gaming machines, pachinko machines and other fixed game machines, calculators, electronic organizers, e-book terminals, electronic translators , voice input devices, video cameras, digital still cameras, electric shavers, microwave ovens, etc. High frequency heating devices, electric rice cookers, electric washing machines, vacuum cleaners, water heaters, electric fans, hair dryers, Air conditioning equipment such as air conditioners, humidifiers, and dehumidifiers, dishwashers, dish dryers, and clothing Dryers, futon dryers, electric refrigerators, electric freezers, electric refrigerator-freezers, freezers for DNA storage, Examples include tools such as flashlights and chainsaws, smoke detectors, and medical equipment such as dialysis machines. In addition, emergency lights, traffic lights, conveyor belts, elevators, escalators, and industrial robots , power storage systems, power leveling and smart grid storage devices and other industrial equipment. In addition, there are engines that use fuel, and electric motors that use electricity from a storage battery. Mobile objects that move around may also be included in the category of electronic devices. , electric vehicles (EV), hybrid vehicles (HEV) that combine internal combustion engines and electric motors, Hybrid electric vehicles (PHEVs), tracked vehicles that use these tires and wheels as tracks, Motorized bicycles including electrically assisted bicycles, motorcycles, electric wheelchairs, golf carts, Small or large ships, submarines, helicopters, aircraft, rockets, satellites, space probes, etc. Examples include planetary probes and spacecraft.

[0516] A portable game machine 2900 shown in FIG. 56(A) includes a housing 2901, a housing 2902, a display unit 2903, display unit 2904, microphone 2905, speaker 2906, operation key 290 7. The portable game machine shown in FIG. 25(A) has two display units 2903 and The display unit 2903 has a display unit 2904, but the number of display units is not limited to this. The device is equipped with a touch screen as an input device, and can be operated with a stylus 2908 or the like. It is possible to create

[0517] The information terminal 2910 shown in FIG. 56(B) includes a housing 2911, a display unit 2912, a microphone 2913, and a 917, a speaker unit 2914, a camera 2913, an external connection unit 2916, and operation buttons The display unit 2912 includes a display panel using a flexible substrate and a The information terminal 2910 is, for example, a smartphone, a mobile phone, , tablet information terminals, tablet personal computers, e-book terminals, etc. It can be used.

[0518] A notebook personal computer 2920 shown in FIG. 56(C) includes a housing 2921, a display 2922, a keyboard 2923, and a pointing device 2924.

[0519] The video camera 2940 shown in FIG. 56(D) includes a housing 2941, a housing 2942, a display unit 2 943, operation keys 2944, a lens 2945, and a connection part 2946. The lens 2945 and the display unit 2944 are provided in the housing 2941. The housing 2941 and the housing 2942 are connected to each other via a connection portion 2946. The angle between the housing 2941 and the housing 2942 is determined by the connection 2946. The angle of the housing 2942 relative to the housing 2941 can be changed. This allows you to change the orientation of the image displayed on the display unit 2943 and switch between displaying and hiding the image. This can be done.

[0520] An example of a bangle-type information terminal is shown in FIG. The display unit 2952 is attached to a housing 2951 having a curved surface. The display unit 2952 is provided with a display panel using a flexible substrate. It is possible to provide an information terminal 2950 that is flexible, lightweight, and easy to use.

[0521] FIG. 56(F) shows an example of a wristwatch-type information terminal. The information terminal 2960 has a housing 2961. , display unit 2962, band 2963, buckle 2964, operation button 2965, input / output terminal The information terminal 2960 is equipped with a mobile phone, an electronic mail, a text browsing and writing device, etc. Various applications such as music playback, Internet communication, and computer games can be executed.

[0522] The display surface of the display unit 2962 is curved, and display can be performed along the curved display surface. The display unit 2962 is also equipped with a touch sensor, and can be used to touch the screen with a finger or a stylus. For example, the icon 2967 displayed on the display unit 2962 can be operated by By touching the operation button 2965, an application can be started. In addition to settings, you can also turn the power on and off, turn wireless communication on and off, activate silent mode, and It can have various functions such as turning on and off the power saving mode, turning on and off the power saving mode, etc. The operating system installed in the information terminal 2960 controls the operation of the operation button 296 You can also set the 5 functions.

[0523] In addition, the information terminal 2960 is capable of performing short-distance wireless communication according to a communication standard. For example, by communicating with a wireless headset, hands-free communication is possible. The information terminal 2960 also has an input / output terminal 2966, and can communicate with other information terminals. Data can be exchanged directly through the terminal and connector. Charging can also be performed via the input / output terminal 2966. This may be achieved by wireless power supply.

[0524] FIG. 56(G) shows an electric refrigerator as an example of a household electrical appliance. The refrigerator has a housing 2971, a refrigerator door 2972, and a freezer door 2973.

[0525] FIG. 56(H) is an external view showing an example of an automobile. The automobile 2980 has a body 2981. , wheels 2982, dashboard 2983, and lights 2984.

[0526] The electronic devices described in this embodiment include the above-described transistors or the above-described semiconductor devices. It is equipped with:

[0527] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is Noh.

[0528] (Embodiment 7) In this embodiment, a deposition chamber in which a sputtering target can be installed is provided. The deposition apparatus (sputtering apparatus) shown in this embodiment will be described. Used in parallel plate sputtering equipment and facing target sputtering equipment. It is possible.

[0529] When forming a film using a facing target sputtering device, damage to the surface to be formed is small. Therefore, it is easy to obtain a film with high crystallinity. In some cases it may be preferable to use a directed target sputtering system.

[0530] The film formation method using a parallel plate sputtering device is called PESP (Parallel It can also be called "opposing target sputtering". The deposition method using a hot-plate sputtering device is called VDSP (Vapor Deposition Sputtering). It can also be called "on Sputtering."

[0531] First, the structure of a film formation apparatus that reduces the amount of impurities mixed into the film during film formation is shown in FIG. This will be explained using Figure 58.

[0532] FIG. 57 is a schematic top view of a single-wafer multi-chamber film forming apparatus 2700. The deposition apparatus 2700 includes a cassette port 2761 for accommodating a substrate and a substrate alignment device. and an atmosphere-side substrate supply chamber 2701 having an alignment port 2762 for performing the alignment. The substrate is transported from the substrate supply chamber 2701 to the atmospheric substrate transport chamber 2702, which transports the substrate. A load lock chamber in which the pressure inside the chamber is switched from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure. 2703a, the substrate is removed, and the pressure in the chamber is reduced to atmospheric pressure, or atmospheric pressure to atmospheric pressure. The unload lock chamber 2703b is switched to a reduced pressure state, and the transfer chamber 2703 is used for transferring substrates in a vacuum. 704, a substrate heating chamber 2705 for heating the substrate, and a deposition chamber in which a target is disposed and a deposition The film forming chamber 2706 includes a film forming chamber 2706a, a film forming chamber 2706b, and a film forming chamber 2706c. The film forming chambers 2706a, 2706b, and 2706c are similar to the film forming chambers described above. It is possible.

[0533] The atmospheric substrate transfer chamber 2702 is provided with a load lock chamber 2703a and an unload lock chamber 2703b. The load lock chamber 2703a and the unload lock chamber 2703b are connected to each other. 3b is connected to a transfer chamber 2704, which is connected to a substrate heating chamber 2705, a film forming chamber 2 706a, which is connected to the film formation chamber 2706b and the film formation chamber 2706c.

[0534] A gate valve 2764 is provided at the connection between the chambers, and the atmosphere side substrate supply chamber 2 Except for the atmospheric side substrate transfer chamber 2702, each chamber can be independently maintained in a vacuum state. In addition, the atmospheric side substrate transfer chamber 2702 and the transfer chamber 2704 are connected to a transfer robot 276. 3 and capable of transporting substrates.

[0535] In addition, it is preferable that the substrate heating chamber 2705 also serves as a plasma processing chamber. Since the substrate can be transported between processes without being exposed to the atmosphere, It is possible to suppress the adsorption of pure substances. In addition, the order of film formation and heat treatment can be freely configured. In addition, the transfer chamber, deposition chamber, load lock chamber, unload lock chamber and substrate heating chamber can be used. The number of chambers is not limited to the above number, but can be set to an optimal number according to the installation space and process conditions. It can be established.

[0536] Next, the dashed dotted line X1-X2, the dashed dotted line Y1-Y2, and the 58 shows a cross section corresponding to the dashed line Y2-Y3.

[0537] FIG. 58(A) shows a cross section of the substrate heating chamber 2705 and the transfer chamber 2704. The thermal chamber 2705 has multiple heating stages 2765 capable of accommodating substrates. The substrate heating chamber 2705 is connected to a vacuum pump 2770 via a valve. The vacuum pump 2770 may be, for example, a dry pump or a mechanical booster pump. A filter or the like can be used.

[0538] In addition, examples of heating mechanisms that can be used in the substrate heating chamber 2705 include resistance heating. Alternatively, the heating mechanism may be a mechanism that uses a medium such as a heated gas to heat the device. The heating mechanism may be a device that heats the object by thermal conduction or thermal radiation. For example, GRTA, L An RTA such as RTA can be used.

[0539] The substrate heating chamber 2705 is connected to a refiner 27 via a mass flow controller 2780. 81. The mass flow controller 2780 and the refiner 2781 are connected to the gas Although the number of heating chambers is equal to the number of types of substrates, only one is shown for ease of understanding. The gas introduced into the furnace has a dew point of -80°C or less, preferably -100°C or less. For example, oxygen gas, nitrogen gas, and rare gas (such as argon gas) can be used. do.

[0540] The transfer chamber 2704 includes a transfer robot 2763. The transfer robot 2763 is The transfer chamber 2704 can be connected to a vacuum pump via a valve. 2770 and a cryopump 2771 are connected. The transfer chamber 2704 is configured to have a pressure ranging from atmospheric pressure to low or medium vacuum (approximately 0.1 to several hundred Pa). The vacuum is evacuated using the empty pump 2770, and the valve is switched to change the vacuum from medium to high or ultra-high. Air (0.1 Pa to 1×10 -7 The pumping temperature was increased to 100 Pa using the Cryopump 2771. do.

[0541] In addition, for example, two or more cryopumps 2771 are connected in parallel to the transfer chamber 2704. With this configuration, even if one cryopump is in regeneration, Even if the amount of the cryopump is increased, the remaining cryopump can still be used to pump the remaining cryopump. Cryopump refers to the process of releasing molecules (or atoms) stored in the cryopump. If the Lyopump accumulates too many molecules (or atoms), its pumping capacity will decrease. Regeneration occurs periodically.

[0542] FIG. 58(B) shows a film forming chamber 2706b, a transfer chamber 2704, and a load lock chamber 2703a. 1 shows a cross section of the

[0543] Here, the details of the film formation chamber (sputtering chamber) will be described with reference to FIG. 58(B). The deposition chamber 2706b shown in FIG. 58(B) includes a target 2766a and a target 276 6b, target shield 2767a, target shield 2767b, and magnet A light source unit 2790a, a magnet unit 2790b, a substrate holder 2768, and an electric Although not shown, the target 2766a and the target 276 6b are fixed to the target holder via a backing plate. A power supply 2791 is electrically connected to the target 2766a and the target 2766b. The magnet unit 2790a and the magnet unit 2790b are The target slits are disposed on the rear side of the target 2766a and the target 2766b. Target Shield 2767a and Target Shield 2767b are the same as Target 2766 a and the end of the target 2766b. The substrate holder 2768 supports a substrate 2769. The target 2 is fixed to the deposition chamber 2706b via the variable member 2784. The substrate is then exposed to the area between the target 2766a and the target 2766b (also called the inter-target area). The holder 2768 can be moved, for example, a substrate holder supporting a substrate 2769. Placing 2768 in the inter-target area can reduce plasma damage. In addition, the substrate holder 2768 may be a substrate holder for holding a substrate 2769 (not shown). A holding mechanism and a heater for heating the substrate 2769 from the rear side may be provided.

[0544] In addition, the target shield 2767 prevents sputtering from the target 2766. The target shield 2767 prevents particles from being deposited in unwanted areas. It is desirable to process the surface so that the accumulated sputtered particles do not peel off. For example, the surface roughness Blasting to increase the thickness or roughening the surface of the Target Shield 2767 Good too.

[0545] The deposition chamber 2706b is connected to a mass flow controller 2782 via a gas heating mechanism 2782. 780, and the gas heating mechanism 2782 is precisely controlled via the mass flow controller 2780. The gas is introduced into the deposition chamber 2706b by a gas heating mechanism 2782. The gas to be treated is heated to a temperature of 40°C or higher and 400°C or lower, preferably 50°C or higher and 200°C or lower. In addition, the gas heating mechanism 2782, the mass flow controller 2780, and the refiner Although the number of gas types is equal to the number of gas types, only one gas type is shown for ease of understanding. The gas introduced into the chamber 2706b has a dew point of -80°C or less, preferably -100°C or less. Gases that can be used include, for example, oxygen gas, nitrogen gas, and rare gases (argon gas). etc.) are used.

[0546] In addition, when a refiner is provided immediately before the gas inlet, the distance from the refiner to the deposition chamber 2706b is The length of the piping is 10 m or less, preferably 5 m or less, and more preferably 1 m or less. By keeping the length of the piping to 10m or less, 5m or less, or 1m or less, the impact of gas released from the piping is reduced. In addition, the gas piping is free of iron fluoride, aluminum oxide, and acid. It is recommended to use metal piping with the inside coated with chromium oxide or the like. The above piping is made of, for example, SUS Compared to 316L-EP piping, the amount of gas containing impurities released is smaller, and the amount of impurities entering the gas is reduced. In addition, the piping joints are equipped with high-performance ultra-small metal gasket joints (UPG In addition, by constructing the piping entirely from metal, it is possible to reduce the In comparison, this is preferable because it can reduce the effects of released gas and external leakage.

[0547] The film-forming chamber 2706b is connected to a turbo molecular pump 2772 and a vacuum pump 2773 via a valve. It is connected to P2770.

[0548] Further, the film formation chamber 2706b is provided with a cryotrap 2751.

[0549] The Cryotrap 2751 is a trap that absorbs molecules (or atoms) with a relatively high melting point, such as water. The turbomolecular pump 2772 is a mechanism that can pump large molecules (or atoms). It is highly productive because it stably exhausts hydrogen and other gases and requires little maintenance. Therefore, in order to improve the pumping capacity for water, etc., a cryotrap is The cryotrap 2751 is connected to the deposition chamber 2706b. The temperature of the refrigerator is 100K or less, preferably 80K or less. If the 2751 has multiple refrigerators, changing the temperature of each refrigerator will allow for more efficient exhaust. For example, the temperature of the first stage refrigerator is set to 100K or less, and The temperature of the second stage refrigerator should be set to 20K or less. In some cases, a higher vacuum can be achieved by using a sublimation pump. In addition, by using an ion pump instead of a cryopump or turbomolecular pump, In some cases, it may be possible to achieve a high vacuum.

[0550] The method of exhausting the film forming chamber 2706b is not limited to this, and may be the same as that of the transfer chamber 2704. The exhaust method may be the same as that of a cryopump and a vacuum pump. Of course, the exhaust method for the transfer chamber 2704 is the same as that for the film forming chamber 2706b (a turbo molecular pump, etc.). (Exhaust method with a vacuum pump) may also be used.

[0551] In addition, the back pressures of the transfer chamber 2704, the substrate heating chamber 2705, and the film forming chamber 2706b are It is preferable that the total pressure and the partial pressure of each gas molecule (atom) are as follows. Since impurities may be mixed into the film to be formed, the back pressure of the film forming chamber 2706b, It is also necessary to pay attention to the partial pressure of each gas molecule (atom).

[0552] The back pressure (total pressure) of each of the above mentioned chambers is 1×10 -4 Pa or less, preferably 3×10 -5 Pa Less than 1×10, more preferably -5 The mass-to-charge ratio (m / The partial pressure of a gas molecule (atom) with z=18 is 3 × 10 -5 Pa or less, preferably 1×1 0 -5 Pa or less, more preferably 3×10 -6 In addition, the above-mentioned The partial pressure of a gas molecule (atom) with m / z of 28 is 3 x 10 -5 Pa or less, preferably 1× 10 -5 Pa or less, more preferably 3×10 -6 In addition, the above-mentioned room temperature is 100°C or less. The partial pressure of a gas molecule (atom) with m / z of 44 is 3×10 -5 Pa or less, preferably 1 ×10 -5 Pa or less, more preferably 3×10 -6 Pa or less.

[0553] The total and partial pressures in the vacuum chamber can be measured using a mass spectrometer. For example, the quadrupole mass spectrometer (also called Q-mass) manufactured by ULVAC, Inc. lee CGM-051 can be used.

[0554] In addition, the above-mentioned transfer chamber 2704, the substrate heating chamber 2705, and the film forming chamber 2706b are It is desirable to have a configuration with little external or internal leakage.

[0555] For example, the transfer chamber 2704, the substrate heating chamber 2705, and the film forming chamber 2706b described above -Crate is 3×10 -6 Pa·m 3 / s or less, preferably 1×10 -6 Pa·m 3 / s or less. Also, the leak rate of a gas molecule (atom) with m / z of 18 is 1×10 - 7 Pa·m 3 / s or less, preferably 3×10 -8 Pa·m 3 / s or less. Also, m / The leak rate of a gas molecule (atom) with z equal to 28 is 1×10 -5 Pa·m 3 / s or less, good Preferably 1×10 -6 Pa·m 3 / s or less. Also, gas molecules with m / z of 44 ( atoms) leak rate is 3×10 -6 Pa·m 3 / s or less, preferably 1×10 -6 Pa m 3 / s or less.

[0556] The leak rate was calculated from the total and partial pressures measured using the mass spectrometer mentioned above. It can be derived from

[0557] The leak rate depends on external and internal leaks. External leaks occur due to tiny holes or An internal leak is when gas enters the vacuum system from outside due to a seal failure. This is caused by leaks from internal valves and other partitions, or by gas released from internal components. In order to keep the above-mentioned values ​​or less, measures must be taken to prevent both external and internal leakage. There is a need.

[0558] For example, the opening and closing part of the deposition chamber 2706b may be sealed with a metal gasket. The gasket is made of metal coated with iron fluoride, aluminum oxide, or chromium oxide. Metal gaskets have a higher adhesion than O-rings and reduce external leakage. It can also reduce the amount of metals coated with iron fluoride, aluminum oxide, chromium oxide, etc. By using the passivation, gases containing impurities released from metal gaskets are suppressed. This reduces internal leakage.

[0559] In addition, the film forming apparatus 2700 is made of aluminum, which emits less gas containing impurities. The alloys used are aluminum, chromium, titanium, zirconium, nickel, or vanadium. The above-mentioned members may be used by being coated with an alloy containing iron, chromium, nickel, etc. Aluminum and nickel-containing alloys are strong, heat resistant, and easy to machine. Therefore, if the surface irregularities of the component are reduced by polishing or the like in order to reduce the surface area, Gas emission can be reduced.

[0560] Alternatively, the components of the film forming apparatus 2700 may be replaced with iron fluoride, aluminum oxide, chromium oxide, etc. The material may be coated with, for example,

[0561] The members of the film forming apparatus 2700 are preferably made of metal as much as possible, for example, quartz. When installing a viewing window made of ferric fluoride, the surface is treated with iron fluoride to suppress gas emission. It is advisable to coat it thinly with aluminum oxide or chromium oxide.

[0562] The substances present in the deposition chamber are adsorbed to the inner walls, etc., and therefore do not affect the pressure in the deposition chamber. However, this causes gas emission when the deposition chamber is evacuated. Therefore, the leak rate and the exhaust speed are Although there is no correlation, it is recommended to use a pump with high exhaust capacity to remove as much of the adsorbed matter as possible from the deposition chamber. It is important to desorb the adsorbed matter by evacuating the gas beforehand. The deposition chamber may be baked. Baking increases the desorption rate of adsorbed substances by about 10 times. Baking can be performed at temperatures between 100°C and 450°C. When removing the adsorbed substances while introducing an inert gas into the deposition chamber, the substances cannot be desorbed by simply evacuating the chamber. The desorption rate of water, which is difficult to remove, can be further increased. By heating to the same temperature as baking, the desorption rate of the adsorbed substances can be further increased. In this case, it is preferable to use a rare gas as the inert gas. Alternatively, oxygen or the like may be used instead of the inert gas. For example, when forming an oxide film, In some cases, it may be preferable to use oxygen, which is the main component. It is preferable to carry out the procedure in this manner.

[0563] Alternatively, an inert gas such as a heated rare gas or oxygen may be introduced into the deposition chamber. It is preferable to increase the pressure and evacuate the deposition chamber again after a certain period of time has elapsed. By introducing gas, it is possible to desorb adsorbed substances in the film formation chamber, and impurities present in the film formation chamber can be removed. This treatment can be performed 2 to 30 times, preferably 5 to 15 times. It is effective to repeat the process no more than once when the temperature is between 40°C and 400°C. In the above, an inert gas or oxygen, etc., preferably at a temperature of 50°C or higher and 200°C or lower, is introduced. The pressure in the deposition chamber is set to 0.1 Pa or more and 10 kPa or less, preferably 1 Pa or more and 1 kPa or less. More preferably, the pressure is set to 5 Pa or more and 100 Pa or less, and the pressure is maintained for 1 minute or more and 300 minutes or less. The deposition chamber is then heated for 5 minutes or more and 300 minutes or less, preferably for 5 minutes or more and 120 minutes or less. The air is evacuated for a period of time not longer than 10 minutes and not longer than 120 minutes.

[0564] Also, the desorption speed of the adsorbed substances can be further increased by forming a dummy film. - Film formation is a process of forming a film on a dummy substrate by a method such as sputtering. A film is deposited on the substrate and the inner wall of the deposition chamber, and impurities in the deposition chamber and substances adsorbed on the inner wall of the deposition chamber are removed by the film. It is preferable to use a dummy substrate that emits less gas. By performing the deposition, it is possible to reduce the impurity concentration in the film to be formed later. The deposition may be performed simultaneously with baking.

[0565] Next, the transfer chamber 2704 and the load lock chamber 2703a shown in FIG. 58(B) and the The atmospheric substrate transfer chamber 2702 and the atmospheric substrate supply chamber 2701 shown in FIG. 8(C) are The following description will be given of the atmospheric side substrate transfer chamber 2702 and the atmospheric side A cross section of the substrate supply chamber 2701 is shown.

[0566] The transfer chamber 2704 shown in FIG. 58(B) is the same as the transfer chamber 2704 shown in FIG. Please refer to the description.

[0567] The load lock chamber 2703a includes a substrate transfer stage 2752. The pressure in the chamber 2703a is increased from a reduced pressure state to atmospheric pressure, and the pressure in the load lock chamber 2703a is increased from the reduced pressure state to atmospheric pressure. When the pressure becomes atmospheric pressure, the transfer robot 27 installed in the atmospheric side substrate transfer chamber 2702 63 to the substrate transfer stage 2752. After the vacuum is drawn in the transfer chamber 2703a and the pressure is reduced, the transfer robot installed in the transfer chamber 2704 The stage 2763 receives the substrate from the substrate transfer stage 2752 .

[0568] The load lock chamber 2703a is connected to a vacuum pump 2770 and a clamp via a valve. It is connected to the ion pump 2771. The vacuum pump 2770 and the cryopump 27 The exhaust system of 71 can be connected by referring to the connection method of the transfer chamber 2704. Therefore, the description will be omitted here. The lock chamber 2703a may have a similar configuration to the lock chamber 2703a.

[0569] The atmospheric substrate transfer chamber 2702 includes a transfer robot 2763. The substrate is transferred between the cassette port 2761 and the load lock chamber 2703a. In addition, the atmosphere side substrate transfer chamber 2702 and the atmosphere side substrate supply chamber 2701 can be For those who use HEPA filters (High Efficiency Particulate Air Filters) A mechanism for cleaning dust or particles such as a IR filter may be provided. stomach.

[0570] The atmospheric substrate supply chamber 2701 has a plurality of cassette ports 2761. The socket 2761 can accommodate multiple substrates.

[0571] The target surface temperature is 100° C. or less, preferably 50° C. or less, and more preferably room temperature. The temperature is set to about 25°C (typically 25°C). However, targets of a size corresponding to a large area are often used. It is difficult to fabricate a seamless target. Although they are arranged in a large shape so that there are no gaps between them, there are still some small gaps. As the surface temperature of the target rises, zinc and other substances evaporate from the small gaps, gradually filling the gaps. If the gap widens, the backing plate or the backing plate may break. The metal of the bonding material used to bond the base and target is sputtered. This causes the impurity concentration to increase. Therefore, the target must be cooled sufficiently. It is preferable that

[0572] Specifically, a metal having high electrical conductivity and high heat dissipation properties ( Specifically, copper is used. In addition, a water channel is formed in the backing plate, and a sufficient amount of By flowing cooling water, the target can be cooled efficiently.

[0573] In addition, when the target contains zinc, the film is formed in an oxygen gas atmosphere, so that the plasma This reduces damage and makes it possible to obtain an oxide in which zinc is less likely to volatilize.

[0574] By using the above-mentioned film forming apparatus, the hydrogen concentration can be measured by secondary ion mass spectrometry (SIMS). 2×10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 The following is better Preferably 1×10 19 atoms / cm 3 Less than 5×10, more preferably 18 atom s / cm 3 An oxide semiconductor film can be formed as follows.

[0575] In addition, the nitrogen concentration was 5×10 19 atoms / cm 3 Less than, preferred 1×10 19 atoms / cm 3 Less than or equal to 5×10 18 atoms / c m 3 Less than 1×10, more preferably 18 atoms / cm 3 An oxide semiconductor having the following structure A film can be formed.

[0576] In addition, the carbon concentration was 5×10 19 atoms / cm 3 Less than, preferred 5×10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / c m 3 Less than 5×10, more preferably 17 atoms / cm 3 An oxide semiconductor having the following structure A film can be formed.

[0577] Thermal Desorption Spectroscopy (TDS) is also used. Gas molecules (atoms) with m / z of 2 (such as hydrogen molecules) as determined by NMR spectroscopy (MES) analysis; Gas molecules (atoms) with m / z of 18, gas molecules (atoms) with m / z of 28, and gas molecules (atoms) with m / z of 19. The amount of gas molecules (atoms) released with z equal to 44 is 1×10 19 pieces / cm 3 Below, good Preferably 1×10 18 pieces / cm 3 An oxide semiconductor film can be formed as follows.

[0578] By using the above-described film formation apparatus, impurities can be prevented from being mixed into the oxide semiconductor. The above-mentioned film formation apparatus is used to form a film in contact with an oxide semiconductor. This can prevent impurities from being mixed into the oxide semiconductor from a film in contact with the oxide semiconductor.

[0579] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is Noh. [Explanation of symbols]

[0580] 100 Transistors 100a transistor 100d structure 101 Substrate 102 Insulators 102a Insulator 103 Insulators 103a Insulator 103b Insulators 103c Insulators 104 Oxide layer 104a Oxide layer 104b Oxide layer 104c oxide layer 104d Oxide layer 104e Oxide layer 104f oxide layer 105 Insulators 105a electrode 105b electrode 105d Insulator 106 Conductors 106d Conductors 107 Insulators 107d Insulators 108 Insulator 108b Insulator 108d Insulator 109a Electric conductor 109b Conductors 109c Conductors 109d Conductors 109e Conductors 109j Conductor 109k Conductor 109l Conductor 109m Conductor 109n Conductor 109o Conductor 110 Insulator 110b Insulator 110d Insulator 111 Insulators 111a Insulator 112 Insulators 112d Contact plug 113a Contact plug 113b Contact plug 113c contact plug 113d Contact plug 114 Conductors 114a Conductor 114b Conductor 114c conductor 117 Conductors 117d conductor 118 Insulator 119 Conductors 126 Conductive Layer 131 Metallic elements 135 areas 141 Capacitive element 142 Capacitive element 145 Mixed layer 150 Transistors 160 Transistors 220 wells 221 p-type semiconductors 223 n-type semiconductor 224 Aperture 225 Aperture 251 Wiring 252 Wiring 253 Wiring 254 Wiring 255 Wiring 256 nodes 257 Capacitive element 260 circuits 270 circuits 273 Electrode 280 circuits 281 Transistor 281a Transistor 281b Transistor 282 Transistor 282a Transistor 282b Transistor 283 Channel Formation Region 284 Low concentration p-type impurity region 285 High concentration p-type impurity region 286 Insulators 287 Conductors 288 Structure 289 Transistor 290 circuits 291 Transistor 300 structures 300d structure 301 Mask 302 Mask 303 Mask 306 Opening 307 Opening 308 Opening 311 Length 312 Length 313 Length 314 Length 315 End 316 End 382 Ec 383a Ec 383b Ec 383c Ec 386 Ec 390 Trap Levels 400 Semiconductor equipment 401 Substrate 402 Insulator 403 Insulators 404 Insulators 405 Insulator 406 Contact plug 406a contact plug 406b contact plug 406c contact plug 407 Insulators 407a Insulator 410 Semiconductor devices 412 Insulators 413 Capacitive element 413a Conductors 413b Conductors 413c Electrical conductor 413d Conductor 414 Element isolation layer 415 Insulators 420 Semiconductor Devices 421 Conductors 422 Conductors 427 Conductors 429 Conductors 430 Semiconductor Devices 442 Insulator 477 Bulkhead 487 Wiring 487a Electric conductor 487b Conductor 488 Conductors 489 Contact plug 550 Interposer 551 Chip 552 Terminal 553 Molding resin 560 Panel 561 Printed Wiring Board 562 packages 563 FPC 564 Battery 585 Insulator 600 Imaging device 601 Photoelectric conversion element 602 Transistor 603 Transistor 604 Transistor 605 Transistor 606 Capacitor 607 nodes 608 Wiring 609 Wiring 610 Pixel driving circuit 611 Wiring 621 Pixel section 622 pixels 622B pixels 622G pixels 622R pixels 623 pixels 624 Filter 624B Filter 624G Filter 624R Filter 625 Lens 626 Wiring group 660 light 681 Photoelectric conversion layer 682 Transparent conductive layer 686 Conductors 686a Conductors 686b Conductors 701 Circuit 702 Circuit 703 Switch 704 Switch 706 Logic Elements 707 Capacitive element 708 Capacitive element 709 Transistor 710 Transistor 713 Transistor 714 Transistor 720 Circuit 730 Memory Element 800 RF Tags 801 Communication Device 802 Antenna 803 radio signal 804 Antenna 805 Rectifier circuit 806 Constant voltage circuit 807 Demodulation Circuit 808 Modulation Circuit 809 Logic Circuit 810 Memory circuit 811 ROM 1189 ROM Interface 1190 Board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Registers 1197 Register Controller 1198 Bus Interface 1199 ROM 1281 Transistor 1283 Channel formation region 1284 Low concentration n-type impurity region 1285 High concentration n-type impurity region 2700 Film deposition equipment 2701 Atmospheric side substrate supply chamber 2702 Atmospheric side substrate transfer chamber 2703a Load Lock Chamber 2703b Unloading lock room 2704 Delivery Room 2705 ​​Substrate heating chamber 2706a Deposition chamber ...

Claims

1. A semiconductor device in which a gate of a first transistor having silicon in a channel formation region is electrically connected to one of a source and a drain of a second transistor having an oxide semiconductor in a channel formation region and one electrode of a capacitor, A first insulator; a first conductor having a region in contact with an upper surface of the first insulator; a second conductor having a region in contact with an upper surface of the first insulator; a second insulator having a region above the first conductor and a region above the second conductor; an oxide semiconductor layer having a region above the second insulator; a third conductor having a region above the oxide semiconductor layer; a fourth conductor having an area below the first insulator; the oxide semiconductor layer includes a channel formation region of the second transistor, the third conductor has a region overlapping with the first conductor with the oxide semiconductor layer interposed therebetween; the third conductor has a region that functions as a first gate electrode of the second transistor; the first conductor has a region that functions as a second gate electrode of the second transistor; the fourth conductor has a region that functions as one electrode of the capacitance element, the second conductor has a region that functions as the other electrode of the capacitance element; a source electrode of the second transistor has a region in contact with a top surface of the oxide semiconductor layer, a drain electrode of the second transistor having a region in contact with an upper surface of the oxide semiconductor layer.

2. a gate of a first transistor having silicon in a channel formation region is electrically connected to one of a source or a drain of a second transistor having an oxide semiconductor in a channel formation region, one of a source or a drain of a third transistor having an oxide semiconductor in a channel formation region, and one electrode of a capacitor; a semiconductor device in which one of a source and a drain of the first transistor is electrically connected to one of a fourth transistor having silicon in a channel formation region, A first insulator; a first conductor having a region in contact with an upper surface of the first insulator; a second conductor having a region in contact with an upper surface of the first insulator; a second insulator having a region above the first conductor and a region above the second conductor; an oxide semiconductor layer having a region above the second insulator; a third conductor having a region above the oxide semiconductor layer; a fourth conductor having an area below the first insulator; the oxide semiconductor layer includes a channel formation region of the second transistor, the third conductor has a region overlapping with the first conductor with the oxide semiconductor layer interposed therebetween; the third conductor has a region that functions as a first gate electrode of the second transistor; the first conductor has a region that functions as a second gate electrode of the second transistor; the fourth conductor has a region that functions as one electrode of the capacitance element, the second conductor has a region that functions as the other electrode of the capacitance element; a source electrode of the second transistor has a region in contact with a top surface of the oxide semiconductor layer, a drain electrode of the second transistor having a region in contact with an upper surface of the oxide semiconductor layer.

3. In claim 1 or 2, The semiconductor device, wherein the first insulator comprises nitrogen and silicon.

4. In any one of claims 1 to 3, The semiconductor device, wherein the oxide semiconductor layer contains indium.

5. In any one of claims 1 to 4, The source electrode and the drain electrode of the second transistor comprise tungsten or titanium.

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